Three-dimensional stacked chip package and method of packaging the same
By incorporating a capacitor layer within a three-dimensional stacked chip package and connecting it to a power network, the problem of transient voltage drop is resolved, resulting in higher stability and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHIHAOTONG (TIANJIN) INFORMATION TECHNOLOGY CO LTD
- Filing Date
- 2024-11-20
- Publication Date
- 2026-05-29
AI Technical Summary
As the number of layers in a 3D chip increases and power consumption rises, transient voltage drop becomes a key factor limiting chip performance, and existing technologies struggle to solve it effectively.
At least one capacitor layer is provided in the three-dimensional stacked chip package and connected to the power network through a vertical conductive channel. The capacitor layer absorbs or releases charge when there are transient current changes to filter power supply noise.
It effectively reduces the impact of transient IR drop, improves chip stability and reliability, and enhances power supply stability and disturbance immunity.
Smart Images
Figure CN122121175A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a three-dimensional stacked chip package and its packaging method. Background Technology
[0002] As the performance of electronic devices continues to improve, the requirements for chip integration and performance are also increasing. Three-dimensional chip technology achieves higher integration and performance by stacking chips with different functions. However, with the increase in the number of chip layers and power consumption, transient voltage (IR) drop has become a key factor limiting chip performance. Transient IR drop refers to the instantaneous drop in power supply voltage caused by rapid changes in current during chip operation, thus affecting the chip's stability and reliability. Summary of the Invention
[0003] In view of this, embodiments of the present invention provide a three-dimensional stacked chip package and a packaging method thereof, which facilitates the reduction of the impact of transient IR drop.
[0004] To achieve the above-mentioned objectives, the following technical solution is adopted: According to a first aspect of the present invention, a three-dimensional stacked chip package is provided, comprising: Functional layer, which includes storage layer, computing layer or interface layer; A power network, which is connected through the functional layer and configured to supply power to the functional layer; At least one capacitor layer, including multiple capacitors integrated side by side, is disposed between at least two functional layers of the storage layer, computing layer and interface layer, and the capacitor layer is electrically connected to the power network through a vertical conductive channel; The at least one capacitor layer is configured to absorb or release charge when a transient current change occurs.
[0005] According to a specific implementation of an embodiment of this application, the at least one capacitor layer is disposed in the middle layer of the three-dimensional stacked chip package, and the power network is connected to each of the functional layers upward or downward through the capacitor layer via the vertical conductive channel.
[0006] According to a specific implementation of an embodiment of this application, the capacitor is a planar capacitor, and multiple capacitors are embedded in parallel between two adjacent functional layers and connected and integrated in the same layer through horizontal interconnect lines to form a capacitor layer.
[0007] According to a specific implementation of an embodiment of this application, the capacitor is a vertical capacitor that penetrates the capacitor layer in a vertical direction and is connected to the power path of each functional layer through the vertical conductive channel, so as to provide transient power regulation for each functional layer.
[0008] According to a specific implementation of an embodiment of this application, the plurality of capacitors are multiple independent capacitor units, each capacitor unit is arranged in a grid pattern within the capacitor layer, and is encapsulated as a whole to lead out wiring pins.
[0009] According to a specific implementation of an embodiment of this application, the power network includes multiple power paths, each power path is distributed with multiple points, and the capacitor layer is connected to the power paths at multiple nodes in multiple layers.
[0010] According to one specific implementation of the embodiments of this application, the capacitor layer and the vertically adjacent functional layer are interconnected by superbonding.
[0011] According to a specific implementation of an embodiment of this application, a heat-conducting pillar is provided through the capacitor layer and at least one functional layer, and the heat-conducting pillar extends to a heat dissipation system outside the chip package.
[0012] According to a second aspect of the embodiments of this application, a method for packaging three-dimensional stacked chips is also provided, the method comprising: At least one stacked layer is provided between at least two functional layers to integrate multiple capacitors, forming a capacitor layer; the functional layers include a storage layer, a computing layer, or an interface layer, and the capacitor layer is configured to absorb or release charge when a transient current change occurs. The capacitor layer is connected to a power network via a vertical conductive channel; the power network extends through the functional layer and is configured to supply power to the functional layer.
[0013] According to a specific implementation of the present application, the step of setting at least one stacked layer between at least two functional layers to integrate multiple capacitors and form a capacitor layer includes: setting the at least one capacitor layer at the middle layer position of the three-dimensional stacked chip package; A power network that connects upwards or downwards to the storage layer, computing layer, or interface layer via vertical conductive channels through the capacitor layer.
[0014] According to a specific implementation of an embodiment of this application, the step of providing at least one stacked layer between at least two functional layers to integrate multiple capacitors and forming a capacitor layer further includes: Planar capacitors are placed between two adjacent functional layers, by integrating multiple capacitors side by side into the same layer; Multiple capacitors are connected by horizontal interconnect lines to form a capacitor layer.
[0015] According to a specific implementation of an embodiment of this application, the step of setting at least one stacked layer between at least two functional layers to integrate multiple capacitors and form a capacitor layer includes: Multiple vertical capacitors are formed in the capacitor layer along the vertical direction, and the vertical capacitors penetrate the capacitor layer. Connecting the capacitor layer to the power network via a vertical conductive channel includes: The power path is connected to the functional layer via a vertical conductive channel to provide transient power regulation for each functional layer.
[0016] According to a specific implementation of an embodiment of this application, the step of setting at least one stacked layer between at least two functional layers to integrate multiple capacitors and form a capacitor layer includes: Multiple capacitors are arranged in a grid pattern within the capacitor layer, and the capacitor unit is encapsulated as a whole. Connect the capacitor to the external power supply path by bringing out the lead-out pins.
[0017] According to a specific implementation of an embodiment of this application, connecting the capacitor layer to the power network via a vertical conductive channel includes: The capacitor layer is connected to the power network through a vertical conductive channel, and multi-point distributed connection is performed on the power path of different layers. The capacitor layer is connected to the power nodes of multiple layers via vertical conductive channels.
[0018] According to a specific implementation of an embodiment of this application, the method further includes: providing a heat-conducting pillar between the capacitor layer and at least one functional layer, and extending the heat-conducting pillar through the capacitor layer and into a heat dissipation channel of the chip package, for conducting the heat of the capacitor layer to a heat dissipation system outside the chip.
[0019] The three-dimensional stacked chip package and its packaging method provided in this application embodiment, by setting at least one capacitor layer in the chip package specifically for integrating large-capacity capacitors and connecting it to the power network, can effectively filter power supply noise by absorbing or releasing charge when transient current changes occur, thereby reducing the impact of transient IR drop. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of an embodiment of the three-dimensional stacked chip package of the present invention; Figure 2This is a schematic flowchart of an embodiment of the packaging method for the three-dimensional stacked chip package of the present invention; Detailed Implementation
[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0023] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0024] 3D chip stacking packaging technology has attracted much attention in recent years due to its higher packaging density and functional integration. However, with the continuous enhancement of chip functions and the increase in power consumption, the problem of power supply voltage drop caused by transient current changes (transient IR drop) has become increasingly prominent, becoming one of the challenges facing the development of 3D chip packaging technology. Some solutions are limited to improving the stability of local circuits and are difficult to cope with transient current changes at the entire system level.
[0025] Reference Figure 1 This invention provides a three-dimensional stacked chip package, suitable for semiconductor device packaging, testing, and high-density interconnection scenarios such as chips; it includes multiple functional layers 110, each including a storage layer, a computing layer, and an interface layer. Each functional layer 110 is interconnected via a power network (not shown in the figure), which runs through the functional layers 110 and is configured to supply power to the functional layers 110.
[0026] At least one capacitor layer 120, comprising multiple capacitors integrated side-by-side, is disposed between at least two functional layers 110 of the storage layer, computing layer, and interface layer, and the capacitor layer 120 is electrically connected to the power network via a vertical conductive channel; the capacitors can be planar capacitors, vertical capacitors, or other types of capacitors to adapt to different integration requirements. The capacitor layer 120 is electrically connected to the power network via a vertical conductive channel. The at least one capacitor layer 120 is configured to absorb or release charge in the event of transient current changes.
[0027] During chip operation, when transient current changes occur, the capacitors in capacitor layer 120 can quickly release or absorb charge to maintain the stability of the power supply voltage, thereby reducing the impact of transient IR drop.
[0028] In this embodiment of the invention, a dedicated stacked layer is created for integrating large-capacity capacitors, forming a capacitor layer 120, which is then connected to the chip's power network. This capacitor layer 120 absorbs or releases charge during transient current changes, effectively filtering power supply noise and reducing the impact of transient IR drops. In some embodiments, the capacitor layer 120 is located between the storage layer and the computing layer. The capacitors in the capacitor layer 120 are integrated using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). These capacitors can be silicon oxide capacitors, silicon nitride capacitors, or capacitors made of other suitable materials.
[0029] In another embodiment, the capacitor layer 120 may be located between the computing layer and the interface layer. The capacitors in the capacitor layer 120 are integrated using a self-aligned salicide method, and the capacitors may be made of nickel silicide, cobalt silicide, or other suitable materials.
[0030] Of course, in practical applications, the integration process of the capacitor layer 120 needs to be compatible with other components of the chip to ensure the consistency and reliability of the entire chip manufacturing and packaging process. In this embodiment, by adding a dedicated stacking layer to integrate a large-capacity capacitor to form the capacitor layer 120 and connecting it to the power path of the power network, transient IR drop can be effectively reduced, improving the stability and reliability of the chip.
[0031] For example, in some embodiments, the chip package includes six layers, wherein the second layer is designed as a dedicated stacking layer for integrating large-capacity capacitors to form a capacitor layer.
[0032] In the second layer, vertical capacitors are chosen to form the capacitor layer, which provides higher capacitance density and better power supply noise filtering. In a dedicated stacked layer (used to form the capacitor layer), advanced semiconductor process technologies, such as deep trench isolation (DTI), are used to integrate large-capacity capacitors.
[0033] Design the power path so that the capacitor is effectively connected to the power network to achieve optimal power noise filtering, thereby reducing the impact of voltage drop during transient current changes.
[0034] After the chip manufacturing and packaging are completed, a series of tests are conducted, including transient current testing and voltage stability testing, to verify the expected effect of capacitor integration.
[0035] Reference Figure 1 At least one capacitor layer 120 of the three-dimensional stacked chip package is disposed in the middle layer of the three-dimensional stacked chip package, and the power network is connected to each of the functional layers 110 upward or downward through the vertical conductive channel via the capacitor layer 120.
[0036] In this embodiment, the power network is connected to the capacitor layer 120 through a vertical conductive channel, and further connected to the upper or lower functional layer 110 to ensure a stable power supply.
[0037] Vertical conductive channels can be fabricated using techniques such as laser, electron beam, or plasma etching to create vias, enabling high-precision channel construction within a tiny space. This allows for conductivity and provides interlayer connection paths for the power network.
[0038] The vertical conductive channel can also be formed by depositing a metallic material, such as copper, aluminum, or their alloys, at predetermined locations using MOCVD (Metal Organic Chemical Vapor Deposition) technology, creating a vertical metal pillar as the conductive channel. This metal pillar can be positioned between multiple layers of the chip package, serving as a connection between the power network and different functional layers 110.
[0039] In other embodiments, the vertical conductive channel can be formed by depositing conductive ink droplets into the vertical channel structure using 3D printing technology to create vertical conductive channels that connect different levels. This process is simple and can quickly realize complex spatial layout designs.
[0040] In some embodiments, the capacitor is a planar capacitor, and multiple capacitors are embedded in parallel between two adjacent functional layers 110 and connected and integrated in the same layer by horizontal interconnect lines to form a capacitor layer 120.
[0041] In this embodiment, by integrating parallel planar capacitors between adjacent functional layers 110 and connecting them in series via horizontal interconnects, a special capacitor layer 120 embedded in the package is formed. By utilizing the energy storage and release characteristics of the capacitors to regulate the local current distribution and voltage fluctuations, the power supply to chip transmission efficiency can be improved.
[0042] Multiple planar capacitors are connected by horizontal interconnects to form a single capacitor layer 120, providing a larger capacitance value and better power supply noise filtering.
[0043] In other embodiments, the capacitor is a vertical capacitor that extends through the capacitor layer 120 in a vertical direction and is connected to the power path of each functional layer 110 through the vertical conductive channel to provide transient power regulation for each functional layer 110.
[0044] In one embodiment, the vertical capacitor layer 120 is located between the storage layer and the computing layer. The vertical capacitors in the capacitor layer 120 can be integrated using the aforementioned self-aligned metallization method. The vertical capacitors penetrate the capacitor layer 120 in a vertical direction and are connected to the power paths of each functional layer 110 through vertical conductive channels. This allows for more efficient provision of transient current regulation among multiple functional layers 110, enabling rapid absorption or release of charge during transient current changes and maintaining stable power supply voltage.
[0045] To improve the layout flexibility of the capacitor layer 120, the multiple capacitors are multiple independent capacitor units, and each capacitor unit is arranged in a grid pattern within the capacitor layer 120 to increase the integration density of the capacitors. The capacitors are also encapsulated and have lead-out pins to enhance power regulation and control.
[0046] Specifically, the power network includes multiple power paths, each power path is distributed with multiple points, and the capacitor layer 120 is connected to the power paths at multiple nodes in multiple layers.
[0047] In this embodiment, a structure is constructed in which multiple power paths are interconnected with capacitor layers 120 to achieve multi-level, multi-point distributed power supply. The power path of each layer is connected to the capacitor layer 120 of the adjacent part through multiple nodes. This multi-level structure can not only effectively improve power distribution and voltage stability, but also significantly improve the energy efficiency and lifespan of the chip.
[0048] Specifically, in this embodiment, the multi-layer, multi-point distributed power network significantly improves the redundancy of the power path, enabling rapid switching to an adjacent layer to continue providing power in the event of a failure in any layer. This ensures the continuity and stability of system operation, which is crucial for the reliability of integrated circuits. Simultaneously, the distributed connection of capacitor layer 120 enhances the energy storage capacity of the power network, effectively mitigating the impact of instantaneous load fluctuations on the system and further improving the system's disturbance rejection and stability.
[0049] In some embodiments, the capacitor layer 120 is interconnected with the vertically adjacent functional layer 110 via superbonding to achieve electrical interconnection between different layers.
[0050] Specifically, an insulating dielectric layer with a thickness of 0.1μm to 0.5μm may be provided between the capacitor layer 120 and the vertically adjacent functional layer 110 to provide electrical isolation and signal integrity. When the vertical conductive channel is used for interconnection between different layers, it is provided through the insulating dielectric layer.
[0051] In this embodiment, by providing an insulating dielectric layer between the capacitor layer 120 and the functional layer 110, the interference between the capacitor layer 120 and the functional layer 110 is effectively reduced, which can improve the electrical isolation effect of the non-interconnected parts between different layers and ensure the reliable connection of the vertical conductive channel.
[0052] To improve the heat dissipation performance of the chip, in some embodiments, a heat-conducting pillar is provided through the capacitor layer 120 and at least one functional layer 110. The heat-conducting pillar extends to the heat dissipation system outside the chip package to effectively dissipate heat and ensure the stable operation of the chip.
[0053] See Figure 1 and Figure 2 As shown in the illustration, this application also provides a method for packaging three-dimensional stacked chips, the method comprising: S210. At least one stacked layer is provided between at least two functional layers 110 to integrate multiple capacitors and form a capacitor layer 120; the functional layer 110 includes a storage layer, a computing layer or an interface layer, and the capacitor layer 120 is configured to absorb or release charge through at least one capacitor layer 120 when a transient current change occurs.
[0054] S220. The capacitor layer 120 is connected to the power network through a vertical conductive channel; the power network is connected through the functional layer 110 and configured to supply power to the functional layer 110. The capacitor layer 120 is configured to absorb or release charge through at least one layer of the capacitor layer 120 when a transient current change occurs.
[0055] It is understandable that functional layers and capacitor layers are located on the packaging substrate 130.
[0056] In some embodiments, the step of setting at least one stacked layer between at least two functional layers 110 to integrate multiple capacitors and form a capacitor layer 120 includes: setting the at least one capacitor layer 120 at the middle layer position of the three-dimensional stacked chip package; A power network is connected upwards or downwards to the storage layer, computing layer, or interface layer via a vertical conductive channel through the capacitor layer 120.
[0057] Depending on the actual design requirements, the capacitors in capacitor layer 120 can adopt different layouts and structures. In some embodiments, the provision of at least one stacked layer between at least two functional layers 110 for integrating multiple capacitors to form capacitor layer 120 further includes: providing planar capacitors between two adjacent functional layers 110, integrating multiple capacitors side by side in the same layer; and connecting multiple capacitors through horizontal interconnects to form capacitor layer 120.
[0058] During the packaging process, a first metal electrode layer is first deposited on the surface of the capacitor layer 120, followed by the deposition of a dielectric material layer, and then a second metal electrode layer. This method forms multiple planar capacitor cells within the capacitor layer 120. Each capacitor cell is connected via horizontal interconnects and further connected to a power network via through-silicon vias (TSVs).
[0059] In some embodiments, the provision of at least one stacked layer between at least two functional layers 110 for integrating multiple capacitors to form a capacitor layer 120 includes: forming multiple vertical capacitors in the capacitor layer 120 along a vertical direction, the vertical capacitors penetrating the capacitor layer 120; wherein, the formation of the vertical capacitors relies on creating vertical channels in the capacitor layer 120 using an etching technique, and depositing dielectric and conductive materials within the channels to form upper and lower electrodes. This vertical capacitor can more efficiently regulate current changes between the functional layers 110, making it particularly suitable for high-load computing scenarios.
[0060] The diameter of the vertical conductive channel is 1μm to 5μm, which is used to reduce the current transmission impedance in the vertical direction and improve the transient current regulation capability.
[0061] Connecting the capacitor layer 120 to the power network via a vertical conductive channel includes: connecting the power path to the functional layer 110 via a vertical conductive channel to provide transient power regulation for each functional layer 110.
[0062] Specifically, each capacitor has a capacitance range of 10pF to 100pF and performs power regulation at different operating frequencies. It is specifically used to cope with transient current changes in the frequency range of hundreds of MHz to GHz, thereby optimizing the power regulation effect and improving the overall performance of the chip.
[0063] In some embodiments, the provision of at least one stacked layer between at least two functional layers 110 for integrating multiple capacitors to form a capacitor layer 120 includes: Multiple capacitors are arranged in a grid pattern within the capacitor layer 120, and the capacitor unit is encapsulated as a whole. Connect the capacitor to the external power supply path by bringing out the lead-out pins.
[0064] In some embodiments, connecting the capacitor layer 120 to the power network via a vertical conductive channel includes: The capacitor layer 120 is connected to the power network through a vertical conductive channel, and multi-point distributed connection is performed on the power path of different layers. Capacitor layer 120 is connected to the power nodes of multiple layers via vertical conductive channels.
[0065] The formation of a vertical conductive channel may include the following steps: Through-silicon vias are formed on the chip wafer using deep silicon etching technology, penetrating the capacitor layer 120 and the functional layer 110.
[0066] Conductive materials, such as copper, are deposited within through-silicon vias to enable electrical interconnects.
[0067] The through-silicon vias are connected to the power network and capacitor layer 120 through a metal layer, ensuring that the power network runs through each functional layer 110 and achieving vertical interconnection.
[0068] In some embodiments, the method further includes: providing a heat-conducting pillar between the capacitor layer 120 and at least one functional layer 110, and extending the heat-conducting pillar through the capacitor layer 120 and into a heat dissipation channel of the chip package, for conducting heat from the capacitor layer 120 to a heat dissipation system outside the chip.
[0069] The heat-conducting pillars include multiple pillars and are made of a material with a thermal conductivity of 20~400W / mk.
[0070] This embodiment provides a packaging method for a three-dimensional stacked chip, specifically for the packaging design of highly integrated chips. This packaging method optimizes the transient power regulation capability of the chip by setting a capacitor layer 120 between functional layers 110 and connecting it to the power network through a vertical conductive channel.
[0071] In summary, the three-dimensional stacked chip package and its packaging method provided in this embodiment of the invention, by setting at least one capacitor layer in the chip package specifically for integrating large-capacity capacitors and connecting it to the power network, can effectively filter power supply noise by absorbing or releasing charge when transient current changes occur, thereby reducing the impact of transient IR drop.
[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0073] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0074] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A three-dimensional stacked chip package, characterized in that, include: Functional layer, which includes storage layer, computing layer or interface layer; A power network, which is connected through the functional layer and configured to supply power to the functional layer; At least one capacitor layer, including multiple capacitors integrated side by side, is disposed between at least two functional layers of the storage layer, computing layer and interface layer, and the capacitor layer is electrically connected to the power network through a vertical conductive channel; The at least one capacitor layer is configured to absorb or release charge when a transient current change occurs.
2. The three-dimensional stacked chip package according to claim 1, characterized in that, The at least one capacitor layer is disposed in the middle layer of the three-dimensional stacked chip package, and the power network is connected to each of the functional layers upward or downward through the capacitor layer via the vertical conductive channel.
3. The three-dimensional stacked chip package according to claim 2, characterized in that, The capacitor is a planar capacitor, and multiple capacitors are embedded in parallel between two adjacent functional layers and connected by horizontal interconnects to form a capacitor layer.
4. The three-dimensional stacked chip package according to claim 2, characterized in that, The capacitor is a vertical capacitor that runs through the capacitor layer in a vertical direction and is connected to the power path of each functional layer through the vertical conductive channel to provide transient power regulation for each functional layer.
5. The three-dimensional stacked chip package according to claim 2, characterized in that, The capacitors are multiple independent capacitor units, and each capacitor unit is arranged in a grid pattern within the capacitor layer and is encapsulated as a whole to lead out wiring pins.
6. The three-dimensional stacked chip package according to claim 1, characterized in that, The power network includes multiple power paths, each power path is distributed with multiple points, and the capacitor layer is connected to the power path at multiple nodes in multiple layers.
7. The three-dimensional stacked chip package according to claim 1, characterized in that, The capacitor layer is interconnected with the vertically adjacent functional layer via superbonding.
8. The three-dimensional stacked chip package according to claim 1, characterized in that, A heat-conducting pillar is provided through the capacitor layer and at least one functional layer, and the heat-conducting pillar extends to the heat dissipation system outside the chip package.
9. A method for packaging three-dimensional stacked chips, characterized in that, The method includes: At least one stacked layer is provided between at least two functional layers to integrate multiple capacitors, forming a capacitor layer; the functional layers include a storage layer, a computing layer, or an interface layer, and the capacitor layer is configured to absorb or release charge when a transient current change occurs. The capacitor layer is connected to a power network via a vertical conductive channel; the power network extends through the functional layer and is configured to supply power to the functional layer.
10. The packaging method for a three-dimensional stacked chip according to claim 9, characterized in that, The provision of at least one stacked layer between at least two functional layers for integrating multiple capacitors to form a capacitor layer includes: providing the at least one capacitor layer at the middle layer position of the three-dimensional stacked chip package; A power network that connects upwards or downwards to the storage layer, computing layer, or interface layer via vertical conductive channels through the capacitor layer.
11. The packaging method for three-dimensional stacked chips according to claim 10, characterized in that, The provision of at least one stacked layer between at least two functional layers for integrating multiple capacitors to form a capacitor layer further includes: Planar capacitors are placed between two adjacent functional layers, by integrating multiple capacitors side by side into the same layer; Multiple capacitors are connected by horizontal interconnect lines to form a capacitor layer.
12. The packaging method for three-dimensional stacked chips according to claim 10, characterized in that, The provision of at least one stacked layer between at least two functional layers for integrating multiple capacitors to form a capacitor layer includes: Multiple vertical capacitors are formed in the capacitor layer along the vertical direction, and the vertical capacitors penetrate the capacitor layer. Connecting the capacitor layer to the power network via a vertical conductive channel includes: The power path is connected to the functional layer via a vertical conductive channel to provide transient power regulation for each functional layer.
13. The packaging method for three-dimensional stacked chips according to claim 10, characterized in that, The provision of at least one stacked layer between at least two functional layers for integrating multiple capacitors to form a capacitor layer includes: Multiple capacitors are arranged in a grid pattern within the capacitor layer, and the capacitor unit is encapsulated as a whole. Connect the capacitor to the external power supply path by bringing out the lead-out pins.
14. The packaging method for three-dimensional stacked chips according to claim 10, characterized in that, The step of connecting the capacitor layer to the power network via a vertical conductive channel includes: The capacitor layer is connected to the power network through a vertical conductive channel, and multi-point distributed connection is performed on the power path of different layers. The capacitor layer is connected to the power nodes of multiple layers through vertical conductive channels.
15. The packaging method for three-dimensional stacked chips according to claim 9, characterized in that, The method further includes: providing a heat-conducting pillar between the capacitor layer and at least one functional layer, and extending the heat-conducting pillar through the capacitor layer and into a heat dissipation channel of the chip package, for conducting the heat of the capacitor layer to a heat dissipation system outside the chip.