A method for preparing a metal layer on a chip

Abstract

The application discloses a method for preparing a metal layer on a chip, and belongs to the technical field of chip manufacturing. In the preparation method, firstly, a trapezoidal structure with an upper positive and a lower negative is formed by crossing positive and negative photoresists, a continuous permeation channel is constructed in the vertical direction, the photoresist stripping solution can quickly permeate to the contact surface of the metal and the photoresist, the Lift-off process time is significantly shortened, and the residual problem caused by the metal bridging is effectively avoided; secondly, a separation layer is deposited on the surface of the positive photoresist, mutual dissolution of the positive photoresist and the negative photoresist in the developing, etching and metal deposition processes can be effectively prevented, the integrity of the double-layer photoresist structure is ensured, and even under the high-temperature or plasma etching working condition, the interface delamination phenomenon does not occur.

Description

Technical Field

[0001] This invention belongs to the field of chip manufacturing technology, and specifically relates to a method for preparing a metal layer on a chip. Background Technology

[0002] The traditional method for fabricating metal layers on chips is the metal deposition lift-off process, which typically uses a single layer of positive photoresist. As the metal layer thickness increases, the photoresist sidewalls are easily covered by metal, causing bridging between the metal and photoresist. This often results in metal residue and photoresist tearing during the lift-off process. While existing research has addressed this issue by improving lift-off efficiency through photoresist pretreatment before development and using high-adhesion formulations, it still cannot reliably lift thick metal layers ≥4μm in thickness. Furthermore, a single layer of positive photoresist cannot simultaneously meet the requirements for high-resolution pattern definition, metal deposition thickness, and subsequent metal lift-off. When the photoresist thickness is too thin, metal deposition is limited, failing to form a metal layer thickness that meets electrical and mechanical performance requirements. When the photoresist thickness is too large, solvent penetration during development, etching, and metal lift-off is hindered, leading to photoresist residue and poor metal adhesion. Therefore, a novel process solution is urgently needed that can maintain high pattern resolution while providing sufficient photoresist thickness for support and achieving efficient lift-off after metal deposition. Summary of the Invention

[0003] Therefore, the object of the present invention is to provide a method for fabricating a metal layer on a chip.

[0004] This invention provides a method for fabricating a metal layer on a chip, comprising the following steps: S1: Fabrication of SiN on a chip layer x Masking layer; in SiN x A positive photoresist is spin-coated onto a masking layer, and the pixel area is exposed by exposure and development to obtain an intermediate device 1 containing a positive photoresist pattern; S2: An isolation layer is prepared on the entire surface of the intermediate device 1 with a positive photoresist pattern on the positive photoresist side; negative photoresist is spin-coated onto the isolation layer until the entire surface is flat; then the position of the pixel area is exposed by exposure and development to obtain the intermediate device 2 with a negative photoresist pattern. S3: The pixel area of ​​the intermediate device 2 containing the negative photoresist pattern is etched with acid to remove the isolation layer on the photoresist sidewall of the pixel area, thus obtaining the intermediate device 3. S4: Etch intermediate device 3 to remove SiN from the pixel area. x The masking layer is applied until the metal pillar is exposed, resulting in intermediate device 4; S5: A metal layer is deposited on the upper surface of the side containing photoresist of intermediate device 4. After the deposition is completed, the photoresist layer is wet-stripped to obtain a chip containing a metal layer.

[0005] Preferably, in step S1, the method for preparing the SiNx masking layer is ICP-CVD deposition. The specific process parameters of ICP-CVD deposition are as follows: deposition temperature is 70~80℃, working gas pressure is 8~9 mtorr, ICP power is 350~400W; SiH4 gas flow rate is 6.8~7.2 mL / min, N2 gas flow rate is 6.3~6.7 mL / min; deposition time is 10~20 min, and the thickness of the SiNx masking layer is 150~280 nm.

[0006] Preferably, in step S1, the spin coating speed is 2000~3000 rpm, the thickness of the positive photoresist is 2~3 μm, and the exposure dose is 120~180 mJ / cm. 2 After exposure, the chip is baked at 100~120℃ for 60~80s before development, which takes 45~60s.

[0007] Preferably, in step S2, the isolation layer is a SiNx isolation layer, and SiN is prepared... x The isolation layer is prepared using ICP-CVD deposition. The specific process parameters for ICP-CVD deposition are: deposition temperature 70~80℃, working gas pressure 8~9 mtorr, ICP power 350~400W; SiH4 gas flow rate 6.8~7.2 mL / min, N2 gas flow rate 6.3~6.7 mL / min; deposition time 2~4 min; SiN... x The thickness of the isolation layer is 30~50nm.

[0008] Preferably, in step S2, the spin coating speed is 2000~3000 rpm, the thickness of the negative photoresist is 2~3 μm (the thickness of the negative photoresist is calculated starting from the top surface of the isolation layer); and the exposure dose is 110~180 mJ / cm. 2 After exposure, the chip is post-baked at 100~120℃ for 60~80s before development, which takes 55~75s.

[0009] Preferably, in step S3, the acid corrosion is carried out by immersion corrosion, the acid is hydrofluoric acid with a volume concentration of 45~50%, and the corrosion rate is 250~300 Å / min.

[0010] Preferably, in step S4, the etching is dry etching, and the process conditions for dry etching are: etching power of 120~140W, vacuum degree of 10~20mTorr; etching gas is a mixture of CHF3 and O2, with CHF3 gas flow rate of 45~55sccm and O2 gas flow rate of 8~11sccm; etching time of 5~8min.

[0011] Preferably, in step S5, the thickness of the metal layer is 3~5μm; the metal layer is an Au metal layer; the evaporation is vacuum evaporation, and during evaporation, 80~120nm is first deposited at a speed of 0.5~0.8Å / s, and then the speed is adjusted to 1.0~1.5Å / s to deposit until the thickness reaches 3~5μm.

[0012] Preferably, in step S5, the wet stripping method for the photoresist layer is as follows: immerse the chip in a photoresist remover solution to remove the photoresist, and after immersion, clean it with alcohol; wherein: the immersion temperature is 70~85℃, and the immersion time is 10~30min.

[0013] Compared with the prior art, one or more of the above technical solutions can achieve at least one of the following beneficial effects: In the preparation method of this invention, firstly, a trapezoidal structure with the top upright and the bottom inverted is formed by the intersection of two layers of photoresist, creating a continuous penetration channel in the vertical direction. This allows the resist remover to quickly penetrate to the contact surface between the metal and the photoresist, significantly shortening the lift-off process time and effectively avoiding residue problems caused by metal bridging. Secondly, an isolation layer is deposited on the surface of the positive photoresist, which effectively prevents the negative photoresist from dissolving into the positive photoresist during development, etching, and metal deposition, ensuring the integrity of the double-layer photoresist structure. Even under high-temperature or plasma etching conditions, no problems will occur. The method of this invention avoids interface delamination. Furthermore, the cumulative thickness of the double-layer photoresist in the method of this invention can reach 3~5µm, providing sufficient structural support for metal deposition. This allows the metal layer thickness to be increased to 3~5µm simultaneously without bridging or peeling failure, meeting the application requirements of high-power electronic devices and MEMS structures for thick metal layers. In addition, this invention uses complementary exposure of bright and dark field masks to form trapezoidal patterns, eliminating the need for additional photolithography steps or complex process window adjustments. This simplifies the process flow, improves product yield, and is fully compatible with existing CMO manufacturing lines. Attached Figure Description

[0014] Figure 1 This is a process flow diagram of step (1) in an embodiment of the present invention.

[0015] Figure 2 This is a process flow diagram of step (2) in an embodiment of the present invention.

[0016] Figure 3 This is a process flow diagram of step (3) in an embodiment of the present invention.

[0017] Figure 4 This is a process flow diagram of step (4) in an embodiment of the present invention.

[0018] Figure 5 This is a process flow diagram of step (5) in an embodiment of the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, the present invention will be described more fully and in detail below with reference to the accompanying drawings and preferred embodiments, but the scope of protection of the present invention is not limited to the following specific embodiments.

[0020] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by those skilled in the art. The technical terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the invention.

[0021] As mentioned above, the present invention provides a method for fabricating a metal layer on a chip, comprising the following steps: S1: Fabrication of SiN on a chip layer x Masking layer; in SiN x A positive photoresist is spin-coated onto a masking layer, and the pixel area is exposed by exposure and development to obtain an intermediate device 1 containing a positive photoresist pattern; S2: An isolation layer is prepared on the entire surface of the intermediate device 1 with a positive photoresist pattern on the positive photoresist side; negative photoresist is spin-coated onto the isolation layer until the entire surface is flat; then the position of the pixel area is exposed by exposure and development to obtain the intermediate device 2 with a negative photoresist pattern. S3: The pixel area of ​​the intermediate device 2 containing the negative photoresist pattern is etched with acid to remove the isolation layer on the photoresist sidewall of the pixel area, thus obtaining the intermediate device 3. S4: Etch intermediate device 3 to remove SiN from the pixel area. x The masking layer is applied until the metal pillar is exposed, resulting in intermediate device 4; S5: A metal layer is deposited on the upper surface of the side containing photoresist of intermediate device 4. After the deposition is completed, the photoresist layer is wet-stripped to obtain a chip containing a metal layer.

[0022] First, the method of this invention constructs a trapezoidal staggered structure formed by overlapping positive and negative double-layer photoresist, creating continuous resist-removing penetration channels in the vertical direction. This significantly improves resist-removing penetration efficiency, enabling rapid dissolution of the photoresist and complete stripping of the metal layer, effectively avoiding problems such as stripping residue and bridging. Second, the invention adds a chemically inert isolation layer between the double-layer photoresist, which completely prevents the positive and negative photoresist layers from dissolving into each other during development, etching, and metal deposition processes, ensuring the integrity of the double-layer structure and preventing interface delamination and structural failure. Third, the total thickness of the double-layer photoresist in this invention is ≥4µm, providing sufficient structural support for the deposition of thick metal layers, enabling stable deposition of 3~5µm thick metal layers, meeting the application requirements of high-power electronic devices and MEMS structures for thick metal layers. Furthermore, this invention relies on the complementary exposure of the double-layer photoresist and bright / dark field masks, eliminating the need for additional photolithography steps to form the trapezoidal structure. This simplifies the process flow while ensuring high-resolution patterns, compatibility with existing CMOS manufacturing processes, and improved production yield.

[0023] The process of this invention utilizes two layers of photoresist with different properties to prepare a high-thickness metal layer, which can solve the problem of the difficulty in peeling off high-thickness metal layers.

[0024] Preferably, in step S1, the preparation of SiN x The masking layer is applied using ICP-CVD deposition. Specific process parameters for ICP-CVD deposition are as follows: deposition temperature is 70~80℃, including but not limited to: 70℃, 72℃, 75℃, 78℃, 80℃, etc.; working gas pressure is 8~9 mtorr, including but not limited to: 8 mtorr, 8.2 mtorr, 8.5 mtorr, 8.8 mtorr, 9 mtorr, etc.; ICP power is 350~400W, including but not limited to: 350W, 360W, 370W, 380W, 390W, 400W, etc.; and the SiH4 gas flow rate is 6. The flow rate of N2 gas is 8~7.2 mL / min, including but not limited to: 6.8 mL / min, 6.9 mL / min, 7.0 mL / min, 7.1 mL / min, 7.2 mL / min, etc.; the gas flow rate of N2 is 6.3~6.7 mL / min, including but not limited to: 6.3 mL / min, 6.4 mL / min, 6.5 mL / min, 6.6 mL / min, 6.7 mL / min, etc.; the coating time is 10~20 min, including but not limited to: 10 min, 12 min, 15 min, 18 min, 20 min, etc.; SiN x The thickness of the masking layer is 150~280nm, including but not limited to: 150nm, 180nm, 200nm, 220nm, 250nm, 280nm, etc.

[0025] Preferably, in step S1, the spin coating speed is 2000~3000 rpm, including but not limited to: 2000 rpm, 2200 rpm, 2500 rpm, 2800 rpm, 3000 rpm, etc.; the thickness of the positive photoresist is 2~3 μm (the thickness of the negative photoresist is calculated from the bottom position of the upper surface of the isolation layer), including but not limited to: 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc.; the exposure dose is 120~180 mJ / cm. 2 Including but not limited to: 120mJ / cm 2 130mJ / cm 2 140mJ / cm 2 150mJ / cm 2 160mJ / cm 2 170mJ / cm 2 180mJ / cm 2 After exposure, the chip is baked at 100~120℃ for 60~80s before development. The development time is 45~60s, including but not limited to: 45s, 50s, 55s, 60s, etc.

[0026] Preferably, in step S2, the isolation layer is SiN. x An isolation layer, the thickness of which is 30~50nm, including but not limited to: 30nm, 35nm, 40nm, 45nm, 50nm, etc. More preferably, SiN is prepared. x The isolation layer is applied using ICP-CVD deposition. Specific process parameters for ICP-CVD deposition are as follows: deposition temperature is 70~80℃, including but not limited to: 70℃, 72℃, 75℃, 78℃, 80℃, etc.; working gas pressure is 8~9 mtorr, including but not limited to: 8 mtorr, 8.2 mtorr, 8.5 mtorr, 8.8 mtorr, 9 mtorr, etc.; ICP power is 350~400W, including but not limited to: 350W, 360W, 370W, 380W, 390W, 400W, etc.; Si The flow rate of H4 is 6.8~7.2 mL / min, including but not limited to: 6.8 mL / min, 6.9 mL / min, 7.0 mL / min, 7.1 mL / min, 7.2 mL / min, etc.; the flow rate of N2 is 6.3~6.7 mL / min, including but not limited to: 6.3 mL / min, 6.4 mL / min, 6.5 mL / min, 6.6 mL / min, 6.7 mL / min, etc.; the coating time is 2~4 min, including but not limited to: 2 min, 3 min, 4 min, etc.

[0027] Preferably, in step S2, the spin coating speed is 2000~3000 rpm, including but not limited to: 2000 rpm, 2200 rpm, 2500 rpm, 2800 rpm, 3000 rpm, etc.; the thickness of the negative photoresist is 2~3 μm; and the exposure dose is 110~180 mJ / cm. 2 Including but not limited to: 110mJ / cm 2 120mJ / cm 2 130mJ / cm 2 140mJ / cm 2 150mJ / cm 2 160mJ / cm 2 170mJ / cm 2 180mJ / cm 2 After exposure, the chip is baked at 100~120℃ for 60~80s before development, with a development time of 55~75s, including but not limited to: 55s, 60s, 65s, 70s, 75s, etc.

[0028] Preferably, in step S3, the acid corrosion is carried out by immersion corrosion, and the acid is hydrofluoric acid with a volume concentration of 45~50% (including but not limited to: 45%, 46%, 47%, 48%, 49%, 50%, etc.) and the corrosion rate is 250~300 Å / min.

[0029] Preferably, in step S4, the etching is dry etching, and the process conditions for dry etching are as follows: etching power is 120~140W, including but not limited to: 120W, 125W, 130W, 135W, 140W, etc.; vacuum degree is 10~20mTorr, including but not limited to: 10mtorr, 12mtorr, 15mtorr, 18mtorr, 20mtorr, etc.; the etching gas is a mixture of CHF3 and O2, the gas flow rate of CHF3 is 45~55sccm, including but not limited to: 45sccm, 48sccm, 50sccm, 52sccm, 55sccm, etc.; the gas flow rate of O2 is 8~11sccm, including but not limited to: 8sccm, 9sccm, 10sccm, 11sccm, etc.; and the etching time is 5~8min, including but not limited to: 5min, 6min, 7min, 8min, etc.

[0030] Preferably, in step S5, the thickness of the metal layer is 3~5μm, including but not limited to: 3μm, 3.5μm, 4μm, 4.5μm, 5μm, etc.; the metal layer is an Au metal layer; the evaporation is vacuum evaporation, and during evaporation, firstly, 80~120nm (including but not limited to: 80nm, 90nm, 100nm, 110nm, 120nm, etc.) is deposited at a speed of 0.5~0.8Å / s (including but not limited to: 0.5Å / s, 0.6Å / s, 0.7Å / s, 0.8Å / s, etc.), and then the speed is adjusted to 1.0~1.5Å / s (including but not limited to: 1Å / s, 1.1Å / s, 1.2Å / s, 1.3Å / s, 1.4Å / s, 1.5Å / s, etc.) until the thickness reaches 3~5μm.

[0031] Preferably, in step S5, the wet stripping method for the photoresist layer is as follows: immersing the chip in a photoresist remover solution to remove the photoresist, and then cleaning it with alcohol after immersion; wherein: the immersion temperature is 70~85℃, including but not limited to: 70℃, 72℃, 75℃, 78℃, 80℃, 82℃, 85℃, etc.; the immersion time is 10~30min, including but not limited to: 10min, 15min, 20min, 25min, 30min, etc.

[0032] Example 1 (1) The process flow diagram for this step is as follows: Figure 1 As shown, a SiNx masking layer was prepared on the chip surface using ICP-CVD deposition (wherein the ICP-CVD deposition conditions were: deposition temperature 75℃, ICP power 380W, SiH4 and N2 flow rates 7.0 and 6.5 mL / min respectively, deposition time 15 min, and deposition thickness 210 nm). x A 2.5µm thick layer of positive photoresist was spin-coated at 2500 rpm. After spin-coating, pre-baking was performed (pre-baking temperature 110℃, pre-baking time 70s). After pre-baking, the pattern was exposed using an I-line lithography machine at an exposure dose of 150mJ / cm². 2 After exposure, the chip is post-baked at 110°C for 70 seconds, then immersed in developer for 50 seconds to expose the pixel area, and then spun dry at 5800 rpm for 18 seconds to obtain intermediate device 1 with positive photoresist pattern.

[0033] (2) The process flow diagram for this step is as follows: Figure 2As shown, a SiNx isolation layer was prepared on the upper surface of the photoresist side of the intermediate device 1 containing a positive photoresist pattern using ICP-CVD deposition (wherein: the ICP-CVD deposition process conditions were: deposition temperature 75℃, ICP power 380W, SiH4 and N2 flow rates 7.0 and 6.5 mL / min respectively, deposition time 3 min, and deposition thickness 40 nm); on the SiN... x A 2.5µm thick layer of negative photoresist (5µm thick in the pixel area) was spin-coated onto the upper surface of the device at 2500 rpm until it was smooth. After spin-coating, a pre-bake was performed (pre-bake temperature 115℃, pre-bake time 75s). After pre-bake, the pattern was exposed using an I-line lithography machine at an exposure dose of 145mJ / cm². 2 After exposure, the chip is post-baked at 110°C for 75 seconds, then immersed in developer for 65 seconds to expose the pixel area, and then spun dry at 5800 rpm for 18 seconds to obtain intermediate device 1 with negative photoresist pattern.

[0034] (3) The process flow diagram for this step is as follows: Figure 3 As shown, the intermediate device 1 containing a negative photoresist pattern is immersed in a 49% hydrofluoric acid solution to etch the SiN on the sidewalls of the positive photoresist layer in the pixel area. x The isolation layer was etched at a rate of 280 Å / min. After etching, it was cleaned with pure water to obtain intermediate device 3.

[0035] (4) The process flow diagram for this step is as follows: Figure 4 As shown, intermediate device 3 is placed in a RIE etching machine for dry etching, wherein: the process parameters for dry etching are: etching power of 130W, etching temperature of room temperature, vacuum degree of 15mTorr; etching gases are CHF3 and O2, CHF3 flow rate of 50sccm, O2 flow rate of 9sccm, etching time of 6min, exposing the W pillar of the pixel area; intermediate device 4 is obtained.

[0036] (5) The process flow diagram for this step is as follows: Figure 5 As shown, intermediate device 4 (with the photoresist layer facing out) is placed in a vacuum evaporation machine. First, an Au metal layer with a thickness of 100 nm is deposited at a speed of 0.7 Å / s. Then, the speed is adjusted to 1.2 Å / s to deposit an Au metal layer with a thickness of 2.9 μm. After the evaporation is completed, the chip is immersed in the photoresist remover solution at 80°C for 20 min. After immersion, it is cleaned with an alcohol spray gun to obtain a chip with a patterned metal layer.

[0037] Using the process of Example 1, 30 chips were produced in a single batch, and 26 qualified chips with patterned metal layers were obtained, with a qualification rate of 86.67%.

[0038] Comparative Example 1 A layer of negative photoresist with a thickness of approximately 3.5 µm was spin-coated onto the chip surface at a speed of 2000 rpm. After spin-coating, a pre-bake was performed (pre-bake temperature 110℃, pre-bake time 70 s). After pre-bake, the pattern was exposed using an I-line lithography machine at an exposure dose of 150 mJ / cm². 2 After exposure, the chip is post-baked at 110°C for 70 seconds, then immersed in developer for 50 seconds to expose the pixel area, and then spun dry at 5800 rpm for 18 seconds to obtain intermediate device 1 with negative photoresist pattern.

[0039] Intermediate device 1 (with the photoresist layer facing out) is placed in a vacuum evaporation machine. First, a 100 nm thick Au metal layer is deposited at a speed of 0.7 Å / s. Then, the speed is adjusted to 1.2 Å / s to deposit a 2.9 μm thick Au metal layer. After evaporation, the chip is immersed in a photoresist remover solution at 80°C for 20 minutes. After immersion, it is cleaned with an alcohol spray gun to obtain a chip with a patterned metal layer.

[0040] Using the process of Comparative Example 1, 30 chips were produced in a single batch, and 20 qualified chips with patterned metal layers were obtained, with a qualification rate of 66.67%.

[0041] The yield rate of the chip with patterned metal layer prepared by the process in Comparative Example 1 was significantly lower than that in Example 1. Possible reasons include: when the single-layer photoresist is too thick, it is prone to collapse, and the exposure accuracy decreases. The holes generated during exposure may suffer from shrinkage and shape changes, thus affecting the metal deposition. Furthermore, the single-layer photoresist process does not allow the use of positive resist for deposition because excessive film thickness results in trapezoidal holes formed by positive resist, hindering the entry of resist stripping solution and making peeling difficult.

[0042] Example 2 (1) The process flow diagram for this step is as follows: Figure 1 As shown, a SiN layer is prepared on the chip surface by ICP-CVD deposition. x Masking layer (wherein: the process conditions for ICP-CVD deposition are: deposition temperature 80℃, ICP power 350W, SiH4 and N2 flow rates 6.8 and 6.3 mL / min respectively, deposition time 10 min, and deposition thickness 150 nm). In SiN x A 3µm thick layer of positive photoresist was spin-coated at 2500 rpm. After spin-coating, pre-baking was performed (pre-baking temperature 100℃, pre-baking time 80s). After pre-baking, the pattern was exposed using an I-line lithography machine at an exposure dose of 120mJ / cm².2 After exposure, the chip is post-baked at 100°C for 80 seconds, then immersed in developer for 60 seconds to expose the pixel area, and then spun dry at 5500 rpm for 20 seconds to obtain intermediate device 1 with positive photoresist pattern.

[0043] (2) The process flow diagram for this step is as follows: Figure 2 As shown, a SiN layer was prepared on the upper surface of the intermediate device 1 containing a positive photoresist pattern via ICP-CVD deposition. x The isolation layer (wherein: the process conditions for ICP-CVD deposition are: deposition temperature 75℃, ICP power 350W, SiH4 and N2 flow rates 6.8 and 6.3 mL / min respectively, deposition time 4 min, and deposition thickness 50 nm); in SiN x A 3µm thick layer of negative photoresist (6µm thick in the pixel area) was spin-coated onto the upper surface of the device at 2500 rpm until it was smooth. After spin-coating, a pre-bake was performed (pre-bake temperature 110℃, pre-bake time 80s). After pre-bake, the pattern was exposed using an I-line lithography machine at an exposure dose of 110mJ / cm². 2 After exposure, the chip is post-baked at 100°C for 80 seconds, then immersed in developer for 75 seconds to expose the pixel area, and then spun dry at 6000 rpm for 15 seconds to obtain intermediate device 1 with negative photoresist pattern.

[0044] (3) The process flow diagram for this step is as follows: Figure 3 As shown, the intermediate device 1 containing a negative photoresist pattern is immersed in a 45% hydrofluoric acid solution to etch the SiN on the sidewalls of the positive photoresist layer in the pixel area. x An isolation layer was etched at a rate of 250 Å / min. After etching, it was cleaned with pure water to obtain intermediate device 3.

[0045] (4) The process flow diagram for this step is as follows: Figure 4 As shown, intermediate device 3 is placed in a RIE etching machine for dry etching. The dry etching process parameters are: etching power of 120W, etching temperature of room temperature, and vacuum degree of 20mTorr; etching gases are CHF3 and O2, CHF3 flow rate of 55sccm, O2 flow rate of 8sccm, and etching time of 5min, exposing the W pillars of the pixel area; thus, intermediate device 4 is obtained.

[0046] (5) The process flow diagram for this step is as follows: Figure 5As shown, intermediate device 4 (with the photoresist layer facing out) is placed in a vacuum evaporation machine. First, an Au metal layer with a thickness of 120 nm is deposited at a speed of 0.8 Å / s. Then, the speed is adjusted to 1.5 Å / s to deposit an Au metal layer with a thickness of 4.88 μm. After the evaporation is completed, the chip is immersed in the photoresist remover solution at 85°C for 10 min. After immersion, it is cleaned with an alcohol spray gun to obtain a chip with a patterned metal layer.

[0047] Example 3 (1) The process flow diagram for this step is as follows: Figure 1 As shown, a SiNx masking layer was prepared on the chip surface using ICP-CVD deposition (wherein the ICP-CVD deposition conditions were: deposition temperature 70℃, ICP power 400W, SiH4 and N2 flow rates 7.2 and 6.7 mL / min respectively, deposition time 20 min, and deposition thickness 280 nm). x A 2µm thick layer of positive photoresist was spin-coated at 3000 rpm. After spin-coating, pre-baking was performed (pre-baking temperature 120℃, pre-baking time 60s). After pre-baking, the pattern was exposed using an I-line lithography machine at an exposure dose of 180mJ / cm². 2 After exposure, the chip is post-baked at 120°C for 60 seconds, then immersed in developer for 45 seconds to expose the pixel area, and then spun dry at 6000 rpm for 15 seconds to obtain intermediate device 1 with positive photoresist pattern.

[0048] (2) The process flow diagram for this step is as follows: Figure 2 As shown, a SiN layer was prepared on the upper surface of the intermediate device 1 containing a positive photoresist pattern via ICP-CVD deposition. x The isolation layer (wherein: the process conditions for ICP-CVD deposition are: deposition temperature 70℃, ICP power 400W, SiH4 and N2 flow rates 7.2 and 6.7 mL / min respectively, deposition time 3 min, and deposition thickness 30 nm); in SiN x A 3µm thick layer of negative photoresist (5µm thick in the pixel area) was spin-coated onto the upper surface of the device at 3000 rpm until it was smooth. After spin-coating, a pre-bake was performed (pre-bake temperature: 125℃, pre-bake time: 70s). After pre-bake, the pattern was exposed using an I-line lithography machine at an exposure dose of 180mJ / cm². 2 After exposure, the chip is post-baked at 120°C for 70 seconds, then immersed in developer for 75 seconds to expose the pixel area, and then spun dry at 5500 rpm for 20 seconds to obtain intermediate device 1 with negative photoresist pattern.

[0049] (3) The process flow diagram for this step is as follows: Figure 3 As shown, the intermediate device 1 containing a negative photoresist pattern is immersed in a 50% hydrofluoric acid solution to etch the SiN on the sidewalls of the positive photoresist layer in the pixel area. x An isolation layer was etched at a rate of 300 Å / min. After etching, the layer was cleaned with pure water to obtain intermediate device 3.

[0050] (4) The process flow diagram for this step is as follows: Figure 4 As shown, intermediate device 3 is placed in a RIE etching machine for dry etching, wherein: the process parameters for dry etching are: etching power of 140W, etching temperature of room temperature, vacuum degree of 10mTorr; etching gases are CHF3 and O2, CHF3 flow rate of 45sccm, O2 flow rate of 11sccm, etching time of 8min, exposing the W pillar of the pixel area; intermediate device 4 is obtained.

[0051] (5) The process flow diagram for this step is as follows: Figure 5 As shown, intermediate device 4 (with the photoresist layer facing out) is placed in a vacuum evaporation machine. First, an 80 nm thick Au metal layer is deposited at a speed of 0.5 Å / s. Then, the speed is adjusted to 1.1 Å / s to deposit a 3.42 μm thick Au metal layer. After evaporation, the chip is immersed in a photoresist remover solution at 70°C for 30 min. After immersion, it is cleaned with an alcohol spray gun to obtain a chip with a patterned metal layer.

[0052] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating a metal layer on a chip, characterized in that, Includes the following steps: S1: Fabrication of SiN on a chip layer x Masking layer; in SiN x A positive photoresist is spin-coated onto a masking layer, and the pixel area is exposed by exposure and development to obtain an intermediate device 1 containing a positive photoresist pattern; S2: An isolation layer is prepared on the entire surface of the intermediate device 1 with a positive photoresist pattern on the positive photoresist side; negative photoresist is spin-coated onto the isolation layer until the entire surface is flat; then the position of the pixel area is exposed by exposure and development to obtain the intermediate device 2 with a negative photoresist pattern. S3: The pixel area of ​​the intermediate device 2 containing the negative photoresist pattern is etched with acid to remove the isolation layer on the photoresist sidewall of the pixel area, thus obtaining the intermediate device 3. S4: Etch intermediate device 3 to remove SiN from the pixel area. x The masking layer is applied until the metal pillar is exposed, resulting in intermediate device 4; S5: A metal layer is deposited on the upper surface of the side containing photoresist of intermediate device 4. After the deposition is completed, the photoresist layer is wet-stripped to obtain a chip containing a metal layer.

2. The method for fabricating a metal layer on a chip according to claim 1, characterized in that, In step S1, the preparation of SiN x The masking layer was applied using ICP-CVD deposition. The specific process parameters for ICP-CVD deposition were: deposition temperature 70~80℃, working gas pressure 8~9 mtorr, ICP power 350~400W; SiH4 gas flow rate 6.8~7.2 mL / min, N2 gas flow rate 6.3~6.7 mL / min; deposition time 10~20 min; SiN... x The thickness of the masking layer is 150~280nm.

3. The method for fabricating a metal layer on a chip according to claim 1 or 2, characterized in that, In step S1, the spin coating speed is 2000~3000 rpm, the thickness of the positive photoresist is 2~3 μm, and the exposure dose is 120~180 mJ / cm. 2 After exposure, the chip is baked at 100~120℃ for 60~80s before development, which takes 45~60s.

4. The method for fabricating a metal layer on a chip according to claim 1, characterized in that, In step S2, the isolation layer is SiN. x Insulation layer, preparation of SiN x The isolation layer is prepared using ICP-CVD deposition. The specific process parameters for ICP-CVD deposition are: deposition temperature 70~80℃, working gas pressure 8~9 mtorr, ICP power 350~400W; SiH4 gas flow rate 6.8~7.2 mL / min, N2 gas flow rate 6.3~6.7 mL / min; deposition time 2~4 min; SiN... x The thickness of the isolation layer is 30~50nm.

5. The method for fabricating a metal layer on a chip according to claim 1 or 4, characterized in that, In step S2, the spin coating speed is 2000~3000 rpm, and the thickness of the negative photoresist is 2~3 μm, wherein: the thickness of the negative photoresist is calculated starting from the top surface of the isolation layer; the exposure dose is 110~180 mJ / cm. 2 After exposure, the chip is post-baked at 100~120℃ for 60~80s before development, which takes 55~75s.

6. The method for fabricating a metal layer on a chip according to claim 1, characterized in that, In step S3, the acid corrosion is carried out by immersion corrosion, the acid is hydrofluoric acid with a volume concentration of 45~50%, and the corrosion rate is 250~300 Å / min.

7. The method for fabricating a metal layer on a chip according to claim 1, characterized in that, In step S4, the etching is dry etching. The process conditions for dry etching are as follows: etching power is 120~140W, vacuum degree is 10~20mTorr; the etching gas is a mixture of CHF3 and O2, the gas flow rate of CHF3 is 45~55sccm, the gas flow rate of O2 is 8~11sccm; and the etching time is 5~8min.

8. The method for fabricating a metal layer on a chip according to claim 1, characterized in that, In step S5, the thickness of the metal layer is 3~5μm; The metal layer is an Au metal layer.

9. The method for fabricating a metal layer on a chip according to claim 1 or 8, characterized in that, In step S5, the evaporation is vacuum evaporation. During evaporation, 80-120 nm is first deposited at a speed of 0.5-0.8 Å / s, and then the speed is adjusted to 1.0-1.5 Å / s to deposit a thickness of 3-5 μm.

10. The method for fabricating a metal layer on a chip according to claim 1, characterized in that, In step S5, the wet stripping method for the photoresist layer is as follows: the chip is immersed in the photoresist remover solution to remove the photoresist, and after immersion, it is cleaned with alcohol; wherein: the immersion temperature is 70~85℃, and the immersion time is 10~30min.

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