A semiconductor structure and a method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises: a silicon carbide substrate, a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; a trench gate structure is located in the silicon carbide epitaxial layer; a shielding structure is located in the silicon carbide epitaxial layer on both sides of the trench gate structure; and a thermistor structure is located in the shielding structure. The application provides a semiconductor structure and a forming method thereof, and the thermistor structure for detecting temperature is formed in the shielding structure on both sides of the trench gate structure, so that an accurate and rapid chip temperature detection technical scheme is provided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Wide bandgap power devices, such as silicon carbide devices, have higher operating temperatures than silicon power devices, making device temperature control crucial for ensuring device lifespan and managing thermoelectric and thermal stress-related risks. Traditional chip temperature sensors, due to their distance from the chip heat source, suffer from low accuracy in detecting actual chip junction temperatures, slow response to temperature changes, and inability to provide effective protection against short-term chip overload events.

[0003] Therefore, it is necessary to provide an accurate and rapid chip temperature detection technology solution. Summary of the Invention

[0004] The purpose of this invention is to provide an accurate and rapid chip temperature detection technology solution.

[0005] One aspect of this application provides a semiconductor structure comprising: a silicon carbide substrate having a silicon carbide epitaxial layer formed on its surface; a trench gate structure located in the silicon carbide epitaxial layer; a shielding structure located in the silicon carbide epitaxial layers on both sides of the trench gate structure; and a thermistor structure located in the shielding structure.

[0006] In some embodiments of this application, the trench gate structure includes: a gate electrode and a gate dielectric layer covering the bottom and sidewalls of the gate electrode, wherein the gate dielectric layer extends to the surface of the silicon carbide epitaxial layer and covers the bottom and sidewalls of the thermistor structure.

[0007] In some embodiments of this application, a second interlayer dielectric layer is also formed on the bottom and sidewalls of the thermistor structure.

[0008] In some embodiments of this application, the depth of the thermistor structure is greater than the depth of the trench gate structure.

[0009] In some embodiments of this application, the distance between the thermistor structure and the trench gate structure is within 5 micrometers.

[0010] In some embodiments of this application, the depth of the shielding structure is 1.5 times or more the depth of the thermistor structure.

[0011] In some embodiments of this application, the material of the thermistor structure includes any one or more of polycrystalline silicon, manganese oxide, nickel oxide, cobalt oxide, and copper oxide.

[0012] Another aspect of this application provides a method for forming a semiconductor structure, comprising: providing a silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; forming a trench gate structure in the silicon carbide epitaxial layer; forming a shielding structure in the silicon carbide epitaxial layers on both sides of the trench gate structure; and forming a thermistor structure in the shielding structure.

[0013] In some embodiments of this application, the trench gate structure includes: a gate electrode and a gate dielectric layer covering the bottom and sidewalls of the gate electrode, wherein the gate dielectric layer extends to the surface of the silicon carbide epitaxial layer and covers the bottom and sidewalls of the thermistor structure.

[0014] In some embodiments of this application, a second interlayer dielectric layer is also formed on the bottom and sidewalls of the thermistor structure.

[0015] In some embodiments of this application, the depth of the thermistor structure is greater than the depth of the trench gate structure.

[0016] In some embodiments of this application, the distance between the thermistor structure and the trench gate structure is within 5 micrometers.

[0017] In some embodiments of this application, the depth of the shielding structure is 1.5 times or more the depth of the thermistor structure.

[0018] In some embodiments of this application, the material of the thermistor structure includes any one or more of polycrystalline silicon, manganese oxide, nickel oxide, cobalt oxide, and copper oxide.

[0019] This application provides a semiconductor structure and a method for forming the same, wherein a thermistor structure for detecting temperature is formed in the shielding structure on both sides of the trench gate structure, providing an accurate and fast chip temperature detection technology solution. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein: Figure 1 This is a schematic diagram of the semiconductor structure described in some embodiments of this application; Figure 2 This is a schematic diagram of the semiconductor structure described in some other embodiments of this application. Detailed Implementation

[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the semiconductor structure described in some embodiments of this application. refer to Figure 1 As shown, some embodiments of this application provide a semiconductor structure 100, including: a silicon carbide substrate 102, on which a silicon carbide epitaxial layer 103 is formed; a trench gate structure located in the silicon carbide epitaxial layer 103; a shielding structure 106 located in the silicon carbide epitaxial layers 103 on both sides of the trench gate structure; and a thermistor structure 122 located in the shielding structure 106.

[0024] In the technical solution of this application, a thermistor structure for temperature detection is formed in the shielding structure on both sides of the trench gate structure. Since the thermistor structure extends into the silicon carbide epitaxial layer, compared to typical external or surface-mounted temperature sensors, it exhibits higher accuracy and faster response speed to chip junction temperature changes. This allows users to obtain more accurate and faster chip over-temperature and over-current protection through the thermistor structure. Furthermore, some protection functions that were previously impossible due to the slow speed of temperature sensors, especially for overload events with short time constants such as short circuits and current surges, can be achieved through chip junction temperature detection in this application, providing an additional layer of protection for device reliability and lifespan.

[0025] In some embodiments of this application, the silicon carbide substrate 102 is made of silicon carbide, and the silicon carbide epitaxial layer 103 is also made of silicon carbide. In some embodiments of this application, the silicon carbide substrate 102 and the silicon carbide epitaxial layer 103 may contain doped ions, such as N-type doped nitrogen or phosphorus ions. The doping concentration of the silicon carbide substrate 102 is 1 x 10⁻⁶. 14 Up to 5x10 16 Atoms per cubic centimeter. The doping concentration of the silicon carbide epitaxial layer 103 is 1 x 103. 17 Up to 1x10 21 Atoms per cubic centimeter.

[0026] Continue to refer to Figure 1 As shown, in some embodiments of this application, a drain metal layer 132 is further formed on the back side of the silicon carbide substrate 102. The thickness of the drain metal layer 132 is 0.1 to 10 micrometers. The material of the drain metal layer 132 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The drain metal layer 132 is connected to a drain signal 132a.

[0027] Continue to refer to Figure 1 As shown, in some embodiments of this application, a first doped region 104 (or bulk doped region) and a second doped region 105 (or source doped region) are sequentially formed on the surface of the silicon carbide epitaxial layer 103. The first doped region 104 is, for example, a p-type doped region, and the doping concentration of the first doped region 104 is 1 x 10⁻⁶. 17 Up to 1x10 18 Atoms per cubic centimeter. The second doped region 105 is, for example, N-type doped, and the doping concentration of the second doped region 105 is 1 x 10⁻⁶. 18 Up to 1x10 21 Atoms per cubic centimeter.

[0028] Continue to refer to Figure 1 As shown, in some embodiments of this application, the trench gate structure includes: a gate electrode 121 and a gate dielectric layer 111 covering the bottom and sidewalls of the gate electrode 121. The gate dielectric layer 111 further extends to the surface of the silicon carbide epitaxial layer 103 and covers the bottom and sidewalls of the thermistor structure 122. The gate electrode 121 is connected to a gate signal 121a. The trench gate structure is formed in a gate trench 101a. The trench gate structure is a conventional structure in silicon carbide power devices, and its detailed structure will not be described in detail here.

[0029] Continue to refer to Figure 1 As shown, the shielding structure 106 is located in the silicon carbide epitaxial layers 103 on both sides of the trench gate structure and its depth is greater than the depth of the trench gate structure. The function of the shielding structure 106 is to provide a depletion region between itself and the silicon carbide epitaxial layer 103 when the device is turned off. The depletion region significantly reduces the electric field of the gate dielectric layer of the trench gate structure, especially at the bottom corner of the gate dielectric layer, when the device is turned off, thereby shielding the source and drain electric fields of the gate dielectric layer when the device is turned off.

[0030] In some embodiments of this application, the shielding structure 106 is, for example, p-type doped, and the doping concentration of the shielding structure 106 is 1 x 10⁻⁶. 18 Up to 1x10 21 Atoms per cubic centimeter. The depth of the shielding structure 106 is 0.5 to 5 micrometers.

[0031] Continue to refer to Figure 1 As shown, the thermistor structure 122 is located within the shielding structure 106 and does not occupy additional chip area. The thermistor structure 122 is preferably of a type that responds quickly to temperature changes, such as a negative temperature coefficient thermistor. The material of the thermistor structure 122 is, for example, a negative temperature coefficient thermistor material, such as polycrystalline silicon, or a semiconductor metal oxide such as manganese oxide, nickel oxide, cobalt oxide, copper oxide, or a combination thereof.

[0032] The technical solution of this application provides electric field protection for the trench gate structure, while also providing a temperature detection structure, namely a thermistor structure 122. The two ends of the thermistor structure 122 are connected to the positive terminal 122a and the negative terminal 122b of the thermistor.

[0033] In some embodiments of this application, the depth of the thermistor structure 122 is greater than the depth of the trench gate structure.

[0034] In some embodiments of this application, the distance between the thermistor structure 122 and the trench gate structure is within 5 micrometers. The thermistor structure 122 is disposed in the second trench 101b, within the same cell as the trench gate structure, and is very close to the sidewall of the first trench 101a, which is the main heat-generating point during chip operation. The main heat-generating point during chip operation is the channel, and in this design, the channel is located on the sidewall of the first trench 101a.

[0035] In some embodiments of this application, the depth of the shielding structure 106 is 1.5 times or more the depth of the thermistor structure 122.

[0036] Continue to refer to Figure 1 As shown, in some embodiments of this application, a first interlayer dielectric layer 112 is further formed on the silicon carbide epitaxial layer 103, covering the silicon carbide epitaxial layer 103 and the trench gate structure. A source metal layer 131 is also formed on the surface of the first interlayer dielectric layer 112, and a portion of the source metal layer 131 penetrates the first interlayer dielectric layer 112 and is electrically connected to the second doped region 105. The source metal layer 131 is connected to the source signal 131a.

[0037] Figure 2 This is a schematic diagram of the semiconductor structure described in some other embodiments of this application.

[0038] refer to Figure 2As shown, in some other embodiments of this application, a second interlayer dielectric layer 213 is further formed on the bottom and sidewalls of the thermistor structure 222. The second interlayer dielectric layer 213 extends to the surface of the silicon carbide epitaxial layer 203 and covers the gate electrode 221. The thickness of the second interlayer dielectric layer 213 is 0.1 to 10 micrometers. The material of the second interlayer dielectric layer 213 includes any one or more of silicon dioxide, doped silicon dioxide, silicon nitride, and aluminum oxide.

[0039] It should be noted that, Figure 2 and Figure 1 Apart from the differences mentioned above, the embodiments are identical in all other structures, and therefore will not be described in detail again. Figure 2 and Figure 1 The numbering in the code is the same except that the first digit is changed from 1 to 2.

[0040] The functions of the second interlayer dielectric layer 213 are as follows: First, it reduces the parasitic capacitance between the thermistor structure 222 and the shielding structure 206, reduces the capacitive coupling between the device power circuit and the temperature detection circuit, and reduces the interference of the power circuit on the temperature detection signal when the device is working; Second, since a large current will flow to the device source through the shielding structure 206 when the device undergoes avalanche breakdown, which may cause damage or even destruction to the gate dielectric layer and the thermistor structure in the second trench, the second interlayer dielectric layer helps to reduce the electric field in the gate dielectric layer in the second trench to protect the gate dielectric layer and the thermistor structure in the second trench when the device undergoes avalanche breakdown; Third, the second interlayer dielectric layer reduces the volume of the thermistor structure filling the second trench, reducing the delay in temperature detection speed or temperature detection error caused by the thermal capacitance of the thermistor structure itself.

[0041] This application provides a semiconductor structure in which a thermistor structure for temperature detection is formed in the shielding structure on both sides of the trench gate structure, providing an accurate and fast chip temperature detection technology solution.

[0042] This application also provides a method for forming the semiconductor structure 100, see reference. Figure 1 As shown, the method includes: providing a silicon carbide substrate 102, on the surface of which a silicon carbide epitaxial layer 103 is formed; forming a trench gate structure in the silicon carbide epitaxial layer 103; forming a shielding structure 106 in the silicon carbide epitaxial layer 103 on both sides of the trench gate structure; and forming a thermistor structure 122 in the shielding structure 106.

[0043] Since the structure of the semiconductor structure 100 has been described in detail above, the structure will not be described again in the method section. Only the formation process of the semiconductor structure 100 will be briefly described.

[0044] refer to Figure 1 As shown, a silicon carbide substrate 102 is provided, and a silicon carbide epitaxial layer 103 is formed on the surface of the silicon carbide substrate 102; a first doped region 104 and a second doped region 105 are sequentially formed by ion implantation; a shielding structure 106 is formed by ion implantation; a first trench 101a and a second trench 102b are formed; a gate dielectric layer 111 is formed; a gate electrode 121 and a thermistor structure 122 are formed; a first interlayer dielectric layer 112 is formed; a source metal layer 131 is formed; and a drain metal layer 132 is formed.

[0045] refer to Figure 2 As shown, with Figure 1 The difference in the formation method of the structure shown is that after forming the gate electrode 221, an additional process is added to form the second interlayer dielectric layer 213, and then the thermistor structure 222 is formed.

[0046] This application provides a semiconductor structure and a method for forming the same, wherein a thermistor structure for detecting temperature is formed in the shielding structure on both sides of the trench gate structure, providing an accurate and fast chip temperature detection technology solution.

[0047] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0048] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "comprise," or "including" as used in this application specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0049] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0050] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, include: A silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; A trench gate structure is located in the silicon carbide epitaxial layer; The shielding structure is located in the silicon carbide epitaxial layers on both sides of the trench gate structure; A thermistor structure is located within the shielding structure.

2. The semiconductor structure as described in claim 1, characterized in that, The trench gate structure includes a gate electrode and a gate dielectric layer covering the bottom and sidewalls of the gate electrode. The gate dielectric layer also extends to the surface of the silicon carbide epitaxial layer and covers the bottom and sidewalls of the thermistor structure.

3. The semiconductor structure as described in claim 1, characterized in that, A second interlayer dielectric layer is also formed on the bottom and sidewalls of the thermistor structure.

4. The semiconductor structure as described in claim 1, characterized in that, The depth of the thermistor structure is greater than the depth of the trench gate structure.

5. The semiconductor structure as described in claim 1, characterized in that, The distance between the thermistor structure and the trench gate structure is within 5 micrometers.

6. The semiconductor structure as described in claim 1, characterized in that, The depth of the shielding structure is 1.5 times or more the depth of the thermistor structure.

7. The semiconductor structure as described in claim 1, characterized in that, The materials used in the thermistor structure include any one or more of polycrystalline silicon, manganese oxide, nickel oxide, cobalt oxide, and copper oxide.

8. A method for forming a semiconductor structure, characterized in that, include: A silicon carbide substrate is provided, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; A trench gate structure is formed in the silicon carbide epitaxial layer; A shielding structure is formed in the silicon carbide epitaxial layers on both sides of the trench gate structure; A thermistor structure is formed in the shielding structure.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The trench gate structure includes a gate electrode and a gate dielectric layer covering the bottom and sidewalls of the gate electrode. The gate dielectric layer also extends to the surface of the silicon carbide epitaxial layer and covers the bottom and sidewalls of the thermistor structure.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, A second interlayer dielectric layer is also formed on the bottom and sidewalls of the thermistor structure.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The depth of the thermistor structure is greater than the depth of the trench gate structure.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The distance between the thermistor structure and the trench gate structure is within 5 micrometers.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The depth of the shielding structure is 1.5 times or more the depth of the thermistor structure.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, The materials used in the thermistor structure include any one or more of polycrystalline silicon, manganese oxide, nickel oxide, cobalt oxide, and copper oxide.

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