Method of manufacturing zero layer alignment marks
By forming a first mask layer on a semiconductor substrate and filling trenches, the problem of poor topography of the zero-layer alignment mark is solved, and the topography of the zero-layer alignment mark is well maintained and the contrast is improved, thereby enhancing the alignment capability of subsequent layers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-02
AI Technical Summary
The existing zero-layer alignment marker has a poor morphology, which leads to a decrease in the alignment capability of subsequent layers and poor contrast.
A first mask layer is formed on a semiconductor substrate. After photolithography defines the alignment mark area, a first trench is etched and filled with a first material layer of different materials. The surface is flattened by CMP. The mask layer is then removed and epitaxial growth is performed to form a flat epitaxial layer to maintain the morphology of the zero-layer alignment mark and to improve contrast through differences in material optical properties.
Maintaining a good morphology for the zero-layer alignment marker and improving contrast enhances the alignment capability of subsequent layers.
Smart Images
Figure CN122138711A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing a zero-layer alignment mark. Background Technology
[0002] With the advancement of technology nodes, the number of lithography layers has increased significantly, and the process has become more complex, placing higher demands on overlay accuracy and stability. Among these, the overlay accuracy from the active area (AA) to the zero layer (ZERO) is the foundation for subsequent layers, and it is necessary to control the stability between lots.
[0003] In some processes where the well region is implanted with ions before alignment (AA), a zero-order layer is required as the first layer to align the well and AA in subsequent layers. The morphology of the zero-order alignment markers directly affects the alignment capability of subsequent layers.
[0004] The ZERO marks currently in use are affected by processes such as thin film, resulting in poor morphology and contrast of the aligned marks.
[0005] like Figure 1 The diagram shown is a flowchart of an existing method for manufacturing zero-layer alignment markers; as shown... Figures 2 to 7 The diagram shown is a schematic representation of the device structure in each step of a conventional method for manufacturing a zero-layer alignment mark. The conventional method for manufacturing a zero-layer alignment mark includes the following steps: Step S101, as follows Figure 2 As shown, a silicon substrate 101 is provided, and a zero-layer oxide layer 102 and a zero-layer silicon nitride layer 103 are formed on the silicon substrate 101.
[0006] exist Figure 1 In step S101, Oxide & Nitride are also used, where Oxide represents the zero-layer oxide layer 102 and Nitride represents the zero-layer silicon nitride 103.
[0007] Step S102, as follows Figure 3 As shown, photolithography (PH) defines the formation area for the zero-layer alignment mark.
[0008] exist Figure 1 In step S102, ZERO-PH is also used, which means performing photolithography to define the formation area of the zero-layer alignment mark, where PH is the abbreviation for photolithography.
[0009] Step S103, as follows Figure 3As shown, the zero-layer silicon nitride 103, the zero-layer oxide layer 102, and the silicon substrate 101 in the formation region of the zero-layer alignment mark are etched (ET) to form trenches 104.
[0010] exist Figure 1 In step S103, ZERO-ET is also used, which means etching the area for forming the zero-layer alignment mark, where ET is an abbreviation for photolithography.
[0011] Step S104, as follows Figure 4 As shown, the zero-layer silicon nitride 103 is removed.
[0012] exist Figure 1 In step S104, SIN remove is also used, where remove means to remove.
[0013] Step S105, as follows Figure 5 As shown, the zero oxide layer 102 is removed.
[0014] exist Figure 1 In the text, step S105 is also represented by OX remove, where OX is short for Oxide.
[0015] Step S106: Perform well implantation to form a well region in the silicon substrate 101.
[0016] exist Figure 1 In step S106, WELL is also used, where WELL represents the well region. The well-related processes need to be configured according to the process requirements of each node. The formation process of the well region is achieved through a well ion implantation (WELL IMP) process loop (lopp).
[0017] Step S107, as follows Figure 6 As shown, a silicon epitaxial layer 105 is formed on the surface of the silicon substrate 101 outside the first material layer 105 by silicon epitaxy (Si EPI).
[0018] Depend on Figure 6 As shown, both the silicon substrate 101 and the silicon epitaxial layer 105 are composed of silicon material. The final morphology of the silicon trench is determined after the silicon epitaxial layer 105 is formed in the trench 104. As shown by the dashed circle 106, the morphology of the trench is changed. The final silicon trench serves as the zero-layer alignment mark, so the morphology of the zero-layer alignment mark is changed.
[0019] Step S108, as follows Figure 7 As shown, an active area (AA) padding layer (PAD) 107 is formed. In Figure 1 In this context, step S108 is also represented by AA PAD DEP. DEP stands for deposition.
[0020] Typically, the active region pad 107 comprises stacked silicon oxide pads and silicon nitride pads.
[0021] After forming the active region cushion layer 107, the following is also included: An active region hard mask layer (HM) is formed on the top surface of the active region pad 107.
[0022] Active region lithography is performed, and the zero-layer alignment mark is used for alignment during active region lithography.
[0023] like Figure 8 The diagram shown is a schematic of the device structure when the zero-layer alignment mark formed by the existing zero-layer alignment mark manufacturing method is aligned with the next layer of photolithography. Figure 8 In this process, both the silicon substrate 101 and the silicon epitaxial layer 105 are made of silicon and are represented by the same pattern. After the film layer 108 is formed, the alignment mark 109 for the next layer of photolithography will be formed. Since the zero-layer alignment mark in the dashed coil 106 has a poor morphology, it will affect the alignment capability of the next layer of photolithography.
[0024] like Figure 9 As shown, it is and Figure 8 A schematic diagram of the device structure when aligning the zero-layer alignment mark with the better morphology for the next layer of photolithography. Figure 9 In the process, when the zero-layer alignment mark is not changed, the side morphology of the corresponding silicon trench remains the same as during etching, as shown by dashed circle 106'. Summary of the Invention
[0025] The technical problem to be solved by the present invention is to provide a method for manufacturing a zero-layer alignment mark, which can maintain the good morphology of the zero-layer alignment mark and improve the contrast of the zero-layer alignment mark.
[0026] To solve the above-mentioned technical problems, the manufacturing method of the zero-layer alignment mark provided by the present invention includes the following steps: A semiconductor substrate is provided, and a zero-layer first mask layer is formed on the semiconductor substrate.
[0027] Photolithography defines the area for forming the zero-layer alignment mark.
[0028] The zero-layer first mask layer and the semiconductor substrate are etched to form a first trench in the formation area of the zero-layer alignment mark; the first trench is formed by superimposing a bottom trench in the semiconductor substrate and a top trench in the zero-layer first mask layer.
[0029] A first material layer is formed, which completely fills the first trench and extends to the surface of the zero-layer first mask layer outside the first trench; the material of the first material layer is different from the material of the zero-layer first mask layer, and the material of the first material layer is different from the material of the semiconductor substrate, thus creating a difference in optical properties to increase the contrast of the zero-layer alignment mark.
[0030] CMP is performed to remove the first material layer outside the first trench and to make the top surface of the first material layer inside the first trench flush with the top surface of the zero layer first mask layer.
[0031] Remove the zero-layer first mask layer.
[0032] An epitaxial growth is performed to form a first epitaxial layer on the surface of the semiconductor substrate outside the first material layer. The top surface of the first epitaxial layer is flush with the top surface of the first material layer. The zero-layer alignment mark is formed by the first material layer and the bottom trench together. During the epitaxial growth, the top surface of the first material layer is flat, thereby maintaining the morphology of the zero-layer alignment mark.
[0033] A further improvement is that the semiconductor substrate is made of silicon.
[0034] A further improvement is that, after forming the zero-layer first mask layer, the method further includes: A second mask layer is formed on the top surface of the first mask layer, and the material of the second mask layer is different from that of the first mask layer.
[0035] The first trench also penetrates the zero-layer second mask layer.
[0036] The CMP also removes the zero-layer second mask layer.
[0037] A further improvement is that the material of the zero-layer second mask layer is the same as the material of the first material layer.
[0038] A further improvement is that the material of the zero-layer first mask layer includes silicon oxide.
[0039] A further improvement is that the material of the first material layer includes silicon nitride.
[0040] A further improvement is that, after removing the zero-layer first mask layer and before forming the first epitaxial layer, the process further includes: Well implantation is performed to form a well region in the semiconductor substrate.
[0041] A further improvement is that, after the first epitaxial layer is formed, it also includes: An active region pad is formed on the surface of the first epitaxial layer and the first material layer.
[0042] Active region lithography is performed, and the zero-layer alignment mark is used for alignment during active region lithography.
[0043] A further improvement is that the growth thickness of the zero-layer first mask layer is set according to the thickness of the subsequent first epitaxial layer, so as to ensure that the top surface of the first epitaxial layer and the top surface of the first material layer are flush after the first epitaxial layer is formed.
[0044] A further improvement is that the width of the first trench is less than twice the growth thickness of the first material layer.
[0045] A further improvement is that the material of the first epitaxial layer includes silicon.
[0046] A further improvement is that the active region pad layer includes stacked silicon oxide pad layer and silicon nitride pad layer.
[0047] A further improvement is that, after forming the active region pad, the method further includes: An active region hard mask layer is formed on the top surface of the active region pad.
[0048] A further improvement is that the optical parameters include refractive index and extinction coefficient.
[0049] In this invention, after forming trenches in the semiconductor substrate, the trenches are not directly used as zero-layer alignment marks. Instead, after forming the first trench and before removing the zero-layer first mask layer, a first material layer is formed to completely fill the first trench. CMP (Continuous Metallurgy) is then used to make the top surface of the first material layer flush with the top surface of the zero-layer first mask layer outside the first trench. Afterward, the zero-layer first mask layer is removed, and a first epitaxial layer is grown. Since the epitaxial growth process does not grow an epitaxial layer on the top surface of the first mask layer, this invention maintains the top surface of the zero-layer first mask layer as a flat surface after CMP. Furthermore, by adjusting the epitaxial growth, the top surface of the first epitaxial layer is made flush with the top surface of the zero-layer first mask layer. Therefore, the surface of subsequent film layers after the formation of the first epitaxial layer is also flat, unlike existing methods where a recessed structure appears at the top of the first trench. Thus, this invention maintains a good morphology for the zero-layer alignment mark, significantly improving its morphology compared to existing methods. Furthermore, this invention can adjust the material of the first material layer based on the difference in optical properties between the material and the semiconductor substrate, thereby improving the contrast of the zero-layer alignment mark. Attached Figure Description
[0050] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of the existing method for manufacturing zero-layer alignment marks; Figures 2-7 This is a schematic diagram of the device structure in each step of the existing zero-layer alignment mark manufacturing method; Figure 8 This is a schematic diagram of the device structure when the zero-layer alignment mark formed by the existing zero-layer alignment mark manufacturing method is aligned with the next layer of photolithography. Figure 9 Is and Figure 8 A schematic diagram of the device structure when aligning the zero-layer alignment mark with the better morphology for the next layer of photolithography. Figure 10 It is a photograph of a zero-layer alignment mark formed by an existing zero-layer alignment mark manufacturing method; Figure 11 This is a flowchart of the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention; Figure 12 This is a flowchart of a preferred embodiment of the manufacturing method of the zero-layer alignment mark of the present invention; Figures 13-19 This is a schematic diagram of the device structure in each step of the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention; Figure 20 This is a schematic diagram of the structure of a zero-layer alignment mark formed by the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention; Figure 21 This is a photograph of a zero-layer alignment mark formed by the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention. Detailed Implementation
[0051] like Figure 11 The diagram shown is a flowchart of a method for manufacturing a zero-layer alignment mark according to an embodiment of the present invention. Figure 12 This is a flowchart of a preferred embodiment of the manufacturing method of the zero-layer alignment mark of the present invention; as shown below. Figures 13 to 19 The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention; the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention includes the following steps: Step S201, as follows Figure 13 As shown, a semiconductor substrate 201 is provided and a zero-layer first mask layer 202 is formed on the semiconductor substrate 201.
[0052] In this embodiment of the invention, the semiconductor substrate 201 is a wafer structure. Since no pattern has been formed on the wafer, it is a bare wafer.
[0053] In this embodiment of the invention, the growth thickness of the zero-layer first mask layer 202 is set according to the thickness of the subsequent first epitaxial layer 206, so as to ensure that the top surface of the first epitaxial layer 206 and the top surface of the first material layer 205 are flush after the first epitaxial layer 206 is formed.
[0054] The semiconductor substrate 201 is made of silicon.
[0055] After forming the zero-layer first mask layer 202, the method further includes: A second mask layer 203 is formed on the top surface of the first mask layer 202, and the material of the second mask layer 203 is different from that of the first mask layer 202.
[0056] In a preferred embodiment, the material of the zero-layer first mask layer 202 includes silicon oxide.
[0057] The material of the first material layer 205 includes silicon nitride.
[0058] exist Figure 12 In the preferred embodiment shown, step S201 is also represented by Oxide & Nitride, where Oxide represents the zero-layer first mask layer 202 and Nitride represents the zero-layer second mask layer 203.
[0059] Step S202, as follows Figure 14 As shown, photolithography defines the formation area of the zero-layer alignment mark.
[0060] exist Figure 12 In the preferred embodiment shown, step S202 is also represented by ZERO-PH, which means performing photolithography to define the formation area of the zero-layer alignment mark, where PH is an abbreviation for photolithography.
[0061] In this embodiment of the invention, the area where the zero-layer alignment mark is formed is also the area where the first trench 204 is formed subsequently. The width of the first trench 204 is less than twice the growth thickness of the first material layer 205 formed subsequently.
[0062] Step S203, as follows Figure 14 As shown, the zero-layer first mask layer 202 and the semiconductor substrate 201 in the formation area of the zero-layer alignment mark are etched to form a first trench 204; the first trench 204 is formed by superimposing a bottom trench located in the semiconductor substrate 201 and a top trench located in the zero-layer first mask layer 202.
[0063] In this embodiment of the invention, the first trench 204 also passes through the zero-layer second mask layer 203, and the etching process involves first etching the zero-layer second mask layer 203 and then etching the zero-layer first mask layer 202.
[0064] exist Figure 12 In the preferred embodiment shown, step S203 is also represented by ZERO-ET, which means etching the formation area of the zero-layer alignment mark, where ET is an abbreviation for photolithography.
[0065] Step S204, as Figure 15 As shown, a first material layer 205 is formed, which completely fills the first trench 204 and extends to the surface of the zero-layer first mask layer 202 outside the first trench 204; the material of the first material layer 205 is different from the material of the zero-layer first mask layer 202, and the material of the first material layer 205 is different from the material of the semiconductor substrate 201, thus creating a difference in optical properties to increase the contrast of the zero-layer alignment mark.
[0066] In this embodiment of the invention, the optical parameters include refractive index (n) and extinction coefficient (k).
[0067] In this embodiment of the invention, the material of the zero-layer second mask layer 203 is the same as the material of the first material layer 205.
[0068] In this embodiment of the invention, the growth thickness of the first material layer 205 is greater than 1 / 2 of the width of the first trench 204, so as to ensure that the first trench 204 is completely filled.
[0069] In a preferred embodiment, the material of the first material layer 205 is silicon nitride.
[0070] exist Figure 12 In the preferred embodiment shown, step S204 is also represented by Nitride Dep, where Dep means deposition, i.e., deposition of silicon nitride.
[0071] Step S205, as follows Figure 16 As shown, CMP is performed to remove all the first material layers 205 outside the first trench 204 and to make the top surface of the first material layer 205 inside the first trench 204 flush with the top surface of the zero layer first mask layer 202.
[0072] In this embodiment of the invention, the CMP also simultaneously removes the zero-layer second mask layer 203. The CMP can be completed by stopping at the zero-layer first mask layer 202.
[0073] exist Figure 12 In the preferred embodiment shown, step S205 is also represented by Nitride CMP, which means performing CMP on silicon nitride to simultaneously perform CMP on the zero-layer second mask layer 203 and the first material layer 205.
[0074] Step S206, as follows Figure 17 As shown, the zero-layer first mask layer 202 is removed.
[0075] exist Figure 12 In the preferred embodiment shown, step S206 is also represented by OX remove, where OX represents the oxide layer, i.e., the silicon oxide material layer of the zero layer first mask layer 202, and remove means to remove.
[0076] In this embodiment of the invention, after removing the zero-layer first mask layer 202 and before forming the first epitaxial layer 206, and before performing step S206 and subsequent step S207, the method further includes: Step S301: Perform well implantation to form a well region in the semiconductor substrate 201.
[0077] exist Figure 12 In the preferred embodiment shown, step S301 is also represented by WELL, where WELL represents the well region.
[0078] Step S207, as follows Figure 18 As shown, an epitaxial layer 206 is formed on the surface of the semiconductor substrate 201 outside the first material layer 205. The top surface of the first epitaxial layer 206 is flush with the top surface of the first material layer 205. The zero-layer alignment mark is formed by the first material layer 205 and the bottom trench. The top surface of the first material layer 205 is flat during the epitaxial growth, thereby maintaining the good morphology of the zero-layer alignment mark.
[0079] In this embodiment of the invention, the material of the first epitaxial layer 206 includes silicon.
[0080] In this embodiment of the invention, after the first epitaxial layer 206 is formed, the method further includes: like Figure 19 As shown, in step S208, an active region (AA) pad (PAD) 207 is formed on the surface of the first epitaxial layer 206 and the first material layer 205. Figure 12 In the preferred embodiment shown, step S208 is also represented by AA PAD DEP.
[0081] In this embodiment of the invention, the active region pad 207 includes a superimposed silicon oxide pad and a silicon nitride pad.
[0082] After forming the active region cushion layer 207, the following is also included: An active region hard mask layer (HM) is formed on the top surface of the active region pad 207.
[0083] Active region lithography is performed, and the zero-layer alignment mark is used for alignment during active region lithography.
[0084] In this embodiment of the invention, after forming trenches in the semiconductor substrate 201, the trenches are not directly used as zero-layer alignment marks. Instead, after forming the first trench 204 and before removing the zero-layer first mask layer 202, a first material layer 205 is formed to completely fill the first trench 204. CMP is then used to make the top surface of the first material layer 205 flush with the top surface of the zero-layer first mask layer 202 outside the first trench 204. Afterward, the zero-layer first mask layer 202 is removed, and a first epitaxial layer 206 is epitaxially grown. Since the epitaxial growth process does not grow an epitaxial layer on the top surface of the first mask layer, this embodiment of the invention can maintain the top surface of the zero-layer first mask layer 202 as a CMP mark. The flat surface after P and the adjustment of epitaxial growth to make the top surface of the first epitaxial layer 206 and the top surface of the zero layer first mask layer 202 flat, so the surface of the subsequent film layer after the formation of the first epitaxial layer 206 is also flat, and there will be no recessed structure at the top of the first trench 204 as in the existing method. Therefore, the embodiment of the present invention can maintain the morphology of the zero layer alignment mark well. Compared with the existing method, the morphology of the zero layer alignment mark in the embodiment of the present invention is greatly improved. The embodiment of the present invention can also set the material of the first material layer 205 according to the difference in optical index between the material and the semiconductor substrate 201, so it can also improve the contrast of the zero layer alignment mark.
[0085] like Figure 20 The diagram shown is a structural schematic of a zero-layer alignment mark formed by the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention. Figure 20 In the diagram, both the semiconductor substrate 201 and the first epitaxial layer 206 are made of silicon and are represented by the same color. It can be seen that the first material layer 205 is completely located within the silicon trench, the sides of the silicon trench are vertical, and the morphology is good. Figure 20 The morphology of silicon trenches and Figure 9 The morphology of the silicon trenches corresponding to the well-defined zero-layer alignment markers is similar, thus avoiding... Figure 8 The existing method forms a zero-layer alignment mark with an arc-shaped side surface of the silicon trench. Furthermore, in this embodiment, the material of the first material layer 205 is specially configured to have excellent contrast with the surrounding silicon material. Figure 21 This is a photograph of a zero-layer alignment mark formed by the manufacturing method of the zero-layer alignment mark according to an embodiment of the present invention.
[0086] This invention improves the morphology and contrast of the zero-layer alignment mark by optimizing the ZERO loop process, thereby enhancing the alignment capability of subsequent layers.
[0087] The characteristic of the process in this embodiment of the invention is the adjustment of the Zero Oxidation thickness and CD size. After Zero-ET, a material with significantly different optical properties (n,k values) from silicon is used to fill the Zero mark trench (i.e., the first trench), and thin film deposition is used to merge the Zero marks. CMP polishing removes the Nitride from the silicon oxide surface, and a wet process removes the Oxide. Because the Nitride mark has already formed, silicon epitaxial deposition only grows on the silicon, without damaging the original good morphology of the mark.
[0088] This invention optimizes the ZERO loop process by filling the ZERO alignment mark with Nitride for protection, thereby improving the morphology of the alignment mark. The significant difference in refractive index between the filled Nitride and the silicon material further enhances the mark's contrast, ultimately improving subsequent layer alignment capabilities.
[0089] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method for manufacturing a zero-layer alignment mark, characterized in that, Including the following steps: A semiconductor substrate is provided, and a zero-layer first mask layer is formed on the semiconductor substrate; Photolithography defines the area for forming the zero-layer alignment mark; The zero-layer first mask layer and the semiconductor substrate in the formation region of the zero-layer alignment mark are etched to form a first trench; The first trench is formed by superimposing a bottom trench located in the semiconductor substrate and a top trench located in the zero-layer first mask layer; A first material layer is formed, which completely fills the first trench and extends to the surface of the zero layer first mask layer outside the first trench; The material of the first material layer is different from the material of the zero-layer first mask layer, and the material of the first material layer is different from the material of the semiconductor substrate, thus creating a difference in optical properties to increase the contrast of the zero-layer alignment mark; CMP is performed to remove the first material layer outside the first trench and to make the top surface of the first material layer inside the first trench flush with the top surface of the zero layer first mask layer; Remove the zero-layer first mask layer; An epitaxial growth is performed to form a first epitaxial layer on the surface of the semiconductor substrate outside the first material layer. The top surface of the first epitaxial layer is flush with the top surface of the first material layer. The zero-layer alignment mark is formed by the first material layer and the bottom trench together. During the epitaxial growth, the top surface of the first material layer is flat, thereby maintaining the morphology of the zero-layer alignment mark.
2. The method for manufacturing the zero-layer alignment mark as described in claim 1, characterized in that: The semiconductor substrate is made of silicon.
3. The method for manufacturing the zero-layer alignment mark as described in claim 2, characterized in that, After forming the zero-layer first mask layer, the process further includes: A second mask layer is formed on the top surface of the first mask layer, and the material of the second mask layer is different from that of the first mask layer. The first trench also penetrates the zero-layer second mask layer; The CMP also removes the zero-layer second mask layer.
4. The method for manufacturing the zero-layer alignment mark as described in claim 3, characterized in that: The material of the second mask layer in the zero layer is the same as the material of the first material layer.
5. The method for manufacturing a zero-layer alignment mark as described in claim 4, characterized in that: The material of the zero-layer first mask layer includes silicon oxide.
6. The method for manufacturing a zero-layer alignment mark as described in claim 5, characterized in that: The material of the first material layer includes silicon nitride.
7. The method for manufacturing a zero-layer alignment mark as described in claim 1, characterized in that: After removing the zero-layer first mask layer and before forming the first epitaxial layer, the method further includes: Well implantation is performed to form a well region in the semiconductor substrate.
8. The method for manufacturing a zero-layer alignment mark as described in claim 7, characterized in that, After the first epitaxial layer is formed, the following is also included: An active region pad is formed on the surface of the first epitaxial layer and the first material layer; Active region lithography is performed, and the zero-layer alignment mark is used for alignment during active region lithography.
9. The method for manufacturing a zero-layer alignment mark as described in claim 3, characterized in that: The growth thickness of the zero-layer first mask layer is set according to the thickness of the subsequent first epitaxial layer to ensure that the top surface of the first epitaxial layer is flush with the top surface of the first material layer after the first epitaxial layer is formed.
10. The method for manufacturing a zero-layer alignment mark as described in claim 3, characterized in that: The width of the first trench is less than twice the growth thickness of the first material layer.
11. The method for manufacturing a zero-layer alignment mark as described in claim 2, characterized in that: The material of the first epitaxial layer includes silicon.
12. The method for manufacturing a zero-layer alignment mark as described in claim 8, characterized in that: The active region padding layer includes stacked silicon oxide padding layer and silicon nitride padding layer.
13. The method for manufacturing a zero-layer alignment mark as described in claim 12, characterized in that: After forming the active region cushion layer, the following is also included: An active region hard mask layer is formed on the top surface of the active region pad.
14. The method for manufacturing a zero-layer alignment mark as described in claim 1, characterized in that: The optical parameters include refractive index and extinction coefficient.