Tmr-based radiation-hardened circuit

Abstract

The application discloses a kind of anti-radiation reinforcement circuits based on TMR, including input unit, latching unit and two-out-of-three voting unit, input unit is for the input signal IN being divided into three paths respectively to reverse processing, output three reverse signals;Latching unit is for one of reverse signal is latched and is handled, and two other reverse signals are handled using double interlocking structure, output three latching signals;Two-out-of-three voting unit is for selecting the same two or three signals from three latching signals as voting result, obtains reinforcement output signal.In the application, latching unit is handled using conventional latching structure and double interlocking structure respectively, output three latching signals, the effect of anti-radiation reinforcement is good, and circuit structure is simple, occupies small area, and reduce power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a radiation hardening circuit based on TMR. Background Technology

[0002] As integrated circuit process dimensions continue to shrink and operating voltages decrease, modern electronic systems are becoming increasingly sensitive to single-event effects induced by space particle radiation. Single-event upsets and single-event transients are among the most common forms of soft errors, which can lead to abnormal storage cell states or glitches in combinational logic, severely impacting the functional correctness and data integrity of electronic systems in fields such as space, aviation, nuclear industry, and high-reliability ground applications.

[0003] To ensure the reliability of electronic systems in high-radiation environments, the industry has developed various radiation hardening technologies, mainly including process-level hardening, circuit-level hardening, and system-level hardening. Among them, TMR, as a classic system-level fault-tolerant technology, is widely used in high-reliability circuit design because its design is relatively independent of the process and its reliability is significantly improved.

[0004] Traditional TMR technology masks errors occurring on a single path by replicating critical circuit modules three times and introducing a majority voter to decide the three outputs. Even if only one of the three modules produces an erroneous output due to radiation effects, the voter can still output the correct result, theoretically reducing the system's soft error rate by one to two orders of magnitude. However, this design incurs significant overhead in terms of area and power consumption. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a radiation hardening circuit based on TMR.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A radiation hardening circuit based on TMR, including The input unit is used to reverse the three input signals respectively and output three reverse signals; the three reverse signals are the first reverse signal T1, the second reverse signal T2 and the third reverse signal T3 respectively. The latch unit is used to latch one inverted signal and to latch the other two inverted signals using a double interlocking structure, outputting three latch signals: a first latch signal S1, a second latch signal S2, and a third latch signal S3. The three-out-of-two voting unit is used to select the same two or three signals from three latched signals as the voting result to obtain a reinforced output signal.

[0007] Furthermore, the input unit includes three input inverters, the input terminal of each input inverter is connected to an input signal IN, and the output terminal of each input inverter is used to output an inverted signal.

[0008] Furthermore, the latching unit includes The first latch circuit is used to latch the input first inverted signal T1 and output the first latch signal S1; and The second latch circuit is used to latch the input second inverted signal T2 and the third inverted signal T3 respectively using a double interlock structure, and output the second latch signal S2 and the third latch signal S3.

[0009] Furthermore, the first latch circuit includes a latch inverter and an AND gate. The first input terminal of the AND gate and the output terminal of the latch inverter are electrically connected and serve as the input terminal of the first latch circuit for inputting the first inverted signal T1. The second input terminal of the AND gate is used to connect to the set signal RSTN. The output terminal of the AND gate and the input terminal of the latch inverter are electrically connected and serve as the output terminal of the first latch circuit for outputting the first latch signal S1.

[0010] Furthermore, the second latching circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to an external voltage VDD; The gate of the second PMOS transistor is electrically connected to the drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the fourth NMOS transistor, and the gate of the eighth NMOS transistor, respectively, and serves as the first input terminal of the second latch circuit for receiving the second inverting signal T2; the gate of the third PMOS transistor is electrically connected to the drain of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the first NMOS transistor, and the gate of the fifth NMOS transistor, respectively, and serves as the first input terminal of the second latch circuit for outputting the second latch signal S2; The gate of the fourth PMOS transistor is electrically connected to the drain of the third PMOS transistor, the drain of the third NMOS transistor, the gate of the second NMOS transistor, and the gate of the sixth NMOS transistor, respectively, and serves as the second input terminal of the second latch circuit for receiving the third inverted signal T3; the gate of the first PMOS transistor is electrically connected to the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, the gate of the third NMOS transistor, and the gate of the seventh NMOS transistor, respectively, and serves as the second input terminal of the second latch circuit for outputting the third latch signal S3; The source of the first NMOS transistor is electrically connected to the drain of the fifth NMOS transistor; the source of the second NMOS transistor is electrically connected to the drain of the sixth NMOS transistor; the source of the third NMOS transistor is electrically connected to the drain of the seventh NMOS transistor; the source of the fourth NMOS transistor is electrically connected to the drain of the eighth NMOS transistor; and the sources of the fifth, sixth, seventh, and eighth NMOS transistors are all grounded.

[0011] Furthermore, the three-out-of-two voting unit includes The low-level voting circuit is used to output a high-level signal when at least two of the three latched signals are low. A high-level voting circuit is used to output a low-level signal when at least two of the three latched signals are high; and The output inverter has its input terminals electrically connected to the output terminals of the low-level voting circuit and the high-level voting circuit, respectively, and its output terminal serves as the first output terminal of the three-out-of-two voting unit to output a reinforced output signal.

[0012] Furthermore, the low-level voting circuit includes three first voting units connected in series, wherein the first terminal of the first-level first voting unit is connected to the external voltage VDD, and the second terminal is electrically connected to the first terminal of the second-level first voting unit; the second terminal of the second-level first voting unit is electrically connected to the first terminal of the third-level first voting unit, and the second terminal of the third-level first voting unit serves as the output terminal of the low-level voting circuit. The three latch signals are divided into three groups of two, with each first voting unit corresponding to one group of latch signals. The first voting unit is used to access two latch signals in the same group and is turned on when both latch signals are low.

[0013] Furthermore, the first voting unit includes two parallel fifth PMOS transistors. The sources of the two fifth PMOS transistors are electrically connected to form the first terminal of the first voting unit, and the drains of the two fifth PMOS transistors are electrically connected to form the second terminal of the first voting unit. The gates of the two fifth PMOS transistors are respectively used as the two input terminals of the first voting unit. The two latch signals of each group are respectively electrically connected to the two input terminals of the corresponding first voting unit.

[0014] Furthermore, the high-level voting circuit includes three second voting units connected in parallel. The first terminals of the three second voting units are electrically connected to each other and serve as the output terminals of the high-level voting circuit. The second terminals of the three second voting units are all grounded. The three latch signals are divided into three groups of two, and each second voting unit corresponds to one group of latch signals. The second voting unit is used to access two latch signals in the same group and is turned on when both latch signals are high.

[0015] Furthermore, the second voting unit includes a ninth NMOS transistor and a tenth NMOS transistor connected in series; the drain of the ninth NMOS transistor serves as the first terminal of the second voting unit, and the source is electrically connected to the drain of the tenth NMOS transistor, with the source of the tenth NMOS transistor serving as the second terminal of the second voting unit; the gates of the ninth and tenth NMOS transistors serve as the two input terminals of the second voting unit, respectively.

[0016] In this invention, the improved DICE circuit is combined with the traditional TMR structure to achieve SEU hardening. It can resist single-event upsets based on the input tri-modal redundancy signal, and can still output correctly even if an error occurs in one path, demonstrating good radiation hardening effect. Furthermore, it requires no additional control clock or other signal read / write inputs, resulting in a simple circuit structure and small footprint. In addition, the 3-out-of-2 voting unit in this embodiment only uses 12 MOSFETs to achieve the 3-out-of-2 voting function, further simplifying the circuit structure, reducing the footprint, and lowering power consumption. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a block diagram of the input module in a traditional triple-redundant architecture.

[0018] Figure 2 This is a block diagram of a traditional three-modal redundancy voting module.

[0019] Figure 3 This is a structural block diagram of an embodiment of the radiation hardening circuit based on TMR of the present invention.

[0020] Figure 4 This is the circuit diagram for the second latch circuit.

[0021] Figure 5 This is the circuit diagram for the two-out-of-three voting unit.

[0022] The diagrams in the instruction manual are labeled as follows: Input unit 100; latch unit 200; first latch circuit 210; second latch circuit 220; three-out-of-two voting unit 300; low-level voting circuit 310; high-level voting circuit 320. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] Triple Modular Redundancy (TMR) is a classic fault-tolerant design technique for high-reliability digital systems. Its core idea is to mask single points of failure through spatial redundancy and majority voting. The TMR circuit architecture achieves ultra-high reliability through a "two-out-of-three" voting mechanism, a system-level fault-tolerant architecture. It trades significant hardware resource overhead for perfect masking of single points of failure, making it one of the cornerstone technologies for building fault-tolerant computing systems. Its basic principle involves using three identical modules to perform the same computation, and a majority voter decides the three outputs. The final output is determined by the majority vote. As long as no more than one of the three modules fails (produces an incorrect output), the voter will give the correct result.

[0025] Please see Figure 1 This is a traditional triple-modular redundancy input module, consisting of three identical input units: Input Unit 1, Input Unit 2, and Input Unit 3. Each input unit includes four inverters and one two-terminal AND gate, requiring a total of 12 inverters and 3 AND gates for the input module.

[0026] The input signal IN1 is copied three times and sent to three input units respectively. The IN1 signal from input unit 1 enters inverter INV10 and outputs signal E; signal E is connected to the input of inverter INV12, outputting signal G; signal E is also connected to the input of a two-terminal AND gate NAND10, outputting signal F; signal E is also connected to the output of inverter INV11, and signal F is connected to the inputs of inverter INV11 and inverter INV13 respectively, outputting signal H. Input units 2 and 3 have the same structure and principle as input unit 1. Input unit 2 outputs signals G1 and H1, and input unit 3 outputs signals G2 and H2.

[0027] Please see Figure 2 This is a traditional triple-redundant voting module, consisting of two conventional 2-out-of-3 voting circuits, namely Voter 1 and Voter 2. Each 2-out-of-3 voting circuit includes three two-terminal AND gates and one three-terminal AND gate, for a total of six two-terminal AND gates and two three-terminal AND gates in the voting module.

[0028] The output signals of input unit 1, input unit 2, and input unit 3 are respectively connected to the input terminals of voter 1 and voter 2. For voter 1, signal G and signal G1 are connected to the two input terminals of two-terminal input AND gate NAND20, and the output is connected to the first input terminal of three-terminal input AND gate NAND23; signal G and signal G2 are connected to the two input terminals of two-terminal input AND gate NAND21, and the output is connected to the second input terminal of three-terminal input AND gate NAND23; signal G1 and signal G2 are connected to the two input terminals of two-terminal input AND gate NAND22, and the output is connected to the third input terminal of three-terminal input AND gate NAND23; the output terminal of three-terminal input AND gate NAND23 is the output OUT_G of voter 1; the structure of voter 2 is the same as that of voter 1.

[0029] The traditional triple-modal redundancy architecture offers high fault tolerance, effectively shielding against single-event upsets (SEUs), transient faults, and permanent failures of individual modules (before redundancy is exhausted). It provides real-time fault tolerance; fault shielding is performed online and in real-time, eliminating the need for detection, diagnosis, and recovery time, resulting in zero latency impact on system performance. However, the costs are also significant, including: an increase in area exceeding 200%, requiring three times the hardware resources (including logic gates and registers); an increase in power consumption exceeding 200%, with power consumption at least three times higher when all three modules operate simultaneously. Furthermore, it increases design complexity, requiring strict synchronization of the three modules (clock, input delays); otherwise, voting errors may occur due to metastability or time races. Placement and routing become more complex.

[0030] Please see Figure 3 , Figure 3 This is a structural block diagram of an embodiment of the radiation hardening circuit based on TMR according to the present invention. The radiation hardening circuit based on TMR in this embodiment includes an input unit 100, a latch unit 200, and a 3-out-of-2 voting unit 300. The input unit 100 is used to invert three input signals respectively, outputting three inverted signals; the three input signals are obtained by splitting the same input signal IN into three paths. The three inverted signals are a first inverted signal T1, a second inverted signal T2, and a third inverted signal T3.

[0031] The input unit 100 generally includes three input inverters. The input terminal of each input inverter is connected to an input signal IN, and the output terminal of each input inverter is used to output an inverted signal. In this embodiment, the three input inverters are inverter INV1, inverter INV2, and inverter INV3. Inverter INV1 outputs a first inverted signal T1, inverter INV2 outputs a second inverted signal T2, and inverter INV3 outputs a third inverted signal T3.

[0032] The latch unit 200 is used to latch one of the inverted signals and to latch the other two inverted signals using a double interlocking structure, correspondingly outputting three latched signals. The three latched signals are a first latched signal S1, a second latched signal S2, and a third latched signal S3. In this embodiment, the latch unit 200 includes a first latch circuit 210 and a second latch circuit 220. The first latch circuit 210 is used to latch the input first inverted signal T1 and output the first latched signal S1; the second latch circuit 220 is used to latch the input second inverted signal T2 and the third inverted signal T3 using a double interlocking structure, and output the second latched signal S2 and the third latched signal S3.

[0033] Please continue reading. Figure 3 The first latch circuit 210 can employ a feedback loop circuit formed by an inverter INV4 (i.e., a latch inverter) and an AND gate NAND. Specifically, the first input terminal of the AND gate NAND and the output terminal of the inverter INV4 are electrically connected and serve as the input terminal of the first latch circuit 210 for inputting the first inverted signal T1; the second input terminal of the AND gate NAND is used to connect to the set signal RSTN, and the output terminal of the AND gate NAND and the input terminal of the inverter INV4 are electrically connected and serve as the output terminal of the first latch circuit 210 for outputting the first latch signal S1.

[0034] Please see Figure 4 The second latch circuit 220 may include a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor, which form two opposite feedback loops. In this embodiment, the first PMOS transistor is P1, the second PMOS transistor is P2, the third PMOS transistor is P3, and the fourth PMOS transistor is P4; the first NMOS transistor is N1, the second NMOS transistor is N2, the third NMOS transistor is N3, the fourth NMOS transistor is N4, the fifth NMOS transistor is N5, the sixth NMOS transistor is N6, the seventh NMOS transistor is N7, and the eighth NMOS transistor is N8.

[0035] The sources of PMOS transistors P1, P2, P3, and P4 are all connected to an external voltage VDD. The gate of PMOS transistor P2 is electrically connected to the drain of PMOS transistor P1, the drain of NMOS transistor N1, the gate of NMOS transistor N4, and the gate of NMOS transistor N8, forming node A. Node A serves as the first input terminal of the second latch circuit 220 for receiving the second inverted signal T2. The gate of PMOS transistor P3 is electrically connected to the drain of PMOS transistor P2, the drain of NMOS transistor N2, the gate of NMOS transistor N1, and the gate of NMOS transistor N5, forming node B. Node B serves as the first input terminal of the second latch circuit 220 for outputting the second latch signal S2.

[0036] The gate of PMOS transistor P4 is electrically connected to the drain of PMOS transistor P3, the drain of NMOS transistor N3, the gate of NMOS transistor N2, and the gate of NMOS transistor N6 to form node C. Node C serves as the second input terminal of the second latch circuit 220 for receiving the third inverted signal T3. The gate of PMOS transistor P1 is electrically connected to the drain of PMOS transistor P4, the drain of NMOS transistor N4, the gate of NMOS transistor N3, and the gate of NMOS transistor N7 to form node D. Node D serves as the second input terminal of the second latch circuit 220 for outputting the third latch signal S3.

[0037] The source of NMOS transistor N1 is electrically connected to the drain of NMOS transistor N5; the source of NMOS transistor N2 is electrically connected to the drain of NMOS transistor N6; the source of NMOS transistor N3 is electrically connected to the drain of NMOS transistor N7; and the source of NMOS transistor N4 is electrically connected to the drain of NMOS transistor N8. The sources of NMOS transistors N5, N6, N7, and N8 are all grounded.

[0038] Compared to conventional DICE circuits, this embodiment eliminates the write WL signal, output BL and BLN signals, and the MOS transistors controlled by these signals. The improved DICE structure in this embodiment directly writes the input signal to nodes A and C and outputs it from nodes B and D, and also has the ability to correct one erroneous input.

[0039] Please see Figure 5 The two-out-of-three voting unit 300 is used to select two or three identical signals from three latched signals as the voting result to obtain a reinforced output signal. The two-out-of-three voting unit 300 may include a low-level voting circuit 310, a high-level voting circuit 320, and an inverter INV5 (i.e., an output inverter).

[0040] The low-level voting circuit 310 outputs a high-level signal when at least two of the three latched signals are low; the high-level voting circuit 320 outputs a low-level signal when at least two of the three latched signals are high. The input of the inverter INV5 is electrically connected to the outputs of the low-level voting circuit 310 and the high-level voting circuit 320, respectively, and its output serves as the first output of the two-out-of-three voting unit 300 to output the reinforced output signal OUT1. Alternatively, the input of the inverter INV5 can also serve as the second output of the two-out-of-three voting unit 300 to output the inverted output signal OUT2.

[0041] The low-level voting circuit 310 may include three first voting units connected in series. The first terminal of the first-level first voting unit is connected to an external voltage VDD, and the second terminal is electrically connected to the first terminal of the second-level first voting unit. The second terminal of the second-level first voting unit is electrically connected to the first terminal of the third-level first voting unit, and the second terminal of the third-level first voting unit serves as the output terminal of the low-level voting circuit 310.

[0042] The three latch signals are divided into three groups of two. In this embodiment, the first latch signal S1 and the second latch signal S2 form the first group, the first latch signal S1 and the third latch signal S3 form the second group, and the second latch signal S2 and the third latch signal S3 form the third group. Each of the first voting units corresponds to one group of latch signals. The first voting unit is used to access two latch signals from the same group and is turned on when both latch signals are low.

[0043] The first voting unit may include two parallel fifth PMOS transistors. The sources of the two fifth PMOS transistors are electrically connected to form the first terminal of the first voting unit, and the drains of the two fifth PMOS transistors are electrically connected to form the second terminal of the first voting unit. The gates of the two fifth PMOS transistors serve as the two input terminals of the first voting unit, respectively. The two latch signals of each group are electrically connected to the two input terminals of the corresponding first voting unit, respectively.

[0044] Specifically, the two fifth PMOS transistors of the first voting unit of the first stage are PMOS transistor P5 and PMOS transistor P6. The sources of PMOS transistor P5 and PMOS transistor P6 are electrically connected and serve as the first terminal of the first voting unit of the first stage, which is connected to the external voltage VDD. The gates of PMOS transistor P5 and PMOS transistor P6 are respectively connected to the first latch signal S1 and the second latch signal S2.

[0045] The two fifth PMOS transistors in the second-stage first voting unit are PMOS transistor P7 and PMOS transistor P8. The sources of PMOS transistors P7 and P8 are electrically connected and then used as the first terminal of the second-stage first voting unit, which is connected to the drains of PMOS transistors P5 and P6. The gates of PMOS transistors P7 and P8 are respectively connected to the first latch signal S1 and the third latch signal S3.

[0046] The two fifth PMOS transistors in the first voting unit of the third stage are PMOS transistor P9 and PMOS transistor P10. The sources of PMOS transistors P9 and P10 are electrically connected and then connected to the drains of PMOS transistors P7 and P8 as the first terminal of the first voting unit of the third stage. The gates of PMOS transistors P9 and P10 are connected to the second latch signal S2 and the third latch signal S3, respectively. The drains of PMOS transistors P9 and P10 are electrically connected to the input terminal of inverter INV5.

[0047] The high-level voting circuit 320 includes three parallel-connected second voting units. The first terminals of the three second voting units are electrically connected to each other and serve as the output terminals of the high-level voting circuit 320. The second terminals of the three second voting units are all grounded. Each second voting unit corresponds to a set of latch signals. The second voting unit is used to access two latch signals from the same set and is turned on when both latch signals are high.

[0048] The second voting unit may include a ninth NMOS transistor and a tenth NMOS transistor connected in series. The drain of the ninth NMOS transistor serves as the first terminal of the second voting unit, and its source is electrically connected to the drain of the tenth NMOS transistor. The source of the tenth NMOS transistor serves as the second terminal of the second voting unit. The gates of the ninth and tenth NMOS transistors serve as the two input terminals of the second voting unit, respectively.

[0049] Specifically, the ninth NMOS transistors of the three second voting units are NMOS transistors N11, N13, and N15, respectively, and the tenth NMOS transistors of the three second voting units are NMOS transistors N12, N14, and N16, respectively. The gates of NMOS transistors N11 and N12 are connected to the first latch signal S1 and the second latch signal S2, respectively; the gates of NMOS transistors N13 and N14 are connected to the first latch signal S1 and the third latch signal S3, respectively; and the gates of NMOS transistors N15 and N16 are connected to the second latch signal S2 and the third latch signal S3, respectively.

[0050] In this embodiment, the improved 3-out-of-2 voting unit 300 is composed of 12 MOS transistors, while the existing conventional voting unit includes two voters, each of which includes 4 AND gates. Each AND gate requires at least 4 MOS transistors, so the existing conventional voting unit requires at least 32 MOS transistors. It can be seen that the voting unit of this embodiment greatly reduces the number of MOS transistors, which is beneficial to the miniaturization of the device.

[0051] The working principle of this embodiment is as follows: Please see Figures 3 to 5 Since the circuits of inverters INV1, INV2, and INV3 are completely identical, under normal circumstances, their output signals (i.e., the first inverted signal T1, the second inverted signal T2, and the third inverted signal T3) are also completely identical. The first inverted signal T1 is latched by the latching circuit composed of inverter INV4 and NAND gate, and outputs the first latched signal S1.

[0052] The second inverting signal T2 and the third inverting signal T3 are connected to the improved DICE structure (i.e., the second latch circuit 220), respectively, and are connected to nodes A and C, respectively, and output the second latch signal S2 and the third latch signal S3. When the second latch circuit 220 is in the off state, when subjected to particle impact, such as when NMOS transistors N1 and N5 are bombarded, PMOS transistor P1 will temporarily be in the on state. At this time, the potential of node A will switch to a high level "1", then PMOS transistor P2 will be turned off, and NMOS transistors N4 and N8 will be turned on. PMOS transistors P2, NMOS transistors N2 and NMOS transistors N6 connected to node B will all be in the off state, so the potential of node B always remains at a high potential "1". The on state of NMOS transistors N4 and N8 pulls node D to a low potential "0", causing NMOS transistors N3 and N7 to turn off. At this time, PMOS transistors P3, NMOS transistors N3 and N7 connected to node C are all off, so node C remains at a low potential "0". Therefore, it can be seen that the potentials of A and D will flip, but the potentials of nodes B and C will not flip.

[0053] When the particle bombardment ends and the node state recovers, NMOS transistors N4 and N8 are turned off, and the entire DICE structure returns to its initial state. Similarly, when other individual nodes in the DICE structure are bombarded, the circuit will eventually return to its original stored state. Therefore, the DICE structure has a certain degree of immunity to the flipping of individual nodes.

[0054] The first latch signal S1, the second latch signal S2, and the third latch signal S3 output by latch unit 200 are connected to the input of the three-out-of-two voting unit 300. The low-level voting circuit 310 provides multiple channels for the low-level logic path, namely: P5-P7-P9, P5-P7-P10, P5-P8-P9, P5-P8-P10, P6-P8-P9, P6-P8-P10, P6-P7-P9, and P6-P7-P10. When two of the first latch signal S1, the second latch signal S2, and the third latch signal S3 are low, or all of them are low, at least one low-level logic path will be activated, allowing the external voltage VDD to be connected to the input of inverter INV5. In other words, the low-level voting circuit 310 votes on two or more low levels and outputs a high level.

[0055] The high-level voting circuit 320 provides three channels for the high-level logic path, namely three second voting units: N11-N12, N21-N22, and N31-N32. When only one of the first latch signal S1, the second latch signal S2, and the third latch signal S3 is low (i.e., there are two high levels) or there is no low level (i.e., all are high levels), at least one second voting unit will be turned on, thereby connecting the input of the inverter INV5 to ground GND through the second voting unit. That is, the high-level voting circuit 320 votes on two or more high levels and outputs a low level.

[0056] The radiation-hardened circuit structure of this embodiment improves the DICE circuit and combines it with the traditional TMR structure to achieve radiation hardening. It can resist single-event upsets based on the input three-mode redundancy signal, and can still output correctly even if an error occurs in one path, resulting in good radiation hardening effect. Furthermore, it does not require an additional control clock or other signal read / write inputs, resulting in a simple circuit structure and small footprint. In addition, the 3-out-of-2 voting unit 300 of this embodiment only uses 12 MOSFETs to achieve the 3-out-of-2 voting function, further simplifying the circuit structure, reducing the footprint, and lowering power consumption.

[0057] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A radiation hardening circuit based on TMR, characterized in that: include The input unit is used to reverse the three input signals respectively and output three reverse signals; the three reverse signals are the first reverse signal T1, the second reverse signal T2 and the third reverse signal T3 respectively. The latch unit is used to latch one of the inverted signals and to latch the other two inverted signals using a double interlocking structure, and outputs three latch signals accordingly; the three latch signals are the first latch signal S1, the second latch signal S2 and the third latch signal S3. as well as The three-out-of-two voting unit is used to select the same two or three signals from three latched signals as the voting result to obtain a reinforced output signal.

2. The radiation hardening circuit based on TMR as described in claim 1, characterized in that: The input unit includes three input inverters. The input terminal of each input inverter is connected to an input signal IN, and the output terminal of each input inverter is used to output an inverted signal.

3. The radiation hardening circuit based on TMR as described in claim 1, characterized in that: The latching unit includes The first latch circuit is used to latch the input first inverted signal T1 and output the first latch signal S1; and The second latch circuit is used to latch the input second inverted signal T2 and the third inverted signal T3 respectively using a double interlock structure, and output the second latch signal S2 and the third latch signal S3.

4. The radiation hardening circuit based on TMR as described in claim 3, characterized in that: The first latch circuit includes a latch inverter and an AND gate. The first input terminal of the AND gate and the output terminal of the latch inverter are electrically connected and serve as the input terminal of the first latch circuit for inputting a first inverted signal T1. The second input terminal of the AND gate is used to connect a set signal RSTN. The output terminal of the AND gate and the input terminal of the latch inverter are electrically connected and serve as the output terminal of the first latch circuit for outputting a first latch signal S1.

5. The radiation hardening circuit based on TMR as described in claim 3, characterized in that: The second latching circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to an external voltage VDD; The gate of the second PMOS transistor is electrically connected to the drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the fourth NMOS transistor, and the gate of the eighth NMOS transistor, respectively, and serves as the first input terminal of the second latch circuit for receiving the second inverting signal T2; the gate of the third PMOS transistor is electrically connected to the drain of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the first NMOS transistor, and the gate of the fifth NMOS transistor, respectively, and serves as the first input terminal of the second latch circuit for outputting the second latch signal S2; The gate of the fourth PMOS transistor is electrically connected to the drain of the third PMOS transistor, the drain of the third NMOS transistor, the gate of the second NMOS transistor, and the gate of the sixth NMOS transistor, respectively, and serves as the second input terminal of the second latch circuit for receiving the third inverted signal T3; the gate of the first PMOS transistor is electrically connected to the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, the gate of the third NMOS transistor, and the gate of the seventh NMOS transistor, respectively, and serves as the second input terminal of the second latch circuit for outputting the third latch signal S3; The source of the first NMOS transistor is electrically connected to the drain of the fifth NMOS transistor; the source of the second NMOS transistor is electrically connected to the drain of the sixth NMOS transistor; the source of the third NMOS transistor is electrically connected to the drain of the seventh NMOS transistor; the source of the fourth NMOS transistor is electrically connected to the drain of the eighth NMOS transistor; and the sources of the fifth, sixth, seventh, and eighth NMOS transistors are all grounded.

6. The radiation hardening circuit based on TMR as described in any one of claims 1 to 5, characterized in that: The three-out-of-two voting unit includes The low-level voting circuit is used to output a high-level signal when at least two of the three latched signals are low. A high-level voting circuit is used to output a low-level signal when at least two of the three latched signals are high; and The output inverter has its input terminals electrically connected to the output terminals of the low-level voting circuit and the high-level voting circuit, respectively, and its output terminal serves as the first output terminal of the three-out-of-two voting unit to output a reinforced output signal.

7. The radiation hardening circuit based on TMR as described in claim 6, characterized in that: The low-level voting circuit includes three first voting units connected in series. The first terminal of the first-level first voting unit is connected to the external voltage VDD, and the second terminal is electrically connected to the first terminal of the second-level first voting unit. The second terminal of the second-level first voting unit is electrically connected to the first terminal of the third-level first voting unit, and the second terminal of the third-level first voting unit serves as the output terminal of the low-level voting circuit. The three latch signals are divided into three groups of two, with each first voting unit corresponding to one group of latch signals. The first voting unit is used to access two latch signals in the same group and is turned on when both latch signals are low.

8. The radiation hardening circuit based on TMR as described in claim 7, characterized in that: The first voting unit includes two parallel fifth PMOS transistors. The sources of the two fifth PMOS transistors are electrically connected to form the first terminal of the first voting unit, and the drains of the two fifth PMOS transistors are electrically connected to form the second terminal of the first voting unit. The gates of the two fifth PMOS transistors are respectively used as the two input terminals of the first voting unit. The two latch signals of each group are respectively electrically connected to the two input terminals of the corresponding first voting unit.

9. The radiation hardening circuit based on TMR as described in claim 6, characterized in that: The high-level voting circuit includes three second voting units connected in parallel. The first ends of the three second voting units are electrically connected to each other and serve as the output end of the high-level voting circuit. The second ends of the three second voting units are all grounded. The three latch signals are divided into three groups of two, and each second voting unit corresponds to one group of latch signals. The second voting unit is used to access two latch signals in the same group and is turned on when both latch signals are high.

10. The radiation hardening circuit based on TMR as described in claim 9, characterized in that: The second voting unit includes a ninth NMOS transistor and a tenth NMOS transistor connected in series; the drain of the ninth NMOS transistor serves as the first terminal of the second voting unit, and the source of the ninth NMOS transistor is electrically connected to the drain of the tenth NMOS transistor, with the source of the tenth NMOS transistor serving as the second terminal of the second voting unit; the gates of the ninth and tenth NMOS transistors serve as the two input terminals of the second voting unit, respectively.

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