Overhanging buffer stackable chiplets on glass core

Abstract

This application discloses overhanging cache stacked chiplets on glass core. A three-dimensional L3 cache producing overhanging cache chiplet architecture. Examples stack cache dies on caches in a system die and hybrid bond (HB) them together, producing a "T" shaped assembly attached to a glass core interposer via a field of solder microbumps. The coefficient of thermal expansion (CTE) of the glass core interposer can be tailored in an application specific manner.

Description

Background Technology

[0001] It is well known that large caches can provide significant performance gains for semiconductor systems and packages. However, the scaling of monolithic static random-access memory (SRAM) has not kept pace with the scaling of other standard cell logic components. Since some small chips can contain more than 50% SRAM in area, improvements in SRAM density and its integration with logic are desired. Attached Figure Description

[0002] Figure 1A This is a comparison table showing various caching architectures.

[0003] Figure 1B This is a simplified cross-sectional illustration of hybrid bonding in a dangling cache chip according to the various embodiments described herein.

[0004] Figure 2 This is a simplified cross-sectional illustration of a dangling cache chiplet architecture in a semiconductor system according to various embodiments.

[0005] Figure 3 The various stages of fabrication of the dangling cache chiplet architecture according to various embodiments are described.

[0006] Figures 4-5 The various stages of fabrication of the glass core and organic substrate for a suspended cache chiplet architecture according to various embodiments are described.

[0007] Figure 6 The assembly stages for implementing the dangling cache architecture according to various embodiments are described.

[0008] Figure 7 The figures illustrate example methods for a dangling cache architecture according to various embodiments.

[0009] Figure 8 The figures illustrate example methods for glass core substrate architectures according to various embodiments.

[0010] Figure 9 It is a top view of a wafer and die that may be included in a microelectronic assembly, according to any of the embodiments disclosed herein.

[0011] Figure 10 This is a simplified cross-sectional side view illustrating an implementation of an integrated circuit according to any of the embodiments disclosed herein, situated on a die that may be included in the various embodiments.

[0012] Figure 11 It may be a cross-sectional side view of a microelectronic component that may include any of the embodiments disclosed herein.

[0013] Figure 12 It may be a block diagram of an example electrical device that may include any of the embodiments disclosed herein. Detailed Implementation

[0014] It is well known that large caches can provide significant performance gains for semiconductor systems and devices. However, the scaling of monolithic static random-access memory (SRAM) has not kept pace with the scaling of other standard cell logic components. Some small chips can contain more than 50% SRAM in area. Large two-dimensional (2D) cache architectures mean larger chips / dies, and since chip / die yields are somewhat proportional to their size, large 2D caches can reduce yields, which can increase wafer / chip costs. Additionally, making the L3 cache larger in two dimensions means greater distances across the cache, which increases cache latency and may therefore actually hinder performance gains in the compute engine.

[0015] Several die-stacking solutions have been introduced to address the aforementioned technical challenges; however, each available die-stacking solution involves associated trade-offs, not limited to power delivery versus cooling, as discussed in... Figure 1A The tables shown and discussed are as follows.

[0016] The embodiments described herein provide technical solutions to these technical challenges in the form of a suspended cache chiplet architecture. The embodiments stack cache dies and employ hybrid bonding (HB), also known as hybrid bonding interconnect (HBI) or direct bond interconnect (DBI). HBI is a packaging technology that involves bonding the surfaces of two semiconductor devices together under applied pressure and / or elevated temperatures, typically as a die-stacking solution, resulting in dielectric-to-dielectric bonding and metal-to-metal bonding. HBI advantageously achieves “small” pitch (defined herein as less than 10 micrometers + / - 10%, and in some cases, less than 1 micrometer + / - 10%). The embodiments of the suspended cache chiplet are fabricated to be attached to a glass core interposer via a solder microbump field. The coefficient of thermal expansion (CTE) of the glass core interposer / substrate can be customized in an application-specific manner. These concepts will be elaborated in more detail below.

[0017] The following description of exemplary embodiments is in conjunction with the accompanying drawings, in which similar reference numerals denote similar elements. Unless otherwise stated, the drawings are not necessarily to scale but may rely on the spatial orientation and relative positioning of features. As will be appreciated, certain terms such as “ceiling” and “floor,” and “upper,” “top,” “lower,” “above,” “below,” “bottom,” and “top” refer to orientation based on observation of the drawings referenced. Furthermore, terms such as “front,” “rear,” “rear,” “side,” “vertical,” and “horizontal” may describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, which becomes clear by referring to the text describing the component in question and the associated drawings. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0018] As used herein, the term “adjacent” refers to layers or components that are in direct physical contact with each other without any layers or components in between. For example, layer X adjacent to layer Y is a layer that is in direct physical contact with layer Y. Conversely, as used herein, the phrase “on top of” (or, in the context of a first layer or component located on a second layer or component, “below,” “above,” or “next to”) includes (i) a configuration in which the first layer or component is directly and physically attached to the second layer (i.e., adjacent), and (ii) a component and configuration in which the first layer or component is attached (e.g., coupled) to the second layer or component via one or more intermediate layers or components.

[0019] The following detailed description is not intended to limit the application and use of the disclosed technology. It will be apparent that novel embodiments can be implemented without every detail described herein. For brevity, well-known structures and devices are shown in block diagram form to facilitate the description of these structures and devices.

[0020] Figure 1AA comparison of architectures for including large L3 caches in multi-die components or systems is provided. The folded core architecture places the CPU die on top of the cache die, with the cache die attached to a silicon interposer. This folded core architecture makes cooling the CPU easy, but delivering power to the cache and CPU through the silicon interposer is difficult. The folded cache architecture places the cache die on top of the CPU die, with the CPU die attached to a silicon interposer. This folded cache architecture makes cooling the CPU a difficult task because it is covered by the cache, but delivering power to the cache and CPU through the silicon interposer presents a moderate challenge. The V-cache architecture attaches the CPU die and cache die side-by-side to a silicon interposer, and then places another cache die on top of the cache die, and a dummy die on top of the CPU die to achieve a consistent top surface. This V-cache architecture makes cooling the CPU slightly easier, with moderate difficulty, but delivering power to the cache and CPU through the silicon interposer is easier than the first two architectures described.

[0021] The rightmost embodiment of the dangling cache architecture differs from the first three embodiments in several ways. First, the total amount of system cache is divided between two dies, where cache dies are stacked and co-bonded to the cache within the system die. Additionally, the embodiment utilizes a glass core interposer / substrate; the glass core interposer / substrate has cavities formed in its upper surface to accommodate or partially enclose the stacked cache dies. The core of the system die, or CPU, is located outside and adjacent to the stacked cache. This embodiment facilitates CPU cooling because the CPU is exposed, and power delivery to the cache and CPU via the glass core interposer is easy. The embodiment is a three-dimensional cache via cache stacking and advantageously delivers lower memory latency. Embodiments of the dangling cache architecture are described in more detail in the following discussion.

[0022] Go to Figure 1B The dangling cache chiplet architecture (also known as dangling cache architecture 100) includes a system die 101 and a dangling cache 102 die (the dangling cache 102 is sometimes referred to as a stacked cache). An exemplary system die 101 includes a first core 106, a second core 110, and a first cache 108 sandwiched between the first core 106 and the second core 110 in the XY plane (in other words, as shown, they are not stacked in the Z direction, but rather...). Figure 1B (The cores are positioned side-by-side from left to right in the X direction). This is a non-limiting example; in other embodiments, there may be only one core, more than two cores, one or more cores, etc.

[0023] Core 106 and Core 110 can be unpackaged integrated circuit dies and may be alternatively referred to as chips, chiplets, chiplet complexes, or chiplet complexes. While the terms die, chip, and chiplet are used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a subset of the functions of a larger integrated circuit component. Chipslets can vary depending on their type / function (e.g., computing, memory, I / O, power management (i.e., controlling power delivery and / or providing power to components)).

[0024] The suspended cache architecture 100 has a first surface 111 (shown as the upper surface in the figure) and a second surface 109 (shown as the lower surface in the figure). Electronic communication between core 106, core 110, cache 108, and cache 102 is facilitated by electronic pathways in the respective components.

[0025] In various embodiments, the attachment method for cache 108 to stacked or dangling cache 102 may be hybrid bonding (HB), first-level interconnect thermal compression bonding (TCB) microspheres, or electroplating.

[0026] In some embodiments, the dangling cache 102 is hybrid-bonded (HB) along an HB interface 103 shared between two cache dies. The HB interface 103 includes: a region of insulating material on a second surface 109 (corresponding to the cache 108 on the system die 101), having a plurality of HB contacts 104-1; and another matching region of insulating material in the stacked cache die 102, having an additional plurality of HB contacts 104-2. At the HB interface 103, the HB contacts 104-1 / 104-2 are exposed on their respective surfaces, and the dielectric is also exposed; in other words, at the HB interface, the respective surfaces have a dielectric material adjacent to the metal / Cu hybrid-bonded contacts.

[0027] HB contact 104-1 and HB contact 104-2 may be metal and may include copper. In various embodiments, at least one hybrid bonding contact 104-1 and at least one hybrid bonding contact 104-2 are exposed at the HB interface 103.

[0028] The insulating material can be any dielectric material, such as suitable nitrides or oxides, such as silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicon glass, which is a material comprising silicon, oxygen, and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material comprising fluorine, silicon, and oxygen), and hydrogen-doped silicon dioxide (H-doped SiO2, which is a material comprising silicon, oxygen, and hydrogen). In some embodiments, the dielectric layer comprises a photo-imageable dielectric (PID). In some embodiments, the dielectric layer comprises an Ajinomoto build-up film (commonly referred to as ABF), which is a material comprising an organic resin matrix comprising different types of fillers (e.g., different sizes of silicon dioxide fillers or different sizes of hollow fillers) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk) and / or dissipation factor (insertion loss) (Df)). In other embodiments, the dielectric material can be any type of epoxy molding compound.

[0029] Accordingly, at the HB interface 103, the insulating or dielectric material of buffer 108 and the insulating or dielectric material of buffer 102 are bonded together (e.g., in the SEM image, the dielectric material SiO2 will be visible). x To SiO x SiO x N y To SiO x N y (etc.), and HB contact 104-1 is bonded to HB contact 104-2. There is no solder material at HB interface 103.

[0030] In some embodiments, the HBI contact portion may be 10 micrometers, while in other embodiments, the HB contact portion may be 2 micrometers. The HBI pitch may be less than 25 micrometers. In a non-limiting example, the HB pitch ranges from 1 to 10 micrometers (inclusive).

[0031] The embodiment forms a "T"-shaped assembly attached to a glass core interlayer via a solder micro-bump field. At the second surface 109 and outside the buffer(s), the first core 106 and the second core 110 include corresponding micro-bump conductive contact fields, as illustrated generally by shaded areas 112-1 and 112-2. Additionally, the surface 105 of the suspended buffer die 102 includes a micro-bump conductive contact field, as illustrated generally by shaded area 112-3.

[0032] The spacing of the microbumps is larger than the spacing of the hybrid bonded interconnect (HBI) contacts. The microbump fields corresponding to the shaded regions 112-1, 112-2, and 112-3 can have solder bump pitch (BP) (commonly referred to as "fine pitch") ranging from 25 micrometers to 55 micrometers plus or minus 10%. In some scenarios, fine pitch BP can be 10 micrometers plus or minus 10%. Alternatively, BP can be "coarse pitch," which refers to a pitch ≥90 micrometers plus or minus 10%.

[0033] Figure 2 This is a simplified cross-sectional view of a pendant cache assembly 200 (sometimes simply referred to as "cache assembly" below) including a pendant cache architecture 100 / 202 attached to the upper surface of the glass core 204. The cache assembly 200 also has an organic building block layer 206 on the lower surface of the glass core 204, and solder bumps 208 on the lower surface of the organic building block layer 206. Molded / underfill (MUF 210) material surrounds the pendant cache architecture 100 / 202 on the upper surface of the glass core 204.

[0034] A dielectric layer 220 may be applied to the upper surface of the glass core 204. An underfill material 210 may surround a suspended buffer 216 within the cavity.

[0035] Figure 3 The various stages of manufacturing the dangling cache architecture 202 are described, and Figure 7 The diagram illustrates a method 700 for manufacturing a suspended architecture 202. At 702, a wafer 300, including cache dies, is tested, and individual known good cache dies are diced to become the final stacked cache 216 dies. Also at 702, a wafer 302 of system dies 101 / 304 is tested, and known good system dies 101 / 304 are selected.

[0036] At 704, stacked cache 216 dies are co-bonded to cache 214 of system die 304, resulting in Example 306. At 706, a seed layer 312 is overlaid on Example 306, resulting in Example 310. Also at 706, photoresist 316 is patterned on the seed layer 312, resulting in Example 314.

[0037] At 708, the photoresist is exposed, then copper is deposited, and the photoresist is removed, resulting in Example 320 with copper bumps. The photoresist is stripped, and the seed layer is removed in an etching process. Example 320 also shows that at 710, the copper bumps are electroplated with solder. At 712, the copper and solder bumps are exposed to heat to allow the solder to reflow, resulting in Example 330, which is similar to the overhanging cache architecture 202.

[0038] Figures 4-5 The various stages of fabrication for the glass core 204 / 402 and the organic substrate or building layer 206 used in the suspended buffer assembly 200 are depicted. Figure 6 The process of attaching a dangling cache architecture 202 to a glass interposer / substrate is depicted, and Figure 8 The diagram illustrates a method 800 for manufacturing a glass core 204 / 402, an attached dangling buffer architecture 202, and producing the final product.

[0039] At 802, the glass layer to be the glass core 204 / 402 is patterned using TGV 404, and a cavity 406 is formed therein. The glass core 204 / 402 may comprise a glass layer (as used herein, the glass may be an alkali-free alkaline earth borosilicate glass, such as a glass comprising aluminum, oxygen, boron, silicon, and alkaline earth metals (e.g., beryllium, magnesium, calcium, strontium, barium, radium), such as a glass comprising SiO2, Al2O3, B2O3, and MgO) or a photosensitive glass (photoprocessable or photostructureable glass). In some embodiments, the photosensitive glass may be a lithium silicate-based glass (e.g., a glass comprising lithium, silicon, and oxygen) comprising metal particles, such as gold, silver, or other suitable metal particles. The glass core 204 / 402 may have a CTE in the range of 2-20 ppm / K. In some embodiments, it is advantageous for glass layer 402 to have a CTE that matches the CTE of the intended dies 106 and 110 in the assembled product. In various embodiments, dies 106 and 110 are integrated circuit dies (e.g., matching the CTE of silicon) or have a CTE that matches the substrate or PCB.

[0040] In some embodiments, glass core 204 / 402 may include a plurality of glass sheets bonded together using an adhesive layer; and may further exhibit a CTE gradient along the Z-axis. In various embodiments, for example, in a glass substrate with a Z-height (in the figures) ranging from about ≤1 mm to 5 mm, or in embodiment 400, glass layer 402 or glass core may have a thickness (Z-height) ranging from about 50 + / - 5 micrometers to about 1.5 mm (+ / - 10%). TGV 404 is a volume in which glass is removed and conductive material is placed, sufficient to enable electrical communication from the upper surface to the lower surface. As illustrated in the embodiment of glass layer 402, TGV 404 is substantially perpendicular to the upper surface of glass layer 402. In each embodiment of panel manufacturing, the X length and the corresponding Y length (defining the area in the top view or plan view) may be within the range of a first length (e.g., X) ranging from 10 mm to 500 mm and a second length (e.g., Y) ranging from 10 mm to 500 mm, the first length being perpendicular to the second length.

[0041] Example 400 depicts a glass core 204 / 402 having a glass via 404 formed therein and a cavity 406 formed in the upper surface of the glass core or glass layer 402. The figures reflect a cross-sectional view, where the portion for the cavity is depicted as its width from left to right on the page; however, in a top view, the portion for the cavity will be shown as its area. The TGV 404 and cavity 406 are created in the glass core or glass layer 204 / 402 by removing a certain amount of glass material. The TGV 404 and cavity 406 can be created by wet etching followed by laser drilling or ablation. The TGV sidewalls and cavity walls are substantially straight (i.e., at 90 degrees, plus or minus 20 degrees, perpendicular to the upper surface of the glass core or glass layer 204 / 402; however, in other embodiments, the cavity walls may be 90 degrees plus or minus 10 degrees) and may have an internal taper reflecting the drilling or ablation process used to create the cavity.

[0042] At 804, Example 410 illustrates the application of copper metallization to fill the TGV holes and form copper pads on the upper and lower surfaces of glass layer 402. Also at 804, Example 415 illustrates the application of solder resist or polyimide film lamination, followed by hot pressing to conform the film to the cavity.

[0043] At 806, the temporary carrier 426 can be removably attached and, in this embodiment, flipped. In some scenarios, a two-sided manufacturing process is performed, as illustrated with Example 420, in which two distinct glass cores are flipped and removably attached to the temporary carrier 426. A first glass core 422 is attached to one side of the temporary carrier 426 at its upper surface, and a second glass core 424 is attached to the opposite surface of the temporary carrier 426 at its upper surface. The corresponding cavity 406 can be filled with a sacrificial material 428, such as a polymer. Some examples of sacrificial materials include polyaldehyde, polyolefin sulfone, and polyurethane.

[0044] refer to Figure 5 At point 808, organic aggregate layers 502 / 504 are formed on the lower surfaces of glass cores 422 and 424, respectively. As is known in the art, the organic aggregate layer comprises one or more dielectric layers with patterned redistribution layer (RDL) conductive traces. The dielectric layer may be a suitable dielectric as described above. The conductive material used for the conductive contacts, HB contacts, and RDL traces and vias may include metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof) or another suitable conductive material.

[0045] After the organic accumulation layer is fabricated, glass core substrates 506 and 508 can be removed from the temporary carrier (at 808). To assemble glass core substrate 508 with the stacked buffer assembly of Example 330, glass core substrates 506 / 508 can be flipped again, and glass carrier 602 can be removably attached to the lower surface of the organic accumulation layer 504 of glass core substrate 508, as shown in Example 600. In various embodiments, solder bumps generated on top of the TGV can withstand heat (reflow).

[0046] At 810, as illustrated in Embodiment 606, a suspended cache architecture or Embodiment 330 is attached to the glass core substrate 508. The attachment extends via microbumps to the upper surface of the glass core substrate 508, such that the suspended cache or stacked cache is fitted into a cavity formed in the upper surface of the glass core, as described earlier herein. As illustrated with Embodiment 608, at 812, application of a mold / underfill (MUF 610) can be performed around the stacked cache assembly or Embodiment 330 on the upper surface of the glass core substrate 508, and deposition of conductive contacts, such as solder balls 612 arranged in a ball grid array (BGA), can be performed, resulting in Embodiment 608.

[0047] At 814, embodiment 608 may undergo further assembly in a system package, such as attachment to a printed circuit board (PCB) or motherboard, having a sealant covering embodiment 608, having a power source electrically coupled to embodiment 608, etc. Further, overmolding and thermal solutions (not shown) may be added.

[0048] The embodiments described above can provide functionality conventionally associated with a system-on-a-chip (SoC) in a multi-die package or multi-die assembly. The above is not an exhaustive list of multi-die assemblies or systems implementing a dangling cache architecture. Those skilled in the art will appreciate that additional multi-die assembly embodiments, not illustrated, are supported based on the accompanying drawings and descriptions included herein. The following drawings and descriptions provide additional context for the aforementioned chips, wafers, and assemblies.

[0049] Figure 9This is a top view of a wafer 900 and a die 902 that may be included in any of the embodiments disclosed herein. The wafer 900 may be made of a semiconductor material and may include one or more dies 902 formed on the surface of the wafer 900. After the fabrication of the integrated circuit components on the wafer 900 is complete, the wafer 900 may undergo a separation process, in which the dies 902 are separated from each other to provide discrete “chips” or integrated circuit components for packaging. Each die 902 including the integrated circuit components may include one or more transistors (e.g., discussed below). Figure 10 The transistors 1040 include some transistors, supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 900 or die 902 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Additionally, multiple devices may be combined on a single die 902. For example, a memory array formed by multiple memory devices may be formed as a processor unit (e.g., ...) on the same die 902. Figure 12 The processor unit 1202 or other logic configured to store information in a memory device or execute instructions stored in a memory array. In some embodiments, die 902 may be attached to a wafer 900 that includes other dies, and wafer 900 may then be separated, a manufacturing process known as die-to-wafer assembly technology.

[0050] Figure 10 This is a cross-sectional side view of an integrated circuit 1000 that may be included in any of the embodiments disclosed herein. One or more of the integrated circuits 1000 may be included in one or more dies 902 ( Figure 9 The integrated circuit 1000 can be located in a die substrate 1002 (e.g., Figure 9 The wafer 900 is formed on the die (e.g., Figure 9 In the 902 core.

[0051] The die substrate 1002 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type material system or a p-type material system (or a combination of both). The die substrate 1002 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1002 may be formed using alternative materials, which may or may not be combined with silicon. These alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1002. Although several examples of materials from which the die substrate 1002 can be formed are described herein, any material that can be used as the basis for the integrated circuit 1000 may be used. The die substrate 1002 may be a discrete die (e.g., Figure 9 The 902 die or chip (e.g., Figure 9 The chip 900 is part of it.

[0052] The integrated circuit 1000 may include one or more device layers 1004 disposed on a die substrate 1002. Device layer 1004 may include features of one or more transistors 1040 (e.g., metal oxide semiconductor field-effect transistors, MOSFETs) formed on the die substrate 1002. Transistor 1040 may include, for example, one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling current flow between S / D regions 1020, and one or more S / D contacts 1024 for routing electrical signals to and / or from the S / D regions 1020.

[0053] The gate 1022 may be formed of at least two layers (a gate dielectric and a gate electrode). The gate dielectric may comprise a stack of one or more layers. One or more layers may comprise silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may comprise elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric when a high-k material is used.

[0054] The gate electrode may be formed on the gate dielectric and, depending on whether the transistor 1040 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NOMS) transistor, may include at least one p-type work function metal or an n-type work function metal. In some implementations, the gate electrode may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as barrier layers.

[0055] For PMOS transistors, metals that can be used as the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that can be used as the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0056] In some embodiments, when viewed as a cross-section of transistor 1040 along the source-channel-drain direction, the gate electrode may include a U-shaped structure and two sidewall portions, the U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1002, and the two sidewall portions substantially perpendicular to the top surface of die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1002 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 1002. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0057] In some embodiments, pairs of sidewall spacers may be formed on opposite sides of the gate stack to be positioned on both sides of the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and include deposition and etching processes. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0058] The S / D region 1020 may be formed within the die substrate 1002, adjacent to the gate 1022 of each transistor 1040. For example, the S / D region 1020 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the die substrate 1002 to form the S / D region 1020. An annealing process to activate the dopant and further diffuse it into the die substrate 1002 may follow the ion implantation process. In the latter process, the die substrate 1002 may be etched first to form a recess at the location of the S / D region 1020. An epitaxial deposition process may then be performed to fill the recess using the material used to fabricate the S / D region 1020. In some implementations, the S / D region 1020 may be fabricated using a silicon alloy (such as silicon germanium or silicon carbide). In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopant such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1020 may be formed using one or more alternative semiconductor materials such as germanium or group III-V materials or alloys. In further embodiments, the S / D region 1020 may be formed using one or more layers of metal and / or layers of metal alloys.

[0059] Electrical signals such as power signals and / or input / output (I / O) signals can be transmitted through one or more interconnect layers disposed on device layer 1004. Figure 10 The interconnect layers (illustrated as interconnect layers 1006-1010) are routed to devices (e.g., transistor 1040) in device layer 1004, and / or routed from devices (e.g., transistor 1040) in device layer 1004. For example, conductive features of device layer 1004 (e.g., gate 1022 and S / D contact 1024) may be electrically coupled to interconnect structures 1028 of interconnect layers 1006-1010. One or more interconnect layers 1006-1010 may form a metallization stack (also referred to as an “ILD” stack) 1019 of integrated circuit 1000.

[0060] Interconnect structure 1028 can be arranged within interconnect layers 1006-1010 to route electrical signals according to a wide range of designs; specifically, the arrangement is not limited to... Figure 10 The specific configuration of the interconnect structure 1028 depicted. Although in Figure 10 The disclosure depicts a specific number of interconnect layers 1006-1010, but embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than depicted.

[0061] In some embodiments, the interconnect structure 1028 may include lines 1028a and / or vias 1028b filled with a conductive material such as a metal. Lines 1028a may be arranged to route electrical signals in a direction substantially parallel to a plane of the die substrate 1002 on which the device layer 1004 is formed. For example, lines 1028a may route electrical signals in the direction of entering and leaving a page, and / or in the direction of crossing a page. Vias 1028b may be arranged to route electrical signals in a direction substantially perpendicular to a plane of the die substrate 1002 on which the device layer 1004 is formed. In some embodiments, vias 1028b may electrically couple lines 1028a of different interconnect layers 1006-1010 together.

[0062] Interconnect layers 1006-1010 may include dielectric material 1026 disposed between interconnect structures 1028, such as... Figure 10 As shown in the figure. In some embodiments, the dielectric material 1026 disposed between interconnect structures 1028 in different interconnect layers 1006-1010 may have different compositions; in other embodiments, the composition of the dielectric material 1026 between different interconnect layers 1006-1010 may be the same. Device layer 1004 may also include dielectric material 1026 disposed between transistor 1040 and the bottom layer of metallization stack. The dielectric material 1026 included in device layer 1004 may have a different composition than the dielectric material 1026 included in interconnect layers 1006-1010; in other embodiments, the composition of the dielectric material 1026 in device layer 1004 may be the same as the dielectric material 1026 included in any of the interconnect layers 1006-1010.

[0063] A first interconnect layer 1006 (referred to as metal 1 or "M1") may be formed directly on device layer 1004. In some embodiments, the first interconnect layer 1006 may include a line 1028a and / or a via 1028b, as shown. The line 1028a of the first interconnect layer 1006 may be coupled to a contact portion (e.g., S / D contact 1024) of device layer 1004. The via 1028b of the first interconnect layer 1006 may be coupled to the line 1028a of the second interconnect layer 1008.

[0064] The second interconnect layer 1008 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 may include vias 1028b to couple lines of the interconnect structure 1028 of the second interconnect layer 1008 to lines 1028a of the third interconnect layer 1010. Although for clarity, lines 1028a and vias 1028b are structurally depicted as lines within separate interconnect layers, in some embodiments, lines 1028a and vias 1028b may be structurally and / or materially adjacent (e.g., simultaneously filled during a dual damascene process).

[0065] The third interconnect layer 1010 (referred to as metal 3 or "M3") (and, if necessary, additional interconnect layers) may be sequentially formed on the second interconnect layer 1008 according to similar techniques and configurations described in conjunction with the second interconnect layer 1008 or the first interconnect layer 1006. In some embodiments, the "higher" (i.e., further away from device layer 1004) interconnect layers in the metallization stack 1019 of the integrated circuit 1000 may be thicker than the lower interconnect layers in the metallization stack 1019, wherein the lines 1028a and vias 1028b in the higher interconnect layers are thicker than the lines 1028a and vias 1028b in the lower interconnect layers.

[0066] The integrated circuit 1000 may include a solder resist 1034 (e.g., polyimide or a similar material) formed on interconnect layers 1006-1010 and one or more conductive contacts 1036. Figure 10 In the illustration, conductive contact 1036 is shown in the form of a bonding pad. Conductive contact 1036 may be electrically coupled to interconnect structure 1028 and configured to route electrical signals from transistor(s) 1040 to an external device. For example, solder bonds may be formed on one or more conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit die including integrated circuit 1000 to another component (e.g., a printed circuit board). Integrated circuit 1000 may include additional or alternative structures for routing electrical signals from interconnect layers 1006-1010; for example, conductive contact 1036 may include other similar features (e.g., pillars) for routing electrical signals to external components.

[0067] In some embodiments where the integrated circuit 1000 is a dual-sided die, the integrated circuit 1000 may include another metallization stack (not shown) on the opposite side of device layer(s) 1004. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1006-1010 to provide a conductive path (e.g., including conductive lines and vias) between device layer(s) 1004 and additional conductive contacts (not shown) on the opposite side of the integrated circuit 1000, away from conductive contact 1036.

[0068] In other embodiments where the integrated circuit 1000 is a dual-sided die, the integrated circuit 1000 may include one or more through-silicon vias (TSVs) through the die substrate 1002; these TSVs may contact one or more device layers 1004 and may provide a conductive path between the one or more device layers and additional conductive contacts (not shown) on the opposite side of the integrated circuit 1000, away from the conductive contact 1036. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of the integrated circuit 1000, away from the conductive contact 1036, to the transistor 1040 and any other components integrated into the integrated circuit 1000 die, and the metallization stack 1019 may be used to route I / O signals from the conductive contact 1036 to the transistor 1040 and any other components integrated into the integrated circuit 1000 die.

[0069] Multiple integrated circuits 1000 may be connected to one or more TSV stacks of devices in a stack, providing connections between one device in the stack and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM die may provide connections between the respective HBM and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0070] Figure 11 This is a cross-sectional side view of a microelectronic assembly 1100, which may include any of the embodiments disclosed herein. The microelectronic assembly 1100 includes a plurality of integrated circuit components disposed on a circuit board 1102 (which may be a motherboard, system board, host board, etc.). The microelectronic assembly 1100 may include components disposed on a first surface 1140 and an opposing second surface 1142 of the circuit board 1102; generally, components may be disposed on one or both of surfaces 1140 and 1142.

[0071] In some embodiments, circuit board 1102 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1102 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 1102 may be a non-PCB substrate. Figure 11 The microelectronic component 1100 illustrated in the figure includes a package-on-interposer (PAI) structure 1136, which is coupled to a first side 1440 of a circuit board 1102 via a coupling member 1116. The coupling member 1116 can electrically and mechanically couple the PAI structure 1136 to the circuit board 1102 and may include solder balls (such as...). Figure 11 The following are included: pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of the socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0072] The on-intermediate package structure 1136 may include an integrated circuit component 1120, which is coupled to the intermediate layer 1104 via a coupling member 1118. The coupling member 1118 may take any suitable form for the application, such as the form discussed above with reference to coupling member 1116. Although Figure 11 A single integrated circuit component 1120 is shown, but multiple integrated circuit components can be coupled to the interposer 1104; in fact, additional interposers can be coupled to the interposer 1104. The interposer 1104 can provide an intermediate substrate for bridging the circuit board 1102 and the integrated circuit component 1120.

[0073] Integrated circuit component 1120 may include one or more integrated circuit dies (e.g., Figure 9 902 core, Figure 10 Packaged or unpackaged integrated circuit components (1000) and / or one or more other suitable components.

[0074] The unpackaged integrated circuit component 1120 includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1104. In embodiments where the integrated circuit component 1120 includes multiple integrated circuit dies, these dies may be of the same type (homogeneous multi-die integrated circuit component) or of two or more different types (heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, the integrated circuit component 1120 may also include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may reside on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These separate integrated circuit dies may be referred to as “chiplets.” In embodiments where the integrated circuit component includes multiple integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or a combination of the foregoing. Packaged multi-chip integrated circuit components can be referred to as multi-chip packages (MCPs) or multi-chip modules (MCMs).

[0075] Intermediate layer 1104 can extend connections to wider spacing or rewire connections into different connections. For example, intermediate layer 1104 can couple integrated circuit component 1120 to the collection of ball grid array (BGA) conductive contacts of coupling component 1116 to couple to circuit board 1102. Figure 11 In the embodiment illustrated, integrated circuit component 1120 and circuit board 1102 are attached to opposite sides of interposer 1104; in other embodiments, integrated circuit component 1120 and circuit board 1102 may be attached to the same side of interposer 1104. In some embodiments, three or more components may be interconnected by means of interposer 1104.

[0076] In some embodiments, the interposer 1104 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1104 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the interposer 1104 may be formed of an alternative rigid or flexible material, including the same materials described above for use in semiconductor substrates (such as silicon, germanium, and other Group III-V and Group IV materials). Intermediate layer 1104 may include metal interconnects 1108 and vias 1110, including but not limited to a through hole via 1110-1 (extending from the first side 1150 of the intermediate layer 1104 to the second side 1154 of the intermediate layer 1104), a blind via 1110-2 (extending from the first side 1150 or the second side 1154 of the intermediate layer 1104 to an intermediate metal layer), and a buried via 1110-3 (connecting to an inner metal layer).

[0077] In some embodiments, the interposer 1104 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect portions on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, the interposer 1104 including the silicon interposer may further include one or more routing layers for routing the connections on the first side of the interposer 1104 to an opposite second side of the interposer 1104.

[0078] Intermediate layer 1104 may further include embedded devices 1114, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices, may also be formed on intermediate layer 1104. The on-intermediate package structure 1136 may take the form of any structure known in the art for on-intermediate package structures.

[0079] Integrated circuit assembly 1100 may include integrated circuit component 1124, which is coupled to a first surface 1140 of circuit board 1102 via coupling component 1122. Coupling component 1122 may take the form of any embodiment discussed above with reference to coupling component 1116, and integrated circuit component 1124 may take the form of any embodiment discussed above with reference to integrated circuit component 1120.

[0080] Figure 11 The integrated circuit assembly 1100 illustrated in the figure includes a package-on-package structure 1134 coupled to a second side 1142 of a circuit board 1102 via a coupling member 1128. The package-on-package structure 1134 may include integrated circuit components 1126 and 1132 coupled together via a coupling member 1130, such that integrated circuit component 1126 is disposed between the circuit board 1102 and integrated circuit component 1132. Coupling members 1128 and 1130 may take the form of any embodiment of the coupling member 1116 discussed above, and integrated circuit components 1126 and 1132 may take the form of any embodiment of the integrated circuit component 1120 discussed above. The package-on-package structure 1134 may be configured according to any package-on-package structure known in the art.

[0081] Figure 12 This may be a block diagram of an example electrical device 1200 that may include one or more embodiments disclosed herein. For example, any suitable component of the electrical device 1200 may include one or more of the following: microelectronic component 1100, integrated circuit component 1120, integrated circuit 1000, integrated circuit die 902, or a structure disclosed herein. Several components in Figure 12 The components are illustrated as being included in electrical device 1200, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1200 may be attached to one or more motherboards, motherboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-a-chip (SoC) die. In various embodiments, electrical device 3000 is enclosed by a housing or integrated with a housing.

[0082] Additionally, in various embodiments, electrical equipment 1200 may not include... Figure 12The electrical device 1200 may include one or more of the components shown in the diagram, but may include interface circuitry for coupling to one or more components. For example, the electrical device 1200 may not include display device 1206, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 1206 may be coupled. In another set of examples, the electrical device 1200 may not include audio input device 1224 or audio output device 1208, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which audio input device 1224 or audio output device 1208 may be coupled.

[0083] Electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor cells). As used herein, the terms “processor cell,” “processing unit,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit can be called an XPU (or xPU).

[0084] Electrical device 1200 may include memory 1204, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard drives. In some embodiments, memory 1204 may include memory located on the same integrated circuit die as processor unit 1202. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0085] In some embodiments, electrical device 1200 may include one or more processor units 1202 that are heterogeneous or asymmetric to another processor unit 1202 in electrical device 1200. Various differences may exist between processor units 1202 in the system in terms of a range of metrics including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, etc. These differences can be effectively manifested in themselves as asymmetry and heterogeneity between processor units 1202 in electrical device 1200.

[0086] In some embodiments, electrical device 1200 may include communication component 1212 (e.g., one or more communication components). For example, communication component 1212 may manage wireless communication for transmitting data to and from electrical device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may use modulated electromagnetic radiation to enable data transmission through a non-solid-state medium. The term "wireless" does not imply that the associated device does not contain any wires, but in some embodiments, the associated device may not contain any wires.

[0087] Communication component 1212 can implement any of several wireless standards or protocols, including but not limited to: Institute for Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision); Long-Term Evolution (LTE) projects and any modifications, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Boardband (UMB) projects (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are generally referred to as WiMAX networks, an acronym for Global Microwave Access Interoperability, and are certification marks used for products that have passed compliance and interoperability testing to the IEEE 802.16 standard. Communication component 1212 can operate under Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication component 1212 can also operate under Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTERAN (E-UTRAN).Communication component 1212 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher generations. In other embodiments, communication component 1212 may operate according to other wireless protocols. Electrical device 1200 may include antenna 1222 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0088] In some embodiments, communication component 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, communication component 1212 may include multiple communication components. For example, a first communication component 1212 may be dedicated to shorter-range wireless communications (such as Wi-Fi or Bluetooth), and a second communication component 1212 may be dedicated to longer-range wireless communications (such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others). In some embodiments, the first communication component 1212 may be dedicated to wireless communications, and the second communication component 1212 may be dedicated to wired communications.

[0089] Electrical device 1200 may include battery / power circuit system 1214. Battery / power circuit system 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of electrical device 1200 to a power source (e.g., AC line power) separate from electrical device 1200.

[0090] Electrical device 1200 may include display device 1206 (or a corresponding interface circuit system, as discussed above). Display device 1206 may include one or more embedded, or wired or wirelessly connected external visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0091] Electrical device 1200 may include audio output device 1208 (or a corresponding interface circuit system, as discussed above). Audio output device 1208 may include any embedded, wired or wirelessly connected external device that generates auditory indicators, such as a speaker, headphones, or earbuds.

[0092] Electrical device 1200 may include audio input device 1224 (or a corresponding interface circuitry system, as discussed above). Audio input device 1224 may include any embedded, wired or wirelessly connected device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). Electrical device 1200 may include Global Navigation Satellite System (GNSS) device 1218 (or a corresponding interface circuitry system, as discussed above), such as a Global Positioning System (GPS) device. GNSS device 1218 may communicate with satellite-based systems and may determine the geographical location of electrical device 1200 based on information received from one or more GNSS satellites, as is known in the art.

[0093] Electrical device 1200 may include another output device 1210 (or a corresponding interface circuit system, as discussed above). Examples of other output devices 1210 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0094] Electrical device 1200 may include another input device 1220 (or a corresponding interface circuit system, as discussed above). Examples of other input devices 1220 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., single-field-of-view or stereo cameras), trackballs, trackpads, touchpads, keyboards, cursor control devices (such as mice), styluses, touchscreens, proximity sensors, microphones, barcode readers, Quick Response (QR) code readers, electrocardiogram (ECG) sensors, photoplethysmogram (PPG) sensors, electrodermal response sensors, any other sensors, or radio frequency identification (RFID) readers.

[0095] Electrical device 1200 may have any desired form factor, such as handheld or mobile electrical devices (e.g., cellular phones, smartphones, mobile internet devices, music players, tablets, laptops, 2-in-1 convertible computers, portable all-in-one computers, netbooks, ultrabooks, personal digital assistants (PDAs), ultra-mobile personal computers, portable game consoles, etc.), desktop electrical devices, servers, rack-mount computing solutions (blade, tray, or skid-mount computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, stationary game consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems as part of vehicles, smart home appliances, consumer electronics products or equipment, or manufacturing equipment). In some embodiments, electrical device 1200 may be any other electronic device that processes data. In some embodiments, electrical device 1200 may include multiple discrete physical components. Given the range of devices that the electrical device 1200 may present in various embodiments, in some embodiments the electrical device 1200 may be referred to as a computing device or computing system.

[0096] While at least one embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the disclosed embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing the disclosed embodiments. Various changes may be made to the function and arrangement of the elements without departing from the scope of this disclosure as set forth in the appended claims and their legal equivalents.

[0097] As used herein, the term “electronic component” can refer to active electronic circuitry (e.g., processing unit, memory, storage device, FET) or passive electronic circuitry (e.g., resistor, inductor, capacitor).

[0098] As used herein, the term "integrated circuit component" can refer to an electronic component disposed on semiconductor material to perform a function. An integrated circuit (IC) component may include one or more of any computing system components described or referenced herein, or any other computing system components, such as processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controllers, memory or network interface controllers, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0099] Non-limiting examples of unpackaged integrated circuit components include a single monolithic integrated circuit die; the die may include solder bumps on contacts attached to the die. When present on the die, solder bumps or other conductive contacts allow the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0100] Non-limiting examples of packaged integrated circuit components include one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. Typically, the housing includes an integrated heat spreader (IHS); the packaged integrated circuit component typically has bumps, leads, or pins attached to the package substrate (either directly or by wires with bumps, leads, or pins attached to the package substrate) for attaching the packaged integrated circuit component to a printed circuit board (or motherboard or substrate) or another component.

[0101] As used herein, phrases such as “embodiment,” “various embodiments,” “some embodiments,” etc., indicate that some embodiments may have some, all, or no features of those described for other embodiments. “First,” “second,” “third,” etc., describe a common object and indicate different instances of the same object mentioned; unless specifically stated otherwise, they do not imply a given sequence in time or space, order, or any other manner. According to patent application terminology, “connected” indicates that elements are in direct physical or electrical contact with each other, and “coupled” indicates that elements cooperate or interact with each other; coupled elements may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” etc., are used synonymously to indicate non-exclusive inclusion.

[0102] As used in this application and in the claims, a list of items joined by the terms "at least one of..." or "one or more of..." may refer to any combination of the listed items. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, and C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0103] As used in this application and claims, the phrase “...individuals” or “...each” followed by a list of items described or stated to have features, characteristics, etc., means that all items in the list have the described or stated features, characteristics, etc. For example, the phrase “individuals of A, B or C include sidewalls” or “A, B or C each include sidewalls” means that A includes sidewalls, B includes sidewalls, and C includes sidewalls.

[0104] The operational theories, scientific principles, or other theoretical descriptions of the apparatuses or methods described herein are provided for the purpose of better understanding and are not intended to limit the scope. The apparatuses and methods in the appended claims are not limited to those that operate in a manner described by such operational theories.

[0105] The following examples relate to additional embodiments of the techniques disclosed herein.

[0106] Example

[0107] Example 1 is an apparatus comprising: a first die including an integrated circuit and a first static random access memory (SRAM) component; wherein the first die has a lower surface defined by a plurality of solder bumps located below the integrated circuit and a first insulating material having a plurality of first conductive contacts located below the first SRAM component; a second die including a second SRAM component and an upper surface including a second insulating material having a corresponding plurality of second conductive contacts; the second die being positioned on and physically coupled to the first SRAM component such that the plurality of first conductive contacts are directly attached to the corresponding plurality of second conductive contacts, and the first insulating material is directly attached to the second insulating material.

[0108] Example 2 includes the subject matter of Example 1, wherein the first insulating material and the second insulating material include dielectric materials.

[0109] Example 3 includes the subject matter of Example 1, wherein the first conductive contact and the second conductive contact comprise metal.

[0110] Example 4 includes the subject matter of Example 1, wherein the first conductive contact and the second conductive contact comprise copper.

[0111] Example 5 includes the subject of Example 1, wherein a first conductive contact and a second conductive contact are used to route control lines and data lines from a first die to a second die.

[0112] Example 6 includes the subject of any of Examples 1-5, wherein the integrated circuit is a central processing unit (CPU) or a graphics processing unit (GPU).

[0113] Example 7 includes the subject matter of any one of Examples 1-6, wherein the first die further includes at least one additional integrated circuit component.

[0114] Example 8 includes the subject matter of any one of Examples 1-7, and further includes: a glass layer having a plurality of glass vias; the glass layer being attached to the lower surface of a first die, wherein each solder bump on the first die is electrically coupled to a conductive material in a corresponding glass via; and wherein the glass layer further has a cavity formed in the upper surface of the glass layer; and wherein the cavity accommodates a second die.

[0115] Example 9 is a multi-die assembly comprising: a cache chiplet including: a first die including an integrated circuit and a first static random access memory (SRAM) component; wherein the first die has a lower surface defined by a plurality of solder bumps located below the integrated circuit and a first insulating material having a plurality of first conductive contacts located below the first SRAM component; a second die including a second SRAM component and an upper surface including a second insulating material having a corresponding plurality of second conductive contacts; the second die being positioned on and physically coupled to the first SRAM component such that the plurality of first conductive contacts are directly attached to the corresponding plurality of second conductive contacts, and the first insulating material is directly attached to the second insulating material; and a glass layer having a plurality of glass vias and a cavity formed in the upper surface of the glass layer; the cache chiplet being attached to the glass layer; wherein each solder bump on the first die is electrically coupled to conductive material in a corresponding glass via; and wherein the cavity accommodates the second die.

[0116] Example 10 includes the subject of Example 9, and further includes an organically constructed layer on the lower surface of the glass layer, the organically constructed layer including a dielectric material having one or more conductive traces therein.

[0117] Example 11 includes the subject matter of Example 10, and further includes: a plurality of solder balls on the lower surface of the organic building layer; and at least one electrical path from the first die to the solder balls.

[0118] Example 12 includes the subject of Example 11, and further includes a printed circuit board attached to a plurality of solder balls.

[0119] Example 13 includes the subject matter of any one of Examples 9-12, wherein the thickness of the glass layer is in the range of 20 micrometers + / - 5 micrometers to 1.5 millimeters + / - 5 micrometers.

[0120] Example 14 includes the subject matter of any one of Examples 9-12, and further includes a molding and underfill material surrounding the first die on the upper surface of the glass layer.

[0121] Example 15 includes the subject matter of any one of Examples 9-14, wherein the first die further includes at least one additional integrated circuit component.

[0122] Example 16 is a method comprising: selecting a first die including an integrated circuit and a first cache component; wherein the first die has a lower surface defined by a plurality of solder bumps located below the integrated circuit and a first insulating material having a plurality of first conductive contacts located below the first cache component; selecting a second die including a second cache component and an upper surface including a second insulating material having a corresponding plurality of second conductive contacts; and co-bonding the second cache component to the first cache component to create a cache stack side of the first die.

[0123] Example 17 includes the subject matter of Example 16, and further includes: depositing a seed layer on the stacked side of the first die; patterning the seed layer with a photoresist; exposing the photoresist; and depositing copper on the exposed photoresist.

[0124] Example 18 includes the subject of Example 17, and further includes removing the photoresist and electroplating copper with solder to create solder bumps.

[0125] Example 19 includes the subject matter of Example 18, further including: a glass substrate having a cavity formed in an upper surface; the glass substrate further including a plurality of glass vias; and attaching the cache stack side of the first die to the glass substrate by positioning the second cache component in the cavity and electrically coupling each solder bump to the respective glass via with a conductive material.

[0126] Example 20 includes the subject of Example 19, and further includes forming an organic accumulation layer on the lower surface of a glass substrate.

Claims

1. An apparatus comprising: The first die includes an integrated circuit and a first static random access memory (SRAM) component. The first die has a lower surface defined by a plurality of solder bumps located below the integrated circuit and a first insulating material having a plurality of first conductive contacts located below the first SRAM component; The second die includes a second SRAM component and a top surface, the top surface including a second insulating material having a corresponding plurality of second conductive contacts therein; The second die is positioned on the first SRAM component and physically coupled to the first SRAM component, such that the plurality of first conductive contacts are directly attached to the corresponding plurality of second conductive contacts, and the first insulating material is directly attached to the second insulating material.

2. The apparatus according to claim 1, wherein, The first insulating material and the second insulating material include dielectric materials.

3. The apparatus according to claim 1, wherein, The first conductive contact and the second conductive contact comprise metal.

4. The apparatus according to claim 1, wherein, The first conductive contact and the second conductive contact comprise copper.

5. The apparatus according to claim 1, wherein, The first conductive contact and the second conductive contact are used to route control lines and data lines from the first die to the second die.

6. The apparatus according to claim 1, wherein, The integrated circuit is a central processing unit (CPU) or a graphics processing unit (GPU).

7. The apparatus according to claim 1, wherein, The first die further includes at least one additional integrated circuit component.

8. The apparatus according to any one of claims 1-7, further comprising: A glass layer with multiple glass through-holes; The glass layer is attached to the lower surface of the first die, wherein each solder bump on the first die is electrically coupled to a conductive material in a corresponding glass via; and The glass layer further comprises a cavity formed in the upper surface of the glass layer; and The cavity contains the second die.

9. A multi-chip assembly, comprising: A cache chiplet architecture, comprising: The first die includes an integrated circuit and a first static random access memory (SRAM) component. The first die has a lower surface defined by a plurality of solder bumps located below the integrated circuit and a first insulating material having a plurality of first conductive contacts located below the first SRAM component; The second die includes a second SRAM component and a top surface, the top surface including a second insulating material having a corresponding plurality of second conductive contacts therein; The second die is positioned on and physically coupled to the first SRAM component, such that the plurality of first conductive contacts are directly attached to the corresponding plurality of second conductive contacts, and the first insulating material is directly attached to the second insulating material; and A glass layer having a plurality of glass through-holes and a cavity formed in the upper surface of the glass layer; The cache chiplet architecture is attached to the glass layer; In this embodiment, each solder protrusion on the first die is electrically coupled to the conductive material in the corresponding glass via; and The cavity contains the second die.

10. The multi-die assembly of claim 9, further comprising an organic building layer on the lower surface of the glass layer, the organic building layer comprising a dielectric material having one or more conductive traces therein.

11. The multi-die assembly of claim 10, further comprising: Multiple solder balls on the lower surface of the organic building block layer; as well as At least one electrical path from the first die to the solder ball.

12. The multi-die assembly of claim 11, further comprising a printed circuit board attached to the plurality of solder balls.

13. The multi-chip assembly according to any one of claims 9-12, wherein, The thickness of the glass layer is in the range of 20 micrometers + / - 5 micrometers to 1.5 millimeters + / - 5 micrometers.

14. The multi-die assembly according to any one of claims 9-13, further comprising a molding and underfill material surrounding the first die on the upper surface of the glass layer.

15. The multi-chip assembly according to any one of claims 9-13, wherein, The first die further includes at least one additional integrated circuit component.

16. A method comprising: Select a first die, the first die including an integrated circuit and a first cache component; The first die has a lower surface defined by a plurality of solder bumps located below the integrated circuit and a first insulating material having a plurality of first conductive contacts located below the first cache component; Select a second die, the second die including a second buffer component and a top surface, the top surface including a second insulating material having corresponding plurality of second conductive contacts therein; and The second cache component is co-bonded onto the first cache component to create the cache stack side of the first die.

17. The method of claim 16, further comprising: A seed layer is deposited on the stacked side of the first die; The seed crystal layer is patterned using a photoresist; Expose the photoresist; as well as Copper is deposited on the exposed photoresist.

18. The method of claim 17, further comprising removing the photoresist and electroplating the copper with solder to create solder bumps.

19. The method of claim 18, further comprising: A glass substrate with a cavity formed in its upper surface; The glass substrate further includes a plurality of glass through-holes; as well as The first die is attached to the glass substrate by positioning the second buffer component in the cavity and electrically coupling each solder bump to the conductive material in the corresponding glass via.

20. The method of claim 19, further comprising forming an organic accumulation layer on the lower surface of the glass substrate.

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