Self-triggered synchronous sampling system based on switch information restoration

Abstract

This application provides a self-triggering synchronous sampling system based on switch information reconstruction, comprising: a switch state signal extraction module for converting the voltage across the power semiconductor device under test into a digital switch state signal; a device state duration acquisition module for determining the on-state duration, off-state duration, and switch cycle within at least one switching cycle; an on-state duration prediction module for predicting the on-state duration of the current switching cycle; a sampling time setting module for determining the sampling time within the on-state duration of the current switching cycle; a fixed-frequency sampling and data filtering module for generating a fixed-frequency sampling trigger timing sequence; and a sampling module for issuing a sampling trigger signal and sampling upon reaching the sampling time or the fixed-frequency sampling trigger timing sequence. This application reconstructs the switch state based on the voltage across the power semiconductor device under test, without relying on a drive signal carrier to generate the sampling trigger signal, thus improving the accuracy and reliability of synchronous sampling.

Description

Technical Field

[0001] This application relates to the field of power electronic converter technology, and more specifically, to a self-triggered synchronous sampling system based on switch information restoration. Background Technology

[0002] In the field of power electronics technology, converters, as core devices for energy conversion and control, have been widely used in key scenarios such as new energy power generation, motor drives, high-voltage direct current transmission, and power quality management. Their control accuracy, operational stability, and synchronous sampling performance of key physical quantities (such as output current, inductor current, and DC bus voltage) are directly related. Only by achieving strict alignment between the sampling time and the switching action of power semiconductor devices can current distortion and power calculation errors caused by phase deviation be effectively avoided, thereby ensuring the tracking accuracy of maximum power point tracking (MPTT), the control performance of field-oriented control (FOC), and the reliability of system protection. Current mainstream synchronous sampling schemes mostly rely on directly acquiring the drive signal (such as PWM pulse) of the power semiconductor device, generating sampling trigger commands through the rising edge, falling edge, or specific phase of the drive signal. The core drawback of this type of scheme lies in its strong dependence on the drive signal, leading to multiple technical bottlenecks in practical engineering applications: The conflict between insulation isolation and signal acquisition is prominent: In high-voltage converters (such as flexible DC transmission converters and power electronic transformers) or high-isolation equipment, the drive circuits of power semiconductor devices are usually located on the high-voltage side, while the sampling and control unit is mostly located on the low-voltage side. If the drive signal is directly extracted, high-precision isolation devices (such as linear optocouplers and fiber optic isolation modules) need to be configured, which not only increases the system size and cost, but also introduces new synchronization errors due to the delay characteristics of the isolation devices. Especially in high-frequency scenarios with switching frequencies higher than 10kHz, this error can cause the sampling phase deviation to exceed 0.5°, seriously affecting the control accuracy. Topology adaptability and system complexity are limited: In multi-module series converter topologies (such as cascaded photovoltaic inverters and solid-state transformers), drive signals are distributed across various power modules. Centralized acquisition requires building a complex signal aggregation and synchronization network, which reduces system reliability and makes it difficult to adapt to the interface specifications of power modules from different manufacturers. Some solutions attempt to solve this problem through hardware clock synchronization (such as GPS timing and PTP protocol), but this requires the deployment of an additional clock module and is susceptible to electromagnetic interference, resulting in insufficient stability in strong interference environments such as industrial sites.

[0003] Sampling accuracy degrades under dynamic operating conditions: When the converter is under dynamic operating conditions such as sudden load changes or rapid duty cycle adjustments, the pulse width and period of the drive signal will change instantaneously. Traditional sampling methods based on fixed phase triggering cannot track the carrier peak and valley positions in real time, causing the sampling point to fall within the signal fluctuation range and resulting in data distortion. For example, in the electric drive system of new energy vehicles, the sudden change in duty cycle during acceleration can cause the current sampling error to increase to more than 5%, directly affecting the dynamic response performance of the motor. To overcome these limitations, the industry has attempted to achieve synchronous sampling through indirect detection, such as methods based on current zero-crossing detection and voltage ripple analysis. However, current zero-crossing detection is susceptible to harmonic interference and has poor reliability under non-sinusoidal operating conditions; voltage ripple analysis relies on precise filtering algorithms, is sensitive to hardware noise, and cannot effectively reconstruct the carrier peak and valley positions, making it difficult to meet high-precision sampling requirements. Another approach involves detecting the switching node voltage to determine the device state, such as patent CN117595204 A, which uses a boost inductor recirculation protection method based on switching node detection. However, this technology is only used for protection logic triggering and does not involve switching cycle reconstruction or sampling time prediction, thus failing to achieve closed-loop control for synchronous sampling.

[0004] Therefore, developing a synchronous sampling system that does not require direct acquisition of drive signals, has strong isolation adaptability, and can dynamically track switch states is of vital engineering value and application prospects for improving the operating performance of converters in complex scenarios such as high voltage, high frequency, and multiple modules. Summary of the Invention

[0005] In view of the deficiencies / one of the existing technologies, the purpose of this application is to provide a self-triggering synchronous sampling system based on switch information restoration.

[0006] A first aspect of this application provides a self-triggered synchronous sampling system based on switch information restoration, comprising: The switch status signal extraction module is used to acquire the voltage across the two ends of the power semiconductor device under test and convert it into a digital switch status signal; The device state duration acquisition module is used to determine the on-state duration, off-state duration, and switching cycle within at least one switching cycle based on the digital switch state signal within a preset time length. The on-state duration prediction module is used to predict the on-state duration of the current switching cycle based on the off-state duration of the previous switching cycle or the switching parameters of the power semiconductor device in phase with the power semiconductor device under test. The sampling time setting module is used to determine at least one sampling time in the conduction state duration of the current switching cycle according to a preset time interval. The fixed-frequency sampling and data filtering module is used to generate the fixed-frequency sampling trigger timing sequence. The sampling module is used to send a sampling trigger signal and perform sampling when the sampling time or the fixed-frequency sampling trigger timing is reached.

[0007] Optionally, it also includes an anomaly processing module, which is used to replace the digital switch state signal of the power semiconductor device under test with the switch parameters of a power semiconductor device that is in phase with the power semiconductor device under test and has the same driving signal carrier when the on-state duration or off-state duration of the power semiconductor device under test is greater than a preset proportion of the switching cycle, and input the on-state duration prediction module to predict the on-state duration of the power semiconductor device under test in the current switching cycle.

[0008] Optionally, the fixed-frequency sampling and data filtering module is used to determine the fixed-frequency sampling trigger timing and send it to the sampling module when the switching frequency of the power semiconductor device under test is less than a preset second threshold, or when the anomaly handling module determines that the conduction duration of the power semiconductor device under test is in an abnormal working state. The sampling module is used to send a sampling trigger signal to the power semiconductor device under test and sample when the sampling time corresponding to the fixed-frequency sampling trigger timing is reached.

[0009] Optionally, the fixed-frequency sampling and data filtering module is further configured to receive the sampling data from the sampling module and determine the valid data points in the sampling data corresponding to a preset target time based on the digital switch status signal and the conduction duration of the current switching cycle.

[0010] Optionally, the switch status signal extraction module includes a high-voltage clamping circuit and a comparison and judgment circuit. The input side of the high-voltage clamping circuit is connected to both ends of the power semiconductor device under test, the output side of the high-voltage clamping circuit is connected to the input end of the comparison and judgment circuit, and the output end of the comparison and judgment circuit outputs the digital switch status signal. The high-voltage clamping circuit is used to acquire the voltage across the two ends of the power semiconductor device under test, and convert the voltage of the power semiconductor device under test in the off state into the withstand voltage of the comparison and judgment circuit. The comparison and judgment circuit is used to determine the digital switch status signal in the off state based on the withstand voltage greater than the preset voltage threshold. The comparison and judgment circuit is also used to determine the digital switch status signal in the on state based on the withstand voltage less than the preset voltage threshold.

[0011] Optionally, the device state duration acquisition module includes a counter and a counter, wherein the counter is used to acquire the digital switching state signal of the power semiconductor device under test within the preset time length according to a preset frequency; The statistician is used to summarize the count points in the continuous off state and the count points in the continuous on state collected by the counter, and to determine the on state duration, off state duration and switching cycle of the power semiconductor device under test in at least one switching cycle according to the preset frequency. The statistical unit is also used to determine the duty cycle of the power semiconductor device under test based on the counting points in the continuous off state and the counting points in the continuous on state. The statistical unit is also used to determine the midpoint of the conduction state duration as the valley position of the carrier of the drive signal of the power semiconductor device under test, and to determine the midpoint of the off state duration as the peak position of the carrier of the drive signal of the power semiconductor device under test, thereby determining the restored carrier waveform of the drive signal of the power semiconductor device under test.

[0012] Optionally, the device state duration prediction module is further configured to construct a difference prediction algorithm based on the duration of the on-state and the duration of the off-state in adjacent switching cycles. The difference prediction algorithm based on the duration of the on-state and the duration of the off-state in adjacent switching cycles includes a first difference prediction algorithm and a second difference prediction algorithm. When the switching frequency of the power semiconductor device under test is greater than a preset first threshold, the conduction duration of the current switching cycle is predicted using the first difference prediction algorithm:

[0013] in, This indicates the duration of the on-state in the current switching cycle. Indicates the duration of the switching cycle. Indicates the duration of the off state in the previous switching cycle; When the switching frequency of the power semiconductor device under test is less than the preset first threshold and greater than the preset second threshold, the second difference prediction algorithm is used to predict the conduction duration of the current switching cycle:

[0014] in, This indicates the duration of the on-state in the current switching cycle. This indicates the duration of the switching cycle. This indicates the duration of the off state in the previous switching cycle. This indicates the duration of the conduction state in the previous switching cycle.

[0015] Optionally, if the conduction duration of the current switching cycle is greater than the sum of a preset first time constant and a preset second time constant, the sampling time determined by the sampling time setting module includes the sampling time at the end of conduction, and the preset time interval is:

[0016] in, This indicates the preset time interval. This indicates the duration of the on-state in the current switching cycle. This represents the preset first time constant; If the conduction duration of the current switching cycle is greater than twice the maximum value of the preset first time constant and the preset second time constant, the sampling time determined by the sampling time setting module includes the sampling time of the conduction midpoint carrier valley value, and the preset time interval is:

[0017] in, This indicates the preset time interval. This indicates the duration of the conduction state in the current switching cycle.

[0018] Optionally, the sampling module performs the sampling value conversion operation after a preset time delay after detecting the sampling trigger signal. The preset time represents the time delay between the sampling module sampling the physical quantity of the power semiconductor device under test and the sampling value conversion output.

[0019] Optionally, the sampled physical quantities of the power semiconductor device under test include at least one of voltage, current, on-state voltage drop, and temperature.

[0020] The self-triggered synchronous sampling system based on switch information reconstruction in this application uses a switch state signal extraction module to convert the voltage across the power semiconductor device under test into a digital switch state signal. A device state duration acquisition module determines the conduction duration, off-state duration, and switch cycle within at least one switching cycle based on the digital switch state signal. A conduction duration prediction module predicts the conduction duration of the current switching cycle. A sampling time setting module determines at least one sampling time from the predicted conduction duration of the current switching cycle, or a fixed-frequency sampling and data filtering module generates a fixed-frequency sampling trigger time. The sampling module automatically sends a sampling trigger signal and samples when the sampling time or fixed-frequency sampling trigger timing is reached. It does not require direct acquisition of the drive signal. It can reconstruct the switching state based solely on the voltage across the power semiconductor device under test, restore the on-state duration, off-state duration, and switching cycle of the device, and thus determine the sampling time. It realizes the automatic generation of the sampling trigger signal without relying on the drive signal carrier, and achieves sampling during the conduction period of the power semiconductor device under test. It significantly improves the accuracy and reliability of synchronous sampling of the power semiconductor device under test while ensuring insulation isolation. Moreover, it has a simple structure and a wide range of topological applications.

[0021] Other technical effects resulting from the additional features will be further illustrated in the corresponding embodiments. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram illustrating the structure of a self-triggered synchronous sampling system based on switch information restoration according to an exemplary embodiment. Detailed Implementation

[0023] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0024] In the description of the embodiments in this application, "multiple" means two or more, unless otherwise explicitly specified. In this application, unless otherwise explicitly specified and limited, the terms "installed," "connected," "linked," "fixed," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or devices.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0027] Existing synchronous sampling schemes for converters rely on directly acquiring the drive signals of power semiconductor devices. Sampling trigger commands are generated based on the rising edge, falling edge, or specific phase of the drive signal, making them highly dependent on the drive signal. Existing schemes that achieve synchronous sampling through interval detection, such as current zero-crossing detection, are susceptible to harmonic interference and have poor reliability under non-sinusoidal operating conditions. Voltage ripple analysis methods, on the other hand, rely on precise filtering algorithms, are sensitive to hardware noise, and cannot effectively reconstruct carrier peak and valley positions, making it difficult to meet high-precision sampling requirements. Based on these problems, this application provides a self-triggered synchronous sampling system based on switch information reconstruction to solve the aforementioned issues.

[0028] Figure 1 This is a schematic diagram illustrating the structure of a self-triggered synchronous sampling system based on switch information restoration according to an exemplary embodiment.

[0029] Reference Figure 1 As shown in one embodiment of this application, a self-triggering synchronous sampling system based on switch information restoration is provided, including: a switch state signal extraction module, a device state duration acquisition module, a conduction state duration prediction module, a sampling time setting module, a fixed frequency sampling and data filtering module, and a sampling module.

[0030] The switch status signal extraction module is used to acquire the voltage across the two ends of the power semiconductor device under test and convert it into a digital switch status signal.

[0031] The device state duration acquisition module is used to determine the on-state duration, off-state duration, and switching cycle within at least one switching cycle based on the digital switch state signal within a preset time length.

[0032] Specifically, the conduction duration is expressed as: The duration of the shutdown state is expressed as The switching period is expressed as .

[0033] The preset time length includes one or more switching cycles, wherein a switching cycle is defined as the time interval between two adjacent on or off moments.

[0034] The on-state duration prediction module is used to predict the on-state duration of the current switching cycle based on the off-state duration of the previous switching cycle and or the switching parameters of the power semiconductor devices in phase with the power semiconductor device under test.

[0035] The sampling time setting module is used to determine at least one sampling time within the conduction duration of the current switching cycle based on a preset time interval.

[0036] The fixed-frequency sampling and data filtering module is used to generate the fixed-frequency sampling trigger timing sequence.

[0037] The sampling module is used to send a sampling trigger signal and perform sampling when the sampling time or the fixed-frequency sampling trigger sequence is reached.

[0038] Specifically, the sampling module sends a sampling trigger signal to the power semiconductor device under test and then samples it.

[0039] The embodiments described above employ a switch state signal extraction module to convert the voltage across the power semiconductor device under test into a digital switch state signal. A device state duration acquisition module determines the conduction duration, off-state duration, and switch cycle within at least one switching cycle based on the digital switch state signal. A conduction duration prediction module predicts the conduction duration of the current switching cycle. A sampling time setting module determines at least one sampling time from the predicted conduction duration of the current switching cycle, or a fixed-frequency sampling and data filtering module generates a fixed-frequency sampling trigger sequence. A sampling module automatically issues a sampling trigger signal and samples upon reaching the sampling time or the fixed-frequency sampling trigger sequence. This eliminates the need for direct acquisition of a drive signal. It reconstructs the switch state based solely on the voltage across the power semiconductor device under test, restoring the conduction duration, off-state duration, and switch cycle, thereby determining the sampling time. This achieves automatic generation of a sampling trigger signal without relying on a drive signal carrier, enabling sampling during the conduction period of the power semiconductor device under test. While ensuring insulation isolation, this significantly improves the accuracy and reliability of synchronous sampling of the power semiconductor device under test. Furthermore, the structure is simple and the topology has a wide range of applications.

[0040] In some specific embodiments of this application, the switch state signal extraction module includes a high-voltage clamping circuit and a comparison and judgment circuit. The input side of the high-voltage clamping circuit is connected to both ends of the power semiconductor device under test, and the output side of the high-voltage clamping circuit is connected to the input end of the comparison and judgment circuit. The output end of the comparison and judgment circuit outputs a digital switch state signal.

[0041] The high-voltage clamping circuit is used to acquire the voltage across the two ends of the power semiconductor device under test and convert the voltage of the power semiconductor device under test in the off state into the withstand voltage of the comparison and judgment circuit.

[0042] Specifically, the high-voltage clamping circuit is used to convert the high-voltage voltage of the power semiconductor device under test in the off state into a lower withstand voltage that the comparison and judgment circuit can withstand.

[0043] Among them, the high voltage of the power semiconductor device under test in the off state is a strong voltage of more than 100V, and the lower withstand voltage that the circuit can withstand is a signal level voltage of less than 10V.

[0044] The comparison and judgment circuit is used to determine the digital switch status signal in the off state based on the withstand voltage greater than the preset voltage threshold. The comparison and judgment circuit is also used to determine the digital switch status signal in the on state based on the withstand voltage less than the preset voltage threshold.

[0045] Specifically, the comparison and judgment circuit is used to detect the input voltage. When the input voltage is greater than a preset voltage threshold, it determines that the power semiconductor device under test is in the off state and generates a digital switch status signal indicating that it is in the off state. When the input voltage is less than the preset voltage threshold, it determines that the power semiconductor device under test is in the on state and generates a digital switch status signal indicating that it is in the on state.

[0046] In the above embodiments of this application, the voltage across the two ends of the power semiconductor device under test is acquired through a high-voltage clamping circuit and a comparison and judgment circuit, and high-voltage clamping and comparison and judgment are performed. The rapidly changing high and low voltages across the two ends of the power semiconductor device under test are converted into digital switch status signals that characterize whether the power semiconductor device under test is in a conducting or turning-off state.

[0047] In order to obtain the device state duration, in some specific embodiments of this application, the device state duration acquisition module includes a counter and a counter. The counter is used to collect the digital switching state signal of the power semiconductor device under test within a preset time length according to a preset frequency.

[0048] Specifically, the preset frequency is expressed as The counter operates at the preset frequency. As a constant frequency, with a fixed time interval The switching state signal of the power semiconductor device under test is sampled to obtain the sampling points of the signal in the on state and the sampling points of the signal in the off state.

[0049] The statistician is used to summarize the count points collected by the counter that are in a continuous off state and the count points that are in a continuous on state, and to determine the on state duration, off state duration and switching cycle of the power semiconductor device under test in at least one switching cycle according to the preset frequency.

[0050] Specifically, the count points in a continuously off state are represented as: The counting points that are in a continuously conducting state are represented as .

[0051] Counting points in a continuously off state Multiply by the counting period 1 / Obtain the duration of device shutdown state .

[0052] Counting points in a continuously conducting state Multiply by the counting period 1 / Obtain the duration of device conduction state .

[0053] The switching cycle is: .

[0054] The counter is also used to determine the duty cycle of the power semiconductor device under test based on the count points that are in a continuous off state and the count points that are in a continuous on state.

[0055] Specifically, the duty cycle of the semiconductor device under test is:

[0056] in, This indicates the duty cycle of the semiconductor device under test. This indicates the count points collected by the counter that are in a continuously off state. This indicates the counting points that are continuously on, collected by the counter.

[0057] The statistical analyzer is also used to determine the midpoint of the on-state duration as the valley position of the carrier wave of the drive signal of the power semiconductor device under test, and to determine the midpoint of the off-state duration as the peak position of the carrier wave of the drive signal of the power semiconductor device under test, thereby determining the carrier waveform of the drive signal of the power semiconductor device under test in the restored drive signal.

[0058] In the above embodiments of this application, the device state duration acquisition module uses a counter to sample the count points of continuous on-state and continuous off-state. The statistician obtains the on-state duration, off-state duration, and switching cycle within one cycle based on the count points of continuous on-state and continuous off-state sampled by the counter. Without relying on the carrier wave of the drive signal, it restores the duty cycle of the power semiconductor device under test and the peak and valley positions of the carrier waveform of the drive signal based only on the voltage across the two ends of the power semiconductor device under test.

[0059] To achieve the prediction of the conduction state duration, in some specific embodiments of this application, the conduction state duration prediction module is also used to construct a difference prediction algorithm based on the conduction state duration and the off state duration of adjacent switch cycles. The difference prediction algorithm based on the conduction state duration and the off state duration of adjacent switch cycles includes a first difference prediction algorithm and a second difference prediction algorithm.

[0060] Each time the power semiconductor device under test ends its continuous off state and enters its continuous on state, the switching cycle determined by the device state duration acquisition module and the off state duration of the previous switching cycle or the switching parameters of the power semiconductor device in phase with the power semiconductor device under test are used to predict the next on state duration of the power semiconductor device under test using either the first difference prediction algorithm or the second difference prediction algorithm.

[0061] Specifically, when the switching frequency of the power semiconductor device under test is greater than a preset first threshold, the conduction duration of the current switching cycle is predicted using a first difference prediction algorithm:

[0062] in, Indicates the duration of the on-state in the current switching cycle. Indicates the switching cycle. This indicates the duration of the off state in the previous switching cycle.

[0063] When the switching frequency of the power semiconductor device under test is greater than the preset first threshold, the conduction duration of the power semiconductor device under test in adjacent switching cycles is approximately regarded as equal, and the conduction duration of the current switching cycle is predicted to be equal to the conduction duration of the previous switching cycle. The first difference prediction algorithm is used to predict the conduction duration of the current switching cycle.

[0064] When the switching frequency of the power semiconductor device under test is less than a preset first threshold and greater than a preset second threshold, the conduction duration of the current switching cycle is predicted using a second difference prediction algorithm:

[0065] in, Indicates the duration of the on-state in the current switching cycle. Indicates the switching cycle. This indicates the duration of the off state in the previous switching cycle. This indicates the duration of the conduction state in the previous switching cycle.

[0066] Specifically, when the switching frequency of the power semiconductor device under test is less than a preset first threshold and greater than a preset second threshold, based on the characteristic that the turn-on and turn-off times of the power semiconductor device under test are approximately symmetrical with respect to the carrier peak and valley values ​​of the driving signal, the conduction duration of the current switching cycle satisfies a preset symmetrical difference relationship with the conduction duration of the previous switching cycle and the turn-off duration of the previous switching cycle. That is, the second difference prediction algorithm is used to predict the conduction duration of the current switching cycle.

[0067] In the embodiments described above, the conduction state duration prediction module predicts the conduction state duration of the current switching cycle by constructing a prediction algorithm based on the difference between the conduction state duration and the off state duration of adjacent switching cycles. This algorithm can predict the conduction duration of the current switching cycle quickly, accurately, and with low complexity, thereby improving the dynamic response speed, control accuracy, and stability of the system, and reducing switching losses.

[0068] To determine the sampling time, in some specific embodiments of this application, the sampling time setting module includes: Sampling includes end-of-conduction sampling and mid-conduction carrier valley sampling. Therefore, the sampling time includes the end-of-conduction sampling time and the mid-conduction carrier valley sampling time.

[0069] In some specific embodiments of this application, a non-negative time constant is determined, namely a preset first time constant. and the preset second time constant Preset first time constant To avoid errors in predicting the on-state duration causing the power semiconductor device under test to trigger sampling during the off-state, a preset second time constant is used. This is to avoid sampling at the moment the power semiconductor device under test is turned on if the sampling position is too close to the moment of conduction.

[0070] The preset first time constant and the preset second time constant are set according to the switching transient time of the power semiconductor device under test, so as to adapt to different topologies and operating modes of the converter.

[0071] In the end-of-conduction sampling mode, if the conduction duration of the current switching cycle is greater than the sum of the preset first time constant and the preset second time constant, the sampling time determined by the sampling time setting module includes the end-of-conduction sampling time, and the preset time interval is:

[0072] in, This indicates the preset time interval. Indicates the duration of the on-state in the current switching cycle. This represents the preset first time constant.

[0073] Specifically, the condition that the conduction duration of the current switching cycle is greater than the sum of a preset first time constant and a preset second time constant is:

[0074] In this embodiment, the preset time interval represents the time interval between the sampling moment at the end of the current conduction and the instant when the power semiconductor device under test is turned on.

[0075] In this embodiment, if the conduction state duration of the current switching cycle is not greater than the sum of a preset first time constant and a preset second time constant, then end sampling during the conduction period will not be performed.

[0076] In the midpoint carrier valley sampling mode during conduction, if the conduction duration of the current switching cycle is greater than twice the maximum value of the preset first time constant and the preset second time constant, the sampling time determined by the sampling time setting module includes the midpoint carrier valley sampling time, and the preset time interval is:

[0077] in, This indicates the preset time interval. This indicates the duration of the on-state during the current switching cycle.

[0078] In this embodiment, the preset time interval represents the time interval between the sampling time of the midpoint carrier valley value during this conduction and the instant when the power semiconductor device under test is turned on.

[0079] Specifically, the condition that the conduction duration of the current switching cycle is greater than twice the maximum value of the preset first time constant and the preset second time constant is:

[0080] In this embodiment, if the conduction state duration of the current switching cycle is not greater than twice the maximum value of the preset first time constant and the preset second time constant, then the midpoint carrier valley value sampling is not performed.

[0081] In the embodiments described above, a preset time interval is set between the sampling time and the instant the power semiconductor device under test transitions from an off state to an on state. This allows the sampling time to avoid the transient states of the power semiconductor device being tested during conduction and turn-off, and to cover the steady state of conduction or the carrier valley position at the midpoint of conduction.

[0082] To perform sampling, in some specific embodiments of this application, the sampling module includes a timer that starts timing the time interval after the power semiconductor device under test enters the on state. When the timing result reaches the time interval corresponding to the sampling time, a sampling trigger signal is automatically sent to the power semiconductor device under test and sampling is performed.

[0083] For example, the sampling physical quantities sampled by the sampling module for the power semiconductor device under test include at least one of voltage, current, on-state voltage drop, and temperature.

[0084] Those skilled in the art should understand that the physical quantities sampled by the power semiconductor device under test are not limited to the physical quantities mentioned above, and may also include other physical quantities.

[0085] In some specific embodiments of this application, the sampling module performs the sampling value conversion operation after a preset time delay after detecting the sampling trigger signal. The preset time represents the time delay between the sampling module sampling the physical quantity of the power semiconductor device under test and the output of the sampling value conversion.

[0086] Specifically, when the sampling module performs sample value conversion, it considers the time delay between the sampled physical quantity and the sample value conversion output. The delay occurs after the sampling module detects the sampling trigger signal. Then, the sampled value conversion output is performed to realize that the sampling result output by the sampling module corresponds to the measured physical quantity at the target sampling time.

[0087] The above embodiments of this application utilize a sampling trigger followed by a delay. Performing the conversion again can compensate for the inherent delay of the sampling module, so that the sampling result accurately corresponds to the measured physical quantity at the target sampling time, thereby improving sampling accuracy and control stability.

[0088] In some specific embodiments of this application, a self-triggering synchronous sampling system based on switch information restoration further includes an anomaly processing module. The anomaly processing module is used to replace the digital switch state signal of the power semiconductor device under test with the switch parameters of the power semiconductor device in phase with the power semiconductor device under test and with the same driving signal carrier when the on-state duration or off-state duration of the power semiconductor device under test is greater than a preset ratio of the switching cycle. The anomaly processing module then inputs the on-state duration prediction module to predict the on-state duration of the power semiconductor device under test in the current switching cycle.

[0089] Specifically, the switching parameters of the power semiconductor device under test, which is in phase and has the same driving signal carrier, are the on / off state signals of the power semiconductor device, which may include the on state duration, the off state duration, and the switching period.

[0090] Specifically, the anomaly handling module acquires the on-state duration and off-state duration of the power semiconductor device under test in real time and compares them with the switching cycle determined by the on-state duration prediction module.

[0091] For example, if the power semiconductor device under test is in a continuous on-state and its on-state duration is longer than the switching cycle, and / or the power semiconductor device under test is in a continuous off-state and its off-state duration is longer than the switching cycle, the prediction of the on-state duration of the current switching cycle using the digital switching state signal of the power semiconductor device under test and the prediction algorithm based on the difference between the on-state duration and off-state duration of adjacent switching cycles is stopped. At this time, if a power semiconductor device with the same power as the power semiconductor device under test and the same driving signal carrier is in normal working condition, the switching parameters of the power semiconductor device with the same power as the power semiconductor device under test and the same driving signal carrier are used as the carrier calculation basis to predict the on-state duration of the power semiconductor device under test in the current switching cycle, and the sampling time setting module is further used to determine the sampling time for self-triggered synchronous sampling.

[0092] When the in-phase power semiconductor device is also in a continuous on state and its on state duration is greater than the switching period and / or in a continuous off state and its off state duration is greater than the switching period, the power semiconductor device under test is in normal working condition, and the switching state signal of the power semiconductor device under test is used in reverse to provide a synchronous sampling basis for the in-phase power semiconductor device.

[0093] In the above embodiments of this application, when the conduction duration and / or off-state duration of the power semiconductor device under test are abnormal, the abnormality handling module replaces them with the switching state signal of the power semiconductor device under test that is in phase and has the same driving signal carrier. This enables the prediction of the conduction duration of the current switching cycle of the power semiconductor device under test and the calculation of the sampling time, thereby maintaining synchronous sampling.

[0094] In some specific embodiments of this application, a self-triggered synchronous sampling system based on switch information restoration further includes a fixed-frequency sampling and data filtering module, which is used to determine the fixed-frequency sampling trigger timing and send it to the sampling module when the switching frequency of the power semiconductor device under test is less than a preset second threshold, or when the abnormality handling module determines that the conduction state duration of the power semiconductor device under test is in an abnormal working state. The sampling module is used to send a sampling trigger signal to the power semiconductor device under test and sample when the sampling time corresponding to the fixed-frequency sampling trigger timing is reached.

[0095] Specifically, when the switching frequency of the power semiconductor device under test is less than the preset second threshold, it indicates that the switching frequency of the power semiconductor device under test is in a low switching frequency state, or the conduction duration of the power semiconductor device under test is greater than the preset ratio of the switching period. The sampling timing setting module is configured to a fixed frequency trigger mode. The sampling module continuously samples one or more of the voltage, current, on-state voltage drop and temperature of the power semiconductor device under test at a constant sampling frequency according to the fixed frequency sampling trigger timing sequence.

[0096] The fixed-frequency sampling and data filtering module is also used to receive the sampling data from the sampling module and determine the valid data points in the sampling data corresponding to the preset target time based on the digital switch status signal and the conduction duration of the current switching cycle.

[0097] Specifically, in the fixed-frequency trigger mode, the effective data points selected by the fixed-frequency sampling and data filtering module at the preset target time are data points near the conduction end or conduction midpoint of the power semiconductor device under test, and there can be one or more such data points.

[0098] The embodiments described above in this application, by employing a fixed-frequency sampling and data filtering module, can achieve the same sampling time restoration capability as the self-triggered synchronous sampling mode under low switching frequency operating conditions.

[0099] In some specific embodiments of this application, the sampling module further includes a sampling circuit for extracting switch status signals and sampling power, as well as auxiliary functional circuits such as power supply, optical isolation or magnetic isolation, conditioning and filtering, and hardware protection.

[0100] In some specific embodiments of this application, a self-triggering synchronous sampling system based on switch information restoration further includes a computation processing and storage module. This module includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When executing the computer program, the processor is configured to perform restoration processing of converter switch state information and self-triggering synchronous control of the sampling system, thereby outputting accurate switch state data and synchronous sampling control signals.

[0101] In some specific embodiments of this application, a self-triggered synchronous sampling system based on switch information restoration further includes a data acquisition, display, and user operation interface module. The data acquisition, display, and user operation interface module includes a field communication bus and a computer program. The field communication bus is used to acquire measured values ​​in real time and interact with an external monitoring system.

[0102] This application provides a self-triggered synchronous sampling system based on switch information restoration. It does not require direct acquisition of the drive signal; instead, it obtains the conduction duration, off-state duration, and switching cycle based solely on the voltage across the power semiconductor device under test (PSD). It also restores the duty cycle of the PSD and the peak and valley positions of the drive signal carrier. By constructing a prediction algorithm based on the difference between the conduction and off-state durations of adjacent switching cycles, it predicts the conduction duration of the current switching cycle each time the PSD transitions from off to on. It calculates the target sampling time near the valley value at the end of conduction or the midpoint of conduction and automatically sends a synchronous sampling trigger signal to the voltage, current, conduction voltage drop, or temperature sampling system. When the PSD is continuously on or off for an extended period, causing prediction anomalies, it can switch to using the switch information of the in-phase power semiconductor device to maintain carrier calculation and synchronous sampling. The system has a simple structure, wide applicability to various topologies, and can significantly improve the synchronous sampling accuracy and reliability of key physical quantities in converters while ensuring insulation isolation.

[0103] The specific embodiments of this application have been described above. It should be understood that this application is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the substantive content of this application. The above-described preferred features can be used in any combination without conflict.

Claims

1. A self-triggering synchronous sampling system based on switch information restoration, characterized in that, include: The switch status signal extraction module is used to acquire the voltage across the two ends of the power semiconductor device under test and convert it into a digital switch status signal; The device state duration acquisition module is used to determine the on-state duration, off-state duration, and switching cycle within at least one switching cycle based on the digital switch state signal within a preset time length. The on-state duration prediction module is used to predict the on-state duration of the current switching cycle based on the off-state duration of the previous switching cycle or the switching parameters of the power semiconductor device in phase with the power semiconductor device under test. The sampling time setting module is used to determine at least one sampling time in the conduction state duration of the current switching cycle according to a preset time interval. The fixed-frequency sampling and data filtering module is used to generate the fixed-frequency sampling trigger timing sequence. The sampling module is used to send a sampling trigger signal and perform sampling when the sampling time or the fixed-frequency sampling trigger timing is reached.

2. The self-triggered synchronous sampling system based on switch information restoration according to claim 1, characterized in that, It also includes an anomaly handling module, which is used to replace the digital switch state signal of the power semiconductor device under test with the switch parameters of a power semiconductor device that is in phase with the power semiconductor device under test and has the same driving signal carrier when the on-state duration or off-state duration of the power semiconductor device under test is greater than a preset proportion of the switching cycle. The anomaly handling module is then input into the on-state duration prediction module to predict the on-state duration of the power semiconductor device under test in the current switching cycle.

3. The self-triggered synchronous sampling system based on switch information restoration according to claim 2, characterized in that, The fixed-frequency sampling and data filtering module is used to determine the fixed-frequency sampling trigger timing and send it to the sampling module when the switching frequency of the power semiconductor device under test is less than a preset second threshold, or when the anomaly handling module determines that the conduction duration of the power semiconductor device under test is in an abnormal working state. The sampling module is used to send a sampling trigger signal to the power semiconductor device under test and sample when the sampling time corresponding to the fixed-frequency sampling trigger timing is reached.

4. The self-triggered synchronous sampling system based on switch information restoration according to claim 3, characterized in that, The fixed-frequency sampling and data filtering module is also used to receive the sampling data from the sampling module, and determine the valid data points in the sampling data corresponding to the preset target time according to the digital switch status signal and the conduction duration of the current switching cycle.

5. The self-triggered synchronous sampling system based on switch information restoration according to claim 1, characterized in that, The switch status signal extraction module includes a high-voltage clamping circuit and a comparison and judgment circuit. The input side of the high-voltage clamping circuit is connected to both ends of the power semiconductor device under test, and the output side of the high-voltage clamping circuit is connected to the input end of the comparison and judgment circuit. The output end of the comparison and judgment circuit outputs the digital switch status signal. The high-voltage clamping circuit is used to acquire the voltage across the two ends of the power semiconductor device under test, and convert the voltage of the power semiconductor device under test in the off state into the withstand voltage of the comparison and judgment circuit. The comparison and judgment circuit is used to determine the digital switch status signal in the off state based on the withstand voltage greater than the preset voltage threshold. The comparison and judgment circuit is also used to determine the digital switch status signal in the on state based on the withstand voltage less than the preset voltage threshold.

6. The self-triggered synchronous sampling system based on switch information restoration according to claim 1, characterized in that, The device status duration acquisition module includes a counter and a statistician. The counter is used to collect the digital switching status signal of the power semiconductor device under test within the preset time length according to a preset frequency. The statistician is used to summarize the count points in the continuous off state and the count points in the continuous on state collected by the counter, and to determine the on state duration, off state duration and switching cycle of the power semiconductor device under test in at least one switching cycle according to the preset frequency. The statistical unit is also used to determine the duty cycle of the power semiconductor device under test based on the counting points in the continuous off state and the counting points in the continuous on state. The statistical unit is also used to determine the midpoint of the conduction state duration as the valley position of the carrier of the drive signal of the power semiconductor device under test, and to determine the midpoint of the off state duration as the peak position of the carrier of the drive signal of the power semiconductor device under test, thereby determining the restored carrier waveform of the drive signal of the power semiconductor device under test.

7. The self-triggered synchronous sampling system based on switch information restoration according to claim 1, characterized in that, The on-state duration prediction module is also used to construct a difference prediction algorithm based on the on-state duration and off-state duration of adjacent switch cycles. The difference prediction algorithm based on the on-state duration and off-state duration of adjacent switch cycles includes a first difference prediction algorithm and a second difference prediction algorithm. When the switching frequency of the power semiconductor device under test is greater than a preset first threshold, the conduction duration of the current switching cycle is predicted using the first difference prediction algorithm: ； in, This indicates the duration of the on-state in the current switching cycle. Indicates the duration of the switching cycle. Indicates the duration of the off state in the previous switching cycle; When the switching frequency of the power semiconductor device under test is less than the preset first threshold and greater than the preset second threshold, the second difference prediction algorithm is used to predict the conduction duration of the current switching cycle: ； in, This indicates the duration of the on-state in the current switching cycle. This indicates the duration of the switching cycle. This indicates the duration of the off state in the previous switching cycle. This indicates the duration of the conduction state in the previous switching cycle.

8. The self-triggered synchronous sampling system based on switch information restoration according to claim 1, characterized in that, If the conduction duration of the current switching cycle is greater than the sum of a preset first time constant and a preset second time constant, the sampling time determined by the sampling time setting module includes the sampling time at the end of conduction, and the preset time interval is: ； in, This indicates the preset time interval. This indicates the duration of the on-state in the current switching cycle. This represents the preset first time constant; If the conduction duration of the current switching cycle is greater than twice the maximum value of the preset first time constant and the preset second time constant, the sampling time determined by the sampling time setting module includes the sampling time of the conduction midpoint carrier valley value, and the preset time interval is: ； in, This indicates the preset time interval. This indicates the duration of the conduction state in the current switching cycle.

9. The self-triggered synchronous sampling system based on switch information restoration according to claim 1, characterized in that, The sampling module performs the sampling value conversion operation after a preset time delay after detecting the sampling trigger signal. The preset time represents the time delay between the sampling module sampling the physical quantity of the power semiconductor device under test and the output of the sampling value conversion.

10. The self-triggered synchronous sampling system based on switch information restoration according to claim 1, characterized in that, The sampled physical quantities of the power semiconductor device under test include at least one of voltage, current, on-state voltage drop, and temperature.

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