An FPGA-based SSD controller verification method and system

Abstract

The application relates to the field of computer storage, and discloses an FPGA-based SSD controller verification method and system, which aims to solve the problems of hardware redundancy, non-systematic verification and poor flexibility of a verification scheme in a high-integration board card environment. Technical solution points: the verification method is divided into three stages, that is, first, a hardware environment is constructed through FPGA integration verification, then, basic functions and performance are tested through data disk verification, and finally, system-level testing and version solidification are completed through system disk verification; the verification system comprises a host computer and an integrated board card, and an FPGA module integrates an SSD controller and network interface function logic. The application does not require additional hardware, realizes low-cost and systematic comprehensive verification, and is suitable for function and performance verification of an SSD controller in a high-integration board card environment.

Description

Technical Field

[0001] This invention mainly relates to the field of computer storage, and specifically to an FPGA-based SSD controller verification method and system. Background Technology

[0002] The increasing intelligence of aerial platforms such as drones has led to increasingly complex mission workloads, placing higher demands on the real-time processing capabilities, energy efficiency, and reliability of airborne computing systems. Under these constraints, computable storage technology, by embedding computing power within memory to achieve "data processing nearby," can significantly reduce latency and power consumption caused by data movement, effectively alleviating the bottleneck of host processor computing power, and becoming one of the key technological paths to improve the overall system performance. For example, transparent compression can improve storage space utilization, or preprocessing units can accelerate the response of critical tasks.

[0003] Flash-based solid-state drives (SSDs) are ideal for computational storage due to their high bandwidth and large capacity, with computing power provided by the SSD controller. To flexibly adapt to various computing functions in embedded scenarios (such as transparent compression and real-time encryption / decryption), implementing the SSD controller using a field-programmable gate array (FPGA) is one of the mainstream solutions.

[0004] The functional and performance verification of the SSD controller is crucial. Its verification involves not only the correctness of the interface logic, but also the system level. For example, it verifies whether the operating system can correctly read and write the data disk, or whether the operating system can be booted as the system disk. In order to meet the stringent requirements of embedded scenarios for size and power consumption, computing systems often adopt a highly integrated design, integrating the processor, memory, storage chips and FPGA-based SSD controllers on the same board. In this integrated environment, the verification of the SSD controller faces new challenges. At present, there are two main publicly available feasible verification schemes: (1) The scheme of reserving an external high-speed interface, which reserves an independent high-speed interface (such as PCIe) for the SSD controller on the board and tests it by connecting to a host computer. Although this scheme can access the controller, it introduces additional hardware overhead and cannot truly simulate the interconnection and access scenario between the processor and the controller inside the board. (2) The scheme of using a commercial SSD, which reserves a standard SSD installation slot on the board and runs the test operating system through a commercial SSD. This scheme is expensive, has hardware redundancy, and requires a dedicated processor or occupies the high-speed interface of the onboard processor.

[0005] In summary, the existing technology has the following defects: (1) High implementation cost, requiring additional hardware resources to be reserved, increasing design cost and complexity; (2) Unsystematic verification, making it difficult to verify the complete data path of "processor-memory-FPGA controller-storage particle" within the board; (3) Insufficient flexibility, making it difficult to support customized verification needs for custom storage protocols or basic software such as bootloaders and operating system kernels that need to be modified.

[0006] Therefore, there is an urgent need in this field for a verification method and system for SSD controllers in highly integrated board environments, which can achieve systematic functional and performance verification in a low-cost and highly flexible manner. Summary of the Invention

[0007] (a) Technical problems to be solved This invention aims to solve the technical problems of existing SSD controller verification schemes, such as high implementation cost, increased design cost and complexity due to the need to reserve additional hardware resources, inability of verification system to cover the complete data path of "processor-memory-FPGA controller-storage chip", and lack of flexibility to support customized verification needs such as custom storage protocols and basic software modifications.

[0008] (II) Technical Solution To address the aforementioned issues, this invention proposes an FPGA-based SSD controller verification method and system. This eliminates the need to reserve additional high-speed test interfaces or commercial SSD mounting slots on the integrated board, enabling comprehensive and systematic verification of everything from underlying hardware functions to upper-level system collaboration directly within the board environment.

[0009] 1. FPGA-based SSD controller verification method This method is a phased, layer-by-layer verification approach that fully utilizes the programmable nature of FPGAs to construct a flexible, self-contained verification environment on an integrated board. The integrated board integrates at least a processor module, memory module, firmware module, FPGA module, and storage chips, and provides necessary peripherals such as network interfaces, serial printer ports, firmware loading interfaces, and FPGA debug ports. The core of the method lies in integrating network interface functional logic within the FPGA and having it work collaboratively with the functional logic of the SSD controller to be verified, establishing a communication foundation for subsequent verification stages. Specifically, it includes the following three verification stages: Figure 1 As shown: S1 FPGA Integration Verification: The goal is to prepare the hardware environment for system-level verification. This involves integrating the network interface logic and SSD controller logic within the FPGA. The network interface logic enables a high-speed data channel between the processor and the FPGA. This can be implemented as a complete soft-core network controller implemented entirely by the FPGA, or, if the processor itself has a network controller, as a bridge between the processor's internal network interface and the board's physical network interface. After integration, it's crucial to ensure that the bootloader running the processor can correctly identify and drive the network interface, thus enabling network boot capability. This step corresponds to... Figure 1 Step 101 in the text.

[0010] S2 Data Disk Verification: The goal is to quickly boot an operating system environment while minimizing board environment dependencies, to verify the basic, full functionality, and performance of the SSD controller's data disk. This step corresponds to step 102 in Figure 1, and is specifically executed according to the 5 steps in Figure 2: S21 creates a simplified operating system: Based on the size of the memory module, unnecessary default installation tools are removed from the complete operating system image file, while basic tools (such as FTP) are retained, and the file system supports a memory virtual disk (ramdisk); at the same time, the operating system kernel image (such as the Linux kernel), the device tree, and the simplified file system are stored on the host computer, the bootloader is modified, and the above files are read from the host computer to the memory module via the network using the TFTP protocol and loaded, and finally the simplified operating system is started.

[0011] S22 Deployment of Cross-Compilation Environment: Deploy the cross-compilation environment on the host computer. On the one hand, compile and generate loadable kernel drivers. On the other hand, use the same kernel source code compilation and testing tools as the simplified operating system (such as FIO, iozone) to generate executable files and confirm the required dynamic runtime libraries.

[0012] S23 Network File Upload: Upload the cross-compiled kernel driver, test tool executable files, and required dynamic runtime libraries to the simplified operating system running in the memory module via the network port.

[0013] S24 Verification Tool Operation: Install the kernel driver in the simplified operating system, check and verify whether the testing tool can run correctly, and ensure that the test environment is ready.

[0014] S25 performs functional and performance tests: Functional correctness is verified through system commands, including using the `lspci` command to check if the SSD controller correctly responds to basic information, using the `lsblk` command to view block device information, and verifying the basic functions of the firmware program running on the SSD controller by creating file directories and files, modifying or deleting files; the complete functionality and performance of the SSD as a data disk are tested by running testing tools.

[0015] S3 System Disk Verification: The goal is to confirm that the SSD controller can be used as a reliable system disk and to perform systemic stress testing on the entire integrated board. This step corresponds to step 103 in Figure 1, and is specifically performed according to the 6 steps in Figure 3: S31 Bootloader Creation: Adapted for integrated board environments, the key is to install relevant drivers in the bootloader to automatically identify hard drive block size and ensure compatibility between the bootloader and the board and SSD.

[0016] Creating an operating system image for S32: Adapting to integrated board environments and actual application needs, with a focus on installing relevant drivers and default tools in the operating system image to ensure the normal operation of the operating system on the board.

[0017] S33 Installation System Disk: Runs a simplified operating system that boots via the network port. Uploads the prepared operating system image to the memory module, then decompresses and installs it onto the recognized SSD, completing the deployment of the system disk.

[0018] S34 conducts system disk testing: First, functional tests are performed, including at least file read / write, application installation, and abnormal power failure tests, to verify the basic usability of the system disk; then, performance tests are performed, including at least read / write stress and stress test, to verify the stable operation capability of the system disk.

[0019] S35 version solidification: After the system disk passes the test, a stable version is solidified, the SSD controller firmware is solidified to the firmware module, and the FPGA integrated bitstream is solidified to the FPGA module; at the same time, the operating system image is reinstalled on the SSD and set to start automatically upon power-on to ensure that the board can run independently.

[0020] S36 performs regression testing: For the integrated board after the version is solidified, repeat the system disk testing steps of S34, and conduct functional and performance tests again to ensure that the solidified version is stable and reliable and that the verification results are consistent.

[0021] 2. FPGA-based SSD controller verification system To implement the above method, the system proposed in this invention consists of a host computer and integrated circuit boards, such as... Figure 4 As shown:

[0022] The host computer plays a support and configuration role, specifically including: storing bootloader files and network operating system files, providing a cross-compilation environment to generate test tools, and connecting and communicating with integrated boards via network and serial ports.

[0023] Integrated circuit boards, serving as both the test object and the verification execution entity, mainly include processor modules, firmware modules, memory modules, FPGA modules, and storage chips.

[0024] The processor module is used to execute bootloader, operating system, and application instructions.

[0025] The firmware module stores the initial bootloader required for startup and can be accessed and updated.

[0026] The memory module provides dynamic data storage space for system operation.

[0027] The FPGA module is the core of this system. Its internal programming integrates the functional logic of the SSD controller and the functional logic of the network interface. It is responsible for data processing and interacts with the processor and the host computer.

[0028] The storage particles are managed by the SSD controller functional logic in the FPGA module, providing high-capacity non-volatile storage for the operating system, applications, and user data.

[0029] (III) Beneficial Effects Compared with the prior art, the present invention has the following beneficial effects: (1) High integration and low cost: Make full use of the existing resources of the board and integrate network logic in the FPGA to eliminate the need for expensive external test interfaces or spare SSDs, which significantly reduces the hardware cost and design complexity of verification.

[0030] (2) Systematic verification: Through three progressive stages, systematic verification was achieved from the internal logic of the FPGA and the basic functions of the SSD to the entire data path of "processor-memory-FPGA controller-storage particle".

[0031] (3) Highly flexible and scalable: The entire verification environment is built on software and FPGA programmability, which can quickly adapt to custom storage protocols and support convenient modification and testing of basic software such as bootloaders and operating system kernels, which greatly improves verification efficiency and flexibility. Attached Figure Description

[0032] Figure 1This is a flowchart of the overall verification process for an FPGA-based SSD controller; Figure 2 This is a flowchart of the data disk debugging and verification process; Figure 3 This is a flowchart of the system disk debugging and verification process; Figure 4 This is a diagram of the FPGA-based SSD controller verification system. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Embodiment 1 of this application provides an overall verification process for an FPGA-based SSD controller, such as... Figure 1 As shown, the steps of the processing flow are as follows: 101. Conduct FPGA integration verification, integrate the network interface functional logic with the SSD controller functional logic, and ensure that the processor module can communicate with the host computer via the logic within the FPGA.

[0035] 102. Conduct data disk verification, set up the host computer, prepare the operating system kernel image, device tree and simplified file system, load the simplified operating system into the memory module through the network interface and use the operating system to conduct verification.

[0036] 103. Conduct system disk verification, complete system disk installation, carry out relevant tests, solidify stable version, and finally conduct regression testing.

[0037] Embodiment 2 of this application provides a data disk debugging and verification process, which is an extended and refined process of the debugging and verification part in step 102, such as... Figure 2 As shown, the steps of the processing flow are as follows: 201. Create a simplified operating system. Based on the memory module size, remove unnecessary default installation tools from the complete operating system image file, and keep the basic tools (such as FTP).

[0038] 202. Deploy a cross-compilation environment. The first step is to compile and generate a loadable kernel driver. The second step is to compile and test tools to generate an executable file and confirm the required dynamic runtime libraries.

[0039] 203 is a simplified operating system that uploads kernel drivers, test tool executables, and dynamic runtime libraries to memory via the network.

[0040] 204. Install the kernel driver and verify that the testing tools are running correctly.

[0041] 205. Conduct functional performance tests: including the basic functional correctness of the firmware program running on the SSD controller, and the complete functionality and performance of the SSD as a data disk.

[0042] Embodiment 3 of this application provides a system disk debugging and verification process, which is an extended and refined process of the debugging and verification part in step 103, such as... Figure 3 As shown, 301. Create a bootloader to adapt to the integrated board environment, complete the installation of relevant drivers and identification of hard disk block size.

[0043] 302. Create an operating system image, adapt it to the integrated board environment and application requirements, and complete the installation of relevant drivers and default tools.

[0044] 303. Install the system disk, run the simplified operating system booted from the network port, upload the operating system image and extract and install it to the SSD.

[0045] 304 indicates that system disk-related tests are being conducted. The first test includes functional tests such as file reading and writing, application installation, and abnormal power failure. The second test includes performance tests such as read / write stress and stress testing.

[0046] 305. To solidify the version, the first step is to solidify the SSD controller firmware and FPGA integrated bitstream into the corresponding module of the board; the second step is to complete the system disk installation and set it to start automatically upon power-on.

[0047] 306. Perform regression testing, repeat step 304, and perform system disk testing again.

[0048] Embodiment 4 of this application provides an FPGA-based SSD controller verification system, such as... Figure 4 As shown, the host computer and integrated circuit board are configured. The integrated circuit board includes a processor module, firmware module, memory module, FPGA module, and storage chips. The host computer connects to the integrated board, accesses the firmware module of the integrated board through the firmware loading interface, interacts with the integrated board through the network interface, receives the debugging output information of the integrated board through the serial port, and downloads the bitstream file to the FPGA module of the integrated board through the FPGA debugging interface.

[0049] The processor module is connected to the firmware module, memory module, and FPGA module. The processor module reads the bootloader from the firmware module, can communicate and transmit data with the host computer via the FPGA module, can read and write data to the memory module, and can read data from the storage chip via the FPGA module.

[0050] The FPGA module connects to the processor module, firmware module, and storage chips. It also connects to the network interface and FPGA debugging interface of the integrated board. It mainly runs the SSD controller function logic and network interface function logic. It can read the SSD controller firmware program from the firmware module and complete the processor module's access to the board's external network port and storage chips.

Claims

1. A verification method for an SSD controller based on an FPGA, characterized in that, This method is applied to a verification system that includes a host computer and an integrated circuit board. The integrated circuit board integrates at least a processor module, a memory module, a firmware module, an FPGA module, and storage chips. The method consists of three progressive stages, specifically including: The S1 FPGA integration verification integrates the network interface functional logic and the SSD controller functional logic within the FPGA module. The network interface functional logic is used to realize a high-speed data channel between the processor module and the FPGA module, ensuring that the bootloader running on the processor module can correctly identify and drive the network interface, enabling the processor module to have network boot capability. S2 data disk verification involves five steps to verify the data disk functionality and performance of the SSD controller. S3 system disk verification involves six steps to verify the SSD controller as a system disk, as well as version fixing and regression testing.

2. The verification method according to claim 1, characterized in that, The network interface function logic in S1 is either a soft-core network controller implemented by the FPGA module, or, when the processor module has a network controller, it enables the bridging function between the internal network interface of the processor module and the physical network interface of the board.

3. The verification method according to claim 1, characterized in that, The five steps of S2 are as follows: S21 creates a simplified version of the operating system by removing unnecessary default installation tools from the complete operating system image file based on the memory module size, while retaining basic tools and supporting memory virtual disks. S22 deploys a cross-compilation environment, compiles and generates loadable kernel drivers and test tool executables, and confirms the required dynamic runtime libraries; S23 is a simplified operating system that uploads kernel drivers, test tool executables, and dynamic runtime libraries to a memory module via a network for execution. S24 installs the kernel driver and verifies that the testing tools are running correctly. The S25 performs functional and performance tests to verify the basic functions of the SSD controller firmware and the full functionality and performance of the SSD as a data drive.

4. The verification method according to claim 3, characterized in that, The simplified version of the S21 operating system modifies the bootloader and uses the TFTP protocol to read the operating system kernel image and device tree from the host computer before loading and starting.

5. The verification method according to claim 3, characterized in that, Functional verification in S25 includes viewing basic SSD controller information using the lspci command, viewing block device information using the lsblk command, and verifying basic firmware functions through file creation, modification, and deletion operations. Performance verification is implemented using FIO or iozone testing tools, which are compiled from the same kernel source code as the simplified operating system by the host computer's cross-compilation environment.

6. The verification method according to claim 1, characterized in that, The six steps of S3 are as follows: S31 creates a bootloader that is adapted for integrated circuit board environments, installs relevant drivers, and automatically identifies hard disk block size. S32 creates an operating system image, adapts it to integrated board environments and application requirements, and installs relevant drivers and default tools; The S33 runs a simplified operating system booted from the network port, uploads the operating system image, and extracts and installs it to the SSD; S34 conducts system disk testing, including functional tests such as file reading and writing, application installation, and abnormal power failure, as well as performance tests such as read and write stress and stress test. The S35 is version-fixed by fixing the SSD controller firmware and FPGA integrated bitstream to the corresponding module, reinstalling the operating system image and setting it to start automatically upon power-on. S36 Repeat the test steps in S34 to complete the regression test.

7. The verification method according to claim 1, characterized in that, In S33, the operating system image is uploaded and decompressed via a memory module and installed onto the SSD.

8. The verification method according to claim 1, characterized in that, In the S35, the FPGA integrates the bitstream and embeds it into the FPGA module, while the SSD controller firmware is embedded into the firmware module.

9. The verification method according to claim 1, characterized in that, The dynamic runtime library in S25 is uploaded to the simplified operating system via the network port.

10. An FPGA-based SSD controller verification system for implementing the verification method according to any one of claims 1-9, characterized in that, The system includes a host computer and an integrated board. The integrated board comprises a processor module, firmware module, memory module, FPGA module, and storage chips. The host computer stores the bootloader file, operating system kernel image, device tree, and simplified file system, provides a cross-compilation environment, and communicates with the integrated board through a firmware loading interface, network interface, serial printer port, and FPGA debugging interface. The processor module connects to the firmware module, memory module, and FPGA module, and is used to execute the bootloader, operating system, and application instructions. It can communicate with the host computer via the network through the FPGA module, read and write data to the memory module, and access the storage chips through the FPGA module. The firmware module stores the initial bootloader and SSD controller firmware required for startup and can be accessed and updated. The memory module provides dynamic data storage space; the FPGA module is internally programmed to integrate the SSD controller functional logic and network interface functional logic, and connects with the processor module, firmware module, storage chips and external interfaces of the board to complete data processing and interaction; the storage chips are managed by the SSD controller functional logic, providing large-capacity non-volatile storage.

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