Memory device and programming operations thereof

Abstract

In certain aspects, a memory device includes a first memory plane including memory cells and word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the first memory plane through the word lines. The peripheral circuit is configured to, in a last cycle of a program operation on the first memory plane, after applying a verify voltage to a select one of the word lines, ramp up a voltage on the select word line from a first supply voltage (Vdd) to a pass voltage, and ramp down the voltage on the select one of the word lines from the pass voltage to the first supply voltage.

Description

Technical Field

[0001] This disclosure relates to storage devices and their operating methods. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as reading, programming (writing), and erasing. For NAND flash memory, erasure operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0003] In one aspect, a storage device includes: a first storage plane including storage cells and word lines respectively coupled to rows of the storage cells; and peripheral circuitry coupled to the first storage plane via the word lines. The peripheral circuitry is configured to: in the final loop of a programming operation on the first storage plane, after applying a verification voltage to a select word line in the word lines, ramp up the voltage on the select word line from a first supply voltage (Vdd) to a pass voltage, and ramp down the voltage on the select word line in the word lines from the pass voltage to the first supply voltage.

[0004] In some embodiments, the peripheral circuitry is further configured to: in the final loop of the programming operation on the first memory plane, after applying the verification voltage to the select word line, apply a bias voltage to the select word line, the bias voltage being between the first supply voltage and the pass voltage, and before ramping the voltage on the select word line from the bias voltage to the first supply voltage, before ramping the voltage on the select word line from the first supply voltage to the pass voltage.

[0005] In some embodiments, the first storage plane further includes select gate transistors coupled to columns of the storage cells and select gate lines coupled to the select gate transistors. In some embodiments, the peripheral circuitry is coupled to the first storage plane via the select gate lines and is further configured to: in the final loop of the programming operation on the first storage plane, ramp up the voltage on the select gate lines from a second supply voltage (Vss) lower than the first supply voltage to the select voltage, and ramp down the voltage on the select gate lines from the select voltage to the second supply voltage.

[0006] In some embodiments, the storage device further includes a second storage plane, the second storage plane including storage cells and word lines respectively coupled to rows of the storage cells. In some embodiments, the peripheral circuitry is coupled to the first storage plane and the second storage plane and configured to: initiate the programming operation simultaneously on the first storage plane and the second storage plane, and stop the programming operation on the first storage plane before the second storage plane.

[0007] In some implementations, the peripheral circuitry is configured to pause the programming operation on the second memory plane from a first time when the voltage on the select word line in the first memory plane begins to slope down from the bias voltage to the first supply voltage until a second time when the voltage on the select word line in the first memory plane slopes down from the pass voltage to the first supply voltage.

[0008] In some embodiments, the peripheral circuitry includes string drivers that are respectively coupled to the word lines in the second memory plane. In some embodiments, to suspend the programming operation on the second memory plane, the string drivers are configured to be disabled to float the voltage on the word lines in the second memory plane.

[0009] In some embodiments, the peripheral circuitry is further configured to apply a programming voltage to the select word line among the word lines in the second memory plane after the second time.

[0010] In some embodiments, the peripheral circuitry is further configured to: in the final loop of the programming operation on the second memory plane, after applying a verification voltage to the select word line, apply the bias voltage to the select word line, ramp down the voltage on the select word line from the bias voltage to the first supply voltage, ramp up the voltage on the select word line from the first supply voltage to the pass voltage, and ramp down the voltage on the select word line from the pass voltage to the first supply voltage.

[0011] In some embodiments, the storage device further includes a third storage plane. In some embodiments, the peripheral circuitry is coupled to the first storage plane, the second storage plane, and the third storage plane and is configured to: initiate the programming operation simultaneously on the first storage plane, the second storage plane, and the third storage plane, and stop the programming operation on the second storage plane before the third storage plane.

[0012] In some embodiments, the peripheral circuitry is configured to: suspend the programming operation on the third storage plane from a first time when the voltage on the select word line in the first storage plane begins to slope down from the bias voltage to the first supply voltage until a second time after the voltage on the select word line in the first storage plane has sloped down from the pass voltage to the first supply voltage; and from a third time when the voltage on the select word line in the second storage plane begins to slope down from the bias voltage to the first supply voltage until a fourth time after the voltage on the select word line in the second storage plane has sloped down from the pass voltage to the first supply voltage.

[0013] In some embodiments, the peripheral circuitry is further configured to: in the final loop of the programming operation on the first memory plane, before applying the bias voltage to the select word line, after applying the verification voltage to the select word line, apply a post-pulse voltage to the select word line in the word line, slope the voltage on the select word line from the post-pulse voltage to the first supply voltage, and then slope the voltage on the select word line from the first supply voltage to the bias voltage.

[0014] In another aspect, a method for operating a storage device is provided. The storage device includes a first storage plane comprising storage cells and word lines respectively coupled to rows of the storage cells. In the final loop of a programming operation on the first storage plane, after applying a verification voltage to a select word line among the word lines, the voltage on the select word line is ramped up from a first supply voltage (Vdd) to a pass voltage. The voltage on the select word line among the word lines is then ramped down from the pass voltage to the first supply voltage.

[0015] In some embodiments, during the final loop of the programming operation on the first memory plane, after applying the verification voltage to the select word line, a bias voltage is applied to the select word line. The bias voltage is between the first supply voltage and the pass voltage. In some embodiments, the voltage on the select word line is sloped down from the bias voltage to the first supply voltage before being ramped up from the first supply voltage to the pass voltage.

[0016] In some embodiments, the first memory plane further includes select gate transistors coupled to columns of the memory cells and select gate lines coupled to the select gate transistors. In some embodiments, in the final loop of the programming operation on the first memory plane, the voltage on the select gate line is ramped up from a second supply voltage (Vss) lower than the first supply voltage to the select voltage, and the voltage on the select gate line is ramped down from the select voltage to the second supply voltage.

[0017] In some embodiments, the storage device further includes a second storage plane, the second storage plane including storage cells and word lines respectively coupled to rows of the storage cells. In some embodiments, the programming operation is started simultaneously on the first storage plane and the second storage plane, and the programming operation is stopped on the second storage plane before the third storage plane.

[0018] In some implementations, the programming operation is paused on the second storage plane from a first time when the voltage on the select word line in the first storage plane begins to slope down from the bias voltage to the first supply voltage until a second time when the voltage on the select word line in the first storage plane slopes down from the pass voltage to the first supply voltage.

[0019] In some embodiments, the storage device further includes string drivers that are respectively coupled to the word lines in the second storage plane. In some embodiments, in order to suspend the programming operation on the second storage plane, the string drivers are disabled to float the voltage on the word lines in the second storage plane.

[0020] In some implementations, after the second time, a programming voltage is applied to the select word line among the word lines in the second memory plane.

[0021] In some implementations, in the final loop of the programming operation on the second storage plane, after applying a verification voltage to the select word line, the bias voltage is applied to the select word line, the voltage on the select word line is ramped down from the bias voltage to the first supply voltage, the voltage on the select word line is ramped up from the first supply voltage to the pass voltage, and the voltage on the select word line is ramped down from the pass voltage to the first supply voltage.

[0022] In some embodiments, the storage device further includes a third storage plane. In some embodiments, the programming operation is initiated simultaneously on the first storage plane, the second storage plane, and the third storage plane, and the programming operation is stopped on the second storage plane before the third storage plane.

[0023] In some embodiments, the programming operation is paused on the third storage plane from a first time when the voltage on the select word line in the first storage plane begins to slope down from the bias voltage to the first supply voltage until a second time after the voltage on the select word line in the first storage plane has sloped down from the pass voltage to the first supply voltage. In some embodiments, the programming operation is paused on the third storage plane from a third time when the voltage on the select word line in the second storage plane begins to slope down from the bias voltage to the first supply voltage until a fourth time after the voltage on the select word line in the second storage plane has sloped down from the pass voltage to the first supply voltage.

[0024] In some implementations, in the final loop of the programming operation on the first storage plane, before applying the bias voltage to the select word line, after applying the verification voltage to the select word line, a post-pulse voltage is applied to the select word line in the word line, the voltage on the select word line is ramped down from the post-pulse voltage to the first supply voltage, and then the voltage on the select word line is ramped up from the first supply voltage to the bias voltage.

[0025] In another aspect, a system includes: a storage device configured to store data; and a memory controller coupled to the storage device and configured to control the storage device. The storage device includes: a first storage plane including storage cells and word lines respectively coupled to rows of the storage cells; and peripheral circuitry coupled to the first storage plane via the word lines. The peripheral circuitry is configured to: in the final loop of a programming operation on the first storage plane, after applying a verification voltage to a select word line in the word lines, ramp up the voltage on the select word line from a first supply voltage (Vdd) to a pass voltage, and ramp down the voltage on the select word line in the word lines from the pass voltage to the first supply voltage. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0027] Figure 1 A schematic diagram of a storage device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0028] Figure 2 A side view of a cross-section of a memory cell array including NAND memory strings is shown, according to some aspects of this disclosure.

[0029] Figure 3 A block diagram of a memory device including a memory cell array and peripheral circuitry, according to some aspects of this disclosure, is shown.

[0030] Figure 4 A schematic diagram of a storage device comprising multiple storage planes, each comprising multiple blocks, is shown according to some aspects of this disclosure.

[0031] Figure 5A and 5B The waveform of the word line voltage applied to the select word line during programming operations is shown according to some aspects of this disclosure.

[0032] Figure 6A A timing diagram of programming operations with multiple loops according to some aspects of this disclosure is shown.

[0033] Figure 6B A timing diagram of another programming operation with multiple loops, based on some aspects of this disclosure, is shown.

[0034] Figure 7 A schematic timing diagram of a multi-plane programming operation with multiple loops is shown.

[0035] Figure 8 A schematic timing diagram of multi-plane programming operations with multiple loops is shown, according to some aspects of this disclosure.

[0036] Figure 9A and 9B A timing diagram of multi-plane programming operations with multiple loops is shown, according to some aspects of this disclosure.

[0037] Figure 10 Some aspects of this disclosure are shown. Figure 9A and Figure 9B Timing diagram of the string driver in the storage plane.

[0038] Figure 11 A schematic timing diagram of another multi-plane programming operation with multiple loops, based on some aspects of this disclosure, is shown.

[0039] Figure 12A flowchart illustrating a method for programming a storage device according to some aspects of this disclosure is shown.

[0040] Figure 13 A flowchart is shown of another method for programming a storage device according to some aspects of this disclosure.

[0041] Figure 14 A block diagram of a system having storage devices according to some aspects of this disclosure is shown.

[0042] Figure 15A A diagram of a memory card having storage devices according to some aspects of this disclosure is shown.

[0043] Figure 15B A diagram of a solid-state drive (SSD) with storage devices is shown, according to some aspects of this disclosure.

[0044] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0045] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can also, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0046] Memory devices (such as NAND flash memory devices) can store more than a single bit of information into each memory cell with multiple states to increase storage capacity bit by bit and reduce cost. Programming operations for NAND flash memory devices involve multiple programming cycles and verification cycles. At the end of each verification cycle, all word lines are restored to the drain supply voltage Vdd, and the drain select gate (DSG) line and source select gate (SSG) line are restored to the source supply voltage Vss, which can downcouple the channel potential (particularly in the memory cell region near the select word line where the NAND string is programmed). However, due to the hot carrier injection (HCI) effect, the downcoupled channel potential can cause programming interference in subsequent programming cycles. To mitigate these problems, a bias voltage can be applied to the word lines near the select word line at the beginning of the affected programming cycle to clean up accumulated electrons in the channel during a so-called "pre-pulse period" in the programming cycle. However, the additional pre-pulse period prolongs the duration of the programming cycle, thus becoming a time-saving programming (t) period. PROG The bottleneck.

[0047] On the other hand, at the end of the verification cycle, when all word lines are restored to Vdd, a failure bit count (FBC) needs to be performed during the retention period. Some efforts have been made to combine the pre-pulse period in the programming cycle and the FBC period in the previous verification cycle into a "combined recovery / pre-pulse period" in order to reduce the total programming time and the power consumption caused by the ramp-up / ramp-down of word line voltages.

[0048] For memory devices with multiple memory planes, different memory planes may be stopped at different times during the same programming operation (e.g., undergoing different numbers of cycles) due to various reasons (such as process and device variations between memory planes or programming failures for one or more memory planes (failing to pass a certain verification level after a threshold number of programming pulses)). However, for a memory plane that stops earlier in the combined recovery / pre-pulse period of the programming operation, the voltage on the word line will be floated at a positive bias voltage, which can shift the threshold voltage of the programmed memory cell in the memory plane and affect the channel potential, as well as introduce noise into the sense current during subsequent read operations.

[0049] To address one or more of the aforementioned problems, this disclosure provides a multi-plane programming scheme that adds an additional time period at the end of the programming operation on those memory planes that stopped during the merged recovery / pre-pulse period of the programming operation. The memory planes can perform operations similar to those in the pre-pulse period of the verification cycle (hence also referred to as "end pre-pulse period"), which can restore the voltage on the word line from a positive bias voltage (e.g., greater than 2V) to a lower supply voltage (e.g., Vdd) to avoid threshold voltage shift, and clean electrons accumulated in the channel due to the bias voltage, thereby resetting the channel potential. In some embodiments, when an end pre-pulse period is added to a memory plane that stopped earlier, the remaining memory planes still undergoing programming operations are temporarily disabled to avoid performing the same operations as the earlier stopped memory planes during the end pre-pulse period, thereby preventing down-coupling of their channel potentials, as described above. After the end pre-pulse period, the remaining memory planes can be enabled to resume their operation during the merged recovery / pre-pulse period.

[0050] Figure 1 A schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein memory cells 106 are provided in the form of an array of NAND memory strings 108, each extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value (such as voltage or charge) depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0051] In some implementations, each storage cell 106 is an SLC with two possible levels (storage states) and thus capable of storing one bit of data. For example, a first level "0" may correspond to a first threshold voltage range, and a second level "1" may correspond to a second threshold voltage range. In some implementations, each storage cell 106 is an xLC capable of storing more than a single bit of data in more than four levels. For example, an xLC may store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC can be programmed to assume a series of possible nominal storage values ​​(i.e., 2^N corresponding to N bits of data). N(pieces). In some embodiments, at least one of the storage units 106 is set to 2. N One of the levels corresponds to an N-bit data segment, where N is an integer greater than 1.

[0052] like Figure 1 As shown, each NAND memory string 108 may further include a source select gate (SSG) transistor 110 (also referred to as a bottom select gate (BSG) transistor) at its source end and a drain select gate (DSG) transistor 112 (also referred to as a top select gate (TSG) transistor) at its drain end. The SSG transistor 110 and the DSG transistor 112 may be configured to activate and select the NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled via a common source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 108 is coupled to a corresponding bit line 116 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage (e.g., a positive voltage greater than the threshold voltage of the DSG transistor 112) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding DSG transistor 112 via one or more DSG lines 113 and / or by applying a selection voltage (e.g., a positive voltage greater than the threshold voltage of the SSG transistor 110) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding SSG transistor 110 via one or more SSG lines 115.

[0053] like Figure 1As shown, NAND memory strings 108 can be organized into multiple blocks 104, each block 104 may have a common source line 114, for example, coupled to an ACS. In some embodiments, each block 104 is the basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Vers) (such as a high positive bias voltage (e.g., 20V or greater)). Memory cells 106 of adjacent NAND memory strings 108 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to multiple memory cells 106. Each word line 118 may include multiple control gates (gate electrodes) and gate lines coupled to the control gates at each memory cell 106.

[0054] like Figure 1 As shown, the memory cell array 101 may include an array of memory cells 106 in multiple rows and multiple columns within each block 104. According to some embodiments, one column of memory cells corresponds to one NAND memory string 108. Multiple rows of memory cells 106 may be coupled to word lines 118, and multiple columns of memory cells 106 may be coupled to bit lines 116. Peripheral circuitry 102 may be coupled to the memory cell array 101 via bit lines 116 and word lines 118.

[0055] Figure 2 A side view of a cross-section of a memory cell array 101 including NAND memory strings 108 is shown, according to some aspects of this disclosure. (See also:) Figure 2 As shown, the NAND memory string 108 can extend vertically through the memory stack 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0056] The memory stack 204 may include staggered gate conductive layers 206 and gate-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the gate of the memory cell 106, the gate of the DSG transistor 112, or the gate of the SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between DSG lines 113 and SSG lines 115.

[0057] like Figure 2 As shown, the NAND memory string 108 includes a channel structure extending vertically through the memory stack 204. In some embodiments, the channel structure includes channel holes filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). It should be understood that, although Figure 2 Additional components, not shown but which may form the memory cell array 101, include, but are not limited to, gate line slits / source contacts, local contacts, interconnect layers, etc.

[0058] Return to reference Figure 1 Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 101 by applying voltage and / or current signals to each selected memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113 and sensing voltage and / or current signals from each selected memory cell 106. Peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuitry may also be included. Figure 3 Additional peripheral circuitry not shown.

[0059] Page buffer / sensor amplifier 304 can be configured to sense (read) data from memory cell array 101 and program (write) data to memory cell array 101 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store one or more pages of programming data to be programmed (written data, referred to herein as "data pages"). In another example, page buffer / sensor amplifier 304 can verify the programmed selected memory cell 106 in each programming / verification cycle of a programming operation to ensure that data has been correctly programmed into the memory cell 106 coupled to select word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify small voltage swings to a recognizable logic level during read operations.

[0060] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and configured to select one or more NAND memory strings 108 by applying bit line voltages generated from voltage generator 310. The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and configured to select / deselect block 104 of memory cell array 101 and select / deselect word lines of block 104. The row decoder / word line driver 308 can also be configured to drive word lines 118 using word line voltages generated from voltage generator 310. In some embodiments, the row decoder / word line driver 118 can also select / deselect and also drive SSG lines 115 and DSG lines 113. Voltage generator 310 can be configured to be controlled by control logic 122 and generate word line voltages (e.g., read voltage, programming voltage, channel pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 101.

[0061] Control logic 312 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 316 can be coupled to control logic 312 and acts as a control buffer to buffer and relay control commands received from the memory controller (not shown) and / or the host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the memory controller and / or the host. Interface 316 can also be coupled to column decoder / bitline driver 306 via data bus 318 and acts as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0062] Figure 4 A schematic diagram of a storage device 400, comprising multiple storage planes 402, each comprising multiple blocks, is shown according to some aspects of this disclosure. The storage device 400 may be... Figure 1 Example storage device 100. (e.g.) Figure 4 As shown, the storage device 400 may include multiple storage planes 402, such as plane A (PLA) and plane B (PLB). Each storage plane 402 may include multiple blocks 404, such as M blocks (block 0 to block M-1). Block 404 may be... Figure 1 An example of block 104. Each block 404 may include multiple pages 406, such as N pages (pages 0 to N-1). Each page 406 may correspond to a storage unit 106 coupled to a word line 118, a portion of a word line 118, or multiple word lines 118, such as... Figure 1 As shown. In some embodiments, each storage plane 402 includes a storage cell 106 and word lines 118 that are respectively coupled to rows of the storage cell 106.

[0063] In the programming operations applied to the storage device 400, each storage plane 402 can be operated in parallel following the same timing of the same control instructions. In some embodiments, the corresponding block 404 (e.g., block 0) in each storage plane 402 is programmed in parallel by the same programming operations.

[0064] To perform the programming operation, in addition to the page buffer / sensor amplifier 304 providing a corresponding data segment to each selected memory cell 106, the row decoder / word line driver 308 can be configured to apply programming and verification voltages to the select word line 118 coupled to the selected row of memory cells 106 in one or more programming / verification cycles, so as to raise the threshold voltage of each selected memory cell 106 to a desired level (within the desired threshold voltage range) based on the corresponding data segment. For example, Figure 5A and Figure 5B The waveform of the word line voltage applied to the select word line during programming operations is shown according to some aspects of this disclosure.

[0065] like Figure 5A and 5B As shown, according to some embodiments, the programming operation includes one or more loops 502, each loop 502 including a programming cycle 504 and a verification cycle 506. Figure 5B As shown, in each cycle 502, the row decoder / word line driver 308 can be configured to apply a programming voltage (Vpgm) on the select word line 118 in programming cycle 504 to select a row of memory cell 106, and sequentially apply one or more verification voltages (Vvfy) with increasing voltage levels in verification cycle 506 to verify the selected row of memory cell 106. That is, in each cycle 502, the peripheral circuitry 102 can perform verification of the selected row of memory cell 106 at one or more levels in verification cycle 506 after applying the programming voltage in programming cycle 504. According to some embodiments, the number of verification voltages applied in verification cycle 506 depends on the level programmed by a particular cycle 502. Therefore, at the end of the programming operation, for example, the selected memory cell 106 can be programmed to 2 based on the corresponding N bits of data to be stored in the selected memory cell 106. N In one of the voltage levels, where N is a positive integer. In some implementations, the programming operation is incremental step pulse programming (ISPP), in which the programming voltage is gradually increased based on a step voltage in different cycles 502. The magnitude of this "step" (e.g., the increase in the magnitude of the programming voltage in each cycle 502 relative to the programming voltage in the immediately preceding cycle 502) is referred to as the "pulse step height".

[0066] Figure 6A A timing diagram of a programming operation with multiple loops according to some aspects of this disclosure is shown. The programming operation may include multiple loops (e.g., N loops). Each loop of the programming operation may include a programming cycle and a verification cycle, as described above. Figure 5A and 5B As described in [the text]. Figure 6AThe diagram illustrates a verification cycle 506 (VFY) in the first loop and a programming cycle 504 (PGM) in the second loop immediately following the first loop. It should be understood that the "first loop" need not be the first loop in the programming operation, as long as another loop (e.g., the "second loop") immediately follows. Verification cycle 506 may include a verification period (phase) in which a verification voltage (Vvfy) with one or more verification voltage pulses is applied to the select word line (selWLn) to verify the selected memory cell coupled to the select word line at one or more levels. At the end of the verification period (e.g., ...), Figure 6A At time ta, a post-pulse voltage (Vpost) can be applied to the select word line. During the verification period, a pass voltage (Vpass) can be applied to each unselected word line. The pass voltage can be greater than the threshold voltage of the unselected memory cell, causing the channel of the selected NAND memory string to become conductive during the verification period. In some implementations, the pass voltage is greater than the verification voltage, causing the channel to become conductive at the end of the verification period, for example, at time ta. Figure 6A At time ta, the voltage on the select word line is upcoupled / boosted to the same post-pulse voltage as the pass voltage.

[0067] After the verification period of verification cycle 506, the voltage on each word line can be ramped down to the corresponding bias voltage (V1, V2, or V3) or supply voltage (Vss, e.g., ground voltage 0V). For example, the voltage on each of the selected word line and the first group of unselected word lines (WLn-4–sel WLn) can be ramped down from the post-pulse voltage or through voltage to the first bias voltage (V1); the voltage on each of the second group of unselected word lines (WLb+1–WLn-5 and WLn+1–WLx) can be ramped down from the through voltage to the second bias voltage (V2); the voltage on each of the third group of unselected word lines (WLa+1–WLb) can be ramped down from the through voltage to the third bias voltage (V3); and the voltage on each of the fourth group of unselected word lines (WL0–WLa and WLx+1–WLz) can be ramped down from the through voltage to the supply voltage (Vss).

[0068] like Figure 6A As shown, the voltage on each word line can be ramped down and then held at the corresponding bias voltage or supply voltage (Vss) during a time period from time ta in the verification cycle 506 of the first cycle to another time tb in the programming cycle 504 of the second cycle. This time period can be regarded as the combined recovery / pre-pulse period across the verification cycle 506 and the programming cycle 504.

[0069] like Figure 6AAs shown, programming cycle 504 may include a programming period (phase) following the merged recovery / pre-pulse period, wherein a programming voltage (Vpgm) with one or more programming voltage pulses is applied to the select word line to program the selected memory cell to one or more levels. During the programming period, a pass voltage may be applied to each unselected word line.

[0070] Figure 6B A timing diagram of another programming operation having multiple loops according to some aspects of this disclosure is shown. The programming operation may include multiple loops (e.g., N loops). Each loop of the programming operation may include a programming cycle and a verification cycle, as described above. Figure 5A and 5B As described in [the text]. Figure 6B The diagram illustrates a verification cycle 506 (VFY) in the first loop and a programming cycle 504 (PGM) in the second loop immediately following the first loop. It should be understood that the "first loop" need not be the first loop in the programming operation, as long as another loop (e.g., the "second loop") immediately follows. Verification cycle 506 may include a verification period (phase) in which a verification voltage (Vvfy) with one or more verification voltage pulses is applied to the select word line (selWLn) to verify the selected memory cell coupled to the select word line at one or more levels. At the end of the verification period (e.g., ...), Figure 6B At time ta, a post-pulse voltage (Vpost) can be applied to the select word line. During the verification period, a pass voltage (Vpass) can be applied to each unselected word line. The pass voltage can be greater than the threshold voltage of the unselected memory cell, causing the channel of the selected NAND memory string to become conductive during the verification period. In some implementations, the pass voltage is greater than the verification voltage, causing the channel to become conductive at the end of the verification period, for example, at time ta. Figure 6B At time ta, the voltage on the select word line is upcoupled / boosted to the same post-pulse voltage as the pass voltage.

[0071] and Figure 6A The difference lies in Figure 6BIn this embodiment, after the verification period of verification cycle 506, the voltage on the select word line can be ramped down from the post-pulse voltage to another supply voltage (Vdd) instead of the first bias voltage (V1), and then immediately ramped up from the supply voltage (Vdd) to the first bias voltage. In some embodiments, the first bias voltage (e.g., approximately 4.5V) is greater than the supply voltage (Vdd, e.g., approximately 2V). Similarly, after the verification period of verification cycle 506, the voltage on each unselected word line can be ramped down from the pass voltage to the supply voltage (Vdd) instead of the corresponding bias voltage (V1, V2, or V3) or supply voltage (Vss), and then immediately ramped up from the supply voltage (Vdd) to the corresponding bias voltage (V1, V2, or V3) or supply voltage (Vss). In some embodiments, the bias voltage (e.g., between 2V and 5V) is greater than the supply voltage (Vdd, e.g., approximately 2V), and Vdd is greater than the supply voltage (Vss, e.g., ground voltage 0V). For example, the voltage on each of the select word lines and the first group of unselected word lines (WLn-4–sel WLn) can be ramped up from the supply voltage (Vdd) to the first bias voltage (V1), the voltage on each of the second group of unselected word lines (WLb+1–WLn-5 and WLn+1–WLx) can be ramped up from the supply voltage (Vdd) to the second bias voltage (V2), the voltage on each of the third group of unselected word lines (WLa+1–WLb) can be ramped up from the supply voltage (Vdd) to the third bias voltage (V3), and the voltage on each of the fourth group of unselected word lines (WL0–WLa and WLx+1–WLz) can be ramped down from the supply voltage (Vdd) to the supply voltage (Vss).

[0072] like Figure 6B As shown, the voltage on each word line can be ramped up / down and then maintained at the corresponding bias voltage or supply voltage (Vss) during a time period from time tc in the verification cycle 506 of the first cycle to another time tb in the programming cycle 504 of the second cycle. This time period can be regarded as the combined recovery / pre-pulse period across the verification cycle 506 and the programming cycle 504.

[0073] Similar to Figure 6A ,like Figure 6B As shown, programming cycle 504 may include a programming period (phase) following the merged recovery / pre-pulse period, wherein a programming voltage (Vpgm) with one or more programming voltage pulses is applied to the select word line to program the selected memory cell to one or more levels. During the programming period, a pass voltage may be applied to each unselected word line.

[0074] When a programming operation with multiple cycles (i.e., a multi-plane programming operation with multiple cycles) is applied to a memory device 400 having multiple memory planes 402, different memory planes 402 may undergo different numbers of cycles 502 for various reasons. In one example, due to variations in manufacturing processes and devices between different memory planes 402, different numbers of cycles may be required in different memory planes 402 to program the memory cells to the desired level. A memory plane 402 that completes the programming operation with fewer cycles may be referred to herein as a "fast plane". In another example, one or more memory planes 402 may fail to pass a certain verification level (programming failure) even after the maximum number of programming pulses. A memory plane 402 that prematurely stops programming due to programming failure may be referred to herein as a "failure plane". Fast planes and failure planes may be referred to herein as "early-stopping planes".

[0075] For example, such as Figure 7 As shown, plane A (PLA) represents the plane that stops earlier, where programming operations can cease after the third cycle, while plane B (PLB) can stop the same programming operations after the fourth cycle, because plane A can be either a fast plane or a failure plane. In other words, when plane A stops programming operations after the third cycle, plane B can continue programming operations on it. For plane A, the final verification cycle (VFY) can include the merged recovery / pre-pulse period in which programming operations cease ( Figure 7 (The "merged recovery" in the text). For example, programming operations on plane A can be performed on plane A. Figure 6A In the combined recovery / pre-pulse period between ta and tb or in Figure 6B The programming operation stops at time t1 within the combined recovery / pre-pulse period between tc and tb. When the programming operation on plane A stops, the voltages on the select word line and some unselected word lines can be at a positive bias voltage (e.g., Figure 6A and 6B V1, V2, and V3 in plane A can be floated until the programming operation on plane B stops after one or more cycles. As a result, the threshold voltage of the programmed memory cell in plane A may be shifted, and noise may be introduced into the sensing current in subsequent read operations.

[0076] To address threshold voltage shift and sensed current noise issues in multi-plane programming operations with multiple cycles and merged recovery / pre-pulse periods, a termination pre-pulse period can be added to the end of the programming operation on the earlier stopped plane. This restores the voltage on the word line from a higher positive bias voltage to a lower supply voltage (e.g., Vdd) and resets the channel potential. Conversely, when a termination pre-pulse period is added to the earlier stopped plane, the remaining memory planes still undergoing programming operations can be temporarily disabled to prevent them from performing the same operations as the earlier stopped plane during the termination pre-pulse period, thus preventing downcoupling of their channel potentials. After the termination pre-pulse period, the remaining memory planes can be enabled to resume their operation during the merged recovery / pre-pulse periods. For example, Figure 8 A schematic timing diagram of multi-plane programming operations with multiple loops is shown, according to some aspects of this disclosure.

[0077] like Figure 8 As shown, according to some embodiments, the peripheral circuit 102 is configured to: simultaneously initiate multi-plane programming operations on a first storage plane (PLA) and a second storage plane (PLB), and stop the multi-plane programming operations on the first storage plane before the second storage plane (e.g., because the first storage plane is a fast plane or a failure plane). Unlike Figure 7 Examples include (where the earlier stopped plane stops programming operations after the last verification loop in the merged recovery / pre-pulse period), such as... Figure 8 As shown, in some embodiments, the peripheral circuit 102 is configured to: after the verification cycle of the last loop of the first storage plane (e.g., in... Figure 8 Between the first time t1 and the second time t2, during the end of the pre-pulse period ( Figure 8 In the "verification pre-pulse" (as described in the text), additional operations are performed on the first memory plane that stopped earlier to restore the word line voltage to a lower level and reset the channel potential. In some embodiments, the peripheral circuit 102 is also configured to suspend programming operations on the second memory plane during the end pre-pulse period between the first time t1 and the second time t2 to avoid the combined recovery / pre-pulse period (as described in the text). Figure 8Interference with the planned operation on the second storage plane during the "merged recovery" in the context of the first storage plane. In some embodiments, the peripheral circuit 102 is also configured to resume programming operations on the second storage plane after the end pre-pulse period (second time t2) of the first storage plane. That is, the first storage plane, which stopped earlier, can stop programming operations after the end pre-pulse period instead of the merged recovery / pre-pulse period, and the second storage plane can be temporarily disabled during the end pre-pulse period of the first storage plane, and can be re-enabled after programming operations on the first storage plane stop. In some embodiments, the peripheral circuit 102 is also configured to: at the end of the verification cycle of the last cycle of the second storage plane, during the end pre-pulse period (second time t2), Figure 8 In the "verification pre-pulse" (in the memory), additional operations are performed on the second memory plane to restore the word line voltage to a lower level and reset the channel potential.

[0078] Figure 9A and 9B Timing diagrams of multi-plane programming operations with multiple loops according to some aspects of this disclosure are shown. For example, Figure 9A The first storage plane that stopped earlier is shown. Figure 8 An example of multiplane programming operations performed on a PLA, and Figure 9B It is shown in the second storage plane ( Figure 8 This is an example of multi-plane programming operations performed on a PLB (Programming Layer Builder). Programming operations can include multiple loops. As mentioned above... Figure 5A , Figure 5B and Figure 8 As described above, each cycle of a programming operation can include a programming cycle and a verification cycle. Figure 8 As described above, according to some embodiments, the number of loops in the programming operations performed on the first storage plane is less than the number of loops in the programming operations performed on the second storage plane. In some embodiments, Figure 9A The final loop of programming operations on the first storage plane is shown (e.g., Figure 8 The verification cycle in the third loop is 506, and Figure 9B The final loop of programming operations on the first storage plane is shown (e.g., Figure 8 The verification cycle 506 in the non-final loop of the programming operation on the second storage plane (the third loop in the middle) is executed simultaneously with the non-final loop of the programming operation on the second storage plane (e.g., Figure 8 The programming cycle 504 is the next loop after the fourth loop in the program.

[0079] In some implementations... Figure 9A and Figure 9BThe verification cycle 506 includes a verification period (phase) in which the word line driver 308 of the peripheral circuitry 102 is configured to apply a verification voltage (Vvfy) with one or more verification voltage pulses on the selected word line (sel WLn) to verify the selected memory cell coupled to the selected word line at one or more levels. According to some embodiments, at the end of the verification period, the word line driver 308 of the peripheral circuitry 102 is configured to apply a post-pulse voltage (Vpost) on the selected word line. For example, the voltage on the selected word line can be ramped up from the verification voltage to the post-pulse voltage. In some embodiments, during the verification period, the word line driver 308 of the peripheral circuitry 102 is also configured to apply a pass voltage (Vpass) to each unselected word line. The pass voltage can be greater than a threshold voltage for the unselected memory cell, causing the channel of the selected NAND memory string to become conductive during the verification period. In some embodiments, the pass voltage is greater than the verification voltage, causing the voltage on the selected word line to be up-coupled / ramped to the same post-pulse voltage as the pass voltage at the end of the verification period.

[0080] In some implementations, the verification cycle 506 further includes a combined recovery / pre-pulse period following the verification period. During the combined recovery / pre-pulse period, the word line driver 308 of the peripheral circuitry 102 may also be configured to: ramp down the voltage on the select word line from the post-pulse voltage to a first supply voltage (Vdd), and then immediately ramp up the voltage on the select word line from the first supply voltage to a first bias voltage (V1). That is, the voltage on the select word line can be ramped down from the post-pulse voltage to the first supply voltage, for example, using a first voltage source (e.g., a drain voltage source). To immediately ramp up the voltage on the select word line, the word line driver 308 of the peripheral circuitry 102 may be configured to ramp up the voltage on the select word line once it reaches the first supply voltage.

[0081] Similarly, during the combined recovery / pre-pulse period, the word line driver 308 of the peripheral circuit 102 can also be configured to: ramp down the voltage on each unselected word line from the pass voltage to the same first supply voltage (Vdd), and then immediately ramp up the voltage on the unselected word line from the first supply voltage to the corresponding bias voltage (e.g., V1, V2, or V3) or second supply voltage (Vss). That is, the same first voltage source (e.g., a drain voltage source) can be used to ramp down the voltage on the unselected word line from the pass voltage to the first supply voltage. To immediately ramp up the voltage on the unselected word line, the word line driver 308 of the peripheral circuit 102 can be configured to ramp up the voltage on the unselected word line once the voltage on the unselected word line reaches the first supply voltage. In some embodiments, the voltage on the selected word line and the voltage on the unselected word line are ramped down from the same first time and ramped up from the same second time.

[0082] Unselected word lines can be grouped into different groups based on their distance from the selected word lines and the programming direction of the word lines. Different bias voltages (e.g., V1, V2, and V3) can be assigned to different groups of unselected word lines to form a bias voltage distribution for better channel cleaning before the next programming cycle. In some implementations, a first bias voltage is greater than a second bias voltage, a second bias voltage is greater than a third bias voltage, and a third bias voltage is greater than a second supply voltage (Vss), i.e., V1>V2>V3>Vss. For example, the first bias voltage may be approximately 4.5V, the second bias voltage may be approximately 3.5V, the third bias voltage may be approximately 2.5V, and the second supply voltage may be 0V. In other words, according to some implementations, the closer the unselected word line group is to the selected word line, the larger the bias voltage assigned to the unselected word line group.

[0083] In such Figure 9A and Figure 9BIn some implementations shown (where the programming direction is from the bit line (BL) to the source line (SL), e.g., from top to bottom), a first bias voltage regulator is used to select the word line and the first set of unselected word lines (WLn-4–sel). The voltage on each of the first set of unselected word lines (WLn) is ramped down from the first supply voltage (Vdd) to the first bias voltage (V1) using a second bias voltage regulator; the voltage on each of the second set of unselected word lines (WLb+1–WLn-5 and WLn+1–WLx) is ramped down from the first supply voltage (Vdd) to the second bias voltage (V2) using a third bias voltage regulator; the voltage on each of the third set of unselected word lines (WLa+1–WLb) is ramped down from the first supply voltage (Vdd) to the third bias voltage (V3) using a third bias voltage regulator; and the voltage on each of the fourth set of unselected word lines (WL0–WLa and WLx+1–WLz) is ramped down from the first supply voltage (Vdd) to the second supply voltage (Vss) using a second voltage source (e.g., a source voltage source). Figure 9A and Figure 9B As shown, the word line driver 308 of the peripheral circuit 102 can also be configured to maintain the voltage on each of the selected and unselected word lines at a corresponding bias voltage (e.g., V1, V2, or V3) or a second supply voltage (Vss) during the combined recovery / pre-pulse period. In other words, a bias voltage or a second supply voltage can be maintained on the word lines during the combined recovery / pre-pulse period.

[0084] In some implementations, such as Figure 9A and Figure 9B (Where the programming direction is from the bit line to the source line) As shown, the word line driver 308 of the peripheral circuit 102 is also configured to ramp down the voltage on the DSG line (DSGL) from the selection voltage to a second supply voltage (Vss) less than the first supply voltage (Vdd) to turn off the DSG transistor coupled to the DSG line. The selection voltage can be higher than the threshold voltage of the DSG transistor, allowing the DSG transistor to be switched from being on to being off during the combined recovery / pre-pulse period. The voltage on the selection word line and the voltage on the DSG line can be ramped down from the same first time to the same second time. In some embodiments, during the combined recovery / pre-pulse period, the word line driver 308 of the peripheral circuit 102 is also configured to ramp up the voltage on the source line to a fourth bias voltage (V4), because Figure 9A The programming direction in the code is from the bit line to the source line.

[0085] Although not shown, it should be understood that in some examples (where the programming direction is from the source line to the bit line, e.g., from bottom to top), during the combined recovery / pre-pulse period, a first bias voltage regulator can be used to select the word line and the first set of unselected word lines (sel). The voltage on each of the first supply voltage (Vdd) is ramped down to the first bias voltage (V1) using a second bias voltage regulator. The voltage on each of the second set of unselected word lines (WLa+1–WLn-1 and WLn+5–WLx) is ramped down to the second bias voltage (V2) using a second bias voltage regulator. The voltage on each of the third set of unselected word lines (WLx+1–WLy) is ramped down to the third bias voltage (V3) using a third bias voltage regulator. The voltage on each of the fourth set of unselected word lines (WL0–WLa and WLy+1–WLz) is ramped down to the second supply voltage (Vss) using a second voltage source (e.g., a source voltage source). Furthermore, the voltage on the SSG line (SSGL) can be ramped down from the selection voltage to a second supply voltage (Vss) less than the first supply voltage (Vdd) to turn off the SSG transistor coupled to the SSG line. The selection voltage can be higher than the threshold voltage of the SSG transistor, allowing the SSG transistor to switch from being on to being off during the combined recovery / pre-pulse period. During the combined recovery / pre-pulse period, when the programming direction is from the source line to the bit line, the voltage on the bit line can be ramped up to the fourth bias voltage (V4).

[0086] It should be understood that the operations performed during the merged recovery / pre-pulse periods are not limited to those described above. Figure 9A and Figure 9B Examples of the description. For example, in some examples, as described above... Figure 6A The operations described for execution during the merged recovery / pre-pulse period can also be performed by multi-plane programming operations. That is, the voltage on each word line can be directly ramped down from the pass voltage or post-pulse voltage to the corresponding bias voltage or second supply voltage (Vss) without first ramping down together to the first supply voltage (Vdd).

[0087] like Figure 9AAs shown, in some embodiments, verification cycle 506 is in the final cycle of a multi-plane programming operation on the first storage plane, which stops at a first time t1 because the first storage plane is the earlier stopped plane. An end pre-pulse period between the first time t1 and a second time t2 can be added after verification cycle 506 in the final cycle. According to some embodiments, during the end pre-pulse period, the word line driver 308 of the peripheral circuitry 102 is configured to ramp down the voltage on the select word line from a first bias voltage (V1) to a first supply voltage (Vdd). The word line driver 308 of the peripheral circuitry 102 can also be configured to ramp up the voltage on the select word line from the first supply voltage to a pass voltage (Vpass), maintain the voltage on the select word line at the pass voltage for a period of time, and then ramp down the voltage on the select word line back to the first supply voltage. Similarly, according to some embodiments, during the end of the pre-pulse period, the word line driver 308 of the peripheral circuit 102 is configured to ramp / boost the voltage on each unselected word line from the corresponding bias voltage (V1, V2, or V3) or the second supply voltage (Vss) to the first supply voltage (Vdd). The word line driver 308 of the peripheral circuit 102 may also be configured to ramp the voltage on each unselected word line from the first supply voltage to a pass voltage (Vpass), maintain the voltage on each unselected word line at the pass voltage for a period of time, and then ramp the voltage on each unselected word line back from the pass voltage to the first supply voltage. In some embodiments, the pass voltage is greater than the bias voltage, and the bias voltage is greater than the first supply voltage. That is, the bias voltage can be between the first supply voltage and the pass voltage.

[0088] like Figure 9A As shown, in some embodiments, during the end of the pre-pulse period, the word line driver 308 of the peripheral circuit 102 is further configured to ramp up the voltage on each select gate line (DSG line or SSG line) from the second supply voltage (Vss) to the select voltage (Vsel), so as to turn on the corresponding select gate transistor (DSG transistor and / or SSG transistor) while the voltage on each word line is ramped up. The select voltage may be greater than the threshold voltage of the select gate transistor. The word line driver 308 of the peripheral circuit 102 may also be configured to maintain the voltage on each select gate line at the select voltage for a period of time while maintaining the voltage on each word line at the pass voltage, and then ramp down the voltage on each select gate line from the select voltage back to the second supply voltage while the voltage on each word line is ramped down.

[0089] Then, when the voltage on each word line is at the first supply voltage (Vdd) instead of a higher bias voltage (V1, V2, or V3), and the voltage on each select word line is at the second supply voltage (Vss), the multi-plane programming operation on the first memory plane can be stopped at the second time t2. Therefore, according to some embodiments, even if the multi-plane programming operation can continue on the second memory plane, the voltage on each select word line is floated at a relatively low supply voltage (Vdd) to avoid shifting the threshold voltage of the programmed memory cells in the first memory plane. Furthermore, according to some embodiments, during the end pre-pulse period, when the voltage on each word line is ramped up to the pass voltage and maintained at the pass voltage, and each select gate line is ramped up to the select voltage and maintained at the select voltage, the channel becomes conductive to be reset.

[0090] like Figure 9B As shown, in some implementations, verification cycle 506 is in a non-last loop of the multi-plane programming operation on the second storage plane, which is not stopped at the first time t1 because the second storage plane is not the earlier stopped plane. This is to avoid performing the above-described... Figure 9A The operation performed on the first storage plane during the end pre-pulse period between the first time t1 and the second time t2 described herein, the peripheral circuit 102 can be configured to: suspend multi-plane programming operations on the second storage plane from the first time t1 until the second time t2 (i.e., throughout the entire end pre-pulse period of the first storage plane). Figure 9B As shown, in some embodiments, during the paused period between a first time t1 and a second time t2, the voltage on each word line is floated at, for example, a corresponding bias voltage (V1, V2, or V3) or a second supply voltage (Vss). The peripheral circuitry 102 can also be configured to resume multiplane programming operations on the second memory plane at the second time t2 when the multiplane programming operation on the first memory plane has stopped.

[0091] The pause of the second storage plane can be controlled by the serial driver of the peripheral circuit 102. For example, Figure 10 Some aspects of this disclosure are shown. Figure 9A and Figure 9B The timing diagram of the string drivers in the memory plane. The word line driver 308 of the peripheral circuitry 102 may include multiple string drivers, each string driver being coupled to a corresponding word line or select gate line to control a corresponding voltage applied thereto in response to a corresponding control signal. Figure 10As shown, the word line driver 308 of the peripheral circuitry 102 of the first storage plane may include a string driver (PLA string driver), each string driver including a driving transistor. The drain of the driving transistor is coupled to a corresponding word line or select gate line (WL / SGL) of the second storage plane, the source of the driving transistor is coupled to a corresponding local word line or local select gate line (LWL / LSGL) of the second storage plane, and the gate of the driving transistor is coupled to a decoder and configured to receive a corresponding control signal (VXD_PLA) of the second storage plane. Similarly, the word line driver 308 of the peripheral circuitry 102 of the second storage plane may include a string driver (PLB string driver), each string driver including a driving transistor. The drain of the driving transistor is coupled to a corresponding word line or select gate line (WL / SGL) of the second memory plane, the source of the driving transistor is coupled to a corresponding local word line or local select gate line (LWL / LSGL) of the second memory plane, and the gate of the driving transistor is coupled to the decoder and configured to receive a corresponding control signal (VXD_PLB) of the second memory plane. Each driving transistor can be a p-type transistor or an N-type transistor.

[0092] like Figure 10 As shown, between the first time t1 and the second time t2 (the end pre-pulse period of the first memory plane), by setting the control signal (VXD_PLB) of the second memory plane to a low level (logic "0"), the string driver (PLB string driver) of the second memory plane can be configured to be disabled to float the voltages on the word lines and select gate lines in the second memory plane (e.g., as shown). Figure 9B (As shown). In contrast, by setting the control signal (VXD_PLA) of the first storage plane to a high level (logic "1"), the string driver (PLA string driver) of the first storage plane can be configured to be enabled to perform operations during the end pre-pulse period of the first storage plane (e.g., as shown). Figure 9A (As shown). At the second time 2, the control signal for the second storage plane can be switched to a high level (logic "1") to enable the serial driver of the second storage plane to resume multi-plane programming operations on the second storage plane, while the control signal for the first storage plane can be switched to a low level (logic "0") to disable the serial driver of the first storage plane to stop multi-plane programming operations on the first storage plane.

[0093] Return to reference Figure 9BMulti-plane programming operations on the second memory plane can be resumed at the second time t2. The programming cycle 504 immediately following the non-last cycle may include a programming period (phase) after the merged recovery / pre-pulse period, wherein the word line driver 308 of the peripheral circuitry 102 may also be configured to apply a programming voltage (Vpgm) with one or more programming voltage pulses to the selected word line to program the selected memory cell to one or more levels. During the programming period, the word line driver 308 of the peripheral circuitry 102 may also be configured to apply a pass voltage to each unselected word line to conduct the channel for programming.

[0094] Although the above text is Figure 8 The description of multi-plane programming operations pertains to two memory planes (first memory plane PLA and second memory plane PLB), but it should be understood that the same approach can be applied to memory devices comprising more than two memory planes (such as three memory planes). For example, Figure 11 A schematic timing diagram of another multi-plane programming operation with multiple loops, based on some aspects of this disclosure, is shown.

[0095] like Figure 11 As shown, according to some embodiments, the peripheral circuit 102 is configured to: simultaneously initiate multi-plane programming operations on the first storage plane (PLA), the second storage plane (PLB), and the third storage plane (PLC); stop multi-plane programming operations on the first storage plane before the second storage plane; and stop multi-plane programming operations on the second storage plane before the third storage plane, for example, because the first and second storage planes are fast planes or failure planes. In some embodiments, the peripheral circuit 102 is configured to: after the verification cycle of the last cycle on the first storage plane (e.g., in...). Figure 11 Between the first time t1 and the second time t2, during the end of the pre-pulse period ( Figure 11 In the "verification pre-pulse" (as described in the text), additional operations are performed on the first storage plane where the operation stopped earliest to restore the word line voltage to a lower level and reset the channel potential. In some embodiments, the peripheral circuit 102 is also configured to: during the end pre-pulse period between the first time t1 and the second time t2, suspend programming operations on the second storage plane and the third storage plane to avoid interrupting the combined recovery / pre-pulse period (as described in the text). Figure 11The interference with planned operations on the second and third storage planes (in the "merged recovery") is addressed. In some embodiments, the peripheral circuitry 102 is further configured to resume multi-plane programming operations on the second and third storage planes after the end pre-pulse period (second time t2) of the first storage plane. That is, the first storage plane that stops earliest can stop programming operations after its end pre-pulse period rather than after the merged recovery / pre-pulse period, and the second and third storage planes can be temporarily disabled during the end pre-pulse period of the first storage plane and can be re-enabled after programming operations on the first storage plane stop.

[0096] In some implementations, the peripheral circuitry 102 is further configured to: after the verification cycle of the last loop of the second storage plane (e.g., in... Figure 11 Between the third time t3 and the fourth time t4, during the end of the pre-pulse period ( Figure 11 In the "verification pre-pulse" (as described in the text), additional operations are performed on the second memory plane that stopped earlier to restore the word line voltage to a lower level and reset the channel potential. In some embodiments, the peripheral circuit 102 is also configured to suspend programming operations on the third memory plane during the end pre-pulse period between the third time t3 and the fourth time t4 to avoid the combined recovery / pre-pulse period (as described in the text). Figure 11 The interference with the planned operation on the third storage plane in the "merged recovery" (as described in the text) is addressed. In some embodiments, the peripheral circuitry 102 is further configured to resume programming operations on the third storage plane after the end pre-pulse period (fourth time t4) of the second storage plane. That is, the second storage plane, which stopped earlier, can stop programming operations after its end pre-pulse period rather than after the merged recovery / pre-pulse period, and the third storage plane can be temporarily disabled again during the end pre-pulse period of the second storage plane and can be re-enabled after programming operations on the second storage plane have stopped.

[0097] In some implementations, the peripheral circuit 102 is also configured to: also at the end of the verification cycle of the last loop in the third storage plane during the end pre-pulse period ( Figure 11 In the "verification pre-pulse" (in the memory), additional operations are performed on the third memory plane to restore the word line voltage to a lower level and reset the channel potential.

[0098] Figure 12A flowchart of a method 1200 for programming a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 400. Method 1200 can be implemented by peripheral circuitry 102, such as a line decoder / word line driver 308, a page buffer / sensor amplifier 304, and control logic 312. It should be understood that the operations shown in method 1200 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously or in conjunction with... Figure 12 The different sequences shown are executed.

[0099] refer to Figure 12 Method 1200 begins at operation 1202, in which programming operations are simultaneously initiated on the first, second, and third storage planes. In some embodiments, programming operations are stopped on the first storage plane before the second storage plane, and programming operations are stopped on the second storage plane before the third storage plane. For example, as... Figure 11 As shown, multi-plane programming operations begin simultaneously on PLA, PLB, and PLC. The multi-plane programming operation is first stopped on PLA, then on PLB, and finally on PLC.

[0100] Method 1200 proceeds to operation 1204, such as... Figure 12 As shown, in operation 1204, programming operations are paused on the second and third memory planes from a first time point to a second time point. In some embodiments, to pause programming operations on the second and third memory planes, the string drivers of the second and third memory planes are disabled to float the voltages on the word lines in the second and third memory planes. For example, as... Figure 11 As shown, from t1 to t2 (where PLA is experiencing its end pre-pulse period), the multi-plane programming operation is paused on both PLB and PLC.

[0101] Method 1200 proceeds to operation 1206, such as... Figure 12 As shown, in operation 1206, programming operations are paused on the third memory plane from the third time to the fourth time. In some embodiments, to pause programming operations on the third memory plane, the string driver of the third memory plane is disabled to float the voltage on the word lines in the third memory plane. For example, as... Figure 11 As shown, from t3 to t4 (during which the PLB is experiencing its end pre-pulse period), the multi-plane programming operation is paused again on the PLC.

[0102] Figure 13A flowchart of a method 1300 for programming a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 400. Method 1300 can be implemented by peripheral circuitry 102, such as a line decoder / word line driver 308, a page buffer / sensor amplifier 304, and control logic 312. It should be understood that the operations shown in method 1300 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously or in conjunction with... Figure 13 The different sequences shown are executed.

[0103] refer to Figure 13 Method 1300 begins at operation 1302, in which a bias voltage is applied to the select word line after a verification voltage is applied to the select word line. For example, as Figure 9A As shown, in the verification cycle 506 of the last cycle of the earlier stopped plane, a verification voltage (Vvfy) is applied to the select word line. Subsequently, during the combined recovery / pre-pulse period of verification cycle 506, a first bias voltage (V1) is applied to the select word line.

[0104] In some implementations, before applying a bias voltage to the select word line, after applying a verification voltage to the select word line, a post-pulse voltage is applied to the select word line in the word line, the voltage on the select word line is ramped down from the post-pulse voltage to a first supply voltage, and then the voltage on the select word line is ramped up from the first supply voltage to the bias voltage. For example, as... Figure 9A As shown, during the combined recovery / pre-pulse period of verification cycle 506, after applying a verification voltage (Vvfy) to the select word line, a post-pulse voltage (Vpost) is applied to the select word line. Then, the voltage on the select word line is ramped down from the post-pulse voltage to the first supply voltage (Vdd), and then immediately ramped up from the first supply voltage to the first bias voltage (V1).

[0105] Method 1300 proceeds to operation 1304, such as... Figure 13 As shown, in operation 1304, the voltage on the select word line is ramped down from the bias voltage to the first supply voltage. For example, as... Figure 9A As shown, starting from the first time t1 in the end of the pre-pulse period, the voltage on the select word line is gradually reduced from the first bias voltage (V1) to the first supply voltage (Vdd).

[0106] Method 1300 proceeds to operation 1306, such as... Figure 13 As shown, in operation 1306, the voltage on the select word line is ramped up from the first supply voltage to the pass voltage. In some embodiments, the bias voltage is between the first supply voltage and the pass voltage. For example, as... Figure 9A As shown, the voltage on the select word line is ramped up from the first supply voltage (Vdd) to the pass voltage (Vpass) and then maintained at the pass voltage for a period of time.

[0107] Method 1300 proceeds to operation 1308, such as... Figure 13 As shown, in operation 1308, the voltage on the select gate line is ramped up from a second supply voltage, which is lower than the first supply voltage, to the select voltage. For example, as... Figure 9A As shown, while the voltage on the select word line is ramped up from the first supply voltage to the pass voltage and then maintained at the pass voltage for a period of time, the voltage on the DSG line or SSG line is ramped up from the first supply voltage (Vdd) to the select voltage (Vsel) and then maintained at the select voltage for a period of time.

[0108] Method 1300 proceeds to operation 1310, such as... Figure 13 As shown, in operation 1310, the voltage on the select word line is ramped down from the pass voltage to the first supply voltage. For example, as... Figure 9A As shown, the voltage on the select word line is sloping down from the pass voltage (Vpass) to the first supply voltage (Vdd).

[0109] Method 1300 proceeds to operation 1312, such as... Figure 13 As shown, in operation 1312, the voltage on the select gate line is ramped down from the select voltage to the second supply voltage. For example, as... Figure 9A As shown, the voltage on the DSG or SSG line will be gradually reduced from the selected voltage (Vsel) to the second supply voltage (Vss).

[0110] As mentioned above Figure 8 and Figure 10 The aforementioned applies to planes that do not stop earlier (e.g., Figure 8 PLB and Figure 11 In the final loop of a multi-programming operation performed on a PLC, an end prepulse period can be added at the end in the same manner as the end prepulse period of the earlier stopped plane to refresh its channel and restore the word line voltage to a lower level. In some embodiments, a programming voltage is applied to the select word line of the second memory plane (not the earlier stopped plane) after a second time when the voltage on the select word line in the first memory plane (the earlier stopped plane) is ramped down from the through voltage to the first supply voltage. For example, as Figure 9BAs shown, in programming cycle 504 after the second time t2, a programming voltage (Vpgm) is applied to the select word line. In some embodiments, in the final loop of the programming operation on the second memory plane (not the earlier stopped plane), after applying the verification voltage to the select word line, a bias voltage is applied to the select word line, the voltage on the select word line is ramped down from the bias voltage to the first supply voltage, the voltage on the select word line is ramped up from the first supply voltage to the pass voltage, and the voltage on the select word line is ramped down from the pass voltage to the first supply voltage. For example, Figure 9A The operations on the first storage plane between the first time t1 and the second time t2 can be similarly applied to the second storage plane in the final loop of the programming operations on the second storage plane.

[0111] Figure 14 A block diagram of a system 1400 having storage devices according to some aspects of this disclosure is shown. System 1400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 14 As shown, system 1400 may include host 1408 and having one or more storage devices 100 (in Figure 1 The memory system 1402 is shown in the diagram and includes a memory controller 1406. The host 1408 can be a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host 1408 can be configured to send data to or receive data from the memory device 100.

[0112] Storage device 100 can be any storage device disclosed herein. According to some embodiments, memory controller 1406 is coupled to storage device 100 and host 1408 and configured to control storage device 100. Memory controller 1406 can manage data stored in storage device 100 and communicate with host 1408. In some embodiments, memory controller 1406 is designed to operate in a low duty cycle environment (e.g., a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, memory controller 1406 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC) used for data storage in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Memory controller 1406 can be configured to control the operation of storage device 100, such as read, erase, and program operations. The memory controller 1406 can also be configured to manage various functions relating to data stored or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1406 is also configured to process error correction codes (ECC) relating to data read from or written to the storage device 100. Any other suitable functions may also be performed by the memory controller 1406, such as formatting the storage device 100. The memory controller 1406 may communicate with external devices (e.g., host 1408) according to specific communication protocols. For example, the memory controller 1406 can communicate with external devices through at least one of various interface protocols, such as USB protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0113] The memory controller 1406 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 1402 can be implemented and packaged into different types of end electronic products. Figure 15AIn one example shown, the memory controller 1406 and a single storage device 100 can be integrated into a memory card 1502. The memory card 1502 may include a PC card (PCMCIA (Personal Computer Memory Card International Association)), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1502 may also include a connection between the memory card 1501 and a host (e.g., Figure 14 The memory card connector 1404 is coupled to the host 1408. In such a... Figure 15B In another example shown, the memory controller 1406 and multiple storage devices 100 can be integrated into the SSD 1506. The SSD 1506 may also include an SSD connector 1508 that connects the SSD 1506 to a host computer (e.g., ...). Figure 14 The SSD 1506 is coupled to the host 1408 in the memory card 1502. In some implementations, the storage capacity and / or operating speed of the SSD 1506 is greater than that of the memory card 1502.

[0114] The foregoing description can be easily modified and / or adapted for various applications to suit specific implementations. Therefore, based on the teachings and guidance provided herein, these adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation.

[0115] The scope and extent of this disclosure should not be limited to any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

[0116] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged with each other in a manner consistent with the scope of this disclosure.

Claims

1. A storage device, comprising: A first storage plane includes storage cells and word lines that are respectively coupled to rows of the storage cells; as well as Peripheral circuitry, coupled to the first memory plane via the word lines, is configured such that, in the final loop of a programming operation on the first memory plane: After applying a verification voltage to the select word line in the word lines, the voltage on the select word line is ramped up from the first supply voltage (Vdd) to the pass voltage; and The voltage on the selected word line in the word line is reduced from the through voltage to the first supply voltage.

2. The storage device according to claim 1, wherein, The peripheral circuitry is also configured to: in the final loop of the programming operation on the first storage plane: After applying the verification voltage to the select word line, a bias voltage is applied to the select word line, the bias voltage being between the first supply voltage and the pass voltage; as well as Before ramping the voltage on the select word line from the first supply voltage to the pass voltage, the voltage on the select word line is ramped down from the bias voltage to the first supply voltage.

3. The storage device according to claim 1 or 2, wherein, The first storage plane further includes: The select gate transistors are respectively coupled to the columns of the memory cells; and The select gate line coupled to the select gate transistor; The peripheral circuitry is coupled to the first memory plane via the selected gate line and is further configured such that, in the final loop of the programming operation on the first memory plane: The voltage on the selected gate line is ramped up from a second supply voltage (Vss) that is lower than the first supply voltage to the selected voltage; and The voltage on the selected gate line is gradually reduced from the selected voltage to the second supply voltage.

4. The storage device according to claim 2, further comprising: The second storage plane includes storage cells and word lines that are coupled to rows of the storage cells. The peripheral circuitry is coupled to the first storage plane and the second storage plane and is configured to: start the programming operation simultaneously on the first storage plane and the second storage plane, and stop the programming operation on the first storage plane before the second storage plane.

5. The storage device according to claim 4, wherein, The peripheral circuitry is configured to pause the programming operation on the second storage plane from a first time when the voltage on the select word line in the first storage plane begins to slope down from the bias voltage to the first supply voltage until a second time when the voltage on the select word line in the first storage plane slopes down from the pass voltage to the first supply voltage.

6. The storage device according to claim 5, wherein, The peripheral circuitry includes string drivers that are respectively coupled to the word lines in the second storage plane; as well as In order to suspend the programming operation on the second storage plane, the string driver is configured to be disabled to float the voltage on the word line in the second storage plane.

7. The storage device according to claim 5 or 6, wherein, The peripheral circuitry is further configured to apply a programming voltage to the select word line among the word lines in the second memory plane after the second time.

8. The storage device according to claim 5, wherein, The peripheral circuitry is also configured to: in the final loop of the programming operation on the second storage plane: After applying the verification voltage to the select word line, the bias voltage is applied to the select word line; The voltage on the select word line is sloppily reduced from the bias voltage to the first supply voltage; The voltage on the select word line is increased from the first supply voltage to the pass voltage; as well as The voltage on the select word line is sloping down from the pass voltage to the first supply voltage.

9. The storage device according to claim 8, further comprising: Third storage plane, The peripheral circuitry is coupled to the first storage plane, the second storage plane, and the third storage plane and is configured to: simultaneously begin the programming operation on the first storage plane, the second storage plane, and the third storage plane, and stop the programming operation on the second storage plane before the third storage plane.

10. The storage device according to claim 9, wherein, The peripheral circuit is configured as follows: The programming operation is paused on the third storage plane from the first time when the voltage on the select word line in the first storage plane starts to slope down from the bias voltage to the first supply voltage until the second time after the voltage on the select word line in the first storage plane slopes down from the pass voltage to the first supply voltage. as well as The programming operation is paused on the third storage plane from a third time when the voltage on the select word line in the second storage plane begins to slope down from the bias voltage to the first supply voltage until a fourth time after the voltage on the select word line in the second storage plane slopes down from the pass voltage to the first supply voltage.

11. The storage device according to claim 2, wherein, The peripheral circuitry is also configured to: in the final loop of the programming operation on the first memory plane, before applying the bias voltage to the select word line: After the verification voltage is applied to the select word line, a post-pulse voltage is applied to the select word line in the word line; The voltage on the select word line is gradually reduced from the post-pulse voltage to the first supply voltage; as well as Then, the voltage on the select word line is increased from the first supply voltage to the bias voltage.

12. A method for operating a storage device, the storage device including a first storage plane, the first storage plane including storage cells and word lines respectively coupled to rows of the storage cells, the method comprising: In the final loop of the programming operations on the first storage plane: After applying a verification voltage to the select word line in the word lines, the voltage on the select word line is ramped up from the first supply voltage (Vdd) to the pass voltage; and The voltage on the selected word line in the word line is reduced from the through voltage to the first supply voltage.

13. The method of claim 12, further comprising: In the final loop of the programming operation on the first storage plane: After applying the verification voltage to the select word line, a bias voltage is applied to the select word line, the bias voltage being between the first supply voltage and the pass voltage; as well as Before ramping the voltage on the select word line from the first supply voltage to the pass voltage, the voltage on the select word line is ramped down from the bias voltage to the first supply voltage.

14. The method according to claim 12 or 13, wherein, The first storage plane further includes select gate transistors that are respectively coupled to columns of the storage cells and select gate lines that are coupled to the select gate transistors; as well as The method further includes: in the final loop of the programming operation on the first storage plane: The voltage on the selected gate line is ramped up from a second supply voltage (Vss) that is lower than the first supply voltage to the selected voltage; as well as The voltage on the selected gate line is gradually reduced from the selected voltage to the second supply voltage.

15. The method according to claim 13, wherein, The storage device further includes a second storage plane, the second storage plane including storage cells and word lines respectively coupled to rows of the storage cells; as well as The method further includes: Simultaneously, the programming operation begins on both the first storage plane and the second storage plane; as well as The programming operation is stopped on the first storage plane before the second storage plane.

16. The method of claim 15, further comprising: The programming operation is paused on the second storage plane from a first time when the voltage on the select word line in the first storage plane begins to slope down from the bias voltage to the first supply voltage until a second time when the voltage on the select word line in the first storage plane slopes down from the pass voltage to the first supply voltage.

17. The method according to claim 16, wherein, The storage device further includes a string driver for the word lines, which are respectively coupled to the second storage plane; as well as Pausing the programming operation on the second storage plane includes disabling the string driver to float the voltage on the word lines in the second storage plane.

18. The method according to claim 16 or 17, further comprising: After the second time, a programming voltage is applied to the select word line among the word lines in the second storage plane.

19. The method of claim 16, further comprising: In the final loop of the programming operation on the second storage plane: After applying the verification voltage to the select word line, the bias voltage is applied to the select word line; The voltage on the select word line is sloppily reduced from the bias voltage to the first supply voltage; The voltage on the select word line is increased from the first supply voltage to the pass voltage; as well as The voltage on the select word line is sloping down from the pass voltage to the first supply voltage.

20. The method according to claim 19, wherein, The storage device further includes a third storage plane; and The method further includes: Simultaneously, the programming operation begins on the first storage plane, the second storage plane, and the third storage plane; and The programming operation is stopped on the second storage plane before the third storage plane.

21. The method of claim 20, further comprising: The programming operation is paused on the third storage plane from the first time when the voltage on the select word line in the first storage plane starts to slope down from the bias voltage to the first supply voltage until the second time after the voltage on the select word line in the first storage plane slopes down from the pass voltage to the first supply voltage. as well as The programming operation is paused on the third storage plane from a third time when the voltage on the select word line in the second storage plane begins to slope down from the bias voltage to the first supply voltage until a fourth time after the voltage on the select word line in the second storage plane slopes down from the pass voltage to the first supply voltage.

22. The method of claim 13, further comprising, in the final loop of the programming operation on the first memory plane, before applying the bias voltage to the select word line: After the verification voltage is applied to the select word line, a post-pulse voltage is applied to the select word line in the word line; The voltage on the select word line is gradually reduced from the post-pulse voltage to the first supply voltage; as well as Then, the voltage on the select word line is increased from the first supply voltage to the bias voltage.

23. A system comprising: Storage device, configured to store data and comprising: A first storage plane includes storage cells and word lines respectively coupled to rows of the storage cells; and Peripheral circuitry, coupled to the first memory plane via the word lines, is configured such that, in the final loop of a programming operation on the first memory plane: After applying a verification voltage to the select word line in the word lines, the voltage on the select word line is ramped up from the first supply voltage (Vdd) to the pass voltage; and The voltage on the selected word line in the word line is ramped down from the through voltage to the first supply voltage; and A memory controller, which is coupled to the memory device and configured to control the memory device.

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