Video signal generator supporting multi-protocol output and programmable timing

Abstract

The application discloses a video signal generator supporting multiple protocol outputs and timing programming, comprising a power module, a clock module, an optical fiber data receiving module, a cache management module and a multiple protocol video and timing generation module. The application takes a field programmable logic gate array as a core architecture, solves the problems of single protocol and non-self-defined video timing of a traditional video signal generator, has the ability of multiple channel independent and synchronous output and non-standard timing video generation, and can provide required signal sources for development and test of various video display devices.

Description

Technical Field

[0001] This invention relates to the field of video signal generation technology, specifically to a video signal generator that supports multiple protocol outputs and has programmable timing. It aims to solve the problems of traditional video signal generators having a single protocol and uncustomizable video timing, and to provide the non-standard video signal source required for the development and testing of various video display devices. Background Technology

[0002] A video signal generator is an electronic device widely used in the development, debugging, and testing of video display equipment. It generates standard test images and video timing signals according to predetermined video formats, playing a crucial role in the research and development and production of monitors, video interfaces, circuit boards, and complete systems. Traditional video signal generators typically output fixed-format video signals, such as common standard resolutions like 640×480, 1280×720, and 1920×1080, and support basic test images such as color bars, grayscale images, and monochrome images for basic functional verification and display quality evaluation of video systems.

[0003] With the continuous development of display technology and video interface technology, the interface protocols adopted by video devices are gradually becoming more diversified. Currently common video interfaces include DVI, HDMI, and LVDS, among others. These interfaces differ significantly in signal levels, electrical characteristics, and encoding methods. Existing video signal generators typically only support one or a few fixed video interface protocols. When facing testing requirements with multiple interface standards coexisting, it is often necessary to use multiple different devices for signal generation, resulting in high equipment costs, complex system integration, and difficulty in meeting the needs of a unified multi-interface testing platform.

[0004] On the other hand, existing video signal generators typically have significant limitations in video timing configuration. Most devices only support a limited number of preset video resolution and refresh rate standards, making it difficult for users to flexibly configure key timing parameters such as horizontal synchronization, vertical synchronization, blanking zones, and pixel clocks. During the R&D and interface debugging of video display devices, engineers often need to generate non-standard video signals with specific timing parameters to verify the performance of display devices under extreme conditions or to conduct compatibility tests. Traditional video signal generators struggle to meet the generation requirements of such non-standard timing videos.

[0005] Furthermore, in the development and testing of complex video systems, it is often necessary to output multiple video signals simultaneously, and to set different resolutions, refresh rates, or interface protocols for each video signal according to different testing requirements. Traditional video signal generators typically adopt a single-channel or multi-channel unified timing output structure, lacking independent configuration capabilities between channels. This makes it difficult to achieve flexible combination and synchronous output of multi-channel video signals, limiting their application scope in the testing of multi-interface video systems.

[0006] Therefore, developing a video signal generator that can support multiple video interface protocol outputs and allows for flexible programming and configuration of video timing parameters is of great significance for meeting the research and testing needs of modern video display devices. Summary of the Invention

[0007] The purpose of this invention is to provide a video signal generator that supports multi-protocol output and programmable timing. It not only provides standard test images and video resolution and frame rate settings typical of traditional video signal generators, but also supports custom configuration of video timing parameters. Furthermore, it supports simultaneous independent output of different test images and video timings from multiple video interfaces, providing the necessary non-standard video signal source for the development and testing of various video display devices.

[0008] The specific technical solution for implementing this invention is as follows: A video signal generator that supports multi-protocol output and programmable timing is characterized by comprising a power supply module, a clock module, an optical fiber data receiving module, a buffer management module, and a multi-protocol video and timing generation module. The power supply module is connected to the clock module, the fiber optic data receiving module, the buffer management module, and the multi-protocol video and timing generation module, respectively, and provides the voltage and current required for the clock module, the fiber optic data receiving module, the buffer management module, and the multi-protocol video and timing generation module to work. The clock module is connected to the fiber optic data receiving module, the buffer management module, and the multi-protocol video and timing generation module respectively, providing different frequency clocks required for the operation of the fiber optic data receiving module, the buffer management module, and the multi-protocol video and timing generation module. The fiber optic data receiving module is connected to the power module, clock module, buffer management module and multi-protocol video and timing generation module to receive control commands and test images. The cache management module is connected to the power module, clock module, fiber optic data receiving module and multi-protocol video and timing generation module respectively, so as to cache multiple test images for independent output by each channel of the multi-protocol video and timing generation module. The multi-protocol video and timing generation module is connected to the power module, clock module, fiber optic data receiving module, and buffer management module to output video signals according to the timing and test images specified by the fiber optic data receiving module.

[0009] Furthermore, the fiber optic data receiving module includes a UDP unpacking module and a command and test image splitting module; The UDP unpacking module and the instruction and test image splitting module are connected to extract the payload in the received MAC frame and transmit it to the instruction and test image splitting module for further classification. The instructions are connected to the test image splitting module and the UDP unpacking module to distinguish between the instructions and test images in the load. The instructions are used to configure the cache management module and the multi-protocol video and timing generation module, while the test images are managed by the configuration cache management module.

[0010] Furthermore, the cache management module includes a DDR4 interface control module, a read / write channel and address management module, a data writing module, a first data reading module, a second data reading module, a third data reading module, and a read / write request arbitration module; The DDR4 interface control module is connected to the read / write request arbitration module and is used to control the physical interface with the DDR4 device and initiate read / write requests generated by the read / write request arbitration module to the DDR4 device. The read / write channel and address management module is connected to the data writing module, the first data reading module, the second data reading module and the third data reading module. According to the instructions issued by the fiber optic data receiving module, it controls the data read / write addresses of the data writing module, the first data reading module, the second data reading module and the third data reading module. The data writing module and read / write channel are connected to the address management module and the read / write request arbitration module, and request the read / write request arbitration module to write the test image transmitted by the fiber optic data receiving module into the write address provided by the read / write channel and the address management module. The first data reading module and read / write channel are connected to the address management module and the read / write request arbitration module. The first data reading module and read / write channel are connected to the address management module. The first data reading module requests the read / write request arbitration module to read the data in the read address provided by the read / write channel and the address management module. The data is then transmitted to the multi-protocol video and timing generation module for the generation of LVDS video signals. The second data reading module and read / write channel are connected to the address management module and read / write request arbitration module. The read / write request arbitration module requests data from the read address provided by the read / write channel and address management module, and transmits the data to the multi-protocol video and timing generation module for the generation of HDMI video signals. The third data reading module and the read / write channel are connected to the address management module and the read / write request arbitration module. The module requests the read / write request arbitration module to read the data in the read address provided by the read / write channel and the address management module, and transmits the data to the multi-protocol video and timing generation module for the generation of DVI video signals.

[0011] Furthermore, the multi-protocol video and timing generation module includes an LVDS video timing generation module, an LVDS video signal output module, an HDMI video timing generation module, an HDMI video signal output module, a DVI video timing generation module, and a DVI video signal output module. The LVDS video timing generation module and the instruction are connected to the test image splitting module and the LVDS video signal output module. The video timing is generated according to the configuration issued by the instruction and the test image splitting module, and then output to the LVDS video signal output module to generate a video signal. The LVDS video signal output module is connected to the LVDS video timing generation module and the buffer management module. It reads the test image buffered in the buffer management module and outputs the LVDS protocol video signal according to the timing given by the LVDS video timing generation module. The HDMI video timing generation module and the instruction are connected to the test image splitting module and the HDMI video signal output module. The video timing is generated according to the configuration issued by the instruction and the test image splitting module, and then output to the HDMI video signal output module to generate a video signal. The HDMI video signal output module is connected to the HDMI video timing generation module and the cache management module. It reads the test image cached in the cache management module and outputs the HDMI protocol video signal according to the timing given by the HDMI video timing generation module. The DVI video timing generation module and the instruction are connected to the test image splitting module and the DVI video signal output module. The DVI video timing is generated according to the configuration issued by the instruction and the test image splitting module, and then output to the DVI video signal output module to generate a video signal. The DVI video signal output module is connected to the DVI video timing generation module and the buffer management module. It reads the test image cached in the buffer management module and outputs the DVI protocol video signal according to the timing given by the DVI video timing generation module. Furthermore, the LVDS video timing generation module, HDMI video timing generation module, and DVI video timing generation module support programming of video timing parameters, including horizontal effective pixels, vertical effective lines, horizontal and vertical front shoulders, horizontal and vertical effective values, horizontal and vertical back shoulders, horizontal total pixel value and vertical total number of lines, resolution, and frame rate.

[0012] Furthermore, the multi-protocol video and timing generation module supports video signal output up to 4K@60Hz.

[0013] The advantages of this invention are: 1) This invention supports multi-protocol video signal output. Through a unified video generation architecture, it simultaneously supports multiple video interface protocols such as LVDS, HDMI, and DVI, reducing the need for multiple signal generation devices and improving system integration.

[0014] 2) This invention supports programmable video timing parameters. This invention can configure video timing parameters such as horizontal effective pixels, vertical effective lines, front shoulder, back shoulder, sync pulse width, total number of pixels, and frame rate, and can generate standard or non-standard timing video signals.

[0015] 3) This invention supports multi-channel independent video output. Through a buffer management module, this invention provides independent data reading paths for each video interface channel, enabling different channels to independently configure resolution, timing parameters, and output protocols, thus achieving parallel output of multiple video signals.

[0016] 4) This invention features a modular structure and strong scalability. The modular design facilitates the expansion of new interface protocols or the addition of video output channels, demonstrating significant engineering application value. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of the present invention; Figure 2 This is a block diagram of the fiber optic data receiving module. Figure 3 This is a structural block diagram of the cache management module; Figure 4 A structural block diagram of the multi-protocol video and timing generation module; Figure 5 This is a flowchart of the process of the present invention. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] See Figure 1 A video signal generator that supports multi-protocol output and programmable timing includes a power supply module 1, a clock module 2, an optical fiber data receiving module 3, a buffer management module 4, and a multi-protocol video and timing generation module 5. The power module 1 is connected to the clock module 2, the fiber optic data receiving module 3, the buffer management module 4, and the multi-protocol video and timing generation module 5 respectively, providing the voltage and current required for the clock module 2, the fiber optic data receiving module 3, the buffer management module 4, and the multi-protocol video and timing generation module 5 to work. The clock module 2 is connected to the fiber optic data receiving module 3, the buffer management module 4, and the multi-protocol video and timing generation module 5 respectively, providing different frequency clocks required for the operation of the fiber optic data receiving module 3, the buffer management module 4, and the multi-protocol video and timing generation module 5. The fiber optic data receiving module 3 is connected to the power module 1, the clock module 2, the buffer management module 4, and the multi-protocol video and timing generation module 5 respectively, so as to receive control commands and test images. The cache management module 4 is connected to the power module 1, the clock module 2, the optical fiber data receiving module 3 and the multi-protocol video and timing generation module 5 respectively, so as to cache multiple test images for independent output by each channel of the multi-protocol video and timing generation module 5. The multi-protocol video and timing generation module 5 is connected to the power module 1, clock module 2, fiber optic data receiving module 3 and buffer management module 4, so as to output video signals according to the timing and test images specified by the fiber optic data receiving module 3.

[0020] See Figure 2 The fiber optic data receiving module 3 includes a UDP unpacking module 31 and a command and test image splitting module 32; The UDP unpacking module 31 is connected to the instruction and test image splitting module 32 to extract the payload in the received MAC frame and transmit it to the instruction and test image splitting module 32 for further classification. The instructions are connected to the test image splitting module 32 and the UDP unpacking module 31 to distinguish the instructions in the load from the test images. The instructions are used to configure the cache management module 4 and the multi-protocol video and timing generation module 5, while the test images are managed by the configuration cache management module 4.

[0021] See Figure 3 The cache management module 4 includes a DDR4 interface control module 41, a read / write channel and address management module 42, a data writing module 43, a first data reading module 44, a second data reading module 45, a third data reading module 46, and a read / write request arbitration module 47. The DDR4 interface control module 41 is connected to the read / write request arbitration module 47 and is used to control the physical interface with the DDR4 device and initiate read / write requests generated by the read / write request arbitration module 47 to the DDR4 device. The read / write channel and address management module 42 is connected to the data writing module 43, the first data reading module 44, the second data reading module 45 and the third data reading module 46. According to the instructions issued by the fiber optic data receiving module 3, it controls the data read / write addresses of the data writing module 43, the first data reading module 44, the second data reading module 45 and the third data reading module 46. The data writing module 43 and the read / write channel are connected to the address management module 42 and the read / write request arbitration module 47, and the test image transmitted by the fiber optic data receiving module 3 requests the read / write request arbitration module 47 to write it into the write address provided by the read / write channel and the address management module 42. The first data reading module 44 is connected to the read / write channel and address management module 42 and the read / write request arbitration module 47. It requests the read / write request arbitration module 47 to read the data in the read address provided by the read / write channel and address management module 42, and transmits the data to the multi-protocol video and timing generation module 5 for the generation of LVDS video signals. The second data reading module 45 is connected to the read / write channel and address management module 42 and the read / write request arbitration module 47. It requests the read / write request arbitration module 47 to read the data in the read address provided by the read / write channel and address management module 42, and transmits the data to the multi-protocol video and timing generation module 5 for the generation of HDMI video signals. The third data reading module 46 is connected to the read / write channel and address management module 42 and the read / write request arbitration module 47. It requests the read / write request arbitration module 47 to read the data in the read address provided by the read / write channel and address management module 42, and transmits the data to the multi-protocol video and timing generation module 5 for the generation of DVI video signals.

[0022] See Figure 4 The multi-protocol video and timing generation module 5 includes an LVDS video timing generation module 51, an LVDS video signal output module 52, an HDMI video timing generation module 53, an HDMI video signal output module 54, a DVI video timing generation module 55, and a DVI video signal output module 56. The LVDS video timing generation module 51 is connected to the optical fiber data receiving module 3 and the LVDS video signal output module 52. The video timing is generated according to the configuration issued by the optical fiber data receiving module 3 and output to the LVDS video signal output module 52 to generate a video signal. The LVDS video signal output module 52 is connected to the LVDS video timing generation module 51 and the buffer management module 4. It reads the test image buffered in the buffer management module 4 and outputs the LVDS protocol video signal according to the timing given by the LVDS video timing generation module 51. The HDMI video timing generation module 53 is connected to the optical fiber data receiving module 3 and the HDMI video signal output module 54. The video timing is generated according to the configuration issued by the optical fiber data receiving module 3 and output to the HDMI video signal output module 54 to generate a video signal. The HDMI video signal output module 54 is connected to the HDMI video timing generation module 53 and the cache management module 4. It reads the test image cached in the cache management module 4 and outputs the HDMI protocol video signal according to the timing given by the HDMI video timing generation module 53. The DVI video timing generation module 55 is connected to the fiber optic data receiving module 3 and the DVI video signal output module 56. The video timing is generated according to the configuration issued by the fiber optic data receiving module 3 and output to the DVI video signal output module 56 to generate a video signal. The DVI video signal output module 56 is connected to the DVI video timing generation module 55 and the buffer management module 4. It reads the test image buffered in the buffer management module 4 and outputs the DVI protocol video signal according to the timing given by the DVI video timing generation module 55. Example

[0023] The modules selected in this embodiment are as follows: the main controllers of the fiber optic data receiving module 3, the buffer management module 4, and the multi-protocol video and timing generation module 5 are implemented using Xilinx's Zynq UltraScale+ series chips, which have abundant logic resources and are equipped with SFP+, DDR4 interfaces and high-speed transceivers, and can support the transmission and buffering requirements of high-bandwidth video signals.

[0024] See Figure 5This embodiment can constitute a video signal generator supporting multi-protocol output and programmable timing. The program is embedded in an SD card, inserted into the system and powered on. An arbitrary designated host is connected to the system using an optical fiber. The designated host sends the video timing and test images from the three channels to the optical fiber data receiving module 3. After processing by the UDP unpacking module 31 and the instruction and test image splitting module 32, the timing parameters and test images are transmitted to the multi-protocol video and timing generation module 5 and the buffer management module 4, respectively. The data writing module 43 sends a write request to the read / write request arbitration module 47 according to the write address provided by the read / write channel and address management module 42. Finally, the test image is buffered through the DDR4 interface control module 41. The first data reading module 44, the second data reading module 45, and the third data reading module 46 are also provided with read addresses by the read / write channel and address management module 42, and then the read / write request arbitration module 47 acts as an intermediary to read the test image from the DDR4 interface control module 41. The LVDS video signal output module 52, HDMI video signal output module 54, and DVI video signal output module 56 acquire test images from the first data reading module 44, the second data reading module 45, and the third data reading module 46, respectively, and output video signals according to the timing sequence of the LVDS video timing generation module 51, the HDMI video timing generation module 53, and the DVI video timing generation module 55, respectively. These three video signals can provide the standard or non-standard video signal sources required for the development and testing of various video display devices.

Claims

1. A video signal generator supporting multi-protocol output and programmable timing, characterized in that, It includes a power supply module (1), a clock module (2), an optical fiber data receiving module (3), a buffer management module (4), and a multi-protocol video and timing generation module (5). The power supply module (1) is connected to the clock module (2), the fiber optic data receiving module (3), the buffer management module (4) and the multi-protocol video and timing generation module (5) respectively, providing the voltage and current required for the clock module (2), the fiber optic data receiving module (3), the buffer management module (4) and the multi-protocol video and timing generation module (5) to work. The clock module (2) is connected to the fiber optic data receiving module (3), the buffer management module (4) and the multi-protocol video and timing generation module (5) respectively, providing different frequency clocks required for the operation of the fiber optic data receiving module (3), the buffer management module (4) and the multi-protocol video and timing generation module (5); The fiber optic data receiving module (3) is connected to the power supply module (1), clock module (2), buffer management module (4) and multi-protocol video and timing generation module (5) respectively, so as to receive control commands and test images; The cache management module (4) is connected to the power module (1), clock module (2), fiber optic data receiving module (3) and multi-protocol video and timing generation module (5) respectively, so as to cache multiple test images for independent output of each channel of the multi-protocol video and timing generation module (5); The multi-protocol video and timing generation module (5) is connected to the power module (1), clock module (2), fiber optic data receiving module (3) and buffer management module (4) to output video signals according to the timing and test images specified by the fiber optic data receiving module (3).

2. The video signal generator according to claim 1, characterized in that, The fiber optic data receiving module (3) includes a UDP unpacking module (31) and a command and test image splitting module (32). The UDP unpacking module (31) and the instruction and test image splitting module (32) are connected to extract the payload in the received MAC frame and transmit it to the instruction and test image splitting module (32) for further classification. The instruction is connected to the test image splitting module (32) and the UDP unpacking module (31) to distinguish the instruction in the load from the test image. The instruction is used to configure the cache management module (4) and the multi-protocol video and timing generation module (5), while the test image is managed by the configuration cache management module (4).

3. The video signal generator according to claim 1, characterized in that, The cache management module (4) includes a DDR4 interface control module (41), a read / write channel and address management module (42), a data writing module (43), a first data reading module (44), a second data reading module (45), a third data reading module (46), and a read / write request arbitration module (47). The DDR4 interface control module (41) is connected to the read / write request arbitration module (47) and is used to control the physical interface between the DDR4 device and initiate read / write requests generated by the read / write request arbitration module (47) to the DDR4 device. The read / write channel and address management module (42) is connected to the data writing module (43), the first data reading module (44), the second data reading module (45) and the third data reading module (46). According to the instructions issued by the fiber optic data receiving module (3), it controls the data read / write addresses of the data writing module (43), the first data reading module (44), the second data reading module (45) and the third data reading module (46). The data writing module (43) is connected to the read / write channel and address management module (42) and the read / write request arbitration module (47), and applies to the read / write request arbitration module (47) to write the test image transmitted by the fiber optic data receiving module (3) into the write address provided by the read / write channel and address management module (42); The first data reading module (44) is connected to the read / write channel and address management module (42) and the read / write request arbitration module (47). It requests the read / write request arbitration module (47) to read the data in the read address provided by the read / write channel and address management module (42) and transmits the data to the multi-protocol video and timing generation module (5) for the generation of LVDS video signals. The second data reading module (45) is connected to the read / write channel and address management module (42) and the read / write request arbitration module (47). It requests the read / write request arbitration module (47) to read the data in the read address provided by the read / write channel and address management module (42) and transmits the data to the multi-protocol video and timing generation module (5) for the generation of HDMI video signals. The third data reading module (46) is connected to the read / write channel and address management module (42) and the read / write request arbitration module (47). It requests the read / write request arbitration module (47) to read the data in the read address provided by the read / write channel and address management module (42) and transmits the data to the multi-protocol video and timing generation module (5) for the generation of DVI video signals.

4. The video signal generator according to claim 1, characterized in that, The multi-protocol video and timing generation module (5) includes an LVDS video timing generation module (51), an LVDS video signal output module (52), an HDMI video timing generation module (53), an HDMI video signal output module (54), a DVI video timing generation module (55), and a DVI video signal output module (56). The LVDS video timing generation module (51), the instruction and test image splitting module (32), and the LVDS video signal output module (52) are connected. The video timing is generated according to the configuration issued by the instruction and test image splitting module (32) and output to the LVDS video signal output module (52) to generate a video signal. The LVDS video signal output module (52) is connected to the LVDS video timing generation module (51) and the buffer management module (4), reads the test image cached in the buffer management module (4) and outputs the LVDS protocol video signal according to the timing given by the LVDS video timing generation module (51); The HDMI video timing generation module (53) is connected to the instruction and test image splitting module (32) and the HDMI video signal output module (54). The video timing is generated according to the configuration issued by the instruction and test image splitting module (32) and output to the HDMI video signal output module (54) to generate a video signal. The HDMI video signal output module (54) is connected to the HDMI video timing generation module (53) and the cache management module (4), reads the test image cached in the cache management module (4) and outputs the HDMI protocol video signal according to the timing given by the HDMI video timing generation module (53); The DVI video timing generation module (55) is connected to the instruction and test image splitting module (32) and the DVI video signal output module (56). The video timing is generated according to the configuration issued by the instruction and test image splitting module (32) and output to the DVI video signal output module (56) to generate a video signal. The DVI video signal output module (56) is connected to the DVI video timing generation module (55) and the cache management module (4), reads the test image cached in the cache management module (4) and outputs the DVI protocol video signal according to the timing given by the DVI video timing generation module (55).

5. The video signal generator according to claim 4, characterized in that, The LVDS video timing generation module (51), HDMI video timing generation module (53) and DVI video timing generation module (55) support programming of video timing parameters, including horizontal effective pixels, vertical effective lines, horizontal and vertical front shoulders, horizontal and vertical effective values, horizontal and vertical back shoulders, horizontal total pixel value and vertical total number of lines, resolution and frame rate.

6. The video signal generator according to claim 1, characterized in that, The multi-protocol video and timing generation module (5) supports video signal output up to 4K@60Hz.

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