Adaptive control circuit of switching converter and switching converter

Abstract

The application provides an adaptive control circuit of a switching converter and the switching converter. The adaptive control circuit performs error operation on an output feedback voltage and a first reference voltage to obtain a compensation signal, performs error amplification on a current sampling signal representing an average current of an inductor and the compensation signal to obtain a second error signal, compares a first ramp signal with a first slope and the second error signal to generate a first comparison signal, compares a second ramp signal with a second slope and a second reference voltage to generate a second comparison signal, and compares a third ramp signal with a third reference voltage to generate a third comparison signal. The first comparison signal, the second comparison signal and the third comparison signal are used to control the switching state of a main switch. The application makes the switching period of the main switch change with the load of the switching converter.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and in particular to an adaptive control circuit for a switching converter and a switching converter. Background Technology

[0002] Switching converters typically use voltage control mode or current control mode to convert input voltage into stable output voltage to achieve energy conversion. Average current mode uses dual-loop control, which has strong anti-interference ability and is widely used.

[0003] The control circuit schematic of an existing switching converter is as follows: Figure 1 As shown, the switching converter includes a current sampling circuit that samples the average current to obtain the average current sampling signal V. CS_AVG The control circuit adopts existing average current mode control, including a first error amplifier 01 forming a voltage loop, a second error amplifier 02 forming a current loop, and a comparator 03. The first error amplifier 01 outputs a feedback signal V that characterizes the output voltage. FB and the first reference voltage V REF1 The error is amplified, and the output is filtered to obtain the compensation signal V. COMP The second error amplifier 02 will compensate the signal V COMP and current sampling signal V CS_AVG The second error signal V is obtained after error amplification and filtering. CA Comparator 03 will convert the second error signal V CA and a fixed-frequency ramp signal V RAMP A comparison is performed to generate a comparison signal CMP to control the switching state of the main switch. The logic control circuit receives the comparison signal CMP and the clock signal CLK, and generates a state-complementary switching control signal V. G1 and V G2 This is to control the switching states of the main switch and rectifier diodes of the switching converter, respectively.

[0004] The waveform diagram of the control circuit is as follows Figure 2 As shown, when the clock signal CLK pulse occurs, the ramp signal V... RAMP Starting from the initial value (zero), the ramp signal V rises... RAMP Rise to the second error signal V CA At that time, the main switch control signal V G1 It becomes invalid, the main switch is turned off, and when the clock signal CLK pulse occurs, V G1 It becomes effective, and the main switch turns on. As can be seen from the waveform, with the load / output current I... OUT A decrease in V will lead to G1The pulse width and period are uneven, and the pulses are concentrated in some places, which will result in large output ripple and unstable output under light load. Summary of the Invention

[0005] The purpose of this invention is to provide an adaptive control circuit and a switching converter for a switching converter, which can adaptively adjust the switching cycle according to the load change in average current mode, so as to achieve low output ripple and stable output voltage.

[0006] This invention proposes an adaptive control circuit for a switching converter, wherein the switching converter includes a main power transistor and an inductor connected in series, and the adaptive control circuit includes:

[0007] The first error amplifier performs error calculation on the output feedback voltage of the switching converter and the first reference voltage to obtain a compensation signal;

[0008] The second error amplifier amplifies the current sampling signal, which characterizes the average inductor current, and the compensation signal to obtain the second error signal.

[0009] A first comparator compares a first ramp signal with a first slope and a second error signal. When the first ramp signal reaches the second error signal, a valid first comparison signal is generated. The first slope is set according to the input voltage and / or output voltage of the switching converter.

[0010] The second comparator compares a first ramp signal with a second slope and a second reference voltage to generate a valid second comparison signal when the first ramp signal reaches the second reference voltage. It sets the second slope based on the input voltage, the output voltage, and the second error signal, and generates the second reference voltage based on the input voltage and / or the output voltage. When the first comparison signal is valid, the slope of the first ramp signal changes from the first slope to the second slope.

[0011] The third comparator compares the second ramp signal with the third reference voltage, and generates a valid third comparison signal when the second ramp signal reaches the third reference voltage.

[0012] The first comparison signal, the second comparison signal, and the third comparison signal are used to control the switching state of the main switch transistor, so that the switching period of the main switch transistor changes accordingly with the load of the switching converter.

[0013] Optionally, the invalid duration of the second comparison signal is a first preset time;

[0014] The invalid duration of the third comparison signal is the second preset time;

[0015] The larger of the first preset time and the second preset time is the switching cycle of the main switch transistor.

[0016] Optional, also includes,

[0017] The AND gate receives the second comparison signal and the third comparison signal, and generates a periodic control signal;

[0018] The logic control unit receives the first comparison signal and the periodic control signal, and generates a switch control signal to control the switching state of the main switch transistor.

[0019] Optionally, the first comparison signal is used to control the conduction time of the main switch, and the period control signal is used to control the switching period of the main switch.

[0020] Optionally, the second slope changes in a positive correlation with the change in the load.

[0021] Optionally, in continuous conduction mode, the second slope is greater than the first slope.

[0022] Optionally, the switching period of the main switch remains unchanged, and the switching period is equal to the second preset time.

[0023] Optionally, in intermittent conduction mode, the switching cycle of the main switch transistor changes negatively with the load.

[0024] Optionally, it also includes a first ramp signal generation circuit and a second ramp signal generation circuit, which are used to generate the first ramp signal and the second ramp signal, respectively;

[0025] The first ramp signal generation circuit includes a first capacitor. A first current charges the first capacitor to generate a first ramp signal with the first ramp rate. A second current charges the first capacitor to generate a first ramp signal with the second ramp rate. The magnitude of the first current is set according to the input voltage and / or output voltage. The magnitude of the second current is set according to the input voltage, output voltage, and the second error signal. When the first comparison signal is valid, the charging current of the first capacitor switches from the first current to the second current.

[0026] The second ramp signal generating circuit includes a second capacitor, and a third current charges the second capacitor to generate the second ramp signal.

[0027] Optionally, when the switching converter is a buck converter, the first current is set to equal V. IN / R, the second current is equal to (N*V) CA / (K*V OUT )-C)*V IN / R, the second reference voltage is equal to K*V IN The second preset time is equal to R*C2, and C1 = K*C2.

[0028] Among them, V IN V is the input voltage. OUT V is the output voltage. CA The second error signal is defined as follows: R is a constant greater than zero; C1 is the capacitance of the first capacitor; C2 is the capacitance of the second capacitor; K is a constant greater than zero; N is a constant greater than 1; and 0 is a constant greater than zero. <C<N-1。

[0029] Optionally, when the switching converter is a boost converter, the first current is set to equal V. OUT / R, the second current is equal to (N*V) CA / (K*V IN )-C)*V OUT / R, the second reference voltage is equal to K*V OUT The preset time is equal to R*C2, and C1 = K*C2;

[0030] Among them, V IN V is the input voltage. OUT V is the output voltage. CA The second error signal is defined as follows: R is a constant greater than zero; C1 is the capacitance of the first capacitor; C2 is the capacitance of the second capacitor; K is a constant greater than zero; N is a constant greater than 1; and 0 is a constant greater than zero. <C<N-1。

[0031] The present invention also provides a switching converter, including a main switching transistor and an inductor, and further including any of the above-described adaptive control circuits for controlling the switching state of the main switching transistor.

[0032] Compared with the prior art, the present invention has the following advantages: In average current mode, when the load, input voltage or output voltage changes, the on / off time and switching period of the main power transistor of the switching converter are adaptively adjusted, resulting in lower output ripple and stable output. Attached Figure Description

[0033] Figure 1 The schematic diagram of an existing switching converter and its adaptive control circuit;

[0034] Figure 2 Here is a diagram of the signal waveforms of the existing control circuit.

[0035] Figure 3 This is a schematic diagram of the switching converter and its adaptive control circuit of the present invention.

[0036] Figure 4 This is a waveform diagram of the adaptive control circuit of the present invention. Detailed Implementation

[0037] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the present invention.

[0038] To provide the public with a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the invention, but those skilled in the art can fully understand the invention without these details.

[0039] See Figure 3 The schematic diagram illustrates the switching converter and its adaptive control circuit of the present invention. The switching converter includes a power circuit, a sampling circuit, and an adaptive control circuit. The power circuit can be a buck topology, a boost topology, a buck-boost topology, a four-switch topology, etc. When the main switch of the power circuit is turned on, the inductor charges; when the auxiliary switch is turned on, the inductor freewheels. The sampling circuit is used to sample the output voltage to obtain the output feedback signal V. FB And the average current sampling signal V is obtained by sampling the average current of the inductor. CS_AVG The adaptive control circuit includes a first error amplifier 01 and its output filter unit 101, a second error amplifier 02 and its output filter unit 201, a first comparator 03, a second comparator 04, a third comparator 05, a first ramp signal generation circuit 06, a second ramp signal generation circuit 07, an AND gate 08, and a logic control unit. See the signal waveform diagram of the adaptive control circuit. Figure 4 The first error amplifier 01 will output a feedback signal V. FB and the first reference voltage V REF The error is amplified, and its output is filtered by the filter unit 101 to obtain the compensation signal V. COMP The second error amplifier 02 will compensate the signal V. COMP (as average current reference signal) and average current sampling signal V CS_AVG The error is amplified, and its output is filtered by filter unit 201 to obtain the second error amplified signal V. CA The first comparator 03 converts the second error signal V CA and the first ramp signal V with the first slope RAMP1 When comparing, the second error signal V CA Reaching the first ramp signal V RAMP1 A valid first comparison signal V1 is generated, and the slope of the first ramp signal switches from the first slope to the second slope (see [reference]). Figure 4 The first slope is set according to the input voltage and / or output voltage of the switching converter, and the second slope is set according to the input voltage, output voltage, and second compensation signal; the second comparator 04 sets the second reference voltage VREF2 and the first ramp signal V with the second slope RAMP1 A comparison is performed, and when the second reference voltage reaches the first ramp signal, a valid second comparison signal V2 is generated; the third comparator 05 converts the second ramp signal V... RAMP2 and the third reference voltage V REF3 Comparison, when the second ramp signal V RAMP2 Reaching the third reference voltage V REF3 A valid third comparison signal V3 is generated. The second ramp and third reference voltage are set according to a preset time, ensuring the invalid time of the third comparison signal is the preset time. The first ramp signal generation circuit 06 is used to generate the first ramp signal V. RAMP1 The second ramp signal generation circuit is used to generate the second ramp signal V. RAMP2 AND gate 08 receives the second comparison signal V2 and the third comparison signal V3. When both the second and third comparison signals are valid, it generates a valid period control signal VT. When the period control signal VT is valid, the first ramp signal and the second ramp signal are reset to their respective initial values ​​(see [link to relevant documentation]). Figure 4 The logic control unit receives the first comparison signal V1 and the periodic control signal VT, and generates a state-complementary switching control signal V. G1 and V G2 V G1 Used to control the switching state of the main switching transistor, V G2 Used to control the switching state of the rectifier diode. The switching states of the rectifier diode and the switching state of the rectifier diode are complementary. When the first comparison signal V1 is valid, the switching control signal V... G1 When the main switch is turned off and the periodic control signal VT is valid, the switch control signal V... G1 Control the main switch to turn on.

[0040] Furthermore, the first ramp signal generation circuit includes a current source I1 and a switch K1 connected in series, a current source I2 and a switch K2 connected in series, a first capacitor C1 and a switch K3 connected in parallel with it. Initially, switch K1 is turned on, and switches K2 and K3 are turned off. The first current source I1 charges the first capacitor C1. The first ramp signal generated by the voltage of the first capacitor C1 rises with a first slope according to the magnitude of the first current source I1, and according to the input voltage V... IN or / and output voltage V OUT Set the magnitude of the first current source I1, and when the first ramp signal reaches the second error signal V... CA When the first comparison signal V1 is valid, it controls switch K1 to turn off and switch K2 to turn on. The second current source I2 continues to charge the first capacitor C1, and the first ramp signal V... RAMP1 The current continues to rise at the second slope based on the magnitude of the second current source I2, and based on the input voltage V. IN Output voltage VOUT Second error signal V CA Set the magnitude of the second current source I2, when the first ramp signal V... RAMP1 Reaching the second reference voltage V REF2 At this time, the second comparison signal V2 is valid. The second ramp signal generation circuit includes a third current source I3 and a switch K4 connected in series, as well as a second capacitor C2 and a switch K5 connected in parallel with it. Initially, switch K4 is on and switch K5 is off. The third current source I3 charges the second capacitor C2, and the second ramp signal V2 is generated by the voltage of the second capacitor C2. RAMP2 Rise, when the second ramp signal reaches the third reference voltage V REF3 At that time, the third comparison signal V3 is valid, and the second ramp signal V... RAMP2 From its initial value (zero) to the third reference voltage V REF3 The time is a preset time. When both the second comparison signal V2 and the third comparison signal V3 are valid, the period control signal VT output by AND gate 08 is valid, which controls K3 and K5 to be turned on briefly so that the first ramp signal and the second ramp signal are reset to their respective initial values.

[0041] Furthermore, taking a buck converter as an example, the power circuit uses a buck topology. When the main switch is turned on (inductor charging) and the auxiliary switch is turned off, the first ramp signal V... RAMP1 Second ramp signal V RAMP2 Starting from zero, the first ramp signal V RAMP1 Reaching the second error signal V CA When the main switch is turned off and the auxiliary switch is turned on, the main switch is turned on for a time T. ON The first ramp signal V RAMP1 From zero to V CA Time taken; after the main switch is turned off, the first ramp signal V RAMP1 Second ramp signal V RAMP2 Continue to rise, first ramp signal V RAMP1 Second ramp signal V RAMP2 When both the second comparison signal V2 and the third comparison signal V3 reach the corresponding reference voltage, i.e., when both are valid, the periodic control signal VT becomes valid, controlling the auxiliary switch to turn off and the main switch to turn on. For example, the first ramp signal V... RAMP1 First reach the second reference voltage V REF2 Second ramp signal V RAMP2 Then the third reference voltage V is reached REF3When the second comparison signal V2 becomes valid first and the third comparison signal V3 becomes valid later (the output of the second comparator flips earlier than the output of the third comparator), only when the third comparison signal V3 becomes invalid do the second comparison signal V2 and the third comparison signal V3 both enter the valid state and the cycle control signal VT becomes valid. Therefore, when the second ramp signal V RAMP2 rises from zero to the third reference voltage V REF3 , the time Ts2 is the switching period Ts. Similarly, if the third comparison signal V3 becomes valid first and the second comparison signal V2 becomes valid later, the switching period Ts is determined by the time Ts1 when the first ramp signal V RAMP1 rises from zero to the second reference voltage V REF2 .

[0042] Design the first current source I1 = V IN / R, the second current source I2 = (N * V CA / (K * V OUT ) - C) * V IN / R, the third current source I3 = V REF3 / R, the second reference voltage V REF2 = K * V IN . According to the capacitor charging formula, I3 / C2 * Ts2 = V REF3 , that is, V REF3 / (R * C2) * Ts2 = V REF3 . Further, Ts2 = R * C2 (R * C2 is a preset time); where 0 < C < N - 1, N is a constant greater than 1, R is a constant greater than zero, K is a constant greater than zero, and K * R * C1 = R * C2. Based on the above parameter design, in the CCM (continuous conduction) mode, it is certain that I2 > I1. The reason is as follows. Taking the preferred N = 2 as an example:

[0043] If I2 = I1, then 2 * V CA / (K * V OUT ) - C - 1 = 0, and V CA = ((C + 1) / 2) * K * V OUT . When the first ramp signal V RAMP1 reaches the second reference voltage V REF2 , I1 / C1 * Ts1 = V REF2 , that is, V IN / (R * C1) * Ts1 = K * V IN . Further, Ts1 = K * R * C1 = Ts2, indicating that the outputs of the second comparator and the third comparator change from invalid to valid simultaneously (the outputs of the second comparator and the third comparator flip simultaneously), and the switching period Ts = Ts1 = Ts2 = K * R * C1. Further, the conduction time T ON of the main switch tube = Ts * D, D = VOUT / V IN is the duty ratio of the buck converter. Further, there is T ON = K * R * C1 * V OUT / V IN , during the conduction period of the main switch tube, the current source I1 charges the capacitor C1, and there is V CA = I1 / C1 * Ton = V IN / (R * C1) * (K * R * C1 * V OUT / V IN ) = K * V OUT , which is contradictory to the above-derived V CA = ((C + 1) / 2) * K * V OUT . Therefore, in the CCM mode, I1 ≠ I2.

[0044] If I2 < I1, there is 2 * V CA / (K * V OUT ) - C - 1 < 0, V CA < ((C + 1) / 2) * K * V OUT < K * V OUT . The second slope corresponding to I2 < I1 becomes smaller compared to the second slope corresponding to I2 = I1. The second comparison signal cannot become valid simultaneously with the third comparison signal. The time for the second comparison signal to become valid is longer than the time for the third comparison signal to become valid (the output of the second comparator flips later). Therefore, there is Ts = Ts1 > Ts2, T ON = Ts1 * D > Ts2 * D, Ts2 * D = R * C2 * V OUT / V IN ; when the first ramp signal V RAMP1 reaches V CA , according to the principle of capacitor charge balance, the charge amount Q1 of the capacitor C1 = C1 * V CA = I1 * T ON , there is T ON = C1 * V CA * R / V IN = Ts1 * D > Ts2 * D. Further, there is C1 * V CA * R / V IN > R * C2 * V OUT / V IN , and we get V CA > K * V OUT , which is contradictory to the above-derived V CA < K * V OUT .

[0045] According to the above analysis, in the CCM mode, I2 must be greater than I1. Compared with the case of I2 = I1, the second slope is larger, and the first ramp signal V RAMP1Reach the second reference voltage V faster REF2 , taking less time. The second comparison signal V2 becomes valid faster (the output of the second comparator flips earlier than the output of the third comparator). The switching period is determined by the valid moment of the third comparison signal V3, and Ts = Ts2 = R * C2. Further, we get V CA = K * V OUT ; As the load further decreases, V CA decreases, and the switching converter enters the DCM (discontinuous conduction) mode from the CCM mode. When just entering the DCM mode, there is still I2 > I1, and V CA > K * V OUT* (C + 1) / 2. Since 0 < C < 1, we have K * V OUT* (C + 1) / 2 < V CA < K * V OUT . The on - time of the main switch decreases, and the peak value of the inductor current decreases. There is still the switching period Ts = Ts2 > Ts1; When the load further decreases, V CA decreases, I2 = I1, Ts = Ts1 = Ts2, and V CA = K * V OUT* (C + 1) / 2; When the load further decreases, V CA further decreases, I2 < I1, K * V OUT * C / 2 < V CA < K * V OUT* (C + 1) / 2. The on - time of the main switch further decreases, and the peak value of the inductor current further decreases. Ts = Ts1 > Ts2; When the load is no - load, V CA further decreases, and further we have V CA < K * V OUT * C / 2. The on - time of the main switch tube will decrease to half and below of the on - time in the CCM mode, and the switching period can extend infinitely.

[0046] The above is the description based on the buck converter as an example of the switching converter. When the switching converter is a boost converter, corresponding designs can also be carried out so that the switching period can adaptively change as the load continuously decreases. The inductor freewheeling current of the boost converter is equal to the load current. As the load current decreases, the inductor freewheeling time decreases, that is, the on-time of the auxiliary switch decreases, and the off-time of the main switch decreases. When the main switch is on (inductor charging), the first ramp signal and the second ramp signal rise from zero. When the first ramp signal reaches the second error signal VCA, the auxiliary switch turns off, and the main switch turns on. The slope of the first ramp signal switches from the first slope to the second slope and continues to rise. When the first ramp signal is greater than the second reference voltage and the second ramp signal is also greater than the third reference voltage, that is, when the second comparison signal and the third comparison signal are both in the valid state, the period control signal is valid, controlling the main switch to turn off and the auxiliary switch to turn on. Design the first current source I1 = V OUT / R, the second current source I2 = (N*V CA / (K*V IN ) - C)*V OUT / R, the third current source I3 = V REF3 / R, the second reference voltage V REF2 = K*V OUT , according to the capacitor charging formula, there is I3 / C2*Ts2 = V REF3 , that is, V REF3 / (R*C2)*Ts2 = V REF3 , further Ts2 = R*C2 (R*C2 is the preset time); where, 0 < C < N - 1, N is a constant greater than 1, R is a constant greater than zero, K is a constant greater than zero, and K*R*C1 = R*C2. According to the above parameter design, still as the load continuously decreases, the on-time of the main switch continuously decreases, the peak current continuously decreases. After entering the DCM mode, the switching period continuously expands as the load decreases. The working principle can be seen in the analysis principle when the switching converter is a buck converter, which will not be elaborated further here.

[0047] When the switching converter is a two-switch buck-boost switching converter, design I1 = (V OUT + V IN ) / R, I2 = (N*V CA / (K*V OUT ) - C)*(V IN + V OUT ) / R, the third current source I3 = V REF3 / R, the second reference voltage V REF2 = K*(V IN + V OUT), further, Ts2 = R * C2 (R * C2 is a preset time), where 0 < C < N - 1, N is a constant greater than zero, R is a constant greater than zero, K is a constant greater than zero, and K * R * C1 = R * C2. The turn-on time of the main switch tube and the switching period can still be adaptively changed with the change of the load, and no further analysis will be carried out here.

[0048] When the switching converter is a four-switch buck-boost switching converter, the boost mode and the buck mode can respectively refer to the control schemes of the above-mentioned boost converter and buck converter for corresponding control, and the switching period can still be adaptively changed with the load.

[0049] See Figure 4 , which shows the waveform diagram of the adaptive control circuit of the present invention. In the figure, I OUT is the output current, representing the load size, V RAMP1 is the first ramp signal, V CA is the second error signal, V G1 is the control signal of the main switch tube. When V G1 is at a high level, the main switch tube is turned on, and the inductor charges and stores energy. When V G1 is at a low level, the main switch tube is turned off, the rectifier tube is turned on, and the inductor continues to conduct current. When the main switch tube is turned on, V RAMP1 rises at the first slope. When the main switch tube is turned off, V RAMP1 rises at the second slope. In the CCM mode and when just entering the DCM mode, the second slope is greater than the first slope. After entering the DCM mode, as I OUT decreases, the second slope changes from greater than the first slope to less than the first slope and gradually decreases. The high-level time (main switch turn-on time) of V G1 becomes shorter, and the switching period gradually becomes longer, realizing the adaptive extension of the switching period.

[0050] According to the above analysis, as the load continuously changes, the conduction time of the main switch tube continuously changes. In the DCM mode, the switching period also continuously changes. The lower the load, the continuously increasing switching period, with regular adaptive changes, and there will be no situation of chaotic switching periods and uneven conduction times of the main switch tube, resulting in a large output ripple problem.

[0051] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all in a relatively simplified form and use non-precise scales to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0052] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.

[0053] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. An adaptive control circuit for a switching converter, the switching converter comprising a main power transistor and an inductor connected in series, characterized in that: include, The first error amplifier performs error calculation on the output feedback voltage of the switching converter and the first reference voltage to obtain a compensation signal; The second error amplifier amplifies the current sampling signal, which characterizes the average inductor current, and the compensation signal to obtain the second error signal. A first comparator compares a first ramp signal with a first slope and a second error signal. When the first ramp signal reaches the second error signal, a valid first comparison signal is generated. The first slope is set according to the input voltage and / or output voltage of the switching converter. The second comparator compares a first ramp signal with a second slope and a second reference voltage to generate a valid second comparison signal when the first ramp signal reaches the second reference voltage. It sets the second slope based on the input voltage, the output voltage, and the second error signal, and generates the second reference voltage based on the input voltage and / or the output voltage. When the first comparison signal is valid, the slope of the first ramp signal changes from the first slope to the second slope. The third comparator compares the second ramp signal with the third reference voltage, and generates a valid third comparison signal when the second ramp signal reaches the third reference voltage. The first comparison signal, the second comparison signal, and the third comparison signal are used to control the switching state of the main switch transistor, so that the switching period of the main switch transistor changes accordingly with the load of the switching converter.

2. The adaptive control circuit for the switching converter according to claim 1, characterized in that: The invalid duration of the second comparison signal is a first preset time; The invalid duration of the third comparison signal is the second preset time; The larger of the first preset time and the second preset time is the switching cycle of the main switch transistor.

3. The adaptive control circuit for the switching converter according to claim 2, characterized in that: It also includes, The AND gate receives the second comparison signal and the third comparison signal, and generates a periodic control signal; The logic control unit receives the first comparison signal and the periodic control signal, and generates a switch control signal to control the switching state of the main switch transistor.

4. The adaptive control circuit for the switching converter according to claim 2, characterized in that: The first comparison signal is used to control the conduction time of the main switch transistor, and the period control signal is used to control the switching period of the main switch transistor.

5. The adaptive control circuit for the switching converter according to claim 2, characterized in that: The second slope changes in a positive correlation with the change in the load.

6. The adaptive control circuit for the switching converter according to claim 4, characterized in that: In continuous conduction mode, the second slope is greater than the first slope.

7. The adaptive control circuit for the switching converter according to claim 5, characterized in that: The switching period of the main switch remains unchanged, and the switching period is equal to the second preset time.

8. The adaptive control circuit for the switching converter according to claim 4, characterized in that: In intermittent conduction mode, the switching cycle of the main switch is negatively correlated with the load.

9. The adaptive control circuit for the switching converter according to claim 2, characterized in that: It also includes a first ramp signal generation circuit and a second ramp signal generation circuit, which are used to generate the first ramp signal and the second ramp signal, respectively. The first ramp signal generation circuit includes a first capacitor. A first current charges the first capacitor to generate a first ramp signal with the first ramp rate. A second current charges the first capacitor to generate a first ramp signal with the second ramp rate. The magnitude of the first current is set according to the input voltage and / or output voltage. The magnitude of the second current is set according to the input voltage, output voltage, and the second error signal. When the first comparison signal is valid, the charging current of the first capacitor switches from the first current to the second current. The second ramp signal generating circuit includes a second capacitor, and a third current charges the second capacitor to generate the second ramp signal.

10. The adaptive control circuit for the switching converter according to claim 9, characterized in that: When the switching converter is a buck converter, the first current is set to equal V. IN / R, the second current is equal to (N*V) CA / (K*V OUT )-C)*V IN / R, the second reference voltage is equal to K*V IN The second preset time is equal to R*C2, and C1 = K*C2. Among them, V IN V is the input voltage. OUT V is the output voltage. CA The second error signal is defined as follows: R is a constant greater than zero; C1 is the capacitance of the first capacitor; C2 is the capacitance of the second capacitor; K is a constant greater than zero; N is a constant greater than 1; and 0 is a constant greater than zero. <C<N-1。 11. The adaptive control circuit for the switching converter according to claim 9, characterized in that: When the switching converter is a boost converter, the first current is set to equal V. OUT / R, the second current is equal to (N*V) CA / (K*V IN )-C)*V OUT / R, the second reference voltage is equal to K*V OUT The preset time is equal to R*C2, and C1 = K*C2; Among them, V IN V is the input voltage. OUT V is the output voltage. CA The second error signal is defined as follows: R is a constant greater than zero; C1 is the capacitance of the first capacitor; C2 is the capacitance of the second capacitor; K is a constant greater than zero; N is a constant greater than 1; and 0 is a constant greater than zero. <C<N-1。 12. A switching converter, comprising a main switching transistor and an inductor, characterized in that: It also includes the adaptive control circuit according to any one of claims 1-11, used to control the switching state of the main switching transistor.

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