High frequency probe card signal optimization method based on dynamic impedance matching and related apparatus

Abstract

The present application relates to the technical field of probe card signal optimization, in particular to a high-frequency probe card signal optimization method based on dynamic impedance matching and related devices. The method steps include: obtaining real-time high-frequency signal reflection parameters of the probe card test channel to provide real-time detection basis for dynamic impedance matching. The present application relies on the real-time acquisition of the high-frequency signal reflection parameters of the probe card test channel to complete the quantitative tracing of the dynamic impedance deviation, and through the closed-loop feedback adjustment, the integrated adjustable impedance network of the driving probe is used to complete the real-time correction of the output impedance. From the root level of transmission line impedance matching, the present application breaks through the inherent limitation of the traditional static matching scheme which can only adapt to the nominal working condition, and can effectively offset the dynamic impedance mismatch introduced by the contact state difference, the probe structure micro-deformation, the device individual parasitic parameter dispersion and the nonlinear evolution of the parasitic parameters under high frequency in the actual test process, and solves the reflection residual problem that cannot be eliminated by static matching.

Description

Technical Field

[0001] This invention relates to the field of probe card signal optimization technology, specifically to a high-frequency probe card signal optimization method and related apparatus based on dynamic impedance matching. Background Technology

[0002] With the continuous upgrading of wafer-level testing requirements for semiconductor components such as third-generation semiconductor radio frequency devices and high-speed digital chips, high-frequency probe cards, as the core adapter components connecting test instruments and wafers under test in the testing process, directly determine the accuracy and reliability of test results through their signal transmission quality. Signal reflection, amplitude attenuation, and phase distortion caused by impedance mismatch are the core factors restricting signal integrity in high-frequency testing scenarios.

[0003] Existing impedance matching solutions for high-frequency probe cards are generally based on static design concepts. Most solutions pre-set matching networks with fixed parameters in the probe card wiring layer to adapt to the industry's common nominal impedance. A few improved solutions can only provide multiple fixed matching networks for manual switching according to the type of device under test before testing. These solutions can only adapt to the nominal impedance requirements under preset operating conditions and cannot cope with the dynamic impedance fluctuations that occur during actual testing.

[0004] In actual testing, differences in contact pressure between the probe and the pin under test, micro-deformation of the probe structure due to long-term use, individual differences in the parasitic parameters of different semiconductor components under test, and nonlinear changes in the parasitic parameters of the transmission path with the test frequency under high-frequency signals can all lead to dynamic impedance mismatch between the probe card channel and the port under test. Static matching schemes cannot make real-time adjustments to this type of dynamic mismatch, and there will still be relatively obvious signal reflection residue, causing test signal distortion and reducing the accuracy of test results.

[0005] The technical problem to be solved by this invention is how to achieve real-time dynamic adjustment of impedance matching during the testing process of a high-frequency probe card, thereby eliminating the impact of dynamically generated impedance mismatch on signal transmission quality during actual testing. Summary of the Invention

[0006] This disclosure proposes a high-frequency probe card signal optimization method and related device based on dynamic impedance matching, aiming to overcome at least one of the defects existing in the prior art.

[0007] To achieve the above objectives, the technical solution disclosed in this invention is as follows: According to one aspect of this disclosure, a method for optimizing high-frequency probe card signals based on dynamic impedance matching is provided, comprising the following steps: The real-time high-frequency signal reflection parameters of the probe card test channel are obtained to provide a real-time detection basis for dynamic impedance matching. Extract the channel real-time impedance deviation value corresponding to the real-time high-frequency signal reflection parameters to quantify the impedance mismatch between the probe card and the semiconductor device under test. Based on the impedance deviation value, a matching adjustment command is generated, and a corresponding impedance matching control signal is output. The control signal drives the adjustable impedance network integrated in the probe card channel to adjust the output impedance, and matches the probe card channel impedance with the impedance of the port under test in real time to suppress signal reflection and optimize signal quality.

[0008] Furthermore, before obtaining the real-time high-frequency signal reflection parameters, a pre-calibration step is also included, in which the impedance of each probe card test channel is initially calibrated to establish the correspondence between the adjustment command and the output impedance of the adjustable impedance network, so as to eliminate the reference deviation caused by the processing error of different channels.

[0009] Furthermore, the step of extracting the impedance deviation value includes: calculating the actual load impedance of the current channel based on the reflection coefficient formula and the characteristic impedance of the transmission line, and then subtracting the actual load impedance from the preset target impedance to obtain the impedance deviation value.

[0010] Furthermore, the step of generating a matching adjustment command based on the impedance deviation value includes inputting the impedance deviation value into a preset fuzzy PID adjustment model to generate a step adjustment command for the adjustable impedance network, which is used to avoid overshoot oscillation during the adjustment process.

[0011] Furthermore, the adjustable impedance network is integrated into the probe root of the probe card to shorten the transmission distance from the matching point to the port of the semiconductor device under test, thereby reducing the impact of parasitic impedance of the transmission line on the matching effect; the adjustable impedance network includes a series adjustable capacitor unit to compensate for the parasitic inductance introduced by the probe's own structure, thereby improving the impedance mismatch problem at high frequencies.

[0012] Furthermore, the adjustable impedance network also includes a parallel adjustable inductor unit to compensate for parasitic capacitance introduced by the probe and channel wiring, thereby optimizing the transmission quality of high-frequency signals.

[0013] Furthermore, after completing impedance adjustment and obtaining a stable signal, the process also includes a parameter storage step, which includes recording the optimal impedance matching parameters corresponding to the current semiconductor device under test. When testing the same type of semiconductor device again, the optimal impedance matching parameters can be directly called to shorten the testing process and improve the efficiency of batch testing.

[0014] According to another aspect of this disclosure, a high-frequency probe card signal optimization system based on dynamic impedance matching is provided for implementing the high-frequency probe card signal optimization method based on dynamic impedance matching as described above, comprising: The real-time parameter acquisition module is used to acquire the real-time high-frequency signal reflection parameters of the probe card test channel, providing a real-time detection basis for dynamic impedance matching; The impedance deviation extraction module is used to extract the real-time impedance deviation value of the channel corresponding to the reflection parameter, and quantify the impedance mismatch between the probe card and the semiconductor device under test. The adjustment command generation module is used to generate a matching adjustment command based on the impedance deviation value and output a control signal corresponding to impedance matching. The impedance adjustment drive module is used to drive the adjustable impedance network integrated in the probe card channel to adjust the output impedance, match the probe card channel impedance with the impedance of the port under test in real time, suppress signal reflection and optimize signal quality.

[0015] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the high-frequency probe card signal optimization method based on dynamic impedance matching as described above.

[0016] According to another aspect of this disclosure, an electronic device is provided, including a memory and a processor, the processor being coupled to the memory, the processor being configured to call and execute a computer program stored in the memory to implement the high-frequency probe card signal optimization method based on dynamic impedance matching as described above.

[0017] The beneficial effects of this invention are: This invention relies on the real-time acquisition of high-frequency signal reflection parameters from the probe card test channel to quantify and trace the source of dynamic impedance deviation. Through closed-loop feedback adjustment, it drives the probe to integrate an adjustable impedance network to complete the real-time correction of the output impedance. It breaks through the inherent limitation of traditional static matching schemes, which can only adapt to nominal operating conditions, from the fundamental level of transmission line impedance matching. It can effectively offset the dynamic impedance mismatch introduced by differences in contact state, micro-deformation of probe structure, dispersion of individual parasitic parameters of devices, and nonlinear evolution of parasitic parameters at high frequencies during actual testing, and solve the problem of reflection residue that cannot be eliminated by static matching.

[0018] Specifically, this invention relies on signal reflection parameters to achieve real-time quantification of impedance deviation. It can adapt to impedance change requirements under different test conditions without the need to introduce a complex preset calibration model. By integrating the adjustable impedance network on the probe side, it can also effectively shorten the transmission distance from the matching point to the port under test and reduce the interference of parasitic parameters of the transmission path on the matching effect.

[0019] Furthermore, compared to existing static matching schemes, this invention can offset dynamic impedance mismatch caused by various factors in real time, effectively suppress signal reflection, reduce amplitude attenuation and phase distortion of test signals, and significantly improve signal integrity in high-frequency testing scenarios. It can not only effectively improve the accuracy of test results for a single semiconductor device under test, but also further shorten the process adjustment time for batch testing of semiconductor devices of the same model by storing and reusing the optimal matching parameters. The optimal matching parameter storage and reuse mechanism can effectively reduce the adjustment overhead of the test process and increase the test throughput of mass production wafer testing. It can perfectly meet the technical requirements of high-precision large-scale wafer-level testing of high-end semiconductor devices such as third-generation semiconductor RF devices and high-speed digital chips.

[0020] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the following describes the preferred embodiments of the present invention in detail with reference to the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a flowchart of the high-frequency probe card signal optimization method based on dynamic impedance matching of the present invention; Figure 2 The Smith chart shows the impedance matching effect of the high-frequency probe card of this invention. Figure 3 This is a schematic diagram of the three-dimensional surface plot of the fuzzy PID control impedance convergence of the present invention; Figure 4 This is the matched signal integrity eye diagram of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The term "comprising" and any variations thereof in the specification and claims of this application are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product or device.

[0024] In embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0025] The present invention provides the following preferred embodiments: Example 1: To address the issue of insufficient testing accuracy caused by signal reflection during high-frequency probe card testing, this example refines the signal optimization method for high-frequency probe cards based on dynamic impedance matching. For example... Figure 1 As shown, the signal optimization method flow is as follows: S100: Acquires real-time high-frequency signal reflection parameters of the probe card test channel, providing real-time detection basis for dynamic impedance matching.

[0026] S200: Extracts the real-time impedance deviation value of the channel corresponding to the real-time high-frequency signal reflection parameters, and quantifies the impedance mismatch between the probe card and the semiconductor device under test.

[0027] S300: Generates matching adjustment commands based on impedance deviation values ​​and outputs corresponding impedance matching control signals.

[0028] S400: Adjusts the output impedance based on the adjustable impedance network integrated in the probe card channel driven by the control signal, and matches the probe card channel impedance with the impedance of the port under test in real time to suppress signal reflection and optimize signal quality.

[0029] After the test process starts, the signal detection unit integrated into the test channel port of the probe card first acquires the real-time high-frequency signal reflection parameters of the test channel. The acquired reflection parameters provide continuous real-time detection data for dynamic impedance matching, adapting to the adjustment requirements of dynamic impedance changes during the test. It is important to understand that the acquired reflection parameters are continuous reflection coefficient information of the port during the test, which can be directly used in the subsequent impedance calculation process without additional format conversion to meet the calculation requirements.

[0030] Furthermore, the acquired real-time high-frequency signal reflection parameters are normalized and transformed to extract the real-time impedance deviation value of the corresponding channel. This impedance deviation value is used to quantify the impedance mismatch between the probe card and the semiconductor device under test. The processed impedance parameters can be mapped to a standard impedance analysis diagram to complete the status display, such as... Figure 2As shown, the impedance matching effect of the high-frequency probe card can be intuitively presented through the distribution of impedance points, facilitating status monitoring during the testing process. It is understandable that the normalization process eliminates the influence of dimensional differences under different testing scenarios on the impedance calculation results, and the obtained impedance deviation value can be directly used as the input quantity for adjusting the calculation unit, adapting to the input requirements of subsequent adjustment processes.

[0031] Furthermore, the obtained real-time impedance deviation value is input into the adjustment calculation unit. Based on the magnitude of the impedance deviation value and its current trend, a corresponding matching adjustment command is generated. Then, the signal output conversion unit outputs the corresponding impedance matching control signal. The output parameters of the control signal correspond one-to-one with the adjustment requirements of the adjustable impedance network, directly driving the adjustable impedance network to complete the impedance parameter adjustment. It is important to understand that the entire adjustment process is a continuous, cyclical, dynamic process. After each impedance adjustment, the high-frequency signal reflection parameters at the port are re-acquired, a new impedance deviation value is calculated, and the next adjustment process is initiated until the impedance deviation falls within the preset matching allowable range.

[0032] Furthermore, after the control signal is transmitted to the adjustable impedance network integrated in the probe card channel, the adjustable element array inside the adjustable impedance network switches the element parameters connected to the network according to the control signal, adjusts the output impedance of the probe card channel, matches the impedance of the probe card channel with the impedance of the port under test in real time, and finally completes the suppression of signal reflection and optimizes the output signal quality.

[0033] The advantage of this embodiment is that by acquiring, calculating and dynamically adjusting the reflection parameters in real time during the test, it can adapt to the port impedance fluctuations of different semiconductor components under test. There is no need for manual recalibration for different test objects. Impedance matching adjustment can be automatically completed during the test, which can meet the test requirements of high-frequency test scenarios where impedance is easily affected by environmental and component parameter fluctuations. It ensures stable signal output during high-frequency test and solves the problem that the existing static matching method cannot cope with impedance changes during the test. It can adapt to the high-frequency semiconductor test requirements in different scenarios.

[0034] Example 2: To address the impedance matching reference offset problem caused by the consistency deviation in multi-channel processing of probe cards, this example further optimizes the preprocessing steps of the high-frequency probe card signal optimization method based on dynamic impedance matching.

[0035] Before the formal testing process begins and real-time high-frequency signal reflection parameters are obtained, the pre-calibration steps of all probe card test channels need to be completed. Each probe card test channel is initially calibrated individually. The calibration process establishes the correspondence between adjustment commands and the output impedance of the adjustable impedance network, eliminating the reference deviation caused by the processing errors of different channels.

[0036] Furthermore, the pre-calibration process uses a standard impedance source as an input reference, scans all adjustable ranges of the adjustable impedance network one by one for a single channel, records the adjustment command output value corresponding to each range and the actual measured output impedance value, establishes the mapping relationship between the two point by point, and stores it in the control storage unit matched with the probe card for subsequent dynamic matching process.

[0037] It's important to understand that during the manufacturing process of probe cards, variations in trace width across different channels, fluctuations in substrate dielectric constant, and parameter tolerances of integrated passive components all introduce individual reference deviations. Even within the same batch of probe cards, the initial impedance references for different channels may differ. Pre-calibration incorporates these individual channel errors into the matching calculation's reference system, eliminating the impact of systematic reference deviations on the matching results from the outset. It's understandable that the pre-calibration process only needs to be performed once before the probe card leaves the factory or when replacing probe cards during test system assembly; it doesn't need to be repeated before each individual device under test (DUT) test, thus not increasing the time overhead of the normal testing process.

[0038] Furthermore, after establishing the mapping relationship through calibration, and generating matching adjustment commands during dynamic adjustment, the actual drive value of the corresponding adjustable impedance network can be directly obtained through the stored mapping relationship. This eliminates the need to recalibrate the reference during testing, and the calibration relationship supports subsequent updates. When the probe card reaches a preset usage period, or after component replacement or repair, the calibration process can be re-executed to update the mapping relationship, adapting to parameter drift caused by long-term component use. Figure 2 As shown, the pre-calibrated dynamic matching impedance points have a higher degree of clustering compared to the uncalibrated matching impedance points, and all impedance points are closer to the target impedance position at the center, resulting in better matching consistency.

[0039] The advantage of this embodiment is that by pre-establishing the correspondence between adjustment commands and the output impedance of the adjustable impedance network, the systematic reference deviation caused by the processing errors of different channels is offset, the consistency of batch dynamic impedance matching of high-density multi-channel probe cards is improved, and the matching failure problem caused by the reference deviation of a single channel is avoided, thus adapting to the batch testing needs of multi-channel high-frequency probe cards.

[0040] Example 3: To address the problem of insufficient accuracy in impedance deviation calculation leading to large matching adjustment errors, this example further refines the steps for extracting impedance deviation values.

[0041] After obtaining the real-time high-frequency signal reflection parameters, the actual load impedance of the current channel needs to be calculated based on the reflection coefficient formula and the characteristic impedance of the transmission line. Then, the impedance deviation value is obtained by subtracting the actual load impedance from the preset target impedance. The reflection coefficient formula used is as follows: Where Γ is the high-frequency signal reflection coefficient obtained in real time, and it is a core output parameter of the real-time high-frequency signal reflection parameters. L Let Z0 be the actual load impedance of the current channel, and Z0 be the preset characteristic impedance of the transmission line. It's important to understand that the reflection coefficient Γ in the formula can be obtained by directly measuring the amplitude ratio and phase difference of the incident and reflected waves through a directional coupler; these are known quantities. Z0 is the preset standard characteristic impedance of the test system, also a known quantity. The unknown actual load impedance can be obtained by transforming the original formula. The transformed formula is: The calculation process retains the complex characteristics of Γ and simultaneously calculates the resistive and reactive components of the actual output impedance, adapting to the complex characteristic calculation requirements of impedance in high-frequency scenarios and avoiding calculation deviations caused by only calculating the impedance amplitude and ignoring the phase.

[0042] Understandably, in high-frequency testing scenarios, the impedance of the connection port between the probe card and the semiconductor device under test is itself a complex impedance, which includes both resistive and reactive components. Retaining the complex form of the calculation results can more accurately reflect the actual impedance mismatch state and provide complete deviation information for subsequent adjustments.

[0043] Furthermore, after calculating the actual load impedance, the real and imaginary components of the actual load impedance are subtracted from the real and imaginary components corresponding to the preset target impedance, respectively. This yields the impedance deviation value in complex form. The impedance deviation simultaneously reflects the magnitude and direction of both resistive and reactive deviations, eliminating information gaps and providing a more comprehensive and accurate input basis for subsequent adjustment processes. Figure 2 As shown, the calculated actual impedance result can be directly mapped onto the Smith chart. The relative position of the actual impedance point and the central target impedance point can intuitively reflect the magnitude and direction of the impedance deviation, facilitating status monitoring during the test process.

[0044] Furthermore, the entire calculation process is implemented using hardware pipelined computation. After each acquisition of reflection parameters, the impedance deviation value can be extracted within a single computation cycle, without causing time delay to the dynamic adjustment process, thus meeting the real-time requirements of high-frequency testing.

[0045] The impedance deviation value obtained through this embodiment can accurately quantify the degree of impedance mismatch between the probe card and the port under test. The calculation process relies on the physically defined reflection coefficient relationship, and there are no additional approximation errors. This can ensure the input accuracy of the subsequent adjustment process and adapt to the impedance calculation accuracy requirements of high-frequency signal testing.

[0046] Example 4: To address the problem of insufficient stability caused by overshoot oscillation during impedance matching adjustment, this example further refines the steps for generating matching adjustment commands.

[0047] After obtaining the impedance deviation value, it is input into a preset fuzzy PID control model. The model then generates a stepped control command for the adjustable impedance network to prevent overshoot oscillations during the control process. Furthermore, the core parameter update formula for the preset fuzzy PID control model is as follows: K p =K p0 +ΔK p K i =K i0 +ΔK i K d =K d0 +ΔK d K p K is the proportional parameter used in the current adjustment cycle. p0 The initial reference value for the pre-set proportional parameter, ΔK p K represents the proportional parameter correction amount obtained through fuzzy inference. i K is the integral parameter used in the current adjustment cycle. i0 The initial reference value for the pre-set integration parameters, ΔK i K represents the integral parameter correction value obtained through fuzzy inference. d K is the differential parameter used in the current adjustment cycle. d0 The initial reference value for the pre-set differential parameter is ΔK. d This refers to the differential parameter correction value obtained through fuzzy inference. The formula for calculating the rate of change of the input deviation is: e c =e k -e k-1 , where e c e represents the rate of change of impedance deviation during the current adjustment cycle. k e is the real-time impedance deviation extracted during the k-th adjustment cycle. k-1 The real-time impedance deviation is extracted during the (k-1)th adjustment cycle.

[0048] It is important to understand that in conventional fixed-parameter PID control, the proportional, integral, and derivative parameters do not adjust with the real-time state of the impedance deviation. Therefore, it cannot adaptively change the adjustment step size for different initial impedance deviations, which can easily lead to slow adjustment speed under large deviations and overshoot oscillation under small deviations. Fuzzy PID control models can adaptively adjust PID parameters according to the real-time state of the impedance deviation, adapting to the adjustment needs of different initial mismatches.

[0049] Furthermore, the adjustment model calculation first adjusts the input real-time impedance deviation e and the impedance deviation change rate e cFuzzification is performed, and the membership degree of the corresponding fuzzy set is obtained according to the preset membership function of the input variable. Then, fuzzy inference is performed according to the preset fuzzy rules to obtain the correction amount of the three PID parameters. The correction amount is then substituted into the parameter update formula to calculate the PID parameters applicable to the current cycle. Finally, the corresponding adjustment amount is output to generate a step adjustment command.

[0050] Understandably, the fuzzy rule is based on the interval division of impedance deviation and deviation change rate. When the impedance deviation is large, a larger proportional correction is output to increase the adjustment step size and speed up deviation convergence. When the impedance deviation enters a smaller interval, the corresponding proportional correction is output to reduce the step size. At the same time, the integral and derivative parameters are adjusted to suppress overshoot and ensure smooth convergence of the adjustment process.

[0051] Furthermore, in this embodiment, the fuzzy set is divided into seven levels, corresponding to different deviation intervals from negative to positive. The membership function adopts the triangular membership function, which takes into account both computational efficiency and inference accuracy. The entire inference process can be completed quickly in the embedded control unit that comes with the probe card without producing obvious adjustment delays or affecting the timing requirements of normal testing.

[0052] Furthermore, each step of the output step adjustment command corresponds to only the smallest level change of the adjustable impedance network. After each adjustment step is completed, the high-frequency signal reflection parameters of the port are re-acquired, the new impedance deviation is calculated, and the next model calculation is started, gradually adjusting the impedance deviation to the preset allowable range, thus avoiding the problem of excessive adjustment at once. Figure 3 As shown, the impedance deviation convergence trajectory of fuzzy PID control exhibits a smooth downward trend. Regardless of the initial impedance deviation magnitude, the impedance deviation gradually converges to the target range as the number of control steps increases. There is no obvious oscillation or rebound during the convergence process, indicating good control stability.

[0053] The advantage of this embodiment is that it adaptively adjusts the adjustment parameters of the impedance matching process through a fuzzy PID adjustment model, and uses the impedance deviation and deviation change rate as inputs to correct the PID parameters in real time. This balances adjustment speed and adjustment stability, avoids the overshoot oscillation problem that is easy to occur in the fixed parameter adjustment process, and can improve the final accuracy of impedance matching while ensuring the adjustment response speed, thus adapting to the dynamic adjustment requirements of high-frequency probe cards.

[0054] Example 5: To address the interference of transmission line parasitic impedance on matching performance and the high-frequency impedance mismatch caused by parasitic inductance introduced by the probe structure itself, this example further optimizes the placement and unit structure of the adjustable impedance network. The adjustable impedance network is integrated into the probe root of the probe card to shorten the transmission distance from the matching point to the port of the semiconductor device under test, thereby reducing the impact of transmission line parasitic impedance on the matching effect.

[0055] Most existing probe cards integrate their impedance matching networks on the printed circuit board (PCB), leaving a transmission distance of several millimeters to centimeters between the probe and the contact point with the device under test (DUT). This transmission trace itself contains parasitic impedance, which accumulates with increasing transmission distance during high-frequency signal transmission. Even if impedance matching is achieved on the PCB, new impedance mismatches will still occur at the probe port. This embodiment moves the matching network to the probe root, eliminating the parasitic impedance accumulation caused by the intermediate transmission segment at the matching position. This ensures that the matching position coincides as closely as possible with the actual signal port, allowing the matched impedance parameters to directly affect the signal output port without being affected by parasitic parameters from the intermediate transmission segment. Figure 2 As shown in the diagram, in this embodiment, the impedance points after dynamic matching are clustered at the target impedance point location, resulting in lower dispersion and more stable matching effect.

[0056] Furthermore, under high-frequency operating conditions, the probe's metal probe structure exhibits a parasitic inductance effect. The higher the operating frequency, the more pronounced the inductive reactance of this parasitic inductance, directly causing the port impedance to deviate from the preset target value. It is important to understand that the adjustable impedance network in this embodiment includes a series adjustable capacitor unit to compensate for the parasitic inductance introduced by the probe's own structure. This series adjustable capacitor unit can capacitively compensate for the parasitic inductance introduced by the probe structure by changing the capacitance value, offsetting the increase in inductive reactance caused by the parasitic inductance, allowing the port impedance to return to the target range, and improving the impedance mismatch problem at high frequencies.

[0057] It is understandable that parasitic inductance is a parasitic parameter connected in series in the signal transmission path. After connecting an adjustable capacitor in series, the capacitive reactance of the capacitor changes in the opposite direction with the adjustment of the capacitance value, which can accurately cancel the parasitic inductance reactance of different sizes and adapt to the compensation requirements of probes with different structures.

[0058] Furthermore, the series adjustable capacitor unit adopts a digitally adjustable capacitor structure. The capacitance value can be adjusted step by step according to the currently detected impedance deviation. The adjustment step size meets the accuracy requirements of high-frequency impedance compensation. The adjustment process can be completed in conjunction with the aforementioned fuzzy PID dynamic adjustment process without manual intervention. During capacitive compensation, the change in capacitive reactance of the series capacitor is opposite to the change in inductive reactance of the parasitic inductance. This can offset the influence of parasitic inductance on impedance over a wide frequency range, adapting to the high-frequency probe testing requirements of different operating frequencies.

[0059] The advantage of this embodiment is that by changing the placement of the adjustable impedance network, the transmission distance from the matching point to the actual signal port is reduced, the influence of parasitic impedance in the intermediate transmission section on the matching result is reduced, and the compensation of probe parasitic inductance is completed with the series adjustable capacitor, which can maintain a stable port impedance under high-frequency operating conditions and improve the consistency of signal transmission.

[0060] Example 6: To address the issue of high-frequency signal transmission quality degradation caused by parasitic capacitance introduced by probes and channel wiring, this example further refines the unit configuration of the adjustable impedance network. Based on the aforementioned adjustable impedance network including a series adjustable capacitor unit, a parallel adjustable inductor unit is added. These two compensation units work together to compensate for different types of parasitic parameters, jointly optimizing the high-frequency signal transmission characteristics.

[0061] Furthermore, in addition to the series parasitic inductance introduced by the probe's own metal structure at the probe root of the high-frequency probe card, the connection between the probe and the printed circuit board channel wiring, as well as the distributed parameters of the wiring itself, will introduce non-negligible parallel parasitic capacitance. Parasitic capacitance will change the imaginary part of the port impedance, leading to impedance mismatch, and will also cause signal phase shift, increase inter-symbol interference, and affect the transmission quality of high-frequency signals.

[0062] It is important to understand that in this embodiment, the parallel adjustable inductor unit is deployed in the grounding branch of the adjustable impedance network. By adjusting the inductance value of the parallel inductor, the inductive reactance of the grounding branch can be changed, thus inductively compensating for the introduced parallel parasitic capacitance. This offsets the increase in capacitive reactance caused by the parasitic capacitance, adjusting the imaginary part of the impedance to the target range. It can be understood that the series adjustable capacitor unit compensates for the parasitic inductance on the series path, while the parallel adjustable inductor unit compensates for the parasitic capacitance on the parallel path. The two units correspond to two different types and locations of parasitic parameters, respectively. Working together, they can completely cover common parasitic parameter deviations at probe card ports without requiring additional compensation units, simplifying the overall structure of the adjustable impedance network. Figure 2 As shown, after the two units work together to compensate, the impedance point of the probe port is more concentrated at the target impedance point, the matching error is smaller, and the matching stability is higher.

[0063] Furthermore, the parallel adjustable inductor unit also adopts a digitally adjustable structure. The inductance adjustment step size is matched with the capacitance adjustment step size of the series adjustable capacitor. The adjustment process is simultaneously incorporated into the dynamic impedance matching adjustment process. During each adjustment process, the parameters of the two units are updated simultaneously according to the impedance deviation. There is no need to adjust them separately. The adjustment process is unified and simple, without adding extra adjustment time or disrupting the original dynamic adjustment logic.

[0064] It's important to understand that the impedance of a high-frequency signal consists of both a real and an imaginary part. Parasitic parameters primarily alter the imaginary part of the impedance. Series parasitic inductance increases the inductive component of the imaginary part, while parallel parasitic capacitance increases the capacitive component. This embodiment uses a series adjustable capacitor to cancel the inductive component and a parallel adjustable inductor to cancel the capacitive component, ultimately bringing the imaginary part of the impedance close to zero and stabilizing the real part at the target value, thus achieving high-precision impedance matching. Furthermore, both units of the adjustable impedance network are integrated at the probe root, coinciding with the signal port. The compensated impedance parameters directly act on the signal transmission path, unaffected by parasitic parameters in intermediate transmission sections. All parameter adjustments apply to the actual operating signal port, resulting in higher accuracy of the matching results.

[0065] The advantage of this embodiment is that by adding a parallel adjustable inductor unit to the adjustable impedance network, the parasitic capacitance introduced by the probe and channel wiring is compensated. Combined with the original series adjustable capacitor unit, it covers the compensation requirements of different types of parasitic parameters, further optimizes the transmission quality of high-frequency signals, and reduces signal distortion caused by parasitic parameters.

[0066] Example 7: In order to solve the problem of lengthy test process and low test efficiency caused by repeated impedance matching adjustment in batch testing, this example further optimizes the subsequent process of dynamic impedance matching and adds parameter storage and retrieval steps.

[0067] Furthermore, after completing impedance adjustment to obtain a stable output signal, the control unit of the probe card will automatically execute the parameter storage step to record the optimal impedance matching parameters corresponding to the semiconductor component under test. The stored parameters include the current range parameters of the series adjustable capacitor and parallel adjustable inductor in the adjustable impedance network, as well as the initial reference parameters of the fuzzy PID adjustment adapted to this model of component.

[0068] It's important to understand that the pin structure and processing parameters of semiconductor components of the same model have relatively small deviations, and the parasitic parameter deviations at the probe contact points are also within a small range. The optimal impedance matching parameters obtained through dynamic adjustment during the initial test can be directly adapted to the testing requirements of other components of the same model, without needing to complete the entire adjustment process from scratch. The parameters are stored in the non-volatile memory of the probe card control unit and will not be lost due to power failure. The stored parameters are bound to the model identifier of the semiconductor component under test, and the control unit can quickly retrieve the corresponding parameters based on the input test task information.

[0069] Understandably, in the current batch testing process, each component under test needs to undergo the complete impedance matching adjustment process again. Even for components of the same model with minimal parameter deviation, multiple steps such as deviation acquisition, parameter calculation, and range adjustment need to be repeated, consuming a significant amount of testing time and slowing down the overall batch testing pace. Figure 4As shown, in this embodiment, after configuring the stored optimal parameters, the eye diagram opening of the matched high-frequency signal meets the signal integrity requirements and can be directly used for subsequent testing. Furthermore, when the test task starts, the control unit first searches the storage unit for the optimal impedance matching parameters corresponding to the current model of the component under test. If they exist, the parameters are directly written into the adjustable impedance network, and the test is started directly after impedance configuration is completed, without needing to re-execute the complete dynamic adjustment process. If they do not exist, the dynamic adjustment process is started, and after obtaining a stable signal, the obtained optimal parameters are stored for subsequent testing of the same model of component.

[0070] It's important to understand that for special components with parameter deviations exceeding the allowable range, after retrieving stored parameters and completing the configuration, only a small range of deviation corrections can be performed, eliminating the need to adjust from scratch and thus shortening the adjustment time. Furthermore, the parameter storage capacity can be expanded according to the needs of batch testing, supporting the storage of matching parameters for hundreds of different models of tested components. This meets the needs of various testing scenarios, from multi-variety small-batch to single-variety large-batch. The parameter storage and retrieval process is automatically completed by the control unit, eliminating the need for manual recording and configuration by test personnel, thus reducing the probability of errors from manual operation.

[0071] The advantage of this embodiment is that by adding the storage and retrieval steps of the optimal impedance matching parameters, the optimal parameters that have been adjusted can be directly retrieved for the same type of semiconductor device under test, saving the time consumption of the complete dynamic adjustment process, shortening the overall test process, and adapting to the efficiency requirements of batch semiconductor testing.

[0072] Example 8: In order to solve the problem that the impedance matching process of high-frequency probe cards lacks a closed-loop modular execution architecture and the adjustment response lag matching accuracy is insufficient, this example further provides a high-frequency probe card signal optimization system based on dynamic impedance matching for implementing the aforementioned signal optimization method.

[0073] The system is functionally divided into four independent modules, which are sequentially connected to form a complete closed-loop adjustment link, providing clear functional support for dynamic impedance matching. The real-time parameter acquisition module is coupled to the signal transmission path of each test channel on the probe card, used to acquire real-time high-frequency signal reflection parameters of the probe card's test channels, providing real-time detection basis for dynamic impedance matching. The acquisition module can be deployed close to the probe port, and the acquired reflection parameters more closely match the actual signal transmission state of the port, avoiding parameter deviations caused by long-distance acquisition.

[0074] Furthermore, the impedance deviation extraction module receives the reflection parameters output by the real-time parameter acquisition module and extracts the corresponding real-time impedance deviation value of the channel, quantifying the impedance mismatch between the probe card and the semiconductor device under test. It's important to understand that there is a definite conversion relationship between the reflection parameters and the impedance deviation. The impedance deviation extraction module has built-in preset conversion logic that can directly convert the acquired reflection coefficient into an adjustable quantized deviation without requiring external instruments for calculation, thus reducing data transmission latency.

[0075] Furthermore, the adjustment command generation module receives the quantized impedance deviation value output by the impedance deviation extraction module, and uses it to generate a matching adjustment command based on the impedance deviation value, outputting a corresponding impedance matching control signal. The adjustment command generation module has a built-in preset fuzzy PID adjustment logic, which can generate adjustment commands with corresponding step sizes based on the magnitude and direction of the deviation, adapting to the adjustment needs at different stages of the dynamic adjustment process.

[0076] Furthermore, the impedance adjustment drive module receives the control signal output by the adjustment command generation module, which is used to drive the adjustable impedance network integrated in the probe card channel to adjust the output impedance, match the probe card channel impedance with the impedance of the port under test in real time, suppress signal reflection, and optimize signal quality. The impedance adjustment drive module is directly connected to the adjustable impedance network integrated at the probe root, resulting in a short control signal transmission path and fast response speed. After adjustment, the adjustment result can be immediately fed back to the real-time parameter acquisition module to enter the next adjustment cycle.

[0077] In this embodiment, the modules are connected sequentially to form a complete closed loop. The output of each module directly serves as the input of the next module, and the entire adjustment process requires no manual intervention. It's important to understand that each test channel corresponds to an independent functional module. During multi-channel parallel testing, each channel can independently complete its own impedance matching adjustment without mutual interference, adapting to the parallel testing requirements of multi-pin semiconductor components. Furthermore, the modules use standardized interface connections; if one module fails, the corresponding module can be replaced directly without replacing the entire system, reducing maintenance costs.

[0078] The advantage of this embodiment is that by modularly dividing different functional units, a complete closed-loop dynamic matching architecture from parameter acquisition to impedance adjustment is formed. Each module has a clear division of labor and logical clarity, and can respond to changes in port impedance in real time to complete high-precision dynamic impedance matching, providing stable architectural support for signal optimization of high-frequency probe cards.

[0079] Example 9: In order to solve the problem that the signal optimization method for dynamic impedance matching is difficult to deploy repeatedly without specific hardware, and the method is difficult to port and update, this example further provides a computer-readable storage medium storing a computer program that implements the aforementioned signal optimization method.

[0080] Furthermore, this storage medium is a non-volatile storage medium. When the stored computer program is executed by the processor, it can completely implement all the execution steps of the aforementioned high-frequency probe card signal optimization method based on dynamic impedance matching. The storage medium itself can run the stored computer program on different hardware platforms without needing to redevelop the algorithm flow for different platforms, thus reducing the cost of method portability and expanding the applicability of the method.

[0081] It is important to understand that the computer program stored on the storage medium covers the entire process of the signal optimization method, including real-time reflection parameter acquisition, impedance deviation extraction, adjustment command generation, adjustable impedance network driving, and optimal matching parameter storage and retrieval. When the program runs, it can execute each step sequentially according to the preset logic, thus fully realizing the signal optimization process of dynamic impedance matching.

[0082] Furthermore, the storage medium adopts a universal, standardized storage structure, compatible with the storage interfaces of most mainstream semiconductor testing equipment. It can be integrated into the probe card's built-in storage unit or stored in a separate storage unit of an external testing device. The storage location can be flexibly selected according to the actual testing scenario without altering the existing hardware structure of the testing system, thus lowering the barrier to method implementation. Understandably, the computer program stored on the storage medium supports version updates; simply rewriting the updated program completes the method's iterative upgrade without modifying the original hardware structure. This facilitates adjusting the logic according to actual testing needs, adapting to the testing requirements of different frequency bands and types of probe cards.

[0083] Furthermore, the computer program employs a modular programming approach, with each functional step corresponding to an independent program module. Adjusting one functional module will not affect the normal operation of other modules. For example, adjusting the logic of the parameter storage module will not affect the functionality of the impedance adjustment module, facilitating subsequent functional expansion and error correction. It's important to understand that the program can directly interface with existing probe cards during operation, eliminating the need for custom interfaces. This ensures strong universal compatibility; both newly manufactured probe cards and existing ones already in use can achieve dynamic impedance matching signal optimization by loading the program from this storage medium. Moreover, in addition to storing the computer program itself, the storage medium also reserves space for storing the optimal impedance matching parameters for different types of semiconductor devices under test, eliminating the need for additional independent storage units and simplifying the overall storage architecture.

[0084] The advantage of this embodiment is that by storing the computer program implementing the signal optimization method on a standardized storage medium, the method can be flexibly deployed on different hardware platforms, facilitating portability, updates, and iterations, and reducing the cost of promoting and using the dynamic impedance matching signal optimization method.

[0085] Example 10: To address the lack of a dedicated computational execution platform for the dynamic impedance matching signal optimization process, and the difficulty of meeting real-time adjustment response requirements with existing general-purpose processing units, this example further provides an electronic device for implementing the aforementioned signal optimization method. The electronic device includes a memory and a processor. The processor is coupled to the memory and is used to call and execute the computer program stored in the memory, fully implementing all steps of the aforementioned high-frequency probe card signal optimization method based on dynamic impedance matching.

[0086] Furthermore, the processor can employ a high-speed digital signal processor to meet the real-time processing requirements of high-frequency signal reflection parameters. It can complete impedance deviation extraction and adjustment instruction generation in a short time, adapting to the real-time adjustment requirements of dynamic impedance matching, without affecting the matching effect due to processing delays. It's important to understand that the memory is divided into two parts: running memory and non-volatile storage units. Running memory is used to temporarily store intermediate data during program execution, such as the real-time reflection parameters and impedance deviation calculation results of the current channel. Non-volatile storage units are used to store the computer program itself and the optimal impedance matching parameters corresponding to different types of measured components. The different storage units work together to ensure both the speed of program execution and the preservation of stored data even when power is lost.

[0087] Furthermore, the processor connects to the probe card's adjustable impedance network via a dedicated high-speed parallel interface, resulting in lower latency in transmitting adjustment control signals. Control commands can then be quickly applied to the adjustable impedance network, shortening the cycle of a single adjustment and improving the overall response speed of dynamic matching. It is understood that this electronic device can be directly integrated into the probe card's control base, deployed as part of the probe card, or it can be used as an independent control unit connected externally between the existing test system and the probe card, without requiring modifications to the core structure of the original test system, thus adapting to different test scenario layout requirements.

[0088] Furthermore, the electronic device is equipped with a standardized communication interface, which can interact with the host test server to exchange data, upload the impedance matching status and signal quality parameters of each channel, and receive test task information from the host server, such as the model of the semiconductor component under test. It can directly retrieve the stored optimal impedance matching parameters based on the model and complete the parameter configuration. The whole process is automated and does not require manual intervention.

[0089] It's important to understand that the electronic device supports multi-channel parallel processing. The processor has multiple independent processing cores, enabling it to simultaneously handle impedance matching adjustments for multiple probe test channels. This adapts to the parallel testing needs of multi-pin semiconductor components, and the adjustment response speed does not decrease with the increase in the number of channels. Furthermore, the electronic device incorporates a passive cooling structure, maintaining the processor and memory within a stable temperature range. This prevents high temperatures from causing processor calculation errors or memory data corruption, ensuring stable operation during long-term batch testing.

[0090] The advantage of this embodiment is that, through the coupled architecture of the processor and memory, it provides a stable and reliable execution carrier for the dynamic impedance matching signal optimization method, which can meet the performance requirements of real-time adjustment under high-frequency testing conditions and adapt to the long-term stable operation requirements of batch semiconductor testing scenarios.

[0091] Although the present invention has been specifically described above with reference to preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above. Various modifications and variations can be made by those skilled in the art without departing from the spirit of the present invention, and such modifications and variations should fall within the scope defined by the appended claims and their equivalents.

Claims

1. A method for optimizing high-frequency probe card signals based on dynamic impedance matching, characterized in that the steps include... include: The real-time high-frequency signal reflection parameters of the probe card test channel are obtained to provide a real-time detection basis for dynamic impedance matching. Extract the channel real-time impedance deviation value corresponding to the real-time high-frequency signal reflection parameters to quantify the impedance mismatch between the probe card and the semiconductor device under test. Based on the impedance deviation value, a matching adjustment command is generated, and a corresponding impedance matching control signal is output. The control signal drives the adjustable impedance network integrated in the probe card channel to adjust the output impedance, and matches the probe card channel impedance with the impedance of the port under test in real time to suppress signal reflection and optimize signal quality.

2. The high-frequency probe card signal optimization method based on dynamic impedance matching as described in claim 1, characterized in that, Before obtaining the real-time high-frequency signal reflection parameters, a pre-calibration step is also included, in which the impedance of each probe card test channel is initially calibrated to establish the correspondence between the adjustment command and the output impedance of the adjustable impedance network, so as to eliminate the reference deviation caused by the processing error of different channels.

3. The high-frequency probe card signal optimization method based on dynamic impedance matching as described in claim 1, characterized in that, The steps for extracting the impedance deviation value include: calculating the actual load impedance of the current channel based on the reflection coefficient formula and the characteristic impedance of the transmission line, and then subtracting the actual load impedance from the preset target impedance to obtain the impedance deviation value.

4. The high-frequency probe card signal optimization method based on dynamic impedance matching as described in claim 1, characterized in that, The step of generating a matching adjustment command based on the impedance deviation value includes inputting the impedance deviation value into a preset fuzzy PID adjustment model to generate a step adjustment command for the adjustable impedance network, which is used to avoid overshoot oscillation during the adjustment process.

5. The high-frequency probe card signal optimization method based on dynamic impedance matching as described in claim 1, characterized in that, The adjustable impedance network is integrated into the probe root of the probe card to shorten the transmission distance from the matching point to the port of the semiconductor device under test, thereby reducing the impact of parasitic impedance of the transmission line on the matching effect. The adjustable impedance network includes a series adjustable capacitor unit to compensate for the parasitic inductance introduced by the probe structure itself, thereby improving the impedance mismatch problem at high frequencies.

6. The high-frequency probe card signal optimization method based on dynamic impedance matching as described in claim 5, characterized in that, The adjustable impedance network also includes a parallel adjustable inductor unit to compensate for parasitic capacitance introduced by probes and channel wiring, thereby optimizing the transmission quality of high-frequency signals.

7. The high-frequency probe card signal optimization method based on dynamic impedance matching as described in claim 1, characterized in that, After obtaining a stable signal through impedance adjustment, the process also includes a parameter storage step, which records the optimal impedance matching parameters corresponding to the current semiconductor device under test. When testing the same type of semiconductor device again, the optimal impedance matching parameters can be directly called to shorten the testing process and improve the efficiency of batch testing.

8. A high-frequency probe card signal optimization system based on dynamic impedance matching, used to implement the high-frequency probe card signal optimization method based on dynamic impedance matching as described in any one of claims 1-7, characterized in that, include: The real-time parameter acquisition module is used to acquire the real-time high-frequency signal reflection parameters of the probe card test channel, providing a real-time detection basis for dynamic impedance matching; The impedance deviation extraction module is used to extract the real-time impedance deviation value of the channel corresponding to the reflection parameter, and quantify the impedance mismatch between the probe card and the semiconductor device under test. The adjustment command generation module is used to generate a matching adjustment command based on the impedance deviation value and output a corresponding impedance matching control signal. The impedance adjustment drive module is used to drive the adjustable impedance network integrated in the probe card channel to adjust the output impedance, match the probe card channel impedance with the impedance of the port under test in real time, suppress signal reflection and optimize signal quality.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the high-frequency probe card signal optimization method based on dynamic impedance matching as described in any one of claims 1 to 7.

10. An electronic device, comprising a memory and a processor, wherein the processor is coupled to the memory, and the processor is configured to call and execute a computer program stored in the memory to implement the high-frequency probe card signal optimization method based on dynamic impedance matching as described in any one of claims 1 to 7.

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