Memory failure processing method, electronic device, storage medium, and program product

Abstract

This application discloses a memory fault handling method, electronic device, storage medium, and program product, relating to the field of server operation and maintenance technology. This application identifies fault modes such as row failures through multi-dimensional feature recognition and performs reverse mapping based on geometric physical addresses to achieve preventative batch isolation of multiple pages on the same physical row. This avoids the problem of repeated operating system jitter or even crashes caused by fault propagation in related solutions. By establishing a soft-first-hard-later filtering mechanism, PPR requests are suppressed for faults that have been successfully isolated by soft methods, avoiding the consumption of effective and irreversible hardware repair resources. Simultaneously, a dynamic gating strategy based on the remaining resource status repairs only high-risk faults when resources are exhausted, extending the lifespan of the memory module. The operating system feeds back the soft isolation execution results to the firmware, solving the blind spot of no one taking over after soft isolation failure in related solutions, ensuring that each memory risk point has a definite final handling status, and effectively reducing the risk of server downtime.

Description

Technical Field

[0001] This application relates to the field of server operation and maintenance technology, and in particular to a memory fault handling method, electronic device, storage medium and program product. Background Technology

[0002] In the field of server operation and maintenance, hardware fault diagnosis and prediction is a technical challenge in the industry. Among them, memory-related server failures account for the highest proportion of all hardware failures. Therefore, effectively diagnosing and isolating memory faults is crucial to ensuring high system availability. To address memory errors, relevant solutions include: at the hardware level, ECC (Error Correction Code) and PPR (Post-Package Repair) to repair faulty hardware; at the software level, the memory page offline mechanism of operating systems such as Linux is used to achieve logical isolation of faulty pages. However, these solutions have significant problems: First, the hardware and software fault handling mechanisms are disconnected, lacking linkage and closed-loop feedback. After software isolation fails, the hardware layer cannot take over in time, resulting in the long-term exposure of high-risk fault points. Second, the operating system lacks awareness of the physical distribution of memory faults and can only isolate faulty pages at a single point, which cannot deal with row-distributed physical faults, easily leading to frequent interruptions and system jitter. Third, PPR repair resources are limited and irreversible, and related solutions are prone to resource abuse and waste. As the memory capacity of a single machine enters the TB (terabyte) level, single-dimensional protection methods can no longer meet the core requirements of high-reliability scenarios. Summary of the Invention

[0003] This application provides a memory fault handling method, electronic device, storage medium, and program product to at least solve the problems of fragmented software and hardware fault handling, single repair strategy, and low utilization of hardware repair resources in related technologies.

[0004] This application provides a memory fault handling method, including: In response to a memory failure event, the memory failure event is parsed to determine the geometric physical address of the faulty memory. Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; Based on memory failure modes, a matching memory page offline instruction is sent to the operating system to control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and the execution result of the soft isolation operation is received from the operating system. Based on the results of the soft isolation operation and the remaining resource status of the memory after the memory fault is encapsulated and repaired, determine whether to trigger the hardware encapsulation and repair operation. If the hardware encapsulation and repair operation is triggered, execute the encapsulation and repair operation.

[0005] This application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the following steps of a memory fault handling method when executing the computer program: In response to a memory failure event, the memory failure event is parsed to determine the geometric physical address of the faulty memory. Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; Based on memory failure modes, a matching memory page offline instruction is sent to the operating system to control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and the execution result of the soft isolation operation is received from the operating system. Based on the results of the soft isolation operation and the remaining resource status of the memory after the memory fault is encapsulated and repaired, determine whether to trigger the hardware encapsulation and repair operation. If the hardware encapsulation and repair operation is triggered, execute the encapsulation and repair operation.

[0006] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the following steps of a memory fault handling method: In response to a memory failure event, the memory failure event is parsed to determine the geometric physical address of the faulty memory. Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; Based on memory failure modes, a matching memory page offline instruction is sent to the operating system to control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and the execution result of the soft isolation operation is received from the operating system. Based on the results of the soft isolation operation and the remaining resource status of the memory after the memory fault is encapsulated and repaired, determine whether to trigger the hardware encapsulation and repair operation. If the hardware encapsulation and repair operation is triggered, execute the encapsulation and repair operation.

[0007] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the following steps of a memory fault handling method: In response to a memory failure event, the memory failure event is parsed to determine the geometric physical address of the faulty memory. Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; Based on memory failure modes, a matching memory page offline instruction is sent to the operating system to control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and the execution result of the soft isolation operation is received from the operating system. Based on the results of the soft isolation operation and the remaining resource status of the memory after the memory fault is encapsulated and repaired, determine whether to trigger the hardware encapsulation and repair operation. If the hardware encapsulation and repair operation is triggered, execute the encapsulation and repair operation.

[0008] This application identifies fault modes such as row failure through multi-dimensional feature recognition and performs reverse mapping based on geometric physical addresses to achieve preventative batch isolation of multiple pages on the same physical row. This avoids the problem of repeated operating system jitter or even crashes caused by fault propagation in related solutions. By establishing a soft-first-hard-later filtering mechanism, PPR requests are suppressed for faults that have been successfully isolated by soft methods, avoiding the consumption of effective and irreversible hardware repair resources. At the same time, a dynamic gating strategy based on the remaining resource status repairs only high-risk faults when resources are exhausted, extending the lifespan of memory modules. By having the operating system feed back the soft isolation execution results to the firmware, the blind spot of no one taking over after soft isolation failure in related solutions is solved, ensuring that each memory risk point has a definite final disposal status and effectively reducing the risk of server downtime. Attached Figure Description

[0009] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This application provides an application environment diagram for a memory fault handling method according to an embodiment of the present application. Figure 2 This application provides an overall flowchart of a memory fault handling method according to an embodiment of the present application. Figure 3 This application provides another overall flowchart of a memory fault handling method according to an embodiment of the present application; Figure 4 This is a schematic diagram of the memory fault mode recognition logic provided in an embodiment of this application; Figure 5 This is a schematic diagram of the decision logic for memory fault handling strategies provided in an embodiment of this application; Figure 6 This is a diagram of the internal structure of an electronic device in one embodiment. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0012] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] It should be noted that the terms "S1," "S2," etc., are used only for descriptive purposes and do not specifically refer to the order or sequence, nor are they intended to limit this application. They are merely for the convenience of describing the method of this application and should not be construed as indicating the sequential order of the steps. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0014] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] The memory fault handling method provided in this application can be applied to, for example... Figure 1In the application environment shown, terminal 102 communicates with a data processing platform set on server 104 via a network. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Server 104 can be implemented as a standalone server or a server cluster consisting of multiple servers.

[0016] like Figure 2 As shown, embodiments of this application provide a memory fault handling method, which is applied to... Figure 1 Taking the terminal in the example, the explanation includes the following steps: S1: In response to a memory failure event, analyze the memory failure event and determine the geometric physical address corresponding to the faulty memory.

[0017] It should be noted that memory fault events refer to correctable errors (CE) or uncorrectable errors (UCE) captured by the memory controller during server operation, which are the starting point for triggering the fault handling process; geometric physical address refers to the physical coordinates of the internal structure of the memory particle (including Socket, Channel, DIMM, Rank, Bank, Row, Column) after being converted by the address decoding algorithm, which is different from the linear physical address used by the operating system.

[0018] S2: Obtain multi-dimensional features, classify memory fault events based on multi-dimensional features, and determine the corresponding memory fault modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features.

[0019] It should be noted that the multi-dimensional features refer to the set of fault features extracted from three dimensions: time, space, and data. These features are used to comprehensively describe the behavioral patterns of memory errors and provide a basis for fault classification. The time dimension features refer to the time-series characteristics of the error occurrence, including the error count, growth trend, and periodicity within a unit of time, used to identify time-sensitive faults such as CE storms. The spatial dimension features refer to the distribution characteristics of the error in the geometric physical address, including the clustering and distribution range of rows and columns, used to identify structural faults such as row failures and column failures. The data dimension features refer to the bit pattern characteristics of the error data, such as whether the XOR operation result of multiple error data points to the same data pin, used to identify faults such as data link or poor contact.

[0020] S3: Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address.

[0021] It should be noted that reverse address mapping refers to the process of querying the system memory address mapping table based on the Row information in the geometric physical address to calculate all operating system page frame numbers covered by the physical row; the operating system page frame number set refers to the combination of page frame numbers of multiple 4KB memory pages mapped to the same physical row at the operating system level, which is used to implement preventive bulk isolation.

[0022] S4: Based on the memory failure mode, send a matching memory page offline instruction to the operating system, control the operating system to execute the soft isolation operation corresponding to the operating system page frame number set, and receive the soft isolation operation execution result fed back by the operating system.

[0023] It should be noted that: Memory page offline instruction: refers to the control instruction sent by the firmware layer to the operating system, used to trigger the operating system to perform data migration and resource reclamation operations on a specified memory page; Soft isolation operation: refers to the fault handling method at the operating system level, including operations such as migrating data in a faulty page to a healthy region and removing a faulty page from the memory allocation list; Soft isolation operation execution result: refers to the status information returned by the operating system after executing the page offline operation, including page frames that were successfully offline, page frames that could not be offline due to kernel locking or other reasons, and the reason for failure.

[0024] S5: Based on the execution result of the soft isolation operation and the remaining resource status of the memory after the memory fault is repaired, determine whether to trigger the hardware repair operation. If the hardware repair operation is triggered, execute the repair operation.

[0025] It should be noted that the Post-Packaging Repair Remaining Resource Status (PPR) refers to the number or proportion of currently available redundant rows in the memory module, stored in the resource status register of the memory chip, and used to decide whether to trigger hardware repair; Hardware Post-Packaging Repair Operation refers to the hardware-level repair operation that uses the redundant rows reserved inside the memory chip to replace the faulty rows, which must be executed by the BIOS during system restart or maintenance window.

[0026] In the above implementation, multi-dimensional feature identification of fault modes such as row failure and reverse mapping based on geometric physical address are used to achieve preventive batch isolation of multiple pages on the same physical row. This avoids the problem of repeated operating system jitter or even crashes caused by fault propagation in related solutions. By establishing a soft-first-hard filtering mechanism, PPR requests are suppressed for faults that have been successfully isolated by soft, avoiding the consumption of effective and irreversible hardware repair resources. At the same time, a dynamic gating strategy based on the remaining resource status repairs only high-risk faults when resources are exhausted, extending the lifespan of the memory module. The operating system feeds back the soft isolation execution results to the firmware, solving the blind spot of no one taking over after soft isolation failure in related solutions. This ensures that each memory risk point has a definite final disposal status, effectively reducing the risk of server downtime.

[0027] In some specific implementations, such as Figure 3 As shown, analyzing memory fault events and determining the corresponding geometric physical address of the faulty memory includes: In response to memory failures, register information in the memory controller is read. In Intel's MCA architecture, the DIMMs on both sides are the memory. Memory failures are divided into two categories: CE (Corrective Error), which is a correctable error and can be automatically corrected by the ECC mechanism. However, too many or frequent CEs may indicate the occurrence of uncorrectable errors, so appropriate measures should be taken after a CE is detected. The other type of error is UCE (Uncorrectable Error). If a UCE occurs, it is usually accompanied by server crashes, which is a serious server failure. The approach to fault memory isolation is to detect CEs, track their occurrence, and take appropriate strategies to prevent UCEs from occurring. Whether a CE or a UCE occurs, detailed fault information is recorded in the IMC (Integrated Memory Controller). The IMC can be understood as a set of registers in the MCA architecture used to store detailed fault information. The register information is parsed to obtain the system physical address corresponding to the memory fault. In particular, by parsing the IMC-related registers, the physical memory address where the CE error occurred can be obtained, which is the system physical address. The address decoding algorithm based on the memory controller converts the system physical address into a geometric physical address. Before performing memory fault mode identification, the system physical address (usually a virtual address) seen by the operating system must be converted into the geometric physical address of the memory chip. The operating system captures the error address and uses the address decoding algorithm of the memory controller (IMC) to parse out the detailed physical address of the memory fault [Socket ID, Channel ID, DIMM ID, Rank ID, BankGroup, Bank, Row, Column]. Only based on the geometric address can the topology of the physical fault be determined. The address decoding algorithm is a commonly used method, and the specific process will not be elaborated here.

[0028] In the above implementation, by parsing the memory controller register information and converting it using the address decoding algorithm, the system physical address at the operating system level is accurately mapped to a granular geometric physical address, thereby obtaining complete topological information including Socket, Bank, Row, Column, etc. This provides a precise physical location basis for subsequent fault mode identification based on spatial distribution characteristics, and thus accurately determines structural faults such as row failure and column failure.

[0029] In some specific implementations, obtaining multi-dimensional features includes: Based on geometric physical addresses, the address distribution features of memory fault events in the spatial dimension are extracted to obtain spatial dimension features; Based on the time series of memory fault events, frequency features in the time dimension are extracted to obtain time dimension features; Based on the geometric physical address, the correlation distribution features of memory fault events in the topological dimension are extracted to obtain the topological dimension features; Based on the fault data corresponding to memory fault events, fault bit pattern features are extracted in the data dimension to obtain data dimension features.

[0030] In some specific implementations, such as Figure 4 As shown, based on multi-dimensional features, memory failure events are classified, and the corresponding memory failure modes are determined, including: If the spatial dimension features show that the fault is fixed at a single coordinate and the temporal dimension features show that the number of times the fault occurs at the target geometric physical address is greater than a first preset threshold, the memory fault mode is determined to be a single-point fixed mode. If the spatial dimension features show that the fault is distributed in the target physical row address and the number of physical column addresses within the distributed target physical row address is greater than the second preset threshold, the memory fault mode is determined to be the row failure mode. In response to the spatial dimension feature showing that the fault is distributed in the target physical column address and the number of distributed physical row addresses is greater than the third preset threshold, the memory fault mode is determined to be column failure mode. The memory fault mode is determined to be error storm mode based on the time dimension feature showing that the number of faults occurring per unit time is greater than the fourth preset threshold and the growth trend conforms to the exponential law. The memory fault mode is determined to be a data pin failure mode because the XOR operation result of multiple fault data points to the target data pin, based on the data dimension feature display. In response to the topology dimension features showing that different geometric physical addresses point to fixed data bits after XOR analysis of data bits, and that there are associated errors in the local coupling area of ​​memory in the same memory column or associated errors on the same channel bus, the memory fault mode is determined to be either data bit mode or link contact abnormal mode.

[0031] The first, second, third, and fourth preset thresholds can all be set according to actual needs. The specific classification method for classifying memory faults based on three-dimensional pattern matching of spatial, temporal, and data feature dimensions is shown in Table 1. Table 1: Memory Fault Classification Table

[0032] Specifically, such as Figure 5As shown, the error capture and multidimensional pattern recognition process begins with the memory controller (IMC) capturing a memory error event. When a correctable error (CE) or uncorrectable error (UCE) occurs during system operation, the hardware logic first decodes the error address, converting the system physical address into a geometric physical address containing Bank, Row, and Column information. Subsequently, the fault mode analysis engine intervenes to perform real-time analysis of the error flow. In this step, the system performs temporal and spatial feature extraction in parallel: on the one hand, the frequency of error occurrence is monitored through the leaky bucket algorithm. Once the error count per unit time exceeds a preset safety threshold, it is determined to be a CE storm. This state is marked as extremely high priority, and emergency isolation is immediately triggered to prevent CPU deadlock. On the other hand, for non-storm-type errors, the distribution characteristics of the errors in the row and column coordinates are analyzed. If the errors are found to be concentrated in the same row but span multiple columns, it is determined to be a row failure mode. If the error is fixed at a single coordinate, it is determined to be a single-point fixation mode. The leaky bucket algorithm is a commonly used method, and the specific process will not be elaborated here.

[0033] In the above implementation, by constructing a fault identification mechanism that integrates time, space, and data three-dimensional features and setting dynamically adjustable multi-level thresholds, the mechanism achieves accurate classification of five fault modes, including single-point fixation, row / column failure, error storm, and data pin failure. This breaks through the limitations of single-dimensional judgment, provides a basis for subsequent differentiated processing strategies, and avoids the abuse of repair resources.

[0034] In some specific implementations, reverse address mapping is performed based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address, including: Based on the row address information in the geometric physical address, determine the physical row address where the memory fault occurs; Based on the mapping table between physical row addresses and system memory addresses, determine the range of physical addresses covered by the physical row addresses; Convert the physical address range to the corresponding operating system page frame number to generate a set of page frame numbers to be isolated.

[0035] In some specific implementations, sending a matching memory page offline instruction to the operating system based on the memory failure mode includes: In response to the memory failure mode being row failure mode, a batch offline instruction is generated based on the set of page frame numbers to be isolated; In response to a memory failure mode of single-point fixation, a single-point offline instruction is generated based on the target page frame number corresponding to the geometric physical address. In response to the memory failure mode being error storm mode, a shutdown instruction carrying an emergency flag is generated based on the set of page frame numbers to be isolated.

[0036] Specifically, after pattern recognition is completed, if the fault type is determined to be suitable for software isolation (such as single point fixation or CE storm), the system reversely searches and calculates the list of operating system page frame numbers mapped to the identified faulty physical row address. The key to this step is that it not only identifies the currently erroneous page, but also predictively identifies other pages on the same physical row that have not yet reported errors but are at high risk (avoiding isolation for a single specific page; if there is a row error, simply offlineing a page is useless). Subsequently, the firmware sends an isolation command to the operating system kernel through a platform-specific interface.

[0037] In the above implementation, reverse address mapping is performed based on the row address information in the geometric physical address, which can accurately calculate all operating system page frame numbers covered by the faulty physical row. This mechanism not only isolates the currently faulty page, but also predictively isolates high-risk pages on the same physical row that have not yet reported errors, realizing topology-aware preventive batch isolation, effectively avoiding repeated downtime caused by fault propagation, and improving system stability.

[0038] In some specific implementations, controlling the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and receiving the soft isolation operation execution results from the operating system, includes: In response to the memory page offline instruction, the operating system page frame number set is parsed to obtain the parsing result; Based on the parsing results, the valid data within multiple page frames in the operating system page frame number set will be migrated to the healthy memory region; In response to the completion of the migration, the page frame that has been migrated is removed from the memory allocation list, the result of the soft isolation operation of the page frame is recorded, and the result of the soft isolation operation is received.

[0039] Specifically, in response to this instruction, the operating system attempts to migrate valid data within the page, release the mapping, and remove the faulty page from the buddy system or free list. If the page is a migrateable page, it performs a normal page offline operation. If it is a locked page, a kernel-reserved page, a large page mapping region, or a page that cannot be migrated, the failure reason is recorded and returned to the firmware. That is, when performing a page offline operation, it attempts to migrate valid data in the affected page to a healthy region and removes the faulty page from the free list so that it can no longer be allocated to any process.

[0040] In the above implementation, by performing a memory page offline operation, the valid data in the faulty page is migrated to the healthy area and removed from the memory allocation list, thereby achieving logical isolation of the faulty page. This mechanism completes fault masking at the operating system level, while recording fine-grained execution results and feeding them back to the firmware layer, providing a basis for subsequent hardware repair decisions and ensuring the integrity of the software-hardware collaborative closed loop.

[0041] In some specific implementations, determining whether to trigger a hardware post-packaging repair operation based on the soft isolation operation execution result and the remaining resource status of the memory corresponding to the memory fault includes: In response to a successful soft isolation execution result, suppress hardware encapsulation repair operation requests for the geometric physical address and mark the geometric physical address as a successful soft isolation state; In response to a failure in the soft isolation execution, the encapsulated repair resource status register in memory is read to obtain the proportion of currently available repair lines. Based on the proportion of remaining available repair lines, determine whether to add the geometric physical address to the repair queue to trigger the hardware packaging repair operation.

[0042] In some specific embodiments, the method further includes: Based on the proportion of remaining available repair rows, the admission threshold for repair after encapsulation is dynamically adjusted. For example, if resources are sufficient (e.g., remaining > 50%), a lenient strategy is adopted to perform PPR on all soft isolation failures. If resources are exhausted (e.g., remaining < 10%), a strict strategy is switched to allow PPR to be performed only on high-risk failures such as row failures, and low-priority repair requests are rejected, thereby achieving refined utilization of resources. If the proportion of remaining available repair lines is greater than the first threshold, it is determined that the resources are sufficient and a lenient repair strategy is adopted. If the proportion of remaining available repair lines is less than the second threshold, it is judged to be in a state of resource depletion, and a strict retention strategy is adopted. In response to the lenient repair strategy, multiple geometric physical addresses that failed to execute soft isolation are added to the repair queue; In response to the stringent retention policy, the geometric physical address corresponding to the failure mode of soft isolation execution that fails is added to the repair queue.

[0043] The first and second thresholds can be set according to actual needs. Specifically, after the operating system completes the page offline operation, it will feed back the execution result (success or failure) to the underlying management firmware (such as BMC). The firmware will make a mutual exclusion decision based on this feedback signal: if the operating system reports successful isolation, it means that the fault has been logically masked. At this time, the firmware marks the physical address as "soft repair successful state". In this state, the system will actively suppress hardware PPR repair requests for the address, that is, it will not add the address to the repair queue, thereby avoiding the consumption of valuable and irreversible PPR resources and realizing the memory fault isolation and repair strategy of "soft repair first". Conversely, if the operating system reports isolation failure (for example, the page belongs to the kernel core code segment, is locked and cannot be migrated, or the error is detected after isolation and continues to overflow), the system will determine that the soft isolation has failed. At this time, the fault handling level will be automatically upgraded, and the faulty physical address will be forcibly written into the PPR repair queue in non-volatile memory and marked as a high-risk pending item, waiting for the system to restart for hardware-level isolation.

[0044] In the above implementation, by establishing a mutual exclusion decision mechanism of software first and then hardware, PPR requests are actively suppressed for faults that have been successfully isolated by software, so as to avoid consuming valuable hardware repair resources. At the same time, based on the dynamic gating strategy of resource status, only high-risk faults are repaired when resources are exhausted, realizing closed-loop management of software and hardware collaboration, extending the service life of memory modules, and ensuring that there is an optimal solution for each fault point.

[0045] In some specific implementations, in response to triggering a post-packaging repair operation, performing the post-packaging repair operation includes: Write the geometric physical address that triggers the repair operation after hardware packaging into the repair queue in non-volatile memory; In response to the operating system entering a preset maintenance window or a restart, the system reads the queue of items to be repaired via the basic input / output system. For the geometric physical addresses in the repair queue, send a hardware-packaged repair instruction to the memory module to replace the faulty line with the redundant line reserved inside the memory chip, and record the hardware repair execution status of the geometric physical address.

[0046] Specifically, when the system enters the scheduled maintenance window or a restart occurs, the BIOS will read the above-mentioned PPR pending repair queue during the memory initialization phase. Among them, for PPR requests that the operating system reports a failure of the page offline operation, the system does not simply trigger PPR based on the failure result, but needs to perform a resource-aware dynamic gating judgment process: (1) The system reads the PPR resource status register of the memory module to obtain the current remaining available repair lines (Spare (2) The system dynamically adjusts the PPR admission threshold according to the remaining resource ratio and executes a differentiated strategy: if PPR resources are detected to be sufficient (e.g., the remaining amount is greater than 50%), the system adopts a lenient repair strategy. At this time, as long as the operating system reports a failure of soft isolation (whether due to kernel locking or incomplete isolation), or the fault manifests as a continuous single point of failure, the system allows the address to be added to the PPR repair queue and uses hardware resources to completely eliminate the hidden danger; (3) if PPR resources are detected to be exhausted (e.g., the remaining amount is less than 10%), the system automatically switches to a strict retention strategy. In this mode, the system significantly increases the severity threshold of PPR admission. For ordinary single point of fixation or low-frequency errors, even if software isolation fails, the system will refuse to perform PPR operations to prevent the valuable small amount of redundant resources from being consumed by low-value faults; (4) for addresses that are refused repair, the system will take downgrade measures (e.g., permanently block the memory Rank at the BIOS level or forcibly discard the address range through OS kernel parameters).

[0047] In the above implementation, by persistently storing the fault address and having the BIOS perform PPR repairs in batches during the restart or maintenance window, the hardware repair is planned and batched. At the same time, based on the resource-aware dynamic gating mechanism, the admission threshold is determined differently according to the proportion of remaining redundant rows. When resources are exhausted, only high-risk faults are repaired, low-priority requests are rejected and downgraded, thus maximizing the use of limited hardware repair resources.

[0048] In some specific implementations, after performing the post-packaging repair operation in response to triggering the hardware post-packaging repair operation, the method further includes: For the memory region that has undergone hardware packaging repair operations, a targeted stress test program is launched to perform high-frequency read and write operations; Monitor whether memory failures occur again during stress testing; If no memory failure occurs again, the repair is considered successful, the fault record of the geometric physical address is cleared, and the memory area is allowed to be put back into use; If a memory failure occurs again, the repair is deemed unsuccessful, and the memory module that underwent hardware-packaged repair is marked as permanently retired.

[0049] In some specific embodiments, the method further includes: Memory modules that have undergone hardware-packaged repair operations are marked as permanently retired, and the identification information of the memory modules is written to the permanent retirement list in the basic input / output system. In response to a restart of the operating system, the Basic Input / Output System skips the initialization of the memory module and sends a memory module replacement alarm to the maintenance system.

[0050] Specifically, for addresses requiring PPR repair, a testing process is added: For each address to be repaired in the queue, the BIOS sends a standard PPR instruction to the memory module, replacing the faulty line with a redundant line at the hardware level. After PPR is completed, the system immediately starts a closed-loop verification program to perform targeted stress tests (such as high-frequency read / write tests) on the newly repaired memory area. If the test passes, the system will clear the fault record and allow the area to be put back into use; if the test still fails, it indicates that the physical damage to the DRAM has exceeded the redundancy repair capability, and the system will execute the final fallback strategy, marking the memory module (DIMM) as permanently retired and issuing the highest-level hardware replacement alarm in the boot log, thus completing the closed loop of the entire fault management.

[0051] In the above implementation, based on the post-repair targeted stress test mechanism, high-frequency read and write verification is performed on the PPR repair area to ensure the authenticity and reliability of the repair effect. Modules that fail to be repaired are permanently retired and synchronized to the BIOS and operation and maintenance system to achieve hardware-level fallback isolation. Based on this, hidden dangers are effectively avoided and the long-term stable operation of the system memory pool is ensured.

[0052] In some specific embodiments, the method further includes: Collect historical memory fault data and memory module operating status parameters; Based on the historical memory fault data and the operating status parameters, the fault risk index of each memory region is calculated using a prediction model. If the fault risk index of the target memory region exceeds a preset risk threshold, an active scan of the target memory region is initiated. In response to the discovery of potential physical defects by the proactive scan, a preventative repair instruction is generated to perform soft isolation operations or hardware encapsulation repair operations during off-peak business periods.

[0053] Specifically, based on historical fault data (such as fault modes, frequency of occurrence, and physical location distribution) and the aging characteristics of memory modules (such as usage time, temperature curves, and read / write load), a fault risk index for each memory region is dynamically calculated using a prediction algorithm. When the risk index exceeds a preset threshold (which can be set according to actual needs), the system proactively triggers a preventative scan of that region. If the scan confirms the presence of potential physical defects (such as row addresses that are about to fail), soft isolation or PPR pre-repair is proactively initiated during off-peak business periods. The prediction algorithm can be based on time series analysis, such as the ARIMA model, which analyzes the time pattern of fault occurrence to predict the next fault time window; or regression analysis, such as logistic regression, which establishes a mapping relationship between fault probability and parameters such as temperature and load; or machine learning classification, such as random forest or XGBoost, which trains a classifier based on historical data to identify high-risk memory regions. The algorithm can be selected according to actual needs. When a key indicator (such as the growth rate of CE count) exceeds a dynamic threshold, an early warning is triggered.

[0054] In the above implementation, by proactively identifying and repairing high-risk memory regions through predictive models, the fault handling mode is upgraded from passive response to proactive prevention, thereby reducing the risk of business interruption caused by sudden memory failures and improving the overall availability of the system.

[0055] The aforementioned memory fault handling method includes: responding to a memory fault event, parsing the memory fault event, and determining the geometric physical address corresponding to the faulty memory; acquiring multi-dimensional features, classifying the memory fault event based on the multi-dimensional features, and determining the corresponding memory fault mode. The multi-dimensional features include one or more of time-dimensional features, spatial-dimensional features, and data-dimensional features; performing reverse address mapping based on the geometric physical address to determine the operating system page frame number set corresponding to the geometric physical address; sending a matching memory page offline instruction to the operating system based on the memory fault mode, controlling the operating system to execute the soft isolation operation corresponding to the operating system page frame number set, and receiving the soft isolation operation execution result fed back by the operating system; determining whether to trigger a hardware packaging and repair operation based on the soft isolation operation execution result and the remaining resource status after packaging and repair of the memory corresponding to the memory fault, and executing the packaging and repair operation in response to triggering the hardware packaging and repair operation. This application achieves permanent isolation of faulty memory at the hardware level by utilizing the factory redundancy of memory, and simultaneously isolates faulty memory at the software level by utilizing the virtual memory management mechanism of the operating system kernel for physical memory during operating system operation. Combining the advantages of software and hardware isolation of faulty memory, it realizes both software and hardware isolation. Collaborative memory fault classification and isolation repair effectively reduces fault downtime. Based on this, (1) improve system stability: physical row damage often leads to multiple OSPage errors, and the OS can only passively isolate them one by one, causing the system to repeatedly jitter or even crash. By distinguishing fault types through pattern recognition, preventive isolation is carried out for large-scale faults such as row failures, avoiding multiple downtimes caused by fault propagation; (2) optimize resource utilization: related solutions often consume PPR resources as soon as a hard error is discovered or can only replace the entire memory after the PPR resources are exhausted. This application establishes a software-first and then hardware-second filtering mechanism, and the faults successfully isolated by software are eliminated. (3) Achieve closed-loop management: Through the feedback mechanism from the OS to the firmware, the blind spot of no one taking over after the failure of soft isolation in the relevant scheme is solved, ensuring that every known memory risk point has a definite final disposal status (either isolated, repaired, or abandoned); (4) Business awareness capability: The refined processing of large pages and the negotiation of the timing of PPR restart merge multiple PPR requests into a single planned restart, maximizing the continuity and performance of key businesses and minimizing the impact of fault maintenance on upper-layer business applications.

[0056] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0057] It should be understood that, although Figures 2-5The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 2-5 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0058] In one embodiment, an electronic device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the electronic device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a memory fault handling method. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the device's casing, or an external keyboard, touchpad, or mouse.

[0059] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0060] Embodiments of this application provide an electronic device, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps in the memory fault handling method embodiments, including: S1: In response to a memory failure event, analyze the memory failure event and determine the geometric physical address corresponding to the faulty memory; S2: Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. S3: Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; S4: Based on the memory failure mode, send a matching memory page offline instruction to the operating system, control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and receive the soft isolation operation execution result fed back by the operating system; S5: Based on the execution result of the soft isolation operation and the remaining resource status of the memory after the memory fault is repaired, determine whether to trigger the hardware repair operation. If the hardware repair operation is triggered, execute the repair operation.

[0061] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the memory fault handling method embodiments at runtime, including: S1: In response to a memory failure event, analyze the memory failure event and determine the geometric physical address corresponding to the faulty memory; S2: Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. S3: Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; S4: Based on the memory failure mode, send a matching memory page offline instruction to the operating system, control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and receive the soft isolation operation execution result fed back by the operating system; S5: Based on the execution result of the soft isolation operation and the remaining resource status of the memory after the memory fault is repaired, determine whether to trigger the hardware repair operation. If the hardware repair operation is triggered, execute the repair operation.

[0062] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0063] Embodiments of this application also provide a computer program product, which includes a computer program. When executed by a processor, the computer program implements the steps in the memory fault handling method embodiments, including: S1: In response to a memory failure event, analyze the memory failure event and determine the geometric physical address corresponding to the faulty memory; S2: Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. S3: Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; S4: Based on the memory failure mode, send a matching memory page offline instruction to the operating system, control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and receive the soft isolation operation execution result fed back by the operating system; S5: Based on the execution result of the soft isolation operation and the remaining resource status of the memory after the memory fault is repaired, determine whether to trigger the hardware repair operation. If the hardware repair operation is triggered, execute the repair operation.

[0064] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps in the memory fault handling method embodiments, including: S1: In response to a memory failure event, analyze the memory failure event and determine the geometric physical address corresponding to the faulty memory; S2: Obtain multi-dimensional features, classify memory failure events based on multi-dimensional features, and determine the corresponding memory failure modes. Multi-dimensional features include one or more of the following: time dimension features, spatial dimension features, topological dimension features, and data dimension features. S3: Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; S4: Based on the memory failure mode, send a matching memory page offline instruction to the operating system, control the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and receive the soft isolation operation execution result fed back by the operating system; S5: Based on the execution result of the soft isolation operation and the remaining resource status of the memory after the memory fault is repaired, determine whether to trigger the hardware repair operation. If the hardware repair operation is triggered, execute the repair operation.

[0065] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0066] The foregoing has provided a detailed description of a memory fault handling method, apparatus, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A memory fault handling method, characterized in that, The method includes: In response to a memory failure event, the memory failure event is parsed to determine the geometric physical address corresponding to the faulty memory. Obtain multi-dimensional features, classify the memory failure events based on the multi-dimensional features, and determine the corresponding memory failure modes. The multi-dimensional features include one or more of time dimension features, spatial dimension features, topological dimension features, and data dimension features. Perform reverse address mapping based on the geometric physical address to determine the set of operating system page frame numbers corresponding to the geometric physical address; Based on the memory failure mode, a matching memory page offline instruction is sent to the operating system, controlling the operating system to execute the soft isolation operation corresponding to the set of operating system page frame numbers, and receiving the soft isolation operation execution result fed back by the operating system; Based on the execution result of the soft isolation operation and the remaining resource status of the memory after encapsulation and repair corresponding to the memory fault, determine whether to trigger the hardware encapsulation and repair operation. In response to triggering the hardware encapsulation and repair operation, execute the encapsulation and repair operation.

2. The memory fault handling method according to claim 1, characterized in that, The memory fault event is analyzed to determine the geometric physical address corresponding to the faulty memory, including: In response to a memory fault, read register information from the memory controller; The register information is parsed to obtain the system physical address corresponding to the memory fault; Based on the address decoding algorithm of the memory controller, the system physical address is converted into the geometric physical address.

3. The memory fault handling method according to claim 1, characterized in that, Obtaining multi-dimensional features includes: Based on the geometric physical address, the address distribution features of the memory fault event in the spatial dimension are extracted to obtain the spatial dimension features; Based on the occurrence time series of the memory fault events, the occurrence frequency features in the time dimension are extracted to obtain the time dimension features; Based on the geometric physical address, the correlation distribution features of the memory fault events in the topological dimension are extracted to obtain the topological dimension features; Based on the fault data corresponding to the memory fault event, fault bit pattern features are extracted in the data dimension to obtain the data dimension features.

4. The memory fault handling method according to claim 1, characterized in that, Based on the aforementioned multi-dimensional features, the memory failure events are classified, and the corresponding memory failure modes are determined, including: In response to the spatial dimension feature indicating that the fault is fixed at a single coordinate and the time dimension feature indicating that the fault occurs at the target geometric physical address more than a first preset threshold, the memory fault mode is determined to be a single-point fixed mode. In response to the spatial dimension feature showing that the fault is distributed in the target physical row address and the number of physical column addresses within the target physical row address is greater than a second preset threshold, the memory fault mode is determined to be a row failure mode. In response to the spatial dimension feature showing that the fault is distributed in the target physical column address and the number of distributed physical row addresses is greater than a third preset threshold, the memory fault mode is determined to be a column failure mode. If the time dimension feature shows that the number of faults occurring per unit time is greater than the fourth preset threshold and the growth trend conforms to an exponential law, the memory fault mode is determined to be an error storm mode. In response to the fact that the XOR operation result of multiple fault data displayed by the data dimension feature all points to the target data pin, the memory fault mode is determined to be a data pin failure mode. In response to the topology dimension features showing that different geometric physical addresses point to fixed data bits after data bit XOR analysis and that there are associated errors in the local coupling area of ​​the same memory column or associated errors on the same channel bus, the memory fault mode is determined to be either data bit mode or link contact abnormal mode.

5. The memory fault handling method according to claim 4, characterized in that, Performing reverse address mapping based on the geometric physical address determines the set of operating system page frame numbers corresponding to the geometric physical address, including: Based on the row address information in the geometric physical address, determine the physical row address where the memory fault occurs; Based on the physical row address and system memory address mapping table, the range of physical addresses covered by the physical row address is determined; The physical address range is converted into the corresponding operating system page frame number to generate a set of page frame numbers to be isolated.

6. The memory fault handling method according to claim 5, characterized in that, Based on the aforementioned memory failure mode, sending a matching memory page offline instruction to the operating system includes: In response to the memory failure mode being row failure mode, a batch offline instruction is generated based on the set of page frame numbers to be isolated; In response to the memory failure mode being single-point fixed mode, a single-point offline instruction is generated based on the target page frame number corresponding to the geometric physical address. In response to the memory failure mode being error storm mode, a shutdown instruction carrying an emergency flag is generated based on the set of page frame numbers to be isolated.

7. The memory fault handling method according to claim 6, characterized in that, Controlling the operating system to execute the soft isolation operation corresponding to the set of page frame numbers of the operating system, and receiving the soft isolation operation execution result fed back by the operating system, includes: In response to the memory page offline instruction, the set of operating system page frame numbers is parsed to obtain the parsing result; Based on the parsing results, the valid data within multiple page frames in the operating system page frame number set are migrated to the healthy memory region; In response to the completion of the migration, the page frame that has been migrated is removed from the memory allocation list, the soft isolation operation execution result of the page frame is recorded, and the soft isolation operation execution result is received.

8. The memory fault handling method according to claim 1, characterized in that, Based on the results of the soft isolation operation and the state of the remaining resources after the memory fault is repaired, determining whether to trigger the hardware repair operation includes: In response to the successful execution of the soft isolation, the hardware encapsulation repair operation request for the geometric physical address is suppressed, and the geometric physical address is marked as a successful soft isolation state. In response to the failure of the soft isolation execution, the encapsulated repair resource status register in the memory is read to obtain the proportion of the currently remaining available repair lines; Based on the proportion of the remaining available repair lines, determine whether to add the geometric physical address to the repair queue to trigger the hardware packaging repair operation.

9. The memory fault handling method according to claim 8, characterized in that, The method further includes: The admission threshold for repair after encapsulation is dynamically adjusted based on the proportion of the remaining available repair lines. If the proportion of remaining available repair lines is greater than a first threshold, it is determined that the resources are sufficient and a lenient repair strategy is adopted. If the proportion of the remaining available repair lines is less than the second threshold, it is determined to be a resource depletion state, and a strict retention strategy is adopted. In response to the lenient repair strategy, multiple geometric physical addresses whose soft isolation execution results are failures are added to the repair queue; In response to the stringent retention policy, the geometric physical address corresponding to the failure mode of the soft isolation execution is added to the repair queue.

10. The memory fault handling method according to claim 1, characterized in that, In response to triggering a post-packaging repair operation, the post-packaging repair operation includes: Write the geometric physical address that triggers the repair operation after hardware packaging into the repair queue in non-volatile memory; In response to the operating system entering a preset maintenance window or undergoing a restart, the queue to be repaired is read through the basic input / output system; For the geometric physical addresses in the queue to be repaired, a hardware-encapsulated repair instruction is sent to the memory module to replace the faulty line with the redundant line reserved inside the memory chip, and the hardware repair execution status of the geometric physical address is recorded.

11. The memory fault handling method according to claim 1, characterized in that, After performing the post-packaging repair operation in response to triggering the hardware packaging repair operation, the method further includes: For the memory region where the hardware packaging repair operation was performed, a targeted stress test program was started; Monitor whether memory failures occur again during stress testing; If no memory failure occurs again, the repair is deemed successful, the fault record of the geometric physical address is cleared, and the memory region is allowed to be put back into use. If a memory failure occurs again, the repair is deemed to have failed, and the memory module that underwent the hardware-encapsulated repair operation is marked as permanently retired.

12. The memory fault handling method according to claim 11, characterized in that, The method further includes: In response to the hardware-after-packaging repair operation, the memory module is marked as permanently retired, and the identification information of the memory module is written into the permanent retirement list in the basic input / output system. In response to restarting the operating system, the basic input / output system skips the initialization of the memory module and sends a memory module replacement alarm message to the operation and maintenance system.

13. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the method as claimed in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the memory fault handling method as described in any one of claims 1 to 12.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the memory fault handling method as described in any one of claims 1 to 12.

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