Display panel, preparation method thereof, display module and electronic device

Abstract

The application provides a display panel, a preparation method thereof, a display module and an electronic device. The display panel comprises adjacent first and second sub-pixel regions arranged along a first direction, a substrate and a planarization layer on the substrate. The planarization layer is provided with a first groove on a side away from the substrate along a second direction. The first groove is in a non-sub-pixel region. The display panel further comprises a first sub-pixel definition layer and a second sub-pixel definition layer. An inorganic isolation layer is arranged between the planarization layer and the first sub-pixel definition layer. A projection of the inorganic isolation layer along the second direction partially overlaps a bottom wall of the first groove. The display panel further comprises a second groove arranged on the first sub-pixel definition layer or the second sub-pixel definition layer. By arranging the first and second grooves between the first and second sub-pixel regions, the transverse crosstalk current in the charge generation layer can be reduced, the crosstalk resistance of the display panel can be improved, and the ghosting problem of the display panel can be improved.

Description

[0001] This application claims priority to Chinese Patent Application No. 202510312203.2, filed on March 14, 2025, with the State Intellectual Property Office of China, entitled “Display Panel and Method for Manufacturing the Same Thereof, Display Module and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more specifically, to a display panel and its manufacturing method, a display module and an electronic device. Background Technology

[0003] In display panel manufacturing, the vapor-deposited material of the charge generation layer (CGL) is a common layer, exhibiting strong conductivity not only vertically but also horizontally. This can cause surrounding pixels of different colors to be illuminated by lateral current when a pixel of a certain color is lit, leading to worsened low-grayscale crosstalk and affecting color accuracy. Furthermore, the increased capacitance of the upper and lower light-emitting units in the display panel, coupled with their differing capacitances, results in unstable first-frame emission, exacerbating motion blur in low-brightness, low-grayscale display scenarios. Therefore, a display panel with high first-frame emission stability and the ability to mitigate motion blur is needed. Summary of the Invention

[0004] This application provides a display panel and its manufacturing method, a display module and an electronic device. The display panel can improve the ghosting problem and has high first-frame light emission stability.

[0005] In a first aspect, a display panel is provided, the display panel comprising: adjacent first sub-pixel regions and second sub-pixel regions arranged along a first direction, the first direction being the direction of the plane on which the display panel is located; a substrate; a planarization layer located on the substrate, the planarization layer having a first groove disposed on a side away from the substrate along a second direction, the first groove being located in a non-sub-pixel region between the first sub-pixel region and the second sub-pixel region, the second direction being a direction perpendicular to the plane on which the display panel is located; a first sub-pixel defining layer and a second sub-pixel defining layer located in the non-sub-pixel region on the side of the planarization layer away from the substrate, the first sub-pixel defining layer and the second sub-pixel defining layer being respectively located on opposite sides of the first groove, the first sub-pixel defining layer being close to the first sub-pixel region, and the second sub-pixel defining layer being close to the second sub-pixel region; an inorganic isolation layer disposed between the first sub-pixel defining layer and the planarization layer, the projection of the inorganic isolation layer on the substrate overlapping the projection of the bottom wall of the first groove on the substrate; a second groove disposed on the side of the first sub-pixel defining layer away from the substrate, and / or a third groove disposed on the side of the second sub-pixel defining layer away from the substrate.

[0006] Based on the above technical solution, by setting a first groove, a second groove and / or a third groove between the first sub-pixel region and the second sub-pixel region, the first groove and the inorganic isolation layer can block the connection of the charge generation layer between the two sub-pixel regions, and the second groove and / or the third groove can reduce the lateral crosstalk current in the charge generation layer, thereby improving the anti-crosstalk capability of the display panel and improving the ghosting problem of the display panel.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the second groove is continuously disposed on the first sub-pixel definition layer and / or the third groove is continuously disposed on the second sub-pixel definition layer.

[0008] Based on the above technical solution, the continuously arranged second and / or third grooves can increase the lateral area of ​​the charge generation layer, increase the lateral resistance of the charge generation layer, reduce the lateral crosstalk current, and improve the crosstalk effect.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the second groove is discontinuously disposed on the first sub-pixel definition layer and / or the third groove is discontinuously disposed on the second sub-pixel definition layer.

[0010] Based on the above technical solution, other devices, such as support pillars, can be set at the positions where the second and / or third grooves are not provided on the display panel. This can improve the crosstalk effect while making more effective use of the space of the non-sub-pixel area of ​​the display panel, thus improving the flexibility of the display panel design.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the second groove includes a discontinuity region located at a corner of the first sub-pixel region.

[0012] Based on the above technical solution, the discontinuity area located at the corner of the first sub-pixel area can be used to set other devices, such as support pillars, and setting the discontinuity area at the corner of the first sub-pixel area can make more efficient use of the space of the non-sub-pixel area of ​​the display panel.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the third groove includes a discontinuity region located at a corner of the second sub-pixel region.

[0014] Based on the above technical solution, the discontinuity area located at the corner of the second sub-pixel region can be used to set other devices, such as support pillars, and setting the discontinuity area at the corner of the second sub-pixel region can make more efficient use of the space of the non-sub-pixel area of ​​the display panel.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, along the first direction, the distance between the first sub-pixel region and the second sub-pixel region is greater than or equal to 10 micrometers and less than or equal to 30 micrometers.

[0016] Based on the above technical solution, by limiting the distance between the first sub-pixel region and the second sub-pixel region, it is convenient for production. In other words, the range of the distance between the first sub-pixel region and the second sub-pixel region can be within the range of mass production.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, along the first direction, the difference between the size of the first groove and the size of the projection of the inorganic isolation layer along the second direction onto the bottom wall of the first groove is greater than or equal to 3 micrometers and less than or equal to 24 micrometers.

[0018] Based on the above technical solution, by limiting the range of the difference between the size of the first groove and the size of the projection of the inorganic isolation layer along the second direction on the bottom wall of the first groove, it is convenient to manufacture. In other words, the range of the difference between the size of the first groove and the size of the projection of the inorganic isolation layer along the second direction on the bottom wall of the first groove can be the range of mass production.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, along the first direction, the size of the second groove is greater than or equal to 1 micrometer and less than or equal to 20 micrometers; and / or along the first direction, the size of the third groove is greater than or equal to 1 micrometer and less than or equal to 20 micrometers.

[0020] Based on the above technical solution, by limiting the size range of the first groove and the second groove, it is convenient to manufacture. In other words, the size range of the first groove and the second groove can be the range of mass production.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the distance between the first sub-pixel region and the end of the inorganic isolation layer away from the first sub-pixel region along the first direction is greater than or equal to 3 micrometers and less than or equal to 24 micrometers.

[0022] Based on the above technical solution, by limiting the distance range between the first sub-pixel region and the end of the inorganic isolation layer away from the first sub-pixel region along the first direction, it is convenient for manufacturing. In other words, the distance range between the first sub-pixel region and the end of the inorganic isolation layer away from the first sub-pixel region along the first direction can be the range of mass production.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, along the first direction, the distance between the end of the first groove near the second sub-pixel region and the second sub-pixel region is greater than or equal to 3 micrometers and less than or equal to 24 micrometers.

[0024] Based on the above technical solution, by limiting the distance range between the end of the first groove near the second sub-pixel region and the second sub-pixel region, it is convenient for manufacturing. In other words, the distance range between the end of the first groove near the second sub-pixel region and the second sub-pixel region can be within the range of mass production.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, an inorganic isolation layer is provided between the second sub-pixel definition layer and the planarization layer.

[0026] In conjunction with the first aspect, in some implementations of the first aspect, the anode is located on the side of the inorganic isolation layer away from the substrate, and the anode is located in the first sub-pixel region and the second sub-pixel region respectively; a common layer is located on the side of the first sub-pixel definition layer and the anode away from the substrate, and on the side of the second sub-pixel definition layer and the anode away from the substrate respectively, the common layer being used to transport charge carriers; the cathode is located on the side of the common layer away from the substrate; along the second direction, in the non-sub-pixel region near the first sub-pixel region, the projections of the anode, the common layer and the cathode fall within the inorganic isolation layer.

[0027] Based on the above technical solution, other devices in the display panel are arranged above the inorganic isolation layer, and the projections of the anode, common layer and cathode fall into the inorganic isolation layer along the second direction, blocking the connection between the common layer and other common layers in the adjacent sub-pixel area, avoiding the transmission of lateral current in the common layer, thereby improving the crosstalk effect.

[0028] In conjunction with the first aspect, in some implementations of the first aspect, the common layer includes a first light-emitting stack, a charge-generating layer and a second light-emitting stack stacked along the second direction, wherein the first light-emitting stack includes a first hole control layer, a first light-emitting layer and a first electron control layer stacked along the second direction and on the side away from the substrate, and the second light-emitting stack includes a second hole control layer, a second light-emitting layer and a second electron control layer stacked along the second direction and on the side away from the substrate.

[0029] Based on the above technical solution, a first light-emitting stack and a second light-emitting stack are provided in the common layer, so that the light-emitting stacks in the display device are connected in series, thereby improving the current efficiency of the display panel.

[0030] In conjunction with the first aspect, in some implementations of the first aspect, the material of the inorganic isolation layer includes any one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or indium tin oxide.

[0031] In a second aspect, a display panel is provided, the display panel comprising: adjacent first sub-pixel regions and second sub-pixel regions arranged along a first direction, the first direction being the direction of the plane on which the display panel is located; a substrate; a planarization layer located on the substrate; a third sub-pixel definition layer located in a non-sub-pixel region on the side of the planarization layer away from the substrate, the non-sub-pixel region being located between the first sub-pixel regions and the second sub-pixel regions, the third sub-pixel definition layer comprising: a fourth groove located on the side of the third sub-pixel definition layer away from the substrate; the fourth groove comprising a first bottom wall, a first side wall and a second side wall opposite to each other in the first direction, the angle between the first bottom wall and the first side wall being α, and the angle between the first bottom wall and the second side wall being β, wherein α and β are different.

[0032] In some possible implementations, α and β are both greater than or equal to 90 degrees.

[0033] According to the embodiments provided in this application, since there is an angle between the first sidewall and the first bottom wall, and an angle between the second sidewall and the first bottom wall, after the charge generation layer is deposited in the fourth groove, the thickness of the charge generation layer can be reduced, the resistance of the charge generation layer can be increased, the lateral crosstalk current can be reduced, and the crosstalk effect can be improved.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the fourth groove is closer to the first sub-pixel region than the second sub-pixel region.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the fourth groove is closer to the second sub-pixel region than the first sub-pixel region.

[0036] In conjunction with the second aspect, in some implementations of the second aspect, the fourth groove includes a first sub-groove and a second sub-groove, the first sub-groove being close to the first sub-pixel region and the second sub-groove being close to the second sub-pixel region.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, the angle between the first bottom wall and the first side wall of the first sub-groove is α1, and the angle between the first bottom wall and the second side wall of the first sub-groove is β1, wherein α1 and β1 are different; the angle between the first bottom wall and the first side wall of the second sub-groove is α2, and the angle between the first bottom wall and the second side wall of the second sub-groove is β2, wherein α2 and β2 are different.

[0038] In conjunction with the second aspect, in some implementations of the second aspect, the display panel further includes: a fifth recess, the fifth recess being located on the side of the third sub-pixel definition layer away from the substrate, the fifth recess being located between the first sub-recess and the second sub-recess.

[0039] In conjunction with the second aspect, in some implementations of the second aspect, the second sidewall of the first sub-groove is closer to the geometric center of the third sub-pixel definition layer relative to the first sidewall of the first sub-groove, α1 > β1; the second sidewall of the second sub-groove is closer to the geometric center of the third sub-pixel definition layer relative to the first sidewall of the second sub-groove, α2 > β2.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the second sidewall is closer to the geometric center of the third sub-pixel definition layer than the first sidewall, where α > β.

[0041] In some possible implementations, α-β > 10°, and further, 120° ≤ α ≤ 140°, 90° ≤ β ≤ 110°. Since α > β, after the charge generation layer is deposited on the fourth groove, the thickness of the charge generation layer closer to the sub-pixel region is thinner than that farther from the sub-pixel region, and the resistance of the charge generation layer closer to the sub-pixel region is higher than that farther from the sub-pixel region. The lateral crosstalk current reduction effect in the charge generation layer closer to the sub-pixel region is better, which can further improve the crosstalk effect.

[0042] In conjunction with the second aspect, in some implementations of the second aspect, along the second direction, the projected area of ​​the first sidewall on the planarization layer is greater than the projected area of ​​the second sidewall on the planarization layer.

[0043] According to the embodiments provided in this application, since the projected area of ​​the first sidewall on the planarization layer is larger than the projected area of ​​the second sidewall on the planarization layer, the thickness of the charge generation layer at the first sidewall is thinner, which is beneficial to increase the resistance of the charge generation layer near the sub-pixel region, reduce the lateral crosstalk current, and improve the crosstalk effect.

[0044] In conjunction with the second aspect, in some implementations of the second aspect, the display panel further includes: an anode located on the side of the planarization layer away from the substrate, and the anode being located in the first sub-pixel region and the second sub-pixel region respectively; a common layer located on the side of the third sub-pixel definition layer and the anode away from the substrate respectively, the common layer being used to transport charge carriers; and a cathode located on the side of the common layer away from the substrate.

[0045] In conjunction with the second aspect, in some implementations of the second aspect, the common layer includes a third light-emitting stack and a charge-generating layer stacked along the second direction. In the non-sub-pixel region, the third light-emitting stack is located above the third sub-pixel defining layer, and the second direction is perpendicular to the plane where the display panel is located. Along the second direction, the projection of the third light-emitting stack on the third sub-pixel defining layer does not overlap with the fourth groove, while the projection of the charge-generating layer on the third sub-pixel defining layer overlaps with the fourth groove.

[0046] According to the embodiments provided in this application, since the third light-emitting stack and the fourth groove do not overlap, the angle between the first sidewall and the first bottom wall will not be affected, the thickness of the charge generation layer deposited on the first sidewall will not be affected, the resistance of the charge generation layer is high, which can reduce the transverse current in the charge generation layer and improve the crosstalk effect.

[0047] In conjunction with the second aspect, in some implementations of the second aspect, the common layer further includes a fourth light-emitting stack near the first sub-pixel region and a fifth light-emitting stack near the second sub-pixel region; in the non-sub-pixel region, the fourth light-emitting stack and the fifth light-emitting stack are located above the charge-generating layer; along the second direction, the projections of the fourth light-emitting stack on the third sub-pixel defining layer and the projections of the fifth light-emitting stack on the third sub-pixel defining layer overlap and respectively overlap with the fourth groove.

[0048] According to the embodiments provided in this application, the projection of the fourth light-emitting stack overlaps with the fourth groove. The fourth light-emitting stack has a large thickness at the first sidewall and the second sidewall, which can adjust the capacitance of the fourth light-emitting stack. Furthermore, the capacitance ratio between the third light-emitting stack and the fourth light-emitting stack can be adjusted to improve the light emission stability of the first frame displayed on the display panel.

[0049] According to the embodiments provided in this application, the fourth and fifth light-emitting stacks can completely cover the charge generation layer after deposition, so that after the cathode is deposited on the common layer, there will be no short circuit between the cathode and the charge generation layer, avoiding the situation where different sub-pixel areas are lit at the same time, improving the yield of the display panel, avoiding the ghosting problem of the display panel, and improving the display effect of the display panel.

[0050] Thirdly, a display module is provided, the display module including a cover plate and a display panel as described in the first aspect and any implementation thereof, or including a cover plate and a display panel as described in the second aspect and any implementation thereof.

[0051] In conjunction with the third aspect, in some implementations of the third aspect, the display module further includes a polarizer located between the cover plate and the display panel.

[0052] Fourthly, an electronic device is provided, comprising: a circuit board assembly and a display module as described in the third aspect and any implementation thereof, wherein the circuit board assembly is electrically connected to the display module.

[0053] Fifthly, a method for manufacturing a display panel is provided, the display panel including a first sub-pixel region and a second sub-pixel region arranged along a first direction, the first direction being the direction of the plane on which the display panel is located; the method includes: setting a substrate and a planarization layer on the substrate; setting a first groove on a side of the planarization layer away from the substrate along a second direction, the first groove being located in a non-sub-pixel region between the first sub-pixel region and the second sub-pixel region, the second direction being a direction perpendicular to the plane on which the display panel is located; setting a first sub-pixel definition layer and a second sub-pixel definition layer in the non-sub-pixel region on the side of the planarization layer away from the substrate. A pixel definition layer, wherein the first sub-pixel definition layer and the second sub-pixel definition layer are respectively located on both sides of the first groove, the first sub-pixel definition layer being close to the first sub-pixel region and the second sub-pixel definition layer being close to the second sub-pixel region; an inorganic isolation layer is provided between the first sub-pixel definition layer and the planarization layer, the projection of the inorganic isolation layer on the substrate overlapping the projection of the bottom wall of the first groove on the substrate; a second groove is provided on the side of the first sub-pixel definition layer away from the substrate, and / or a third groove is provided on the side of the second sub-pixel definition layer away from the substrate.

[0054] Based on the above technical solution, by setting a first groove, a second groove and / or a third groove between the first sub-pixel region and the second sub-pixel region, the first groove and the inorganic isolation layer can block the connection of the charge generation layer between the two sub-pixel regions, and the second groove and / or the third groove can reduce the lateral crosstalk current in the charge generation layer, thereby improving the anti-crosstalk capability of the display panel and improving the ghosting problem of the display panel.

[0055] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the second groove is continuously provided on the first sub-pixel definition layer and / or the third groove is continuously provided on the second sub-pixel definition layer.

[0056] Based on the above technical solution, the continuously arranged second and / or third grooves can increase the lateral area of ​​the charge generation layer, increase the lateral resistance of the charge generation layer, reduce the lateral crosstalk current, and improve the crosstalk effect.

[0057] In conjunction with the fifth aspect, in some implementations of the fifth aspect, the second groove is discontinuously provided on the first sub-pixel definition layer and / or the third groove is discontinuously provided on the second sub-pixel definition layer. Based on the above technical solution, other devices, such as support pillars, can be provided at locations on the display panel where the second groove and / or the third groove are not provided. This allows for more effective utilization of the space in the non-sub-pixel areas of the display panel while improving crosstalk effects, thus increasing the flexibility in display panel design.

[0058] A sixth aspect provides a method for manufacturing a display panel, the display panel including a first sub-pixel region and a second sub-pixel region arranged along a first direction, the first direction being the direction of the plane on which the display panel is located; the method includes: setting a substrate and a planarization layer on the substrate, setting a third sub-pixel definition layer in a non-sub-pixel region on a side of the planarization layer away from the substrate, and setting a fourth groove, the fourth groove being disposed on the side of the third sub-pixel definition layer away from the substrate, wherein the fourth groove includes a first bottom wall, a first side wall and a second side wall opposite to each other in the first direction, the angle between the first bottom wall and the first side wall being α, and the angle between the first bottom wall and the second side wall being β, wherein α and β are different.

[0059] In conjunction with the sixth aspect, in some implementations of the sixth aspect, the fourth groove includes a first sub-groove and a second sub-groove, and the method further includes: setting the first sub-groove and the second sub-groove, wherein the first sub-groove is close to the first sub-pixel region and the second sub-groove is close to the second sub-pixel region. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this application.

[0061] Figure 2 This is a schematic diagram of the structure of a display module provided in an embodiment of this application.

[0062] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0063] Figure 4a This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0064] Figure 4b This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0065] Figure 4c This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0066] Figure 5 yes Figure 4a Cross-sectional view along the AA direction.

[0067] Figure 6a This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0068] Figure 6b This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0069] Figure 6c This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0070] Figure 7 yes Figure 6a Cross-sectional view along the DD direction.

[0071] Figure 8a This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0072] Figure 8b This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0073] Figure 8c This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0074] Figure 9 yes Figure 8a Cross-sectional view along the EE direction.

[0075] Figure 10a This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0076] Figure 10b This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0077] Figure 11a This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0078] Figure 11b This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0079] Figure 12 This is a schematic diagram of the manufacturing process of the display panel provided in the embodiments of this application.

[0080] Figure 13 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0081] Figure 14This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0082] Figure 15 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0083] Figure 16 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0084] Figure 17 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0085] Figure 18 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0086] Figure 19 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0087] Figure 20 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0088] Figure 21 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0089] Figure 22 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0090] Figure 23 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0091] Figure 24 This is a schematic diagram of the manufacturing process of a display panel provided in an embodiment of this application.

[0092] Figure 25 This is a schematic diagram of the manufacturing process of a display panel provided in an embodiment of this application.

[0093] Figure 26 This is a schematic diagram of the manufacturing process of a display panel provided in an embodiment of this application. Detailed Implementation

[0094] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0095] It should be noted that in the embodiments of this application, the terms "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the embodiments of this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The sequence numbers of the processes below do not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0096] In the description of the embodiments of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. "Vertical" is not strictly vertical, but within the allowable error range. "Parallel" is not strictly parallel, but within the allowable error range.

[0097] In this embodiment, references to "one embodiment" or "some embodiments" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. In this application, words such as "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the embodiments of this application, descriptions such as "when," "in the case of," "if," and "if" all refer to the device taking corresponding actions under certain objective circumstances, not to limiting the time, nor to requiring the device to perform a judgment action during implementation, nor implying any other limitations.

[0098] The term "and / or" in the embodiments of this application is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in the embodiments of this application generally indicates that the preceding and following related objects have an "or" relationship.

[0099] Furthermore, it should be noted that, in the description of the embodiments of this application, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0100] Figure 1 This is a schematic diagram of an electronic device 10 provided in an embodiment of this application.

[0101] The electronic device 10 may include a display module 20, a housing 30, a battery assembly 40, and a circuit board assembly 50. The display module 20 is used to implement the display function of the electronic device 10; for example, the display module 20 can display images, text, and other information. The circuit board assembly 50 may include one or more electronic components, such as one or more processors, one or more antennas, a mobile communication module, or a wireless communication module. The battery assembly 40 can be electrically connected to both the display module 20 and the circuit board assembly 50, and is used to power both the circuit board assembly 50 and the display module 20.

[0102] In some examples, the display module 20 may be mounted on the housing 30, and a receiving space 60 may be formed between the display module 20 and the housing 30, in which the battery assembly 40 and the circuit board assembly 50 of the electronic device 10 may be housed. Exemplarily, the circuit board assembly 50 may be located close to the display module 20, and the battery assembly 40 may be located on the side of the circuit board assembly 50 away from the display module 20; or, the battery assembly 40 may be positioned close to the housing 30, and the circuit board assembly 50 may be positioned close to the display module 20.

[0103] Figure 2 This is a schematic diagram of the structure of a display module 20 provided in an embodiment of this application.

[0104] In some examples, the display module 20 may include a cover plate 21, a polarizer 22, and a display panel 100, wherein the cover plate 21 and the display panel 100 are located on opposite sides of the polarizer 22, or in other words, the polarizer 22 is located between the cover plate 21 and the display panel 100.

[0105] In some examples, the cover plate 21 can be used to protect the display module 20 from the influence of the external environment, such as dust, moisture, and physical damage. In some examples, in order to improve the display effect of the display module 20 and reduce the adverse effects of the cover plate 21 on the display effect of the display module 20, the cover plate 21 is composed of a material with good transparency.

[0106] For example, the cover plate 21 may be composed of chemically strengthened glass or physically strengthened glass to give the cover plate 21 high impact resistance and abrasion resistance. For example, the cover plate 21 may also be composed of a thin film material to make the cover plate 21 flexible or foldable.

[0107] Exemplarily, the cover plate 21 may also include one or more functional coatings, such as an anti-reflective coating, an anti-fingerprint coating, a hardening coating, or an anti-blue light coating. The anti-reflective coating can reduce the reflection of ambient light on the surface of the cover plate 21, thereby improving the visibility of the display module 20. The anti-fingerprint coating can reduce the accumulation of fingerprints and other stains on the surface of the cover plate 21. The hardening coating can increase the hardness of the surface of the cover plate 21, improving its scratch resistance. The anti-blue light coating can absorb some of the blue light emitted by the display panel 100, thereby reducing the harmful effects of blue light on the eyes.

[0108] In some examples, a polarizer (POL) 22 can be used to reduce the reflection of ambient light on the surface of the display module 20, thereby improving the contrast and readability of the display module 20 in bright light environments.

[0109] For example, the polarizer 22 may be composed of one or more thin film materials. For instance, the polarizer 22 may be composed of a polyvinyl alcohol film and / or a polyester film. The polyvinyl alcohol film can be used to adjust the propagation mode of ambient light in the display module 20, and the polyester film can be used to protect the display module 20.

[0110] In some examples, the display module 20 can also adopt a polarizer-free structure, that is, the polarizer 22 can be replaced by a color filter and a black matrix, thereby forming a color on encapsulation (COE) architecture. The black matrix is ​​positioned between the color filters, and the color filters can correspond to the anode layer in the display panel 100, while the black matrix can correspond to the pixel definition layer in the display panel 100.

[0111] Color filters solve the problems of reflection and light transmission. When external light enters the screen, unwanted light is absorbed by the black matrix, while the remaining light passes through the RGB pixels in the color filter. The RGB pixels then display colors and reflect light. During the reflection process, some light is blocked by the black matrix, while the rest is absorbed by the color filter. Polarizer-free technology can achieve lower screen power consumption at the same display brightness, or higher screen brightness at the same power consumption. Furthermore, since color filters are typically only about 10 micrometers thick, they can significantly reduce screen thickness compared to polarizers, extending the lifespan of foldable screens and reducing the cost of polarizers. In other words, the COE architecture light-gathering solution leads to a decrease in the frontal color gamut, but the COE architecture can improve the color gamut, achieving product goals. Additionally, the COE architecture can convert reflected light incident on the screen into scattered light, thus locking it within the screen and reducing reflectivity.

[0112] In some examples, the display module 20 may also include an adhesive layer 23 located between the polarizer 22 and the cover plate 21, which may be used to fix the polarizer 22 and the cover plate 21 relative to each other. For example, the side of the adhesive layer 23 facing the cover plate 21 may be bonded to the cover plate 21, and the side of the adhesive layer 23 facing the polarizer 22 may be bonded to the polarizer 22, thereby fixing the cover plate 21 and the polarizer 22 relative to each other.

[0113] In some examples, the display panel 100 can be used to implement the display function of the display module 20. Exemplarily, the display panel 100 may include a display module and a control module, wherein the display module is used to display images and / or text; the control module is electrically connected to the display module and is used to control the display content and / or display mode of the display module.

[0114] It should be understood that when the display module 20 is roughly circular, the thickness direction of the display panel 100 can also be understood as the axial direction of the display module 20 (the direction parallel to the axis OO in the figure).

[0115] It should also be understood that the display panel 100 may be, for example, an organic light-emitting diode (OLED) display panel, and may also be a quantum dot light-emitting diode (QLED) or a micron light-emitting diode (micro LED). Display panels with structures such as emitting diodes (micro-LEDs), but not limited to these.

[0116] To facilitate understanding, the technical terms used in this application will be explained and described below.

[0117] Figure 3 This is a schematic diagram of the structure of a display panel 100 provided in an embodiment of this application.

[0118] In some possible implementations, the display panel 100 may include a substrate 110, a planarization layer (PLN) 120, a display element layer 200, and an encapsulation layer 130 stacked together.

[0119] The substrate 110 can be a thin-film transistor (TFT) substrate, which may include a base and TFTs disposed on the base. The TFT may include an active layer, a source, a drain, a gate insulating layer, and a gate. The materials of the active layer of the TFT include, but are not limited to, low-temperature polysilicon (LTPS), oxides, amorphous silicon (a-Si), low-temperature polycrystalline oxide (LTPO), and organic materials. The substrate serves as the supporting structure for the display panel 100, and the planarization layer 120, display element layer 200, and encapsulation layer 130 can all be supported on the substrate.

[0120] In some possible implementations, the substrate can be a rigid substrate. Exemplarily, the substrate can be any of a glass substrate, a quartz substrate, or a ceramic substrate. For example, a glass substrate can be composed of soda-lime glass and / or borosilicate glass. These types of substrates can possess good mechanical strength and good thermal stability.

[0121] In some possible implementations, the substrate can be a flexible substrate. Exemplarily, the substrate can be composed of polymeric materials, such as one or more of the following: polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethylene naphthalate (PEN), or cycloolefin copolymer (COC). These polymeric materials can possess good optical and mechanical properties, enabling the substrate to bend and deform, thereby allowing the display panel 100 to meet the requirements of foldable electronic devices (such as foldable mobile phones).

[0122] In some embodiments, the substrate may also be composed of the inorganic material constituting the rigid substrate and the polymer material constituting the flexible substrate, and this application does not limit this.

[0123] Exemplarily, the substrate may have a multilayer structure. For example, the substrate may include a first synthetic resin layer, multiple or single inorganic layers, and a second synthetic resin layer disposed on the multiple or single inorganic layers. Each of the first and second synthetic resin layers may contain a polyimide resin.

[0124] The planarization layer 120 is located on the substrate 110, and the planarization layer 120 is mainly used to form a flat surface on the surface of the substrate 110. The materials of the planarization layer 120 include, but are not limited to, organic polymers such as polyimide, siloxane, polyamide, and acrylic.

[0125] The display element layer 200 can be disposed between the planarization layer 120 and the encapsulation layer 130. In some examples, the display element layer 200 may include an anode 210, a cathode 220, a common layer 230, and a pixel definition layer (PDL) 240. The anode 210 and the pixel definition layer 240 are located on the side of the planarization layer 120 away from the substrate 110. The pixel definition layer 240 (also called a pixel defining layer) can be used to define the boundary of each pixel in the display panel 100, reducing the probability of light-emitting materials diffusing into each other in different pixel areas. The common layer 230 can be located on the side of the anode 210 and the pixel definition layer 240 away from the substrate 110. The cathode 220 can be located on the side of the common layer 230 away from the substrate 110.

[0126] The encapsulation layer 130 can be disposed on the side of the display element layer 200 away from the substrate 110. More specifically, the encapsulation layer 130 can be disposed on the side of the cathode 220 away from the substrate 110. The encapsulation layer 130 can employ thin film encapsulation (TFE), which can seal the display element layer 200 to prevent moisture, oxygen, and foreign matter such as dust particles from entering the display element layer 200. The encapsulation layer 130 can have a certain mechanical strength, thereby improving the scratch resistance, abrasion resistance, and other physical properties of the display panel 100 to a certain extent.

[0127] In some examples, the encapsulation layer 130 may be composed of inorganic materials such as glass and ceramics, which possess good mechanical properties. In this scenario, the encapsulation layer 130 may also be referred to as a rigid encapsulation layer, and the glass, ceramics, and other materials constituting the encapsulation layer may also be referred to as rigid encapsulation materials. Exemplarily, the rigid encapsulation material may include one or more of the following: inorganic materials, metals, metal oxides, or polymer composite materials, etc.

[0128] In some examples, the encapsulation layer 130 may be composed of organic materials such as polymers, which can have good flexibility and bend or deform under stress without being damaged. In this scenario, the encapsulation layer 130 may also be referred to as a flexible encapsulation layer, and the polymer material constituting the encapsulation layer may also be referred to as a flexible encapsulation material. Exemplarily, the flexible encapsulation material may include one or more of the following: polyimide, polyethylene terephthalate, acrylic resin, or polycarbonate, etc.

[0129] In some examples, the encapsulation layer 130 may also be composed of both the inorganic and organic materials mentioned above, and this application does not impose any restrictions on this.

[0130] For example, refer to Figure 3 The encapsulation layer 130 may include multiple thin-film encapsulation layers. The encapsulation layer 130 may include a first inorganic encapsulation layer 131, an organic encapsulation layer 132 disposed on the first inorganic encapsulation layer 131, and a second inorganic encapsulation layer 133 disposed on the organic encapsulation layer 132. The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 protect the display element layer 200 from moisture / oxygen, while the organic encapsulation layer 132 protects the display element layer 200 from foreign matter such as dust particles.

[0131] For example, such as Figure 3 As shown, multiple sub-pixel regions may include sub-pixel region A and sub-pixel region B. The emissive layers in sub-pixel region A and sub-pixel region B can emit light of different colors or wavelengths. The colors of the light emitted from the multiple sub-pixel regions can include the three primary colors. For example, sub-pixel region A / sub-pixel region B can be a red sub-pixel region, a green sub-pixel region, or a blue sub-pixel region. As another example, sub-pixel region A / sub-pixel region B can be a cyan sub-pixel region, a yellow sub-pixel region, or a magenta sub-pixel region.

[0132] exist Figure 3 In the display panel shown, the light-emitting layers in sub-pixel regions A and B can emit light of different wavelengths or colors. The pixel definition layer 240 can be spaced between pixels of different wavelengths or colors to reduce pixel crosstalk. However, considering that the hole injection layer, hole transport layer, electron transport layer, and electron injection layer in the common layer 230 are all integrally covered, lateral migration of carriers in the common layer 230 will occur in both single-device OLED and tandem OLED structures (e.g., ...). Figure 3As indicated by the arrows in the diagram, this can lead to varying degrees of pixel crosstalk, causing other color subpixels to become slightly brighter and affecting the display panel's performance. This is especially true for tandem OLEDs, where the charge generation layer (CGL) exhibits high lateral carrier mobility, resulting in severe pixel crosstalk.

[0133] Based on this, this application creates grooves on the planarization layer and the pixel definition layer in the display panel, thereby blocking the lateral transport of charge carriers in the OLED device, reducing the probability of pixel crosstalk, and also improving the light emission stability of the first frame of the OLED device display, preventing the occurrence of ghosting problems.

[0134] The following combination Figures 4a to 11b This application provides detailed structural schematic diagrams of various display panels provided in its embodiments.

[0135] Figure 4a This is a top view structural diagram of a display panel provided in an embodiment of this application. Figure 5 yes Figure 4a Cross-sectional view along the AA direction.

[0136] Combination Figure 4a as well as Figure 5 The display panel 100 includes multiple sub-pixel regions. The shaded area in the figure represents the third groove 241b, and the blank area represents the first groove 121. The first groove 121 can be set on each of the four sides of sub-pixel region A, and the third groove 241b is set around all four sides of sub-pixel region B. That is, the third groove 241b can be set around sub-pixel region B, and the third groove 241b is continuously set. Continuous setting means that the third groove 241b is set uninterruptedly around the second sub-pixel definition layer 240b around the periphery of sub-pixel region B. When the third groove 241b is set around sub-pixel region B, an inorganic isolation layer 250 is set around other sub-pixel regions adjacent to sub-pixel region B. For example, the first groove 121 is set around the periphery of sub-pixel region A and sub-pixel region C, and the first groove 121 is not continuously set. For example, the outer side of each side of sub-pixel region A is respectively set with mutually discontinuous first grooves 121.

[0137] In the following embodiments, the first direction can also be understood as the direction from any sub-pixel region to its adjacent sub-pixel region, the second direction is the direction perpendicular to the plane where the display panel is located, the second direction can be understood as the thickness direction of the display panel, the first direction is perpendicular to the second direction, and the first direction is parallel to the direction of the plane where the display panel is located.

[0138] like Figure 5As shown, the plane on which the display panel 100 is located includes adjacent sub-pixel regions A and B arranged along a first direction. There is a non-sub-pixel region C between the sub-pixel regions A and B of the display panel 100. The first sub-pixel definition layer 240a and the second sub-pixel definition layer 240b are located in the non-sub-pixel region C on the side of the planarization layer 120 away from the substrate 110. The pixel definition layers can be disposed between adjacent sub-pixel regions. For example, the first sub-pixel definition layer 240a can be disposed in the non-sub-pixel region C near the side of sub-pixel region A, and the second sub-pixel definition layer 240b can be disposed in the non-sub-pixel region C near the end of sub-pixel region B. Along the second direction, the first sub-pixel definition layer 240a and the second sub-pixel definition layer 240b respectively include protrusions.

[0139] In this context, sub-pixel region A can be considered as the first sub-pixel region, and sub-pixel region B can be considered as the second sub-pixel region, or sub-pixel region B can be considered as the first sub-pixel region, and sub-pixel region A can be considered as the second sub-pixel region.

[0140] The planarization layer 120 has a first groove 121 on the side away from the substrate 110 along the second direction. The first groove 121 is disposed in the non-sub-pixel region C, and the second sub-pixel definition layer 240b is partially located in the first groove 121.

[0141] An inorganic isolation layer 250 is disposed in the sub-pixel region A and part of the non-sub-pixel region C, as shown in FIG4. Along the second direction, the inorganic isolation layer 250 is disposed between the anode 210 and the planarization layer 120 in the sub-pixel region A, and the inorganic isolation layer 250 extends from left to right along the first direction to the left sidewall of the first groove 121 and continues to extend beyond the sidewall, so that the projection of the inorganic isolation layer 250 along the second direction overlaps with the bottom wall of the first groove 121.

[0142] In both the non-sub-pixel region C and the sub-pixel region B, the inorganic isolation layer 250 is disposed between the anode 210 and the planarization layer 120.

[0143] It should be noted that the projections of other layers above the inorganic isolation layer 250 along the second direction all fall within the inorganic isolation layer 250. For example, the projections of the common layer 230 and the cathode 220 along the second direction all fall within the inorganic isolation layer 250, which cuts off the common layer 230 between adjacent sub-pixel regions A and B, interrupting the lateral current transmission of the common layer 230 along the first direction, thereby improving the crosstalk effect.

[0144] The third groove 241b is disposed in the non-sub-pixel region C near the sub-pixel region B, that is, the third groove 241b is disposed on the second sub-pixel definition layer 240b. The inorganic isolation layer 250 and the third groove 241b are respectively disposed on opposite sides of the first groove 121 along the first direction.

[0145] Based on the above technical solution, by setting a first groove and a third groove between adjacent sub-pixel regions, the first groove can isolate the connection of the charge generation layer between the two sub-pixel regions, and the third groove can reduce the lateral crosstalk current in the charge generation layer. This can improve the ghosting problem of the display panel, reduce crosstalk and color accuracy problems, and improve the display effect of the display panel.

[0146] The third groove 241b can be continuously set on the second sub-pixel definition layer 240b, meaning that the third groove 241b is set to completely and continuously surround the second sub-pixel region on the second sub-pixel definition layer 240b. For example... Figure 4a As shown, the third groove 241b is a continuous ring surrounding the sub-pixel region B.

[0147] Based on the above technical solution, the continuously arranged third groove can increase the lateral area of ​​the charge generation layer, increase the lateral resistance of the charge generation layer, reduce the lateral crosstalk current, and improve the crosstalk effect.

[0148] Figure 4b and Figure 4c This is a top view of another display panel provided in an embodiment of this application.

[0149] The third groove 241b can be discontinuously set on the second sub-pixel definition layer 240b. Discontinuous setting means that the third groove 241b is not continuously set around the second sub-pixel region on the second sub-pixel definition layer 240b; that is, the third groove 241b is spaced apart around the second sub-pixel region, rather than continuously connected. For example... Figure 4b As shown, the third groove 241b has an ungrooved notch at the corner of the sub-pixel region B. Or as... Figure 4c As shown, four third grooves 241b are respectively provided around the sub-pixel region B, and the four third grooves 241b are discontinuous with each other.

[0150] Based on the above technical solution, other devices, such as point supporting (PS) pillars, can be set at the position where no third groove is set on the display panel. The PS pillars are used to support the mask or other structural devices in the display panel 100, thereby making more effective use of the space of the non-sub-pixel area of ​​the display panel while improving the crosstalk effect.

[0151] In some possible implementations, the third groove 241b can also be a strip-shaped arrangement similar to the first groove, such as... Figure 4c As shown, four third grooves 241b are provided around the sub-pixel region B.

[0152] Still Figure 5 As shown, further, along the first direction, the non-subpixel region C in the display panel 100 can be divided into non-subpixel region A1, non-subpixel region B1 and non-subpixel region B2.

[0153] In the sub-pixel region A, a substrate 110, a planarization layer 120, an inorganic isolation layer 250, an anode 210, a common layer 230, and a cathode 220 are stacked along the second direction.

[0154] The sub-pixel region A can be the region between the left end of the anode 210 and the right end of the anode 210 that contacts the first sub-pixel definition layer 240a along the first direction.

[0155] In the non-sub-pixel region A1, a substrate 110, a planarization layer 120, an inorganic isolation layer 250, a first sub-pixel definition layer 240a, a common layer 230, and a cathode 220 are stacked along the second direction.

[0156] The non-sub-pixel region A1 can be the region between the left side of the first sub-pixel definition layer 240a and the right side of the inorganic isolation layer 250 along the first direction.

[0157] In the non-sub-pixel region B1, a substrate 110, a planarization layer 120, a second sub-pixel definition layer 240b, a common layer 230, and a cathode 220 are stacked along the second direction.

[0158] The non-sub-pixel region B1 can be the region between the right side of the inorganic isolation layer 250 and the right sidewall of the first groove 121 along the first direction.

[0159] In the non-sub-pixel region B2, a substrate 110, a planarization layer 120, an inorganic isolation layer 250, a second sub-pixel definition layer 240b, a common layer 230, and a cathode 220 are stacked along the second direction.

[0160] The non-sub-pixel region B2 can be the region between the right sidewall of the first groove 121 and the position where it contacts the second sub-pixel definition layer 240b and the anode 210 along the first direction.

[0161] In the sub-pixel region B, a substrate 110, a planarization layer 120, an inorganic isolation layer 250, an anode 210, a common layer 230, and a cathode 220 are stacked along the second direction.

[0162] The sub-pixel region B can be the region between the location where the second sub-pixel definition layer 240b and the anode 210 contact each other along the first direction and the right end of the anode 210.

[0163] In the non-sub-pixel region A1 and the non-sub-pixel region B1, the planarization layer 120 is provided with a first groove 121 along the second direction away from the substrate 110; in the sub-pixel region A and the non-sub-pixel region A1, the inorganic isolation layer 250 extends from left to right along the first direction to the left sidewall of the first groove 121, and continues to extend to the right along the first direction, such that the projection of the inorganic isolation layer 250 along the second direction overlaps with the bottom wall of the first groove 121.

[0164] In the sub-pixel region B and the non-sub-pixel region B1, the inorganic isolation layer 250 extends from right to left along the first direction to the right sidewall of the first groove 121, that is, the projection of the inorganic isolation layer 250 along the second direction does not overlap with the bottom wall of the first groove 121.

[0165] In the non-subpixel region B2, a third groove 241b is provided on the side of the second subpixel definition layer 240b away from the substrate.

[0166] The material used to form the inorganic isolation layer 250 can be an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or indium tin oxide. The embodiments of this application do not limit this.

[0167] For example, along the first direction, the distance between sub-pixel region A and sub-pixel region B can be 10μm-30μm, that is, the length of L1+L2+L3 in the figure is between 10μm and 30μm. This can also be understood as the size range of non-sub-pixel region C being 10μm-30μm. Alternatively, the distance range between the first sub-pixel definition layer 240a and the second sub-pixel definition layer 240b can be 10μm-30μm, for example, 10μm, 11μm, 12μm, 13μm, 14μm, etc. μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm, 30μm, etc.; the size of the non-sub-pixel region C refers to the distance in the first direction between the position where the left side of the anode 210 of sub-pixel region A contacts the first sub-pixel definition layer 240a and the position where the left side of the anode 210 of sub-pixel region B contacts the second sub-pixel definition layer 240b.

[0168] For example, along the first direction, the size of the non-sub-pixel region A1 can range from 3μm to 24μm, that is, the length of L1 in the figure is between 3μm and 24μm. The distance from the anode 210 opening boundary of the sub-pixel region A to the inorganic isolation layer 250 can range from 3μm to 24μm. For example, it can be 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, etc. The size of the non-sub-pixel region A1 refers to the distance between the sub-pixel region A and the end of the inorganic isolation layer 250 away from the sub-pixel region A along the first direction in the first direction between adjacent sub-pixel regions A and B.

[0169] For example, along the first direction, the size of the non-sub-pixel region B1 can range from 3μm to 24μm, that is, the length of L2 in the figure can be between 3μm and 24μm. For example, it can be 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, etc. The size of the non-sub-pixel region B1 refers to the distance between the end of the inorganic isolation layer 250 away from the anode 210 and the right sidewall of the first groove 121 in the first direction, or in other words, the difference between the size of the first groove 121 and the length of the projection of the inorganic isolation layer 250 onto the bottom wall of the first groove 121 along the second direction.

[0170] For example, along the first direction, the size of the non-sub-pixel region B2 can be in the range of 3μm-24μm, that is, the length of L3 in the figure can be between 3μm and 24μm. For example, it can be 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, etc. The size of the non-sub-pixel region B2 refers to the distance between the end of the first groove 121 near the sub-pixel region B and the sub-pixel region B in the first direction between adjacent sub-pixel regions A and B.

[0171] For example, along the first direction, the size of the third groove 241b can be in the range of 1μm-20μm, that is, the length of L4 in the figure can be between 1μm and 20μm, for example, it can be 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc. The size of the third groove 241b refers to the distance between the two sidewalls of the third groove 241b in the first direction.

[0172] Figure 6a This is a top view of another display panel provided in an embodiment of this application. Figure 7 yes Figure 6a Cross-sectional view along the DD direction.

[0173] and Figure 4a Compared to the display panel 100 shown, the second groove 241a is disposed in the non-sub-pixel region near the sub-pixel region A, the second groove is disposed on the first sub-pixel definition layer 240a, and the inorganic isolation layer 250 and the second groove 241a are disposed on the same side of the first groove 121 along the first direction, that is, both are disposed in the non-sub-pixel region A1.

[0174] Combination Figure 6a and Figure 7 The display panel 100 includes multiple sub-pixel regions. The shaded area in the figure represents the second groove 241a, and the blank area in the figure represents the first groove 121. The second groove 241a is provided around the sub-pixel region A. That is, the second groove 241a can be set around the sub-pixel region A, and the second groove 241a is set continuously without interruption. It can be considered that the second groove 241a is set along the first sub-pixel definition layer 240a around the sub-pixel region A.

[0175] Based on the above technical solution, by setting a first groove and a second groove between adjacent sub-pixel regions, the first groove can isolate the connection of the charge generation layer between the two sub-pixel regions, and the second groove can reduce the lateral crosstalk current in the charge generation layer. This can improve the ghosting problem of the display panel, reduce crosstalk and color accuracy problems, and improve the display effect of the display panel.

[0176] It should be noted that, Figure 7 The dimensions of each non-sub-pixel region in the image can be referenced. Figure 5 The corresponding description in the text, along the first direction, Figure 7 The range of the dimension L5 of the second groove 241a in the middle can be referenced. Figure 5 The range of the size L4 of the third groove 241b is not described here for the sake of simplicity.

[0177] The second groove 241a can be continuously set on the first sub-pixel definition layer 240a, meaning that the second groove 241a is set to completely and continuously surround the first sub-pixel region on the first sub-pixel definition layer 240a. For example... Figure 6a As shown, the second groove 241a is a continuous ring surrounding the sub-pixel region A.

[0178] Based on the above technical solution, the continuously arranged second groove can increase the lateral area of ​​the charge generation layer, increase the lateral resistance of the charge generation layer, reduce the lateral crosstalk current, and improve the crosstalk effect.

[0179] Figure 6b and Figure 6c This is a top view of another display panel provided in an embodiment of this application.

[0180] The second groove 241a can be non-continuously set on the first sub-pixel definition layer 240a. This means that the second groove 241a is not continuously set around the first sub-pixel region on the first sub-pixel definition layer 240a; that is, the second groove 241a is spaced apart around the first sub-pixel region, rather than being continuously continuous. Figure 6b As shown, the second groove 241a has an ungrooved notch at the corner of the sub-pixel region A. Or as... Figure 6c As shown, four second grooves 241a are respectively provided around the sub-pixel region A, and the four second grooves 241a are discontinuous with each other.

[0181] Based on the above technical solution, other devices, such as PS pillars, can be set at the position where the second groove is not set on the display panel, so as to make more effective use of the space of the non-sub-pixel area of ​​the display panel while improving the crosstalk effect.

[0182] Figure 8a This is a top view of another display panel provided in an embodiment of this application. Figure 9 yes Figure 8a Cross-sectional view along the EE direction.

[0183] and Figure 4aCompared to the display panel 100 shown, the second groove 241a is disposed in a non-sub-pixel region near sub-pixel region A. The second groove 241a is disposed on the first sub-pixel definition layer 240a. The third groove 241b is disposed in a non-sub-pixel region near sub-pixel region B. The third groove 241b is disposed on the second sub-pixel definition layer 240b. The second groove 241a and the third groove 241b are respectively disposed between adjacent sub-pixel regions A and B. The second groove 241a is disposed in non-sub-pixel region A1, and the third groove 241b is disposed in non-sub-pixel region B2. That is, the two second grooves are respectively disposed on both sides of the first groove 121 along the first direction.

[0184] Combination Figure 8a as well as Figure 9 The display panel 100 includes multiple sub-pixel regions. The shaded area in the figure represents the second groove 241a or the third groove 241b, and the blank area in the figure represents the first groove 121. The second groove 241a is provided around the sub-pixel region A, that is, the second groove 241a can be set around the sub-pixel region A, and the second groove 241a is continuously and uninterruptedly set. It can be considered that the second groove 241a is set along the first sub-pixel definition layer 240a around the sub-pixel region A. When the second groove 241a and the first groove 121 are provided around the sub-pixel region A, the third groove 241b is provided around the other sub-pixel regions adjacent to the sub-pixel region A. For example, the third groove 241b is provided around the sub-pixel region B, that is, the third groove 241b can be set around the sub-pixel region B, and the third groove 241b can be continuously and uninterruptedly set.

[0185] Based on the above technical solution, by setting a first groove, a second groove, and a third groove between adjacent sub-pixel regions, the first groove can isolate the connection of the charge generation layer between two sub-pixel regions, and the simultaneous setting of the second and third grooves further increases the lateral area of ​​the charge generation layer, thereby increasing the lateral resistance of the charge generation layer. This can improve the ghosting problem of the display panel, reduce crosstalk and color accuracy problems, reduce lateral crosstalk current, and improve the display effect of the display panel.

[0186] It should be noted that, Figure 9 The dimensions of each non-sub-pixel region in the image can be referenced. Figure 5 The corresponding descriptions are omitted here for the sake of brevity.

[0187] The second groove 241a can be continuously set on the first sub-pixel definition layer 240a, meaning that the second groove 241a is set to completely and continuously surround the first sub-pixel region on the first sub-pixel definition layer 240a. For example... Figure 8aAs shown, the second groove 241a is a continuous ring surrounding the sub-pixel region A.

[0188] In some possible implementations, the third groove 241b can be continuously disposed on the second sub-pixel definition layer 240b, meaning that the third groove 241b is disposed such that it completely and continuously surrounds the second sub-pixel region on the second sub-pixel definition layer 240b. For example... Figure 8a As shown, the third groove 241b is a continuous ring surrounding the sub-pixel region B.

[0189] Based on the above technical solution, the continuously arranged second and third grooves can increase the lateral area of ​​the charge generation layer, increase the lateral resistance of the charge generation layer, reduce the lateral crosstalk current, and improve the crosstalk effect.

[0190] Figure 8b and Figure 8c This is a top view of another display panel provided in an embodiment of this application.

[0191] The second groove 241a can be non-continuously set on the first sub-pixel definition layer 240a. This means that the second groove 241a is not continuously set around the first sub-pixel region on the first sub-pixel definition layer 240a; that is, the second groove 241a is spaced apart around the first sub-pixel region, rather than being continuously continuous. Figure 8b As shown, the second groove 241a has an ungrooved notch at the corner of the sub-pixel region A. Or as... Figure 8c As shown, four second grooves 241a are respectively provided around the sub-pixel region A, and the four second grooves 241a are discontinuous with each other.

[0192] In some possible implementations, the third groove 241b can be discontinuously set on the second sub-pixel definition layer 240b. This means that the third groove 241b is not discontinuously set around the second sub-pixel region on the second sub-pixel definition layer 240b; that is, the third groove 241b is spaced apart around the second sub-pixel region, rather than being continuously continuous. For example... Figure 8b As shown, the third groove 241b has an ungrooved notch at the corner of the sub-pixel region B. Or as... Figure 8c As shown, four third grooves 241b are respectively provided around the sub-pixel region B, and the four third grooves 241b are discontinuous with each other.

[0193] Based on the above technical solution, other devices, such as PS pillars, can be set at the positions where the second and third grooves are not set on the display panel, thereby making more effective use of the space of the non-sub-pixel area of ​​the display panel while improving the crosstalk effect.

[0194] In some possible implementations, the second groove 241a can also be a strip-shaped arrangement similar to the first groove, such as... Figure 8c As shown, four second grooves 241a are respectively provided around the sub-pixel region A.

[0195] It should be noted that the third groove 241b can also be set intermittently similar to the second groove 241a. For the sake of simplicity, it will not be described in detail here.

[0196] It should be noted that the display panel 100 also contains other components, combined with... Figure 10a , Figure 10b , Figure 11a and Figure 11b Other components in the display panel provided in the embodiments of this application will be described.

[0197] In some examples, such as Figure 10a or Figure 10b As shown, the display panel 100 can be a structure containing a single OLED device, and the common layer 230 can include a first light-emitting stack 231. The first light-emitting stack 231 can include components along the thickness direction of the display panel 100 (i.e., ...). Figure 2 In the D2 direction, which is also the second direction, Figure 2 The first hole control layer 2311, the first light-emitting layer 2313, and the first electron control layer 2312 are stacked along the D1 direction (which is the first direction). The first hole control layer 2311 may include a first hole injection layer (HIL) and a first hole transport layer (HTL), and the first electron control layer 2312 may include a first electron transport layer (ETL) and a first electron injection layer (EIL). In other words, the common layer 230 may include the first hole injection layer, the first hole transport layer, the first light-emitting layer 2313, the first electron transport layer, and the first electron injection layer stacked along the D2 direction.

[0198] For example, along Figure 5 The BB direction analysis in the middle can obtain the following: Figure 10a The stacked structure shown indicates that the light-emitting area (such as sub-pixel area A) of the display panel 100 may include a substrate 110, a planarization layer 120, an inorganic isolation layer 250, an anode 210, a first hole injection layer, a first hole transport layer, a first light-emitting layer 2313, a first electron transport layer, a first electron injection layer, a cathode 220, and an encapsulation layer 130 stacked along the D2 direction.

[0199] The anode 210 can be electrically connected to the drain on the substrate 110 through vias in the inorganic isolation layer 250 and the planarization layer 120. By applying voltages to the anode 210 and the cathode 220 respectively, holes can be injected from the anode 210 and electrons from the cathode 220, causing the electrons and holes to meet in the first light-emitting layer 2313 to form excitons (electron-hole pairs), thereby exciting the light-emitting layer 2313 to emit light. At the same time, the display brightness of the display panel 100 can also be adjusted by adjusting the voltage input to the anode 210.

[0200] For example, along Figure 5 The CC-direction analysis in the middle can yield the following results: Figure 10b The stacked structure shown includes a non-light-emitting area (such as non-sub-pixel area A1) of the display panel 100, which may include a substrate 110, a planarization layer 120, an inorganic isolation layer 250, a first sub-pixel definition layer 240a, a first hole injection layer, a first hole transport layer, a first light-emitting layer 2313, a first electron transport layer, a first electron injection layer, a cathode 220, and an encapsulation layer 130 stacked along the D2 direction.

[0201] In other examples, such as Figure 11a As shown, the display panel 100 can be a series structure (i.e., Tandem OLED) containing multiple light-emitting devices (OLEDs, such as dual-device OLEDs), and the common layer 230 can include a first light-emitting stack 231, a charge-generating layer 232 and a second light-emitting stack 233 stacked along the D2 direction.

[0202] The first light-emitting stack 231 may include a first hole control layer 2311, a first light-emitting layer 2313, and a first electron control layer 2312 stacked along the D2 direction. The first hole control layer 2311 may include at least one of a first hole injection layer and a first hole transport layer, and the first hole transport layer may include at least one of a first hole buffer layer and a first electron blocking layer. The first electron control layer 2312 may include at least one of a first electron transport layer and a first electron injection layer, and the first electron control layer 2312 may also include a first hole blocking layer.

[0203] The second light-emitting stack 233 may include a second hole control layer 2331, a second light-emitting layer 2333, and a second electronic control layer 2332 stacked along the D2 direction. The second hole control layer 2331 may include at least one of a second hole injection layer and a second hole transport layer. The second electronic control layer 2332 may include at least one of a second electron injection layer and a second electron transport layer. The descriptions of the first hole control layer 2311 and the first electronic control layer 2312 are equally applicable to the descriptions of the second hole control layer 2331 and the second electronic control layer 2332.

[0204] In some examples, the light emitted from the first light-emitting stack 231 and the second light-emitting stack 233 may have the same wavelength. For example, the light emitted from the first light-emitting stack 231 and the second light-emitting stack 233 may be blue light, which is not limited in this application. In other examples, the wavelength ranges of the light emitted from the first light-emitting stack 231 and the second light-emitting stack 233 may be different from each other. For example, at least one of the first light-emitting stack 231 and the second light-emitting stack 233 may emit blue light, and the other of the first light-emitting stack 231 and the second light-emitting stack 233 may emit green light, thereby enabling the light-emitting element comprising the first light-emitting stack 231 and the second light-emitting stack 233 to emit white light.

[0205] A charge generation layer 232 can be disposed between the first light-emitting stack 231 and the second light-emitting stack 233. When a voltage is applied to the charge generation layer 232, charges (electrons and holes) are generated through redox reactions to form complexes. Furthermore, the charge generation layer 232 can provide the generated charges to each of the first light-emitting stack 231 and the second light-emitting stack 233. The charge generation layer 232 can double the efficiency of the current generated in each of the first and second light-emitting stacks 231 and 233, and plays a role in controlling the charge balance between the first and second light-emitting stacks 231 and 233.

[0206] refer to Figure 11a The charge generation layer 232 may have a layer structure in which a first charge generation layer and a second charge generation layer are bonded to each other. The first charge generation layer may be an n-type charge generation layer disposed adjacent to the first light-emitting stack 231 and providing electrons to the first light-emitting stack 231. The second charge generation layer may contain an arylamine organic compound. The second charge generation layer may be a p-type charge generation layer disposed adjacent to the second light-emitting stack 233 and providing holes to the second light-emitting stack 233. The second charge generation layer may contain a charge generation compound composed of a metal, metal oxide, carbide, fluoride, or a mixture thereof.

[0207] For example, along Figure 5 The BB direction analysis in the middle can obtain the following: Figure 11b The stacked structure shown includes a light-emitting area (such as sub-pixel area A) of the display panel 100, which may include a substrate 110, a planarization layer 120, an inorganic isolation layer 250, an anode 210, a first hole injection layer, a first hole transport layer, a first light-emitting layer 2313, a first electron transport layer, a first electron injection layer, a first charge generation layer, a second charge generation layer, a second hole injection layer, a second hole transport layer, a second light-emitting layer 2333, a second electron transport layer, a second electron injection layer, a cathode 220, and an encapsulation layer 130.

[0208] For example, along Figure 5 The CC-direction analysis in the middle can yield the following results: Figure 11b The stacked structure shown includes a non-light-emitting area (such as non-sub-pixel area A1) of the display panel 100, which may include a substrate 110, a planarization layer 120, an inorganic isolation layer 250, a first sub-pixel definition layer 240a, a first hole injection layer, a first hole transport layer, a first light-emitting layer 2313, a first electron transport layer, a first electron injection layer, a first charge generation layer, a second charge generation layer, a second hole injection layer, a second hole transport layer, a second light-emitting layer 2333, a second electron transport layer, a second electron injection layer, a cathode 220, and an encapsulation layer 130.

[0209] It should be noted that, in Figure 11b Middle Figure 5 The stacked structure of the non-sub-pixel region obtained by CC-direction analysis can be deposited using a common metal mask (CMM). That is, when using a CMM for deposition, the first light-emitting layer 2313 and the second light-emitting layer 2333 will be retained in the non-sub-pixel region. In some possible implementations, when using a fine metal mask (FMM) for deposition, the first light-emitting layer 2313 and the second light-emitting layer 2333 will not be included in the non-sub-pixel region of the display panel. It should be understood that this application does not limit the number of light-emitting devices. In some possible implementations, the common layer 230 may include three light-emitting stacks and two charge-generating layers disposed between the three light-emitting stacks; alternatively, the common layer 230 may include more light-emitting stacks and charge-generating layers disposed between multiple light-emitting stacks.

[0210] Combination Figure 5 , Figure 10a , Figure 10b , Figure 11a and Figure 11b It is understood that the display area of ​​the display panel 100 may include multiple sub-pixel areas (light-emitting areas) and non-sub-pixel areas (non-light-emitting areas) adjacent to the sub-pixel areas, and the non-sub-pixel areas may surround the sub-pixel areas. In this application, the sub-pixel areas may be defined to correspond to the portion of the anode 210 exposed by the pixel opening, or the non-sub-pixel areas may be defined to correspond to the area of ​​the pixel definition layer 240.

[0211] Figure 12 This is a schematic diagram of the manufacturing process of the display panel provided in the embodiments of this application.

[0212] The display panel 100 may include the following processing steps: S101, Fabrication of a substrate. It should be understood that the substrate can be a TFT substrate, which specifically may include a base and TFT circuits and peripheral driving circuits fabricated on the base.

[0213] In some possible implementations, a TFT circuit may include an active layer, a source, a drain, a gate insulating layer, and a gate. The materials of the active layer of a TFT include, but are not limited to, LTPS, oxides, a-Si, LTPO, and organic materials.

[0214] In some possible implementations, the substrate can be a rigid substrate. Exemplarily, the substrate can be any of a glass substrate, a quartz substrate, or a ceramic substrate. For example, a glass substrate can be composed of soda-lime glass and / or borosilicate glass. These types of substrates can possess good mechanical strength and good thermal stability.

[0215] In some possible implementations, the substrate can be a flexible substrate. Exemplarily, the substrate can be composed of polymer materials, such as one or more of the following: PI, PET, PC, PEN, or COC. These polymer materials can possess good optical and mechanical properties, enabling the substrate to bend and deform, thereby allowing the display panel to meet the requirements of foldable electronic devices (such as foldable phones).

[0216] In some possible implementations, the substrate may also be composed of the inorganic material that constitutes the rigid substrate and the polymer material that constitutes the flexible substrate, and this application does not limit this.

[0217] Exemplarily, the substrate may have a multilayer structure. For example, the substrate may include a first synthetic resin layer, multiple or single inorganic layers, and a second synthetic resin layer disposed on the multiple or single inorganic layers. Each of the first and second synthetic resin layers may contain a polyimide resin.

[0218] S102, a planarization layer is formed on the surface of the substrate.

[0219] For example, a planarization layer can be formed on a substrate through processes such as film formation, exposure, and development. The material used to obtain the planarization layer is an organic polymer such as polyimide, siloxane, polyamide, or acrylic.

[0220] S103 forms an inorganic isolation layer on the surface of the planarization layer.

[0221] For example, an inorganic isolation layer can be formed on the planarization layer through processes such as film formation, exposure, and development. The inorganic isolation layer is made of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or indium tin oxide.

[0222] The inorganic isolation layer can be formed near sub-pixel region A or near sub-pixel region B.

[0223] S104, forming the first groove in the planarization layer.

[0224] For example, since the planarization layer is typically made of organic materials, an etching solvent that is effective against organic materials can be used to etch the planarization layer while leaving the inorganic isolation layer on the surface of the planarization layer, thereby forming the first groove.

[0225] S105, an anode is formed on the side of the planarization layer away from the substrate.

[0226] For example, an anode can be formed on an inorganic isolation layer through processes such as film formation, exposure, development, and etching. The anode is located in the sub-pixel region (light-emitting region). The anode material can be a metal / metal oxide / alloy such as silver, aluminum, or indium tin oxide.

[0227] S106, a pixel definition layer is formed on the side of the inorganic isolation layer away from the substrate.

[0228] For example, a patterned pixel definition layer can be formed on an inorganic isolation layer through processes such as film formation, exposure, and development. The pixel definition layer is disposed between adjacent sub-pixel regions.

[0229] The process of forming a pixel definition layer includes forming a first sub-pixel definition layer at a location close to sub-pixel region A and forming a second sub-pixel definition layer at a location close to sub-pixel region B.

[0230] S107a, a second groove is formed in the first sub-pixel definition layer.

[0231] For example, the second groove can be formed on the first sub-pixel definition layer through processes such as exposure, development, and etching.

[0232] S107b forms a third groove in the second sub-pixel definition layer.

[0233] For example, a third groove can be formed on the second sub-pixel definition layer through processes such as exposure, development, and etching.

[0234] It should be noted that S107a and S107b are optional steps, meaning that the second groove can be formed in the first sub-pixel definition layer, or the third groove can be formed in the second sub-pixel definition layer.

[0235] In some possible implementations, both S107a and S107b can be performed, that is, a second groove can be formed on the first sub-pixel definition layer and a third groove can be formed on the second sub-pixel definition layer. S107a can be performed first and then S107b; or S107b can be performed first and then S107a.

[0236] S108, a common layer is formed on the side of the anode and the first sub-pixel definition layer away from the substrate.

[0237] In some possible implementations, the common layer 230 may include a first hole injection layer, a first hole transport layer, a first light-emitting layer, a first electron transport layer, and a first electron injection layer stacked along a second direction, thereby forming an OLED that is a display panel with a single light-emitting device.

[0238] In some possible implementations, the common layer 230 may include a first hole injection layer, a first hole transport layer, a first light-emitting layer, a first electron transport layer, a first electron injection layer, a first charge generation layer, a second charge generation layer, a second hole injection layer, a second hole transport layer, a second light-emitting layer, a second electron transport layer, and a second electron injection layer, thereby forming an OLED that is a multi-emitting device display panel (i.e., Tandem OLED).

[0239] For details regarding common layer 230, please refer to [link / reference]. Figure 11a and Figure 11b For the sake of brevity, the relevant descriptions in the document will not be repeated here.

[0240] The following is a detailed description of the structural schematic diagram of the display panel provided in the embodiments of this application, with reference to the figures.

[0241] Figure 13 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0242] Figure 14 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0243] Figure 14 It can be Figure 13 Cross-sectional view along the FF direction.

[0244] Combination Figure 13 as well as Figure 14 The display panel 300 includes a substrate 310, a planarization layer 320, an anode 330, and a third sub-pixel definition layer 340 stacked together. A fourth recess 350 is disposed on the third sub-pixel definition layer 340. The display panel 300 includes multiple sub-pixel regions. The shaded area in the figure represents the fourth recess 350, which may be disposed around sub-pixel region A. Figure 13As shown, the fourth groove 350 can be set around sub-pixel region C, sub-pixel region E, sub-pixel region G, or sub-pixel region I. The fourth groove 350 can be set continuously around the sub-pixel region, or it can be set non-continuously around the sub-pixel region.

[0245] In some embodiments, the fourth groove 350 is closer to the sub-pixel region B relative to the sub-pixel region A, and in this case, the number of fourth grooves 350 can be one. In some embodiments, the fourth groove 350 is closer to the sub-pixel region A relative to the sub-pixel region B, and in this case, the number of fourth grooves 350 can be one. In some embodiments, the number of fourth grooves 350 is multiple, with one of the multiple fourth grooves 350 being closer to the sub-pixel region A, and another of the multiple fourth grooves 350 being closer to the sub-pixel region B.

[0246] In some embodiments, the second sidewall 352 is closer to the geometric center of the third sub-pixel definition layer 340 relative to the first sidewall 351. Alternatively, the first sidewall 351 is closer to the sub-pixel region relative to the second sidewall 352.

[0247] The fourth groove 350 includes a first bottom wall 353, a first side wall 351, and a second side wall 352. The angle between the first bottom wall 353 and the first side wall 351 is α, and the angle between the first bottom wall 353 and the second side wall 352 is β. α and β are different, and both α and β are greater than or equal to 90 degrees. In some embodiments, the first side wall 351 is closer to the sub-pixel region A, and the second side wall 352 is farther from the sub-pixel region A.

[0248] In some possible implementations, along the second direction, the projected area of ​​the first sidewall 351 on the planarization layer 320 is greater than the projected area of ​​the second sidewall 352 on the planarization layer 320, and the second direction is the direction perpendicular to the plane where the display panel 300 is located.

[0249] According to the embodiments provided in this application, since the projected area of ​​the first sidewall on the planarization layer is larger than the projected area of ​​the second sidewall on the planarization layer, the thickness of the charge generation layer at the first sidewall is thinner, which is beneficial to increase the resistance of the charge generation layer near the sub-pixel region, reduce the lateral crosstalk current, and improve the crosstalk effect.

[0250] It should be noted that, Figure 13 and Figure 14 Taking the fourth groove 350 near sub-pixel region A as an example, the situation of the fourth groove 350 near sub-pixel region B can be referred to the description of the above embodiment, and will not be described here for the sake of brevity.

[0251] According to the embodiments provided in this application, since there is an angle between the first sidewall 351 and the first bottom wall 353, and an angle between the second sidewall 352 and the first bottom wall 353, after the charge generation layer is deposited in the fourth groove 350, the thickness of the charge generation layer can be reduced, the resistance of the charge generation layer can be increased, the lateral crosstalk current can be reduced, and the crosstalk effect can be improved.

[0252] In some embodiments, α > β.

[0253] According to the embodiments provided in this application, since α > β, after the charge generation layer is deposited on the fourth groove, the thickness of the charge generation layer on the side closer to the sub-pixel region is thinner than the thickness of the charge generation layer on the side farther from the sub-pixel region. The resistance of the charge generation layer on the side closer to the sub-pixel region is higher than the resistance of the charge generation layer on the side farther from the sub-pixel region. The lateral crosstalk current reduction effect in the charge generation layer closer to the sub-pixel region is better, which can further improve the crosstalk effect.

[0254] In some embodiments, 120°≤α≤140°, 90°≤β≤110°.

[0255] In some embodiments, α-β ≥ 10°.

[0256] According to the embodiments provided in this application, α and β satisfy specific conditions. After the charge generation layer is deposited on the fourth groove, the thickness of the charge generation layer on the side closer to the sub-pixel region is thinner than the thickness of the charge generation layer on the side farther from the sub-pixel region. The resistance of the charge generation layer on the side closer to the sub-pixel region is higher than the resistance of the charge generation layer on the side farther from the sub-pixel region. The lateral crosstalk current reduction effect in the charge generation layer closer to the sub-pixel region is better, which can further improve the crosstalk effect.

[0257] Figure 15 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0258] Figure 16 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0259] Figure 16 It can be Figure 15 Cross-sectional view along the GG direction.

[0260] Combination Figure 15 as well as Figure 16The display panel 300 includes a substrate 310, a planarization layer 320, an anode 330, and a third sub-pixel definition layer 340 stacked together. A first sub-groove 350a and a second sub-groove 350b are disposed on the third sub-pixel definition layer 340. The first sub-groove 350a and the second sub-groove 350b can be collectively referred to as a fourth groove. The display panel includes multiple sub-pixel regions. The shaded area in the figure represents the fourth groove, and each sub-pixel region is provided with a fourth groove. The fourth groove can be continuously surrounding the sub-pixel regions, or it can be non-continuously surrounding them. In this case, there are multiple fourth grooves, with one of the multiple fourth grooves near sub-pixel region A and another of the multiple fourth grooves near sub-pixel region B.

[0261] Alternatively, the fourth groove can be described as including the first sub-groove and the second sub-groove, with the first sub-groove located near sub-pixel region A and the second sub-groove located near sub-pixel region B.

[0262] Still Figure 15 and Figure 16 As shown, the fourth groove near sub-pixel region A can be referred to as the first sub-groove 350a, and the fourth groove near sub-pixel region B can be referred to as the second sub-groove 350b. The first sub-groove 350a includes a first sub-bottom wall 353a, a first sub-side wall 351a and a second sub-side wall 352a opposite to each other in a first direction. The second sub-groove 350b includes a second sub-bottom wall 353b, a third sub-side wall 351b and a fourth sub-side wall 352b opposite to each other in a first direction.

[0263] It should be noted that the first sub-bottom wall can also be called the first bottom wall of the first sub-groove, the first sub-side wall can also be called the first side wall of the first sub-groove, and the second sub-side wall can also be called the second side wall of the first sub-groove.

[0264] It should be noted that the second sub-bottom wall can also be called the first bottom wall of the second sub-groove, the third sub-side wall can also be called the first side wall of the second sub-groove, and the fourth sub-side wall can also be called the second side wall of the second sub-groove.

[0265] In some embodiments, the second sub-sidewall 352a is closer to the geometric center of the third sub-pixel definition layer 340 relative to the first sub-sidewall 351a, and the fourth sub-sidewall 352b is closer to the geometric center of the third sub-pixel definition layer 340 relative to the third sub-sidewall 351b.

[0266] In some embodiments, the angle between the first sub-bottom wall 353a and the first sub-side wall 351a is α1, and the angle between the first sub-bottom wall 353a and the second sub-side wall 352a is β2, wherein α1 and β1 are different. The angle between the second sub-bottom wall 353b and the third sub-side wall 351b is α2, and the angle between the second sub-bottom wall 353b and the fourth sub-side wall 352b is β2, wherein α2 and β2 are different. In some possible implementations, α1 > β1, α2 > β2. In some embodiments, 120° ≤ α1 ≤ 140°, 90° ≤ β1 ≤ 110°. In some embodiments, α1 - β1 ≥ 10°. In some embodiments, 120° ≤ α2 ≤ 140°, 90° ≤ β2 ≤ 110°. In some embodiments, α2 - β2 ≥ 10°.

[0267] It is understood that the characteristics between α1 and β1, and between α2 and β2, can be referred to the description of α and β in this application, and will not be repeated here for the sake of brevity. It is understood that α1 and α2 are different, and β1 and β2 are different.

[0268] Along the first direction, the distance between sub-pixel region A and sub-pixel region B can be 10μm-30μm. Alternatively, the size of non-sub-pixel region C can be 10μm-30μm, and W1 represents the size of non-sub-pixel region C. For example, W1 can be 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm, 30μm, etc.

[0269] Along the first direction, in the non-sub-pixel region C near the sub-pixel region A, W2 represents the distance between the end of the first sub-sidewall 351a away from the substrate 310 and the boundary of the third sub-pixel defining layer 340, and W2 ranges from 3μm to 20μm. W2 and W6 can be the same.

[0270] Along the first direction, in the non-sub-pixel region C near sub-pixel region A, W3 represents the distance between the end of the first sub-sidewall 351a away from the substrate 310 and the end of the second sub-sidewall 352a away from the substrate 310, and W3 ranges from 2μm to 10μm. W3 can also be referred to as the width of the fourth groove. W3 and W5 can be the same.

[0271] Along the first direction, in the non-sub-pixel region C, W4 represents the distance between the end of the second sub-sidewall 352a away from the substrate 310 and the end of the fourth sub-sidewall 352b away from the substrate 310. W4 can also be referred to as the distance between a plurality of adjacent fourth grooves, and the range of W4 is 2μm-10μm.

[0272] Along the first direction, in the non-sub-pixel region C near sub-pixel region A, W7 represents the length of the portion where the anode 330 overlaps with the third sub-pixel definition layer 340. W7 and W10 can be the same.

[0273] Along the first direction, in the non-sub-pixel region C near sub-pixel region A, W8 represents the distance between the end of the anode 330 near sub-pixel region B and the end of the first sub-sidewall 351a near substrate 310, with W8 ranging from 0.5μm to 10μm. W8 and W9 can be the same. Along the second direction, in the non-sub-pixel region C near sub-pixel region A, W11 represents the distance between the side of the third sub-pixel defining layer 340 away from substrate 310 and the first sub-bottom wall 353a. W11 can also be referred to as the depth of the first sub-groove 350a, or the depth of the fourth groove. W11 ranges from 0.3μm to 1.5μm.

[0274] According to the embodiments provided in this application, by limiting the above-mentioned distance range, the production and manufacturing of the display panel is facilitated. In other words, the above-mentioned distance range can be the range for mass production.

[0275] Figure 17 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0276] Figure 18 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0277] Figure 18 It can be Figure 17 A cross-sectional view along the HH direction.

[0278] Figure 18 It can be Figure 16 The diagram shown is a structural schematic of the display panel obtained after the vapor deposition process. Figure 17 and Figure 18 The display panel shown is formed after the third light-emitting stack 410, the charge-generating layer 440, the fourth light-emitting stack 420 and the cathode 360 ​​are formed. The cathode 360 ​​can cover the display panel 300.

[0279] It should be noted that the anode 330 is located on the side of the planarization layer 320 away from the substrate 310, and the anode 330 is located in sub-pixel region A and sub-pixel region B respectively.

[0280] It should be noted that the common layer is located on the side of the third sub-pixel definition layer 340 and the anode 330 away from the substrate 310. The common layer is used to transport charge carriers. Other characteristics of the common layer can be found in other relevant descriptions in this application. For the sake of brevity, they will not be repeated here.

[0281] The common layer may include a third light-emitting stack 410 and a charge-generating layer 440. In non-sub-pixel regions, the third light-emitting stack 410 is located above the third sub-pixel defining layer 340. The common layer also includes a fourth light-emitting stack 420 near the first sub-pixel region and a fifth light-emitting stack 430 near the second sub-pixel region. In non-sub-pixel regions, the fourth light-emitting stack 420 and the fifth light-emitting stack 430 are located above the charge-generating layer 440. Along the second direction, the projections of the fourth light-emitting stack 420 and the fifth light-emitting stack 430 onto the third sub-pixel defining layer 340 overlap and respectively overlap with the fourth groove.

[0282] The projection of the fourth light-emitting stack 420 onto the third sub-pixel definition layer 340 overlaps with the projection of the fifth light-emitting stack 430 onto the third sub-pixel definition layer 340. The projection of the fourth light-emitting stack 420 onto the third sub-pixel definition layer 340 overlaps with the fourth groove, which could mean that the projection of the fourth light-emitting stack 420 onto the third sub-pixel definition layer 340 overlaps with the first sub-groove 350a.

[0283] The projection of the fifth light-emitting stack 430 onto the third sub-pixel definition layer 340 overlaps with the fourth groove, which can mean that the projection of the fifth light-emitting stack 430 onto the third sub-pixel definition layer 340 overlaps with the second sub-groove 350b.

[0284] According to the embodiments provided in this application, the fourth and fifth light-emitting stacks can completely cover the charge generation layer after deposition, so that after the cathode is deposited on the common layer, there will be no short circuit between the cathode and the charge generation layer, avoiding the situation where different sub-pixel areas are lit at the same time, improving the yield of the display panel, avoiding problems such as ghosting, power-on flickering, crosstalk, and power-on image retention in the display panel, and improving the display effect of the display panel.

[0285] like Figure 18 As shown, in sub-pixel region A, there are a substrate 310, a planarization layer 320, an anode 330, a third light-emitting stack 410, a charge-generating layer 440, a fourth light-emitting stack 420, and a cathode 360 ​​stacked together.

[0286] In the non-subpixel region C1, the display panel 300 includes a substrate 310, a planarization layer 320, an anode 330, a third subpixel definition layer 340, a third light-emitting stack 410 (near the subpixel region A), a charge generation layer 440, a fourth light-emitting stack 420, and a cathode 360, which are stacked together.

[0287] In the non-sub-pixel region C2, the display panel 300 includes a substrate 310, a planarization layer 320, an anode 330, a third sub-pixel definition layer 340, a charge generation layer 440, a fourth light-emitting stack 420, and a cathode 360, all stacked together. The fourth recess (first sub-recess 350a) is located in the non-sub-pixel region C2.

[0288] In the non-subpixel region C3, the display panel 300 includes a substrate 310, a planarization layer 320, a third subpixel definition layer 340, a charge generation layer 440, a fourth light-emitting stack 420, a fifth light-emitting stack 430, and a cathode 360, which are stacked together.

[0289] In the non-subpixel region C4, the display panel 300 includes a substrate 310, a planarization layer 320, a third subpixel definition layer 340, a charge generation layer 440, a fourth light-emitting stack 420, a fifth light-emitting stack 430, and a cathode 360, which are stacked together.

[0290] In the non-subpixel region C5, the display panel 300 includes a substrate 310, a planarization layer 320, an anode 330, a third subpixel definition layer 340, a third light-emitting stack 410 (near the subpixel region B), a charge generation layer 440, a fifth light-emitting stack 430, and a cathode 360, which are stacked together.

[0291] Anode 330 may extend from sub-pixel region A to non-sub-pixel region C1. Third light-emitting stack 410 (near sub-pixel region A) may extend from sub-pixel region A to non-sub-pixel region C1. Third light-emitting stack 410 (near sub-pixel region B) may extend from sub-pixel region B to non-sub-pixel region C5. Charge generation layer 440 may extend from sub-pixel region A to non-sub-pixel regions C1 and C2, and non-sub-pixel region B. Fourth light-emitting stack 420 may extend from sub-pixel region A to non-sub-pixel regions C1, C2, and C3. Fifth light-emitting stack 430 may extend from sub-pixel region B to non-sub-pixel regions C5, C4, and C3.

[0292] Along the second direction, the projection of the third light-emitting stack 410 onto the third sub-pixel definition layer 340 does not overlap with the fourth groove, while the projection of the charge generation layer 440 onto the third sub-pixel definition layer 340 overlaps with the fourth groove.

[0293] According to the embodiments provided in this application, since α > β, in the second direction, the width of the projection of the first sidewall onto the substrate is greater than the width of the projection of the second sidewall onto the substrate. After the light-emitting stack is deposited on the fourth groove, the light-emitting stack near the sub-pixel region A is thinner, which can reduce the capacitance of the light-emitting stack and improve the display effect of the display panel. The deposition of the light-emitting stack on the fourth groove can refer to the deposition of the third light-emitting stack and the deposition of the fourth light-emitting stack on the fourth groove. The capacitance ratio of the third light-emitting stack and the fourth light-emitting stack can be well controlled, thereby improving the display effect of the display panel.

[0294] According to the embodiments provided in this application, the projection of the third light-emitting stack on the third sub-pixel definition layer does not overlap with the fourth groove, and the value of the included angle α is not affected. After the charge generation layer is deposited on the fourth groove, the thickness of the charge generation layer at the first sidewall does not increase, which can increase the resistance of the charge generation layer, reduce the lateral crosstalk current, improve the crosstalk effect, and improve the display effect of the display panel.

[0295] Along the second direction, the projection of the fourth light-emitting stack 420 onto the third sub-pixel definition layer 340 overlaps with the fourth groove.

[0296] According to the embodiments provided in this application, after the fourth light-emitting stack is deposited on the fourth groove, the thickness of the fourth light-emitting stack is relatively large, which can increase the capacitance of the fourth light-emitting stack and adjust the ratio between the capacitance of the third light-emitting stack and the capacitance of the fourth light-emitting stack, thereby improving the display effect of the display panel.

[0297] According to the embodiments provided in this application, the fourth light-emitting stack is thicker and extends from the sub-pixel region A to the non-sub-pixel region C3, which can isolate the charge generation layer and the cathode, avoid short-circuiting the charge generation layer and the cathode, reduce the ghosting of the display panel, and improve the display effect of the display panel.

[0298] Figure 19 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0299] The display panel 300 includes a substrate, a planarization layer 320, and a third sub-pixel definition layer 340 stacked together, and a fourth recess 350 disposed on the third sub-pixel definition layer 340. The fourth recess 350 is not discontinuously disposed around the sub-pixel area. For example, the position where the fourth recess 350 is not disposed can be used to set other structures of the display panel, such as an anode jumper hole or a support post. Figure 19 The schematic diagram of section II in the middle can be used Figure 16 express.

[0300] Figure 20This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0301] The display panel 300 includes a substrate, a planarization layer 320, and a third sub-pixel definition layer 340 stacked together, and a fourth recess 350 disposed on the third sub-pixel definition layer 340. The fourth recess 350 is discontinuously disposed around the sub-pixel area, and the perimeter of the fourth recess 350 can be adjusted. Figure 20 The JJ cross-sectional diagram in the diagram can be used Figure 16 express.

[0302] Figure 21 This is a top view structural diagram of a display panel provided in an embodiment of this application.

[0303] The display panel 300 includes a substrate, a planarization layer 320, and a third sub-pixel definition layer 340 stacked together. A first sub-groove 350a, a fifth sub-groove 341, and a second sub-groove 350b are respectively disposed on the third sub-pixel definition layer 340. The first sub-groove 350a, the fifth sub-groove 341, and the second sub-groove 350b are respectively located on the side of the third sub-pixel definition layer 340 away from the substrate.

[0304] In some possible implementations, the number of fifth grooves can be multiple.

[0305] Figure 22 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application. Figure 22 It can be Figure 21 Cross-sectional view along the KK direction.

[0306] Combination Figure 21 as well as Figure 22 As shown, the third sub-pixel definition layer 340 is further provided with a first sub-groove 350a, a fifth groove 341, and a second sub-groove 350b, with the fifth groove 341 located between the first sub-groove 350a and the second sub-groove 350b. Alternatively, the first sub-groove 350a, the fifth groove 341, and the second sub-groove 350b are arranged sequentially along a first direction.

[0307] Figure 23 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.

[0308] like Figure 23 As shown, multiple fifth grooves 341 can be provided between the first sub-groove 350a and the second sub-groove 350b. The number of fifth grooves 341 can be multiple, for example, two, three, four or more.

[0309] Because the third sub-pixel definition layer has multiple grooves, the charge generation layer is formed on these grooves, which further reduces the lateral current transmission capability of the charge generation layer, reduces the lateral crosstalk current, improves the crosstalk effect, and improves the display effect of the display panel.

[0310] In some embodiments, the shape of the sub-pixel region can be rectangular, square, circular, elliptical, or triangular, or other polygonal shapes.

[0311] Figure 24 This is a schematic diagram of the manufacturing process of a display panel provided in an embodiment of this application.

[0312] The display panel 300 may include the following processing steps: S201, Fabrication of substrate 310. It should be understood that the substrate can be a TFT substrate, which specifically may include a substrate and TFT circuits and peripheral driving circuits fabricated on the substrate.

[0313] In some possible implementations, a TFT circuit may include an active layer, a source, a drain, a gate insulating layer, and a gate. The materials of the active layer of a TFT include, but are not limited to, LTPS, oxides, a-Si, LTPO, and organic materials.

[0314] In some possible implementations, the substrate can be a rigid substrate. Exemplarily, the substrate can be any of a glass substrate, a quartz substrate, or a ceramic substrate. For example, a glass substrate can be composed of soda-lime glass and / or borosilicate glass. These types of substrates can possess good mechanical strength and good thermal stability.

[0315] In some possible implementations, the substrate can be a flexible substrate. Exemplarily, the substrate can be composed of polymer materials, such as one or more of the following: PI, PET, PC, PEN, or COC. These polymer materials can possess good optical and mechanical properties, enabling the substrate to bend and deform, thereby allowing the display panel to meet the requirements of foldable electronic devices (such as foldable phones).

[0316] In some possible implementations, the substrate may also be composed of the inorganic material that constitutes the rigid substrate and the polymer material that constitutes the flexible substrate, and this application does not limit this.

[0317] Exemplarily, the substrate may have a multilayer structure. For example, the substrate may include a first synthetic resin layer, multiple or single inorganic layers, and a second synthetic resin layer disposed on the multiple or single inorganic layers. Each of the first and second synthetic resin layers may contain a polyimide resin.

[0318] S202, a planarization layer 320 is formed on the surface of the substrate 310.

[0319] For example, a planarization layer can be formed on a substrate through processes such as film formation, exposure, and development. The material used to obtain the planarization layer is an organic polymer such as polyimide, siloxane, polyamide, or acrylic.

[0320] S203, an anode 330 is formed on the side of the planarization layer 320 away from the substrate 310.

[0321] For example, an anode can be formed on an inorganic isolation layer through processes such as film formation, exposure, development, and etching. The anode is located in the sub-pixel region (light-emitting region). The anode material can be a metal / metal oxide / alloy such as silver, aluminum, or indium tin oxide.

[0322] S204, a pixel definition layer is formed on the side of the planarization layer 320 away from the substrate 310.

[0323] For example, a patterned pixel definition layer can be formed on the planarization layer through processes such as film formation, exposure, and development. The pixel definition layer is disposed between adjacent sub-pixel regions. The pixel definition layer is partially located above the anode.

[0324] The process of forming a pixel definition layer includes forming a third sub-pixel definition layer 340 between sub-pixel region A and sub-pixel region B. Forming the third sub-pixel definition layer 340 can be achieved by first forming photoresist on the planarization layer 320, and then etching the photoresist to form a patterned third sub-pixel definition layer 340.

[0325] S205, a fourth groove 350 is formed in the third sub-pixel definition layer 340.

[0326] For example, a fourth groove can be formed on the third sub-pixel definition layer through processes such as exposure, development, and etching.

[0327] In some embodiments, forming a fourth groove may include forming a first sub-groove, or forming a second sub-groove, or forming a first sub-groove and a second sub-groove.

[0328] In some possible implementations, the magnitudes of α, α1, α2, β, β1, or β2 can be achieved by controlling the gas flow rate during the exposure or development process, or by controlling the power during the etching process, i.e., etching in a single step.

[0329] In some possible implementations, the magnitudes of α, α1, α2, β, β1, or β2 can be controlled through multiple exposure processes or development processes.

[0330] In some embodiments, after step S205, the processing step further includes forming a common layer and a cathode on the side of the anode and the third sub-pixel definition layer away from the substrate.

[0331] Figure 25 This is a schematic diagram of the manufacturing process of a display panel provided in an embodiment of this application.

[0332] The display panel 300 may include the following processing steps: S301, Fabrication of substrate 310. It should be understood that the substrate can be a TFT substrate, which specifically may include a substrate and TFT circuits and peripheral driving circuits fabricated on the substrate.

[0333] In some possible implementations, a TFT circuit may include an active layer, a source, a drain, a gate insulating layer, and a gate. The materials of the active layer of a TFT include, but are not limited to, LTPS, oxides, a-Si, LTPO, and organic materials.

[0334] In some possible implementations, the substrate can be a rigid substrate. Exemplarily, the substrate can be any of a glass substrate, a quartz substrate, or a ceramic substrate. For example, a glass substrate can be composed of soda-lime glass and / or borosilicate glass. These types of substrates can possess good mechanical strength and good thermal stability.

[0335] In some possible implementations, the substrate can be a flexible substrate. Exemplarily, the substrate can be composed of polymer materials, such as one or more of the following: PI, PET, PC, PEN, or COC. These polymer materials can possess good optical and mechanical properties, enabling the substrate to bend and deform, thereby allowing the display panel to meet the requirements of foldable electronic devices (such as foldable phones).

[0336] In some possible implementations, the substrate may also be composed of the inorganic material that constitutes the rigid substrate and the polymer material that constitutes the flexible substrate, and this application does not limit this.

[0337] Exemplarily, the substrate may have a multilayer structure. For example, the substrate may include a first synthetic resin layer, multiple or single inorganic layers, and a second synthetic resin layer disposed on the multiple or single inorganic layers. Each of the first and second synthetic resin layers may contain a polyimide resin.

[0338] S302, a planarization layer 320 is formed on the surface of the substrate 310.

[0339] For example, a planarization layer can be formed on a substrate through processes such as film formation, exposure, and development. The material used to obtain the planarization layer is an organic polymer such as polyimide, siloxane, polyamide, or acrylic.

[0340] S303, an anode 330 is formed on the side of the planarization layer 320 away from the substrate 310.

[0341] For example, an anode can be formed on an inorganic isolation layer through processes such as film formation, exposure, development, and etching. The anode is located in the sub-pixel region (light-emitting region). The anode material can be a metal / metal oxide / alloy such as silver, aluminum, or indium tin oxide.

[0342] S304, a first photoresist is formed on the side of the planarization layer 320 away from the substrate 310.

[0343] S305, etch the first photoresist to form the first protrusion.

[0344] S306, a second photoresist is formed on the side of the planarization layer 320 away from the substrate 310.

[0345] S307, etch the second photoresist to form the second protrusion.

[0346] The first protrusion and the second protrusion form a third sub-pixel definition layer with a fourth groove.

[0347] The second photoresist can be a positive photoresist, and the first photoresist can be a negative photoresist.

[0348] The first protrusion can be a trapezoidal structure, the first bottom wall of the fourth groove is located on the second protrusion, the first side wall is located on the second protrusion, and the second side wall is located on the first protrusion.

[0349] For example, a patterned pixel definition layer can be formed on the planarization layer through processes such as film formation, exposure, and development. The pixel definition layer is disposed between adjacent sub-pixel regions. The pixel definition layer is partially located above the anode.

[0350] In some embodiments, forming a fourth groove may include forming a first sub-groove, or forming a second sub-groove, or forming a first sub-groove and a second sub-groove.

[0351] In some embodiments, the first sub-groove and the second sub-groove may be formed by the first protrusion and the second protrusion together.

[0352] In some possible implementations, the sizes of α, α1, and α2 can be controlled by adjusting the morphology of the positive gel.

[0353] In some possible implementations, the magnitudes of β, β1, and β2 can be controlled by adjusting the morphology of the negative gel.

[0354] In some embodiments, after step S307, the processing step further includes forming a common layer and a cathode on the side of the anode and the third sub-pixel definition layer away from the substrate.

[0355] Figure 26 This is a schematic diagram of the manufacturing process of a display panel provided in an embodiment of this application.

[0356] S401, Fabrication of substrate 310. It should be understood that the substrate can be a TFT substrate, which specifically may include a base and TFT circuits and peripheral driving circuits fabricated on the base.

[0357] In some possible implementations, a TFT circuit may include an active layer, a source, a drain, a gate insulating layer, and a gate. The materials of the active layer of a TFT include, but are not limited to, LTPS, oxides, a-Si, LTPO, and organic materials.

[0358] In some possible implementations, the substrate can be a rigid substrate. Exemplarily, the substrate can be any of a glass substrate, a quartz substrate, or a ceramic substrate. For example, a glass substrate can be composed of soda-lime glass and / or borosilicate glass. These types of substrates can possess good mechanical strength and good thermal stability.

[0359] In some possible implementations, the substrate can be a flexible substrate. Exemplarily, the substrate can be composed of polymer materials, such as one or more of the following: PI, PET, PC, PEN, or COC. These polymer materials can possess good optical and mechanical properties, enabling the substrate to bend and deform, thereby allowing the display panel to meet the requirements of foldable electronic devices (such as foldable phones).

[0360] In some possible implementations, the substrate may also be composed of the inorganic material that constitutes the rigid substrate and the polymer material that constitutes the flexible substrate, and this application does not limit this.

[0361] Exemplarily, the substrate may have a multilayer structure. For example, the substrate may include a first synthetic resin layer, multiple or single inorganic layers, and a second synthetic resin layer disposed on the multiple or single inorganic layers. Each of the first and second synthetic resin layers may contain a polyimide resin.

[0362] S402, a planarization layer 320 is formed on the surface of the substrate 310.

[0363] For example, a planarization layer can be formed on a substrate through processes such as film formation, exposure, and development. The material used to obtain the planarization layer is an organic polymer such as polyimide, siloxane, polyamide, or acrylic.

[0364] S403, an anode 330 is formed on the side of the planarization layer 320 away from the substrate 310.

[0365] For example, an anode can be formed on an inorganic isolation layer through processes such as film formation, exposure, development, and etching. The anode is located in the sub-pixel region (light-emitting region). The anode material can be a metal / metal oxide / alloy such as silver, aluminum, or indium tin oxide.

[0366] S404, a first photoresist is formed on the side of the planarization layer 320 away from the substrate 310.

[0367] S405 etches the first photoresist to form multiple first protrusions.

[0368] S406, a second photoresist is formed on the side of the planarization layer 320 away from the substrate 310.

[0369] The second photoresist can be deposited on the surface of the planarization layer and fill the gaps between the multiple first protrusions.

[0370] S407 is used to etch the second photoresist.

[0371] After the second photoresist is etched, a fifth groove can be formed.

[0372] S408 is used to etch the second photoresist.

[0373] After etching, the second photoresist can form a second protrusion and a fourth groove, wherein the fourth groove may include a first sub-groove and a second sub-groove. The first protrusion and the second protrusion form a third sub-pixel definition layer having the fourth groove.

[0374] The second photoresist can be a positive photoresist, and the first photoresist can be a negative photoresist.

[0375] In some possible implementations, the sizes of α, α1, and α2 can be controlled by adjusting the morphology of the positive gel.

[0376] In some possible implementations, the magnitudes of β, β1, and β2 can be controlled by adjusting the morphology of the negative gel.

[0377] The first protrusion can be a trapezoidal structure, the first bottom wall of the fourth groove is located on the second protrusion, the first side wall is located on the second protrusion, and the second side wall is located on the first protrusion.

[0378] For example, a patterned pixel definition layer can be formed on the planarization layer through processes such as film formation, exposure, and development. The pixel definition layer is disposed between adjacent sub-pixel regions. The pixel definition layer is partially located above the anode.

[0379] In some embodiments, after step S408, the processing step further includes forming a common layer and a cathode on the side of the anode and the third sub-pixel definition layer away from the substrate.

[0380] According to the embodiments provided in this application, the fourth groove can be formed by an exposure process. Since the exposure process has high uniformity, the morphology of the fourth groove has high uniformity, which can improve the uniformity of the light-emitting stacking effect, improve the low grayscale image quality of the display panel, and increase the production yield of the display panel.

[0381] This application also provides a foldable electronic device, which includes the display panel provided in the embodiments of this application. After the foldable electronic device is folded, the mechanical properties of the display panel are less affected, and the folded display panel is not easily damaged, which is beneficial to the application of the display panel in foldable electronic devices.

[0382] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel (100) includes: Adjacent first sub-pixel regions and second sub-pixel regions arranged along a first direction, wherein the first direction is the direction of the plane in which the display panel (100) is located; substrate(110); A planarization layer (120) is located on the substrate (110). The planarization layer (120) has a first groove (121) on the side away from the substrate (110) along a second direction. The first groove (121) is located in the non-sub-pixel region between the first sub-pixel region and the second sub-pixel region. The second direction is a direction perpendicular to the plane where the display panel (100) is located. The first sub-pixel definition layer (240a) and the second sub-pixel definition layer (240b) are located in the non-sub-pixel region on the side of the planarization layer (120) away from the substrate (110). The first sub-pixel definition layer (240a) and the second sub-pixel definition layer (240b) are respectively located on both sides of the first groove (121). The first sub-pixel definition layer (240a) is close to the first sub-pixel region, and the second sub-pixel definition layer (240b) is close to the second sub-pixel region. An inorganic isolation layer (250) is provided between the first sub-pixel definition layer (240a) and the planarization layer (120), and the projection of the inorganic isolation layer (250) on the substrate (110) overlaps with the projection of the bottom wall of the first groove (121) on the substrate (110). The second groove (241a) is disposed on the side of the first sub-pixel definition layer (240a) away from the substrate (110), and / or The third groove (241b) is disposed on the side of the second sub-pixel definition layer (240b) away from the substrate (110).

2. The display panel according to claim 1, characterized in that, The second groove (241a) is continuously disposed on the first sub-pixel definition layer (240a) and / or the third groove (241b) is continuously disposed on the second sub-pixel definition layer (240b).

3. The display panel according to claim 1, characterized in that, The second groove (241a) is discontinuously disposed on the first sub-pixel definition layer (240a) and / or the third groove (241b) is discontinuously disposed on the second sub-pixel definition layer (240b).

4. The display panel according to any one of claims 1-3, characterized in that, Along the first direction, the distance between the first sub-pixel region and the second sub-pixel region is greater than or equal to 10 micrometers and less than or equal to 30 micrometers.

5. The display panel according to any one of claims 1-4, characterized in that, Along the first direction, the difference between the size of the first groove (121) and the size of the projection of the inorganic isolation layer (250) onto the bottom wall of the first groove (121) along the second direction is greater than or equal to 3 micrometers and less than or equal to 24 micrometers.

6. The display panel according to any one of claims 1-5, characterized in that, Along the first direction, the size of the second groove (241a) is greater than or equal to 1 micrometer and less than or equal to 20 micrometers; and / or Along the first direction, the size of the third groove (241b) is greater than or equal to 1 micrometer and less than or equal to 20 micrometers.

7. The display panel according to any one of claims 1-6, characterized in that, Between the first sub-pixel region and the second sub-pixel region, along the first direction, the distance between the first sub-pixel region and the end of the inorganic isolation layer (250) away from the first sub-pixel region along the first direction is greater than or equal to 3 micrometers and less than or equal to 24 micrometers.

8. The display panel according to any one of claims 1-7, characterized in that, Between the first sub-pixel region and the second sub-pixel region, along the first direction, the distance between the end of the first groove (121) near the second sub-pixel region and the second sub-pixel region is greater than or equal to 3 micrometers and less than or equal to 24 micrometers.

9. The display panel according to any one of claims 1-8, characterized in that, An inorganic isolation layer (250) is provided between the second sub-pixel definition layer (240b) and the planarization layer (120).

10. The display panel according to claim 9, characterized in that, The display panel (100) also includes: The anode (210) is located on the side of the inorganic isolation layer (250) away from the substrate (110), and the anode (210) is located in the first sub-pixel region and the second sub-pixel region respectively; A common layer (230) is located on the side of the first sub-pixel definition layer (240a) and the anode (210) away from the substrate (110), and on the side of the second sub-pixel definition layer (240b) and the anode (210) away from the substrate (110), respectively. The common layer (230) is used to transport charge carriers. The cathode (220) is located on the side of the common layer (230) away from the substrate (110); Along the second direction, in the non-sub-pixel region near the first sub-pixel region, the projections of the anode (210), the common layer (230), and the cathode (220) fall within the inorganic isolation layer (250).

11. The display panel according to claim 10, characterized in that, The common layer (230) includes a first light-emitting stack (231), a charge-generating layer (232), and a second light-emitting stack (233) stacked along the second direction. The first light-emitting stack (231) includes a first hole control layer (2311), a first light-emitting layer (2313), and a first electronic control layer (2312) stacked along the second direction and away from the substrate (110). The second light-emitting stack (233) includes a second hole control layer (2331), a second light-emitting layer (2333), and a second electronic control layer (2332) stacked along the second direction and away from the substrate (110).

12. The display panel according to any one of claims 1-11, characterized in that, The inorganic isolation layer (250) is made of any one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or indium tin oxide.

13. A display panel, characterized in that, The display panel includes: Adjacent first sub-pixel regions and second sub-pixel regions arranged along a first direction, wherein the first direction is the direction of the plane in which the display panel is located; substrate; A planarization layer is located on the substrate; A third sub-pixel definition layer is located in the non-sub-pixel region on the side of the planarization layer away from the substrate. This non-sub-pixel region is situated between the first sub-pixel region and the second sub-pixel region. The third sub-pixel definition layer includes: The fourth groove is located on the side of the third sub-pixel definition layer away from the substrate; The fourth groove includes a first bottom wall, a first side wall and a second side wall opposite to each other in the first direction, the angle between the first bottom wall and the first side wall is α, and the angle between the first bottom wall and the second side wall is β, wherein α and β are different.

14. The display panel according to claim 13, characterized in that, The fourth groove is closer to the first sub-pixel region than the second sub-pixel region.

15. The display panel according to claim 13, characterized in that, The fourth groove is closer to the second sub-pixel region than the first sub-pixel region.

16. The display panel according to claim 13, characterized in that, The fourth groove includes a first sub-groove and a second sub-groove, the first sub-groove being close to the first sub-pixel region and the second sub-groove being close to the second sub-pixel region.

17. The display panel according to claim 16, characterized in that, The angle between the first bottom wall of the first sub-groove and the first side wall of the first sub-groove is α1, and the angle between the first bottom wall of the first sub-groove and the second side wall of the first sub-groove is β1, wherein α1 and β1 are different; The angle between the first bottom wall of the second sub-groove and the first side wall of the second sub-groove is α2, and the angle between the first bottom wall of the second sub-groove and the second side wall of the second sub-groove is β2, wherein α2 and β2 are different.

18. The display panel according to claim 16 or 17, characterized in that, The display panel also includes: The fifth groove is located on the side of the third sub-pixel definition layer away from the substrate, and is located between the first sub-groove and the second sub-groove.

19. The display panel according to claim 17 or 18, characterized in that, The second sidewall of the first sub-groove is closer to the geometric center of the third sub-pixel definition layer than the first sidewall of the first sub-groove, and α1 > β1; The second sidewall of the second sub-groove is closer to the geometric center of the third sub-pixel definition layer than the first sidewall of the second sub-groove, and α2 > β2.

20. The display panel according to any one of claims 13-19, characterized in that, The second sidewall is closer to the geometric center of the third sub-pixel definition layer than the first sidewall, where α > β.

21. The display panel according to any one of claims 13-20, characterized in that, The display panel also includes: The anode is located on the side of the planarization layer away from the substrate, and the anode is located in the first sub-pixel region and the second sub-pixel region respectively; A common layer is located on the side of the third sub-pixel definition layer and the anode that is away from the substrate, respectively, and the common layer is used to transport charge carriers; The cathode is located on the side of the common layer away from the substrate.

22. The display panel according to claim 21, characterized in that, The common layer includes a third light-emitting stack and a charge-generating layer stacked along a second direction. In the non-sub-pixel region, the third light-emitting stack is located above the third sub-pixel defining layer, and the second direction is perpendicular to the plane where the display panel is located. Along the second direction, the projection of the third light-emitting stack on the third sub-pixel definition layer does not overlap with the fourth groove, while the projection of the charge-generating layer on the third sub-pixel definition layer overlaps with the fourth groove.

23. The display panel according to claim 22, characterized in that, The common layer further includes a fourth light-emitting stack near the first sub-pixel region and a fifth light-emitting stack near the second sub-pixel region; In the non-sub-pixel region, the fourth light-emitting stack and the fifth light-emitting stack are located above the charge-generating layer; Along the second direction, the projections of the fourth light-emitting stack on the third sub-pixel definition layer and the projections of the fifth light-emitting stack on the third sub-pixel definition layer overlap and respectively overlap with the fourth groove.

24. A display module, characterized in that, include: Cover plate (21) and display panel (100) as claimed in any one of claims 1 to 23.

25. The display module according to claim 24, characterized in that, The display module (20) also includes a polarizer (22) located between the cover plate (21) and the display panel (100).

26. An electronic device, characterized in that, include: The circuit board assembly (50) and the display module (20) as claimed in claim 24 or 25, wherein the circuit board assembly (50) is electrically connected to the display module (20).

27. A method for manufacturing a display panel, characterized in that, The display panel (100) includes a first sub-pixel region and a second sub-pixel region arranged along a first direction, wherein the first direction is the direction of the plane in which the display panel (100) is located; The method includes: A substrate (110) and a planarization layer (120) are provided on the substrate (110). A first groove (121) is provided on the side of the planarization layer (120) away from the substrate (110) along a second direction. The first groove (121) is located in a non-sub-pixel region between the first sub-pixel region and the second sub-pixel region. The second direction is a direction perpendicular to the plane where the display panel (100) is located. A first sub-pixel definition layer (240a) and a second sub-pixel definition layer (240b) are disposed in the non-sub-pixel region on the side of the planarization layer (120) away from the substrate (110). The first sub-pixel definition layer (240a) and the second sub-pixel definition layer (240b) are respectively located on both sides of the first groove (121). The first sub-pixel definition layer (240a) is close to the first sub-pixel region, and the second sub-pixel definition layer (240b) is close to the second sub-pixel region. An inorganic isolation layer (250) is provided between the first sub-pixel definition layer (240a) and the planarization layer (120), and the projection of the inorganic isolation layer (250) on the substrate (110) overlaps with the projection of the bottom wall of the first groove (121) on the substrate (110). A second groove (241a) is provided, the second groove (241a) being disposed on the side of the first sub-pixel definition layer (240a) away from the substrate (110), and / or A third groove (241b) is provided on the side of the second sub-pixel definition layer (240b) away from the substrate (110).

28. The preparation method according to claim 27, characterized in that, The second groove (241a) is continuously provided on the first sub-pixel definition layer (240a) and / or the third groove (241b) is continuously provided on the second sub-pixel definition layer (240b).

29. The preparation method according to claim 28, characterized in that, The second groove (241a) is discontinuously disposed on the first sub-pixel definition layer (240a) and / or the third groove (241b) is discontinuously disposed on the second sub-pixel definition layer (240b).

30. A method for manufacturing a display panel, characterized in that, The display panel includes a first sub-pixel region and a second sub-pixel region arranged along a first direction, wherein the first direction is the direction of the plane in which the display panel is located. The method includes: A substrate and a planarization layer are provided on the substrate, and a third sub-pixel definition layer is provided in a non-sub-pixel region on the side of the planarization layer away from the substrate; A fourth groove is provided on the side of the third sub-pixel definition layer away from the substrate. The fourth groove includes a first bottom wall, a first side wall and a second side wall opposite to each other in the first direction. The angle between the first bottom wall and the first side wall is α, and the angle between the first bottom wall and the second side wall is β. α and β are different.

31. The preparation method according to claim 30, characterized in that, The fourth groove includes a first sub-groove and a second sub-groove, and the method further includes: A first sub-groove and a second sub-groove are provided, with the first sub-groove being close to the first sub-pixel area and the second sub-groove being close to the second sub-pixel area.

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