Material chemistry calculation simulation guided directional experiment verification and performance test method

Abstract

This invention discloses a method for directional experimental verification and performance testing guided by computational simulation in materials chemistry, belonging to the field of materials performance testing technology. The method includes: acquiring the structural parameters of semiconductor devices and initial parameters of interface defects; calculating the characteristic time constant of carrier trapping by interface traps; simulating and generating a theoretical capacitance-voltage hysteresis loop; then performing bidirectional voltage scan tests within a sensitive scan rate range; finally, updating the inversion parameters and resimulating, iteratively adjusting until the characteristic deviation between the theoretical loop and the measured data meets the convergence condition, thus outputting an interface state density distribution map. This invention, through computational simulation-guided directional experiments, achieves accurate capture and non-destructive in-situ characterization of the dynamic response characteristics of interface states, effectively establishing the dynamic structure-property relationship between microscopic interface defects and macroscopic device performance, and significantly improving the accuracy and reliability of interface defect parameter inversion.

Description

Technical Field

[0001] This invention relates to the field of materials performance testing technology, and in particular to a method for targeted experimental verification and performance testing guided by materials chemical calculation simulation. Background Technology

[0002] Performance testing methods for optoelectronic and semiconductor materials require continuous updating and improvement. Traditional performance testing often relies on single technical means, while emerging optoelectronic and semiconductor materials often require more multi-dimensional and refined testing methods. Combining simulation and experimentation can provide a new perspective for performance testing. For optoelectronic and semiconductor materials, existing methods for targeted experimental verification and performance testing guided by materials chemistry computational simulations mainly follow a closed-loop implementation process of "theoretical prediction - targeted preparation - multi-dimensional verification - feedback optimization".

[0003] First, atomic-level microscopic models of materials are constructed based on first-principles calculations or molecular dynamics to theoretically predict key properties such as band structure, density of states, optical absorption coefficient, and carrier mobility. This clarifies the structure-property relationship and screens out target candidate systems, providing clear theoretical guidance for experimental synthesis. Subsequently, based on the optimal composition and structural parameters predicted by simulation, a targeted synthesis strategy is formulated to precisely prepare the target material, effectively avoiding the blindness of traditional trial-and-error methods. In the crucial experimental verification and performance testing stages, addressing the difficulty of traditional single testing methods in comprehensively characterizing the complex properties of emerging materials, a simulation-guided multidimensional refined testing strategy is adopted: on the one hand, combining the crystal structure and chemical bonding information predicted by simulation, X-ray diffraction analysis, spherical aberration electron microscopy, and X-ray photoelectron spectroscopy are used to refine the microstructure and elemental valence states of the material at multiple scales; on the other hand, dynamic and in-situ tests are conducted focusing on the carrier behavior and defect mechanisms revealed by simulation, such as using transient fluorescence spectroscopy to verify carrier lifetime and using Kelvin probe force microscopy to test surface potential distribution. By cross-validating and correlating microscopic simulation data with macroscopic multidimensional test results, we can not only confirm whether the actual performance of the material meets expectations, but also gain a deeper understanding of the microscopic physical mechanisms behind performance differences. Finally, the experimental test data is fed back into the computational model to correct simulation parameters or boundary conditions. Through iterative cycles, the material design and preparation process are continuously optimized, thereby achieving efficient and precise development of optoelectronic and semiconductor materials.

[0004] For example, Chinese patent application CN118688407B discloses a multi-dimensional performance testing system suitable for semiconductor material processing, including: a performance testing module, a test analysis module, a component evaluation module, and a centralized analysis module. The performance testing module, test analysis module, component evaluation module, and centralized analysis module are sequentially connected in communication; the component evaluation module and centralized analysis module are both connected in communication with the performance testing module; the timing of component evaluation is analyzed according to a set marking judgment logic, and the overall performance status of the entire test component is evaluated at an appropriate time based on the test results of the test objects that have been tested. This dynamic test analysis method improves the efficiency of semiconductor material performance testing.

[0005] However, in the process of implementing the inventive technical solution in the embodiments of this application, it was found that the above-mentioned technology has at least the following technical problems:

[0006] The performance of semiconductor devices (such as heterojunction solar cells) is highly dependent on interface quality. However, computational simulations typically assume that the interface is an ideal model with atomically flat and perfectly bonded surfaces, neglecting microscopic defects such as interface states, component interdiffusion layers, and dangling bonds that are prevalent in actual fabrication processes. This leads to significant discrepancies between theoretical predictions and experimental results. Existing interface testing technologies face severe challenges in the verification process: Specifically, mainstream characterization methods such as X-ray photoelectron spectroscopy and transmission electron microscopy are destructive, easily introducing artificial damage or altering the original state of the interface during sample preparation, making it difficult to obtain a true physical image of the interface; secondly, existing technologies lack the ability to capture the dynamic evolution of interface state density and its impact on carrier transport in situ and in real time under optical, electrical, and thermal conditions, making it difficult to establish a dynamic structure-property relationship between microscopic interface defects and macroscopic device performance, severely hindering accurate verification and optimization for interface testing engineering. Summary of the Invention

[0007] To address the technical problem in existing semiconductor material performance testing methods that struggle to capture the dynamic evolution of interface defects and their impact on device performance in real-time and in situ, thus preventing the establishment of a dynamic structure-property relationship between microscopic defects and device performance, this invention provides a method for directional experimental verification and performance testing guided by materials chemistry computational simulation. The technical solution is as follows:

[0008] A method for directional experimental verification and performance testing guided by materials chemistry computational simulation is proposed. This method includes: acquiring the structural parameters and initial parameters of interface defects in a semiconductor device; calculating the characteristic time constant for carrier trapping in interface traps based on the structural parameters and initial parameters; determining a sensitive scan rate range reflecting the dynamic response characteristics of the interface state based on the matching relationship between the characteristic time constant and the voltage scan period; simulating the dynamic hysteresis behavior of interface charges based on the structural parameters, initial parameters of interface defects, and the sensitive scan rate range to generate a theoretical capacitance voltage hysteresis loop; performing bidirectional voltage scan tests on the semiconductor device using the scan rate within the sensitive scan rate range and acquiring measured capacitance voltage hysteresis loop data; and calculating the measured capacitance voltage. The integral value of the hysteresis loop area is used to obtain the interface charge density based on the physical mapping relationship between the hysteresis area and the interface trap charge density. The defect energy level position is analyzed by combining the loop broadening characteristics to obtain the interface defect inversion parameters. The interface defect inversion parameters are used as the initial parameters of the interface defect to regenerate the theoretical capacitance voltage hysteresis loop. The characteristic deviation between the regenerated theoretical capacitance voltage hysteresis loop and the measured capacitance voltage hysteresis loop data is calculated. It is determined whether the characteristic deviation meets the preset convergence condition. If not, the initial parameters of the interface defect are adjusted with the goal of minimizing the characteristic deviation and the simulation is repeated until the characteristic deviation meets the preset convergence condition. Based on the initial parameters of the interface defect that meet the preset convergence condition, the interface state density distribution map is output.

[0009] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0010] This invention constructs a closed-loop feedback mechanism of "computational simulation prediction - targeted experimental verification - parameter iterative optimization". By pre-locking the sensitive scan rate range through computational simulation, blind scanning tests are avoided, significantly improving the targeting and efficiency of the tests. Simultaneously, by updating the model using inversion parameters and minimizing the characteristic deviation between theoretical and measured data through iterative calculations, errors caused by the initial ideal model assumptions are effectively corrected. This ensures that the final output interface state density distribution map has extremely high accuracy and reliability, providing solid data support for the precise verification and optimization of semiconductor device interface engineering.

[0011] Specifically, in existing technologies, mainstream characterization methods such as X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) are destructive, easily introducing artificial damage or altering the original state of the interface during sample preparation, and are difficult to test under actual operating conditions. In contrast, this invention employs computationally simulated bidirectional voltage scanning testing, effectively avoiding damage to the sample caused by physical slicing or ion etching. It can capture the dynamic evolution information of the interface state density in situ and in real time under the actual optical, electrical, and thermal operating conditions of the device, thereby obtaining a more realistic and accurate physical image of the interface that closely reflects the actual operating state.

[0012] Meanwhile, existing technologies often conduct microstructure observations or macroscopic performance tests independently, lacking effective means to correlate the two, making it difficult to clarify the specific impact mechanism of microscopic defects on macroscopic carrier transport. This invention calculates the characteristic time constant of carrier trapping by interface traps and matches it with the voltage scan period, accurately pinpointing the sensitive scan rate range reflecting the dynamic response characteristics of interface states. Based on this, by analyzing the area integral and broadening characteristics of the measured capacitor voltage hysteresis loop, it successfully correlates the microscopic interface charge density, defect energy level positions, and macroscopic electrical hysteresis response, filling the gap in existing technologies for establishing the dynamic structure-property relationship between microscopic defects and device performance.

[0013] Furthermore, existing computational simulations typically assume an atomically smooth and perfectly bonded interface, neglecting defects commonly found in actual fabrication processes, leading to significant discrepancies between theoretical predictions and experimental results. This invention constructs a closed-loop feedback mechanism. By introducing experimental data to continuously correct the initial parameters of interface defects in the theoretical model, it effectively eliminates errors caused by the ideal model assumption. Compared to existing methods that rely solely on theoretical calculations or experimental tests, this invention significantly improves the accuracy and reliability of the interface density of states distribution map by minimizing the characteristic deviation between theoretical and experimental data.

[0014] Furthermore, existing electrical testing methods often require extensive frequency or rate scans to find effective signals, resulting in low testing efficiency and susceptibility to noise interference. This invention utilizes computational simulation to pre-determine the sensitive scan rate range, giving subsequent experimental verification a clear direction and avoiding blind full-parameter domain scanning. This not only significantly shortens testing time but also effectively improves the signal-to-noise ratio and sensitivity of the test signal, providing an efficient technical means for the precise verification and optimization of semiconductor device interface engineering.

[0015] In summary, this invention can capture the dynamic evolution of interface states in real time and in situ by combining computational simulation with experimental verification, accurately reflecting the impact of micro-interface defects on macro-device performance. It avoids interface damage and human error that may be introduced in traditional testing techniques, providing strong technical support for the optimized design and performance improvement of semiconductor devices, and effectively promoting the accurate testing and optimization of semiconductor devices such as heterojunction solar cells. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1A flowchart of a material chemistry calculation simulation-guided directional experimental verification and performance testing method provided in the embodiments of this application;

[0018] Figure 2 A flowchart illustrating the process of obtaining the hysteresis area integral value for the material chemistry calculation simulation-guided directional experimental verification and performance testing method provided in this application embodiment. Detailed Implementation

[0019] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present disclosure are shown in the drawings, it should be understood that embodiments of the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure.

[0020] It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure. In the description of the embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "this embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects.

[0021] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0022] With the development of semiconductor materials, especially in the research of high-efficiency devices such as heterojunction solar cells, interface quality has become a key factor affecting device performance testing. Interface defects, such as interface states, component interdiffusion layers, and dangling bonds, are widespread in the semiconductor device manufacturing process, significantly impacting carrier transport and device performance. However, existing testing techniques often suffer from sample preparation damage or lack the ability to capture the dynamic evolution of interface defects in situ and in real time, making it impossible to accurately establish the dynamic structure-property relationship between microscopic defects and macroscopic performance. This limitation severely restricts the performance optimization of semiconductor devices and the accurate verification of interface defect testing engineering. Therefore, a new method is urgently needed to effectively solve this technical bottleneck.

[0023] like Figure 1The diagram shows a flowchart of the material chemistry computational simulation-guided directional experimental verification and performance testing method provided in this application embodiment. This invention successfully combines the microscopic analysis of semiconductor device interface defects with macroscopic performance testing through the synergistic effect of material chemistry computational simulation and directional experimental verification, forming a systematic testing and optimization method. This complementary synergy between computation and experimentation greatly improves the efficiency and accuracy of semiconductor device performance testing, promotes the establishment of a dynamic structure-property relationship between microscopic interface defects and device macroscopic performance, and provides strong technical support for the precise design and optimization of semiconductor devices, with broad engineering application prospects.

[0024] The first step of the material chemistry computational simulation-guided directional experimental verification and performance testing method is as follows: obtain the structural parameters of the semiconductor device and the initial parameters of the interface defects, and calculate the characteristic time constant of the interface trap capturing carriers based on the structural parameters and the initial parameters of the interface defects. This step lays the foundation for the entire analysis process, ensures the accuracy of subsequent simulations and experiments, and makes the data-driven process reliable and scientific.

[0025] It should be added that the structural parameters include semiconductor substrate doping concentration, oxide layer thickness, oxide layer dielectric constant, semiconductor dielectric constant, device area, ambient temperature, and effective mass of semiconductor material. Specifically, the structural parameters constitute the geometric and material basis of the semiconductor device physical model, and all have undergone de-normalization. Their specific definitions and acquisition methods are as follows: Semiconductor substrate doping concentration is defined as the concentration of impurity atoms in the substrate material. This parameter determines the Fermi level position and depletion layer width of the semiconductor. Its value can be estimated based on the ion implantation dose in the device fabrication process, or extracted by inverting the minimum capacitance value of the inversion region through high-frequency capacitance-voltage testing of a standard MOS structure; Oxide layer thickness is defined as the geometric thickness of the insulating dielectric layer. This parameter directly determines the size of the oxide layer capacitance. It can be measured non-destructively using an elliptic polarization spectrometer, or observed through a transmission electron microscope. The sample cross-section is read directly; the dielectric constant of the oxide layer and the dielectric constant of the semiconductor respectively characterize the dielectric energy storage capacity of the insulating layer and the semiconductor material. They are usually obtained by consulting standard property manuals based on the material type, or they can be calculated by combining the measured capacitance value and geometric thickness; the device area is defined as the effective electrode area used for electrical testing. This parameter is used to normalize the capacitance and can be determined based on the design dimensions of the photolithography pattern, or measured using a high-precision optical microscope on the actual fabricated electrodes; the ambient temperature is defined as the thermodynamic temperature of the device during the test. This parameter affects the thermal emission rate of charge carriers and is precisely set and recorded using a temperature-controlled probe station or environmental test chamber; the effective mass of the semiconductor material is defined as the inertial mass of the charge carriers after considering the influence of the lattice periodic potential field. It is determined by consulting semiconductor physics databases based on the specific crystal orientation and band structure of the semiconductor material and is used to calculate the thermal velocity and density of states of the charge carriers.

[0026] The initial parameters for interface defects include the initial value of the interface density of states, the defect energy level location, and the carrier trapping cross section. These initial parameters, serving as the starting variables for iterative simulation calculations, have all undergone de-normalization. Their specific definitions and settings are as follows: The initial value of the interface density of states is defined as the number of interface defects per unit energy interval and per unit area. In the initial stage of the simulation, this value can be set as a rough estimate based on process experience or preset with reference to low-frequency noise test results. Subsequent iterations will optimize and approximate the true value. The defect energy level location is defined as the energy position of the interface defect within the semiconductor bandgap, typically expressed as an energy offset relative to the conduction band bottom or valence band top. The initial setting can be assumed to be a deep energy level near the center of the bandgap, or set as an energy level sequence conforming to a specific statistical distribution (such as a U-shaped distribution), depending on the device's process characteristics. The carrier trapping cross section is defined as the effective collision cross-sectional area for the interface trap to capture electrons or holes. This parameter reflects the defect's ability to trap carriers. The initial value is usually set with reference to literature reports on similar semiconductor material systems and dynamically adjusted in subsequent steps based on the broadening characteristics of the hysteresis loop. The clear definition and acquisition of the above parameters provide the necessary data support for the subsequent accurate calculation of the characteristic time constant of carriers captured by the interface trap.

[0027] It should also be noted that the characteristic time constant for carrier trapping in interface traps, calculated based on structural parameters and initial parameters of interface defects, specifically includes:

[0028] First, the thermal velocity of charge carriers is calculated based on the ambient temperature and the effective mass of the semiconductor material. According to the principles of statistical thermodynamics, the thermal velocity of charge carriers is directly related to temperature and material properties. Specifically, the thermal velocity of charge carriers is calculated by substituting the obtained ambient temperature and the effective mass of the semiconductor material into the thermal velocity formula.

[0029] Secondly, based on the Poisson equation and structural parameters, the correspondence between the gate voltage and the carrier concentration on the semiconductor surface is determined, and the surface carrier concentration under the current scanning voltage is obtained. The process of carrier trapping by interface traps occurs on the semiconductor surface, and the surface carrier concentration is regulated by the gate voltage. In specific implementation, based on semiconductor physics theory and the Poisson equation, combined with the semiconductor substrate doping concentration, oxide layer thickness, oxide layer dielectric constant, and semiconductor dielectric constant in the structural parameters, a numerical mapping relationship between the gate voltage and the semiconductor surface potential and surface carrier concentration is established.

[0030] In one specific embodiment, the potential distribution of the applied gate voltage on the oxide layer and semiconductor substrate is simulated by solving the one-dimensional Poisson equation. When the gate voltage changes, the electric field strength and potential on the semiconductor surface are calculated based on the electroneutrality condition and the change in depletion layer width. Then, using the Boltzmann distribution relationship, the surface carrier concentration corresponding to the current scanning voltage point is accurately calculated. This step achieves a precise conversion from macroscopic bias voltage to microscopic interface carrier concentration.

[0031] Next, based on the SRH (Shockley-Read-Hall) trapping kinetics model, the characteristic time constant of carrier trapping by interface traps is determined by the trapping coefficient and the surface carrier concentration. Specifically, the carrier trapping coefficient is obtained by calculating the product of the carrier trapping cross section and the carrier thermal velocity, and the reciprocal of the product of the carrier trapping coefficient and the surface carrier concentration is determined as the characteristic time constant of carrier trapping by interface traps.

[0032] By combining the above steps, calculating the characteristic time constant of carrier trapping in interface traps based on structural parameters and initial parameters of interface defects enables accurate modeling of interface defect trapping behavior. This facilitates a deeper understanding of the interaction between carriers and interface defects, providing a more reliable physical model for optimizing device design. Furthermore, this calculation process can provide more accurate predictions of the dynamic behavior of interface charges for subsequent capacitor-voltage hysteresis loop analysis, ensuring efficient improvement and precise control of device performance.

[0033] As a further approach, in semiconductor devices, the presence of interface defects, especially near-interface traps in the oxide layer, significantly impacts carrier trapping and transport behavior. Therefore, introducing the perpendicular distance of the defect from the semiconductor interface and the electron wavefunction attenuation coefficient, and calculating the tunneling probability based on these factors, is an important supplement to existing interface defect models, enabling a more accurate description of the interaction between carriers and near-interface traps. This analytical step helps to more comprehensively capture the dynamic influence of interface states on device performance, particularly providing more accurate predictions when dealing with high-frequency signals and high-voltage device behavior. Specifically, calculating the characteristic time constant of carrier trapping by interface traps also includes:

[0034] First, for near-interface traps in the oxide layer, the vertical distance from the defect to the semiconductor interface and the electron wave function attenuation coefficient are introduced. The vertical distance is defined as the vertical distance from the geometric center of the oxide trap to the physical interface of the semiconductor / oxide layer, in nanometers. The electron wave function attenuation coefficient characterizes the rate at which the electron wave function decays with distance in the oxide barrier. Its value depends on the barrier height of the oxide layer and the effective mass of the charge carriers. It is usually obtained by querying a material property database or by calculating based on a barrier model.

[0035] Secondly, the tunneling probability of charge carriers is calculated based on the vertical distance and the attenuation coefficient of the electron wavefunction. The tunneling probability decreases exponentially with increasing vertical distance. The product of the charge carrier trapping cross section and the tunneling probability is determined as the effective trapping cross section. The characteristic time constant of the interface traps for trapping charge carriers is updated based on the effective trapping cross section. According to the quantum mechanical tunneling theory, the probability of charge carriers interacting with traps within the oxide layer decreases rapidly with increasing distance. This embodiment uses an exponential decay model to calculate the tunneling probability. The specific calculation formula is as follows: ;in, Indicates the tunneling probability. Represents the attenuation coefficient of the electron wave function. Indicates vertical distance.

[0036] Through the above steps, this invention can not only simulate ideal interface states, but also accurately quantify the dynamic response speed of near-interface traps in oxide layers at different depths from the interface. This makes the calculation model of the characteristic time constant more consistent with the transport physics of charge carriers at the microscale, laying a theoretical foundation for the subsequent accurate separation of interface states and near-interface traps.

[0037] The second step of the materials chemistry computational simulation-guided directional experimental verification and performance testing method is as follows: Based on the matching relationship between the characteristic time constant and the voltage scan period, the sensitive scan rate range used to reflect the dynamic response characteristics of the interface state is determined. Then, based on the structural parameters, the initial parameters of the interface defects, and the sensitive scan rate range, the dynamic hysteresis behavior of the interface charge is simulated to generate the theoretical capacitance voltage hysteresis loop. This step helps to establish the dynamic characteristics of the interface defects, which can provide an accurate time scale for subsequent testing and theoretical simulation, making the experimental process more consistent with the theoretical calculation.

[0038] It should be noted that, based on the matching relationship between the characteristic time constant and the voltage scan period, the sensitive scan rate range used to reflect the dynamic response characteristics of the interface state is determined, specifically including:

[0039] The characteristic frequency of the interface state response is determined based on the characteristic time constant. Using the scan rate corresponding to the characteristic frequency as a benchmark, a scan rate range where the scan period and the characteristic time constant are on the same order of magnitude is selected as the sensitive scan rate range. According to the dynamic response theory of interface states, when the scan period and the characteristic time constant are on the same order of magnitude, the charging and discharging process of the interface state is comparable to the rate of change of the applied voltage. At this time, the interface state neither completely follows the voltage change (non-quasi-static) nor is it completely frozen (non-high-frequency cutoff), and the dynamic hysteresis behavior of the interface charge is most significant. Therefore, this embodiment uses the scan rate corresponding to the characteristic frequency as the benchmark center point, that is, selects a scan rate that satisfies the condition that the scan period and the characteristic time constant are on the same order of magnitude as the benchmark rate.

[0040] It is important to understand that the sensitive scan rate range is the rate range within which the interface state generates the maximum hysteresis response window during charging and discharging. The lower limit of the sensitive scan rate range is determined by the quasi-static condition that the interface state can completely follow voltage changes, while the upper limit is determined by the high-frequency condition that the interface state response is completely frozen. To ensure that the test covers the complete transition window of the interface state response, this embodiment determines the upper and lower limits of the range based on physical boundary conditions: Lower limit rate determination: determined based on quasi-static conditions. When the scan rate is too low, causing the scan period to be much larger than the characteristic time constant, the interface state has sufficient time to complete the charging and discharging process and can completely follow changes in the applied voltage. At this point, the hysteresis effect disappears, and the capacitance-voltage curve converges to a single quasi-static curve. Therefore, the rate corresponding to the scan period value starting to significantly exceed the characteristic time constant (e.g., the scan period value is greater than ten times the characteristic time constant) is set as the lower limit of the sensitive scan rate range. Upper limit rate determination: determined based on high-frequency freezing conditions. When the scan rate is too high, causing the scan period to be much smaller than the characteristic time constant, the interface states cannot complete carrier capture or emission within the time window of voltage change. The interface state response is "frozen," and its contribution to capacitance is only manifested as a fixed geometric capacitance; the hysteresis effect also disappears. Therefore, the rate at which the scan period value begins to be significantly smaller than the characteristic time constant (e.g., the scan period value is less than 0.1 times the characteristic time constant) is set as the upper limit of the sensitive scan rate range.

[0041] By determining the sensitive scan rate range based on the matching relationship between the characteristic time constant and the voltage scan period, this invention ensures a perfect match between the scan rate and the dynamic response characteristics of the interface state during the experiment. The precise determination of the sensitive scan rate range not only maximizes the reflection of the dynamic hysteresis response of the interface state but also improves the reliability and accuracy of experimental data, thus providing crucial support for interface defect analysis and semiconductor device performance optimization.

[0042] It should also be noted that generating the theoretical capacitor voltage hysteresis loop specifically includes: first, constructing a bidirectional voltage scanning sequence, setting the voltage scanning rate and scanning step size according to the sensitive scanning rate range; second, establishing a dynamic differential equation describing the charging and discharging rate of interface trap charges based on the characteristic time constant, and solving the dynamic differential equation using the numerical integration method to obtain the instantaneous value of the interface trap charge corresponding to each voltage point during the bidirectional scanning process.

[0043] Specifically, to describe the non-instantaneous response characteristics of interface trap charge with voltage changes, a dynamic differential equation describing the charge and discharge rate of interface trap charge is established based on the characteristic time constant. At any given time, the rate of change of interface trap charge is determined by the difference between the equilibrium charge and the instantaneous charge at the current voltage, as shown in the following equation: ;in, This represents the rate of change of charge in the interface trap. Indicates the balance charge. Indicates instantaneous charge quantity. The characteristic time constant can be calculated based on the Fermi level position and interface state density distribution under the current voltage. Since this differential equation is difficult to solve analytically, this embodiment uses numerical integration methods (such as the fourth-order Runge-Kutta method or the forward Euler method) to discretize and solve it. Through point-by-point iterative calculation of time, the instantaneous values ​​of interface trap charges at each voltage point during the bidirectional scan are obtained. This step successfully simulates the physical process of interface state charging and discharging lagging behind voltage changes, which is the physical root cause of hysteresis loop formation.

[0044] Next, based on the gate voltage drift caused by the instantaneous value of the interface trap charge, and combined with the physical relationship between the semiconductor surface potential and the total capacitance, the theoretical capacitance value is calculated, generating the theoretical capacitance voltage hysteresis loop. During the forward and reverse scanning processes, the difference in the instantaneous value of the interface trap charge leads to different theoretical capacitance values ​​under the same gate voltage, thus forming two separate curves in the voltage-capacitance coordinate system, namely the theoretical capacitance voltage hysteresis loop.

[0045] The process of generating the theoretical capacitance-voltage hysteresis loop provides a refined theoretical framework for device performance analysis by accurately modeling the dynamic response of interface trap charges. Through a combination of bidirectional scan sequences, solving dynamic differential equations, numerical integration, and the physical relationship between potential and capacitance, the dynamic response of the interface states can be comprehensively and accurately described, ensuring that the generated theoretical loop reflects the electrical behavior of the actual device. This process not only provides a powerful tool for interface state analysis but also offers a theoretical basis for the precise optimization of device performance.

[0046] The third step of the materials chemistry computational simulation-guided directional experimental verification and performance testing method is as follows: A bidirectional voltage scan test is performed on the semiconductor device using a scan rate within the sensitive scan rate range, and measured capacitance voltage hysteresis loop data is collected. The loop area integral value of the measured capacitance voltage hysteresis loop data is calculated. Based on the physical mapping relationship between the hysteresis area and the interface trap charge density, the interface charge density is obtained. The defect energy level position is analyzed by combining the loop broadening characteristics to obtain the interface defect inversion parameters. By accurately simulating the dynamic behavior of the interface charge, this step provides a theoretical basis for actual testing and can accurately predict the response characteristics of the interface charge, helping to optimize experimental design.

[0047] As a further option, such as Figure 2 The diagram shown is a flowchart of obtaining the hysteresis area integral value of the material chemistry calculation simulation-guided directional experimental verification and performance testing method provided in this application embodiment. (Refer to...) Figure 2Calculate the integral value of the hysteresis loop area of ​​the measured capacitor voltage hysteresis loop data, specifically including:

[0048] First, after selecting one or more target scan rates within the sensitive scan rate range, forward voltage scanning and reverse voltage scanning are performed on the semiconductor device to acquire forward scan capacitor voltage data sequences and reverse scan capacitor voltage data sequences, respectively. First, the capacitor voltage data sequence during the forward scan process is acquired from the starting voltage to the ending voltage. Then, the reverse scan is immediately performed from the ending voltage back to the starting voltage to acquire the capacitor voltage data sequence during the reverse scan process.

[0049] Next, voltage coordinate normalization is performed on the forward scan capacitor voltage data sequence and the reverse scan capacitor voltage data sequence. Then, a measured capacitor voltage hysteresis loop with consistent voltage coordinates is constructed by interpolation algorithm (such as linear interpolation, cubic spline interpolation or nearest neighbor interpolation).

[0050] Secondly, the difference between the reverse scanning capacitance value and the forward scanning capacitance value under the same voltage coordinate in the measured capacitor voltage hysteresis loop is calculated. The difference is then integrated within the test voltage range to obtain the loop area integral value. The loop area integral value is used to characterize the total charge exchange of the interface trap during the charging and discharging process.

[0051] By acquiring forward and reverse scan data, normalizing voltage coordinates, interpolating, and calculating the loop area integral, this invention can accurately quantify the total charge exchange of interface traps during charging and discharging. This method not only improves the processing accuracy of measured data but also provides an important analytical tool for the charge response characteristics of interface states through quantitative calculation of the loop area. This makes interface defect analysis more detailed and provides reliable data support for optimizing semiconductor device performance.

[0052] It should also be noted that the interface charge density is obtained based on the physical mapping relationship between the hysteresis area and the interface trap charge density, and the defect energy level positions are analyzed by combining the loop broadening feature to obtain the interface defect inversion parameters, specifically including:

[0053] First, the interface trap charge density is calculated based on the loop area integral value, the test voltage range, and the oxide layer capacitance parameters. In practice, according to the law of conservation of charge and the physical definition of capacitance, the loop area integral value is numerically equivalent to the total amount of charge exchanged by the interface trap during bidirectional scanning, that is, the ratio of the loop area integral value to the effective area of ​​the device.

[0054] Secondly, the hysteresis window width characteristics of the measured capacitor voltage hysteresis loop are extracted. Using the mapping relationship between the gate voltage and the semiconductor surface potential (which can be obtained by solving the aforementioned Poisson equation), the hysteresis window width is converted into the energy response range of the interface trap level in the bandgap.

[0055] Next, based on the asymmetry characteristics of the measured capacitor voltage hysteresis loop, the peak voltage position of the interface trap response is located, and this peak voltage position is mapped to the center position of the interface defect energy level. Combined with the interface trap charge density and energy response range, the interface defect inversion parameters are obtained. Note that because the response rates of interface traps at different energy level positions differ during the scanning process, the width of the hysteresis loop varies under different voltage biases. This embodiment extracts the peak voltage position corresponding to the maximum hysteresis loop width or the highest loop area density. Using the same gate voltage and surface potential mapping relationship, this is converted to the corresponding surface potential, which is then mapped to the center position of the interface defect energy level.

[0056] By using area integration, charge density calculation, hysteresis window width characteristic analysis, and peak voltage location based on hysteresis loop data, this invention can accurately obtain the inversion parameters of interface defects. This series of analyses can deeply reveal the charge density, energy distribution, and influence range of interface traps, providing important quantitative support for interface defect analysis and optimization of semiconductor devices. This not only helps improve device performance but also provides a scientific foundation and methodology for future interface defect engineering.

[0057] The fourth step of the materials chemistry computational simulation-guided directional experimental verification and performance testing method is as follows: The initial parameters of the interface defects are updated to the interface defect inversion parameters. Based on the updated initial parameters, the theoretical capacitance-voltage hysteresis loop is regenerated. The characteristic deviation between the regenerated theoretical capacitance-voltage hysteresis loop and the measured capacitance-voltage hysteresis loop is calculated. It is then determined whether the characteristic deviation meets the preset convergence condition. If not, the initial parameters of the interface defects are adjusted to minimize the characteristic deviation, and the simulation is repeated until the characteristic deviation meets the preset convergence condition. This step, through the acquisition of experimental data and the calculation of physical mapping relationships, provides accurate measurement basis for the quantification of interface defects. Furthermore, through the analysis of defect energy level positions, the physical characteristics of the interface defects are further refined.

[0058] As a further step, the characteristic deviation between the regenerated theoretical capacitor voltage hysteresis loop and the measured capacitor voltage hysteresis loop data is calculated, specifically including:

[0059] First, the regenerated theoretical capacitor voltage hysteresis loop and the measured capacitor voltage hysteresis loop are mapped to a unified voltage coordinate axis, and their geometric characteristic parameters are calculated. Among them, the geometric characteristic parameters include the hysteresis area deviation, which characterizes the error of the total amount of interface trap charge, the hysteresis width deviation, which characterizes the error of the defect energy level distribution range, and the waveform correlation coefficient, which characterizes the degree of fitting of the loop shape.

[0060] Specifically, the hysteresis area deviation is calculated by dividing the theoretical and measured hysteresis area integrals (i.e., the area enclosed by the forward and reverse scan curves) by the theoretical and measured hysteresis area integrals, and then calculating the absolute value or relative error percentage of the difference between the two area values. This parameter characterizes the simulation error of the total amount of interface trap charge, reflecting the order-of-magnitude accuracy of the simulated interface density of states.

[0061] Hysteresis width deviation: A specific capacitance reference (such as the full width at half maximum of a normalized capacitor or the voltage difference at a specific capacitance value) is selected, and the hysteresis window widths of the theoretical and measured loops are measured respectively. The difference between the two is calculated. This parameter is used to characterize the error in the range of defect energy level distribution and reflects the simulation model's ability to capture the energy span of interface traps in the bandgap.

[0062] Waveform correlation coefficient: Based on statistical methods, the Pearson correlation coefficient between the theoretical capacitance sequence and the measured capacitance sequence is calculated.

[0063] Next, a multidimensional feature deviation evaluation function is constructed based on the geometric feature parameters, and the feature deviation is calculated. The specific form of the multidimensional feature deviation evaluation function is as follows: ;in, This represents the multidimensional characteristic deviation evaluation function. , , These are the weighting coefficients for hysteresis area deviation, hysteresis width deviation, and waveform correlation coefficient, which are set according to specific testing requirements and key considerations. Indicates the hysteresis area deviation. This represents the area of ​​the measured loop. Indicates the hysteresis width deviation. Indicates the width of the measured loop. This represents the waveform correlation coefficient.

[0064] By quantifying multiple geometric features such as hysteresis area, hysteresis width, and waveform shape, a multidimensional feature deviation evaluation function is constructed. This function not only accurately reveals the impact of interface defects on electrical performance but also helps improve the accuracy of theoretical models, providing strong data support for device design and optimization. This method effectively combines experimental data with theoretical models, promoting in-depth development in semiconductor device performance analysis and understanding of interface defects.

[0065] The fifth step of the materials chemistry computational simulation-guided directional experimental verification and performance testing method is as follows: based on the initial parameters of the interface defects that meet the preset convergence conditions, output the interface density of states distribution map. This iterative optimization process ensures a high degree of consistency between theoretical and experimental data, and ultimately obtains an accurate description of the interface defects and the interface density of states distribution through parameter optimization. This provides a precise optimization scheme for interface defect engineering and promotes the improvement of device performance.

[0066] It should be noted that, based on the initial parameters of the interface defects that meet the preset convergence conditions, the output interface state density distribution map is provided, which specifically includes:

[0067] First, initial parameters of interface defects that meet preset convergence conditions are extracted. Based on the mapping relationship between gate voltage and semiconductor surface potential, a coordinate data sequence of interface state density as a function of bandgap energy is calculated. When the iterative calculation meets the preset convergence conditions, the corresponding initial parameters of interface defects are extracted as the final optimization result. At this point, the parameter set contains accurate information on interface state density and defect energy levels. Based on the physical mapping relationship between gate voltage and semiconductor surface potential established in the previous steps, the defect distribution in the voltage domain is transformed into the energy domain. Specifically, the energy positions in the bandgap are calculated using semiconductor physics formulas, typically expressed as the energy difference relative to the intrinsic Fermi level or the conduction band bottom and valence band top.

[0068] Then, a coordinate system is constructed with energy coordinates as the horizontal axis and interface density of states as the vertical axis. Distribution curves are plotted based on the coordinate data sequence, generating and outputting an interface density of states distribution map. A two-dimensional Cartesian coordinate system is constructed based on the calculated coordinate data sequence. In specific implementation, energy coordinates (i.e., the positions of defect energy levels within the band gap) are used as the horizontal axis, and interface density of states as the vertical axis. A data visualization module or drawing engine is invoked to plot a smooth distribution curve in the coordinate system based on the coordinate data sequence. This curve visually demonstrates the distribution shape of the interface density of states with energy level position (e.g., whether a U-shaped distribution or peak distribution exists). Finally, an interface density of states distribution map containing coordinate axis labels, numerical scales, and distribution curves is generated and output to a display device or storage medium, providing quantitative physical basis for device process optimization and interface quality assessment.

[0069] The interface density of states distribution map based on the initial parameters output by the interface defects not only provides researchers with comprehensive data on the energy level distribution of interface defects, but also offers important theoretical support for device design, optimization, and performance improvement. By combining the voltage-potential mapping relationship and accurately calculating the changes in the interface density of states, the distribution of defects in the bandgap can be clearly shown, thus providing effective data support for interface layer defect optimization and device performance improvement.

[0070] Overall, this invention combines materials chemistry computational simulation with targeted experimental verification to form a highly synergistic testing and optimization method, solving several technical challenges in analyzing the dynamic evolution of interface defects and their relationship with performance in semiconductor devices. The various steps work together to form a complete closed-loop optimization process. First, initial parameters of the interface defects are obtained through computational simulation, providing a theoretical basis for subsequent experimental verification, and the characteristic time constant for carrier trapping in interface traps is calculated, ensuring the accuracy of the experimental parameters. Next, by combining the voltage scan period and the characteristic time constant, the sensitive scan rate range is determined, simulating the dynamic hysteresis behavior of interface charges, and providing a theoretical basis for experimental testing of the actual capacitor voltage hysteresis loop.

[0071] Furthermore, the measured data obtained through bidirectional voltage scanning experiments were compared with the theoretical model, forming a dynamic connection between the calculated and experimental data. By optimizing the interface defect parameters, the error between the theoretical and measured data was minimized, ultimately achieving high-precision model-experiment consistency. In addition, the interface charge density and defect energy level positions obtained through inversion not only improved the accuracy of the interface state density distribution spectrum but also provided effective guidance for the optimized design of device performance.

[0072] The synergistic effect between each step, especially in the optimization and updating of initial parameters for interface defects, forms a continuous feedback mechanism, ensuring a high degree of agreement between the final theoretical capacitance-voltage hysteresis loop and the measured data. This process not only provides a profound understanding of interface defects in semiconductor devices but also enables real-time, in-situ capture of the dynamic impact of defects on carrier transport, thus providing solid technical support for improving device performance.

[0073] In summary, the steps of this invention, through close coordination, effectively overcome the limitations of existing technologies, enabling accurate and non-destructive analysis and optimization of semiconductor device interface defects, and promoting the establishment of a dynamic structure-property relationship between microscopic defects and device performance. This comprehensive method combining computational simulation and experimental verification has broad application prospects and can significantly improve the design accuracy and performance optimization of semiconductor devices, especially in the research and development of high-performance devices such as solar cells.

[0074] Through the above description of the implementation methods, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the above functions can be divided into different functional modules to complete all or part of the functions described above.

[0075] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0076] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units, located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0077] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0078] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to the solution, or all or part of the technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of directed experimental validation and performance testing guided by computational simulation of materials chemistry, characterized in that, Includes the following steps: Obtain the structural parameters and initial parameters of interface defects of semiconductor devices, and calculate the characteristic time constant of carrier trapping by interface traps based on the structural parameters and initial parameters of interface defects. Based on the matching relationship between the characteristic time constant and the voltage scan period, the sensitive scan rate range for reflecting the dynamic response characteristics of the interface state is determined. Based on the structural parameters, the initial parameters of the interface defects, and the sensitive scan rate range, the dynamic hysteresis behavior of the interface charge is simulated to generate the theoretical capacitor voltage hysteresis loop. The semiconductor device is subjected to bidirectional voltage scanning test by scanning rate within the sensitive scanning rate range and the measured capacitor voltage hysteresis loop data is collected. The loop area integral value of the measured capacitor voltage hysteresis loop data is calculated. The interface charge density is obtained based on the physical mapping relationship between hysteresis area and interface trap charge density. The defect energy level position is analyzed by combining the loop broadening characteristics to obtain the interface defect inversion parameters. The interface defect inversion parameters are used as the initial parameters of the interface defect to regenerate the theoretical capacitor voltage hysteresis loop. The characteristic deviation between the regenerated theoretical capacitor voltage hysteresis loop and the measured capacitor voltage hysteresis loop data is calculated. It is determined whether the characteristic deviation meets the preset convergence condition. If it does not meet the condition, the initial parameters of the interface defect are adjusted with the goal of minimizing the characteristic deviation and the simulation is repeated until the characteristic deviation meets the preset convergence condition. Based on the initial parameters of the interface defects that meet the preset convergence conditions, the interface state density distribution map is output.

2. The method of claim 1, wherein the material chemical calculation simulation guided directed experimental validation and performance testing method is characterized by, The structural parameters include semiconductor substrate doping concentration, oxide layer thickness, oxide layer dielectric constant, semiconductor dielectric constant, device area, ambient temperature, and effective mass of semiconductor material. The initial parameters of the interface defects include the initial value of the interface state density, the defect energy level position, and the carrier trapping cross section.

3. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 2, characterized in that, The calculation of the characteristic time constant for carrier capture by interface traps based on structural parameters and initial parameters of interface defects specifically includes: The thermal motion velocity of charge carriers is calculated based on the ambient temperature and the effective mass of the semiconductor material. Based on the Poisson equation and structural parameters, the relationship between the gate voltage and the charge carrier concentration on the semiconductor surface is determined, and the surface charge carrier concentration under the current scanning voltage is obtained. The carrier trapping coefficient is obtained by calculating the product of the carrier trapping cross section and the carrier thermal velocity. The reciprocal of the product of the carrier trapping coefficient and the surface carrier concentration is determined as the characteristic time constant for carrier trapping by the interface trap.

4. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 3, characterized in that, The characteristic time constant for carrier capture by the computational interface trap also includes: To address near-interface traps in the oxide layer, the perpendicular distance from the defect to the semiconductor interface and the electron wave function attenuation coefficient are introduced. The tunneling probability of carriers is calculated based on the vertical distance and the attenuation coefficient of the electron wave function. The tunneling probability decreases exponentially with the increase of the vertical distance. The product of the carrier trapping cross section and the tunneling probability is determined as the effective trapping cross section. The characteristic time constant of the interface trap for trapping carriers is updated based on the effective trapping cross section.

5. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 1, characterized in that, The determination of the sensitive scan rate range reflecting the dynamic response characteristics of the interface state based on the matching relationship between the characteristic time constant and the voltage scan period specifically includes: The characteristic frequency of the interface state response is determined based on the characteristic time constant. The scan rate corresponding to the characteristic frequency is used as the benchmark. The scan rate range in which the value of the scan period and the value of the characteristic time constant are on the same order of magnitude is selected as the sensitive scan rate range. The sensitive scan rate range is the rate range within which the interface state generates the maximum hysteresis response window during charging and discharging. The lower limit of the sensitive scan rate range is determined by the quasi-static condition that the interface state can completely follow the voltage change, and the upper limit of the sensitive scan rate range is determined by the high-frequency condition that the interface state response is completely frozen.

6. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 1, characterized in that, The generation of the theoretical capacitor voltage hysteresis loop specifically includes: Construct a bidirectional voltage scanning sequence, and set the voltage scanning rate and scanning step size according to the sensitive scanning rate range; A dynamic differential equation describing the charging and discharging rate of interface trap charge is established based on the characteristic time constant. The dynamic differential equation is solved by numerical integration method to obtain the instantaneous value of interface trap charge at each voltage point during the bidirectional scanning process. Based on the gate voltage drift caused by the instantaneous value of the interface trap charge, and combined with the physical relationship between the semiconductor surface potential and the total capacitance, the theoretical capacitance value is calculated, and the theoretical capacitance voltage hysteresis loop is generated.

7. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 1, characterized in that, The calculation of the integral value of the loop area of ​​the measured capacitor voltage hysteresis loop data specifically includes: After selecting the target scan rate within the sensitive scan rate range, forward voltage scanning and reverse voltage scanning are performed on the semiconductor device, and forward scan capacitor voltage data sequences and reverse scan capacitor voltage data sequences are collected respectively. Voltage coordinate normalization is performed on the forward scan capacitor voltage data sequence and the reverse scan capacitor voltage data sequence, and an interpolation algorithm is used to construct a measured capacitor voltage hysteresis loop with consistent voltage coordinates. The difference between the reverse scanning capacitance value and the forward scanning capacitance value under the same voltage coordinate in the measured capacitor voltage hysteresis loop is calculated. The difference is then integrated within the test voltage range to obtain the loop area integral value. The loop area integral value is used to characterize the total charge exchange of the interface trap during the charging and discharging process.

8. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 1, characterized in that, The interface charge density is obtained based on the physical mapping relationship between the hysteresis area and the interface trap charge density, and the defect energy level position is analyzed by combining the loop broadening feature to obtain the interface defect inversion parameters, specifically including: Based on the integral value of the loop area, the test voltage range, and the oxide layer capacitance parameters, the interface trap charge density is calculated. The hysteresis window width characteristics of the measured capacitor voltage hysteresis loop are extracted, and the mapping relationship between gate voltage and semiconductor surface potential is used to convert the hysteresis window width into the energy response range of the interface trap level in the bandgap. Based on the asymmetric characteristics of the measured capacitor voltage hysteresis loop, the peak voltage position of the interface trap response is located, and the peak voltage position is mapped to the center position of the interface defect energy level. Combined with the interface trap charge density and energy response range, the interface defect inversion parameters are obtained.

9. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 1, characterized in that, The characteristic deviations between the recalculated theoretical capacitor voltage hysteresis loop and the measured capacitor voltage hysteresis loop data specifically include: After mapping the regenerated theoretical capacitor voltage hysteresis loop and the measured capacitor voltage hysteresis loop to a unified voltage coordinate axis, the geometric characteristic parameters of the two are calculated. Based on the geometric characteristic parameters, a multidimensional characteristic deviation evaluation function is constructed, and the characteristic deviation is calculated. The geometric feature parameters include the hysteresis area deviation, which characterizes the error in the total amount of interface trap charge; the hysteresis width deviation, which characterizes the error in the range of defect energy level distribution; and the waveform correlation coefficient, which characterizes the degree of fit of the loop shape.

10. The method for directional experimental verification and performance testing guided by materials chemistry calculation simulation as described in claim 1, characterized in that, The output of the interface state density distribution map based on the initial parameters of the interface defects that meet the preset convergence conditions specifically includes: Extract the initial parameters of the interface defects that meet the preset convergence conditions, and calculate the coordinate data sequence of the interface state density as a function of the bandgap energy based on the mapping relationship between the gate voltage and the semiconductor surface potential. A coordinate system is constructed with energy coordinates as the horizontal axis and interface density of states as the vertical axis. Distribution curves are plotted based on the coordinate data sequence, and an interface density of states distribution map is generated and output.

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