Method and apparatus for saving and restoring processor, computer device and storage medium

Abstract

This application discloses a method, apparatus, computer device, and storage medium for saving and restoring a processor. The method includes: monitoring the occurrence of trigger events associated with saving or restoring the processor core during its operation; upon detecting a trigger event, determining a selected register from the processor core's register file based on the configuration state of the trigger control domain and the specific identifier of the register identifier domain, and determining whether to perform a save operation or a restore operation; and transmitting the data of the selected register to a storage unit in the block memory at high speed through multiple parallel data channels connecting the register file and the block memory to complete the save operation, or transmitting the data stored in the storage unit to the selected register at high speed to complete the restore operation, wherein the high-speed transmission rate is higher than the normal transmission rate of the processor core accessing the block memory through conventional memory access instructions.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of computer technology, and in particular to a method, apparatus, computer device, and storage medium for saving and restoring a processor. Background Technology

[0002] In processor architecture, when program execution jumps due to events such as function calls, interrupts, or exceptions, it is necessary to save the current runtime context so that it can be correctly restored and execution can continue upon subsequent return. The runtime context mainly includes the contents of the register file and related control status registers and other critical data.

[0003] Existing technologies typically use software instructions to push the register data that needs to be saved onto the memory stack area sequentially, and then pop it off the stack during restoration. Although this method is flexible and completely visible and controllable by the software, it requires multiple instructions to perform the push and pop operations, resulting in high performance overhead, extended response time, increased code size, and impact on execution efficiency. Summary of the Invention

[0004] In view of this, embodiments of this application provide at least one method, apparatus, computer device, and storage medium for saving and restoring a processor.

[0005] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a method for saving and restoring a processor, applied to a processor whose processor core is provided with a block memory, the block memory being composed of multiple physically independent and parallel-accessible memory units; the processor also includes a software-accessible control status register, the control status register including a trigger control field for controlling the trigger mode and a register identifier field for identifying the register to be operated; the method includes: During the operation of the processor core, the occurrence of triggering events associated with field saving or recovery is monitored; Upon detecting the triggering event, the selected register is determined from the register file of the processor core based on the configuration status of the trigger control domain and the specific identifier of the register identifier domain, and a save operation or a restore operation is performed. By connecting the register file and the block memory through multiple parallel data channels, the data of the selected register is transferred at high speed to the storage unit in the block memory to complete the saving, or the data stored in the storage unit is transferred at high speed to the selected register to complete the recovery. The high-speed transfer rate is higher than the normal transfer rate of the processor core accessing the block memory through regular memory access instructions.

[0006] On the other hand, embodiments of this application provide a processor storage and recovery device, applied to a processor. The processor core of the processor is provided with a block memory, which consists of multiple physically independent storage units that can be accessed in parallel. The processor is also provided with a software-accessible control status register, which includes a trigger control field for controlling the trigger mode and a register identifier field for identifying the register to be operated. The device includes: A monitoring module is used to monitor the occurrence of triggering events associated with field saving or recovery during the operation of the processor core; The processing module is used to, upon detecting the triggering event, determine the selected register from the register file of the processor core based on the configuration status of the trigger control domain and the specific identifier of the register identifier domain, and determine whether to perform a save operation or a restore operation. The execution module is used to transfer data from the selected register to a storage unit in the block memory at high speed through multiple parallel data channels connecting the register file and the block memory to complete the saving, or to transfer data stored in the storage unit to the selected register at high speed to complete the recovery. The high-speed transfer rate is higher than the normal transfer rate of the processor core accessing the block memory through conventional memory access instructions.

[0007] In another aspect, embodiments of this application provide a computer device, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described processor save and restore method.

[0008] In another aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the processor's save and restore method described above.

[0009] In another aspect, embodiments of this application provide a computer program including computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps in the above-described save and restore method for implementing the processor.

[0010] In another aspect, embodiments of this application provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described processor's save and restore method.

[0011] This application embodiment monitors various trigger events and parses programmable configurations through hardware, enabling automatic or semi-automatic operation initiation. Utilizing segmented tightly coupled memory and parallel direct data channels, it batch transfers register data flexibly specified by the software at speeds several times faster than traditional software stack pushing or conventional hardware access, without requiring modification of the instruction set or compilation toolchain. The saved data is fully visible and accessible to the software, while the hardware implementation cost is low and there are no stack depth limitations, thereby significantly reducing interrupt response time and function call overhead, and improving the overall operating efficiency of the processor.

[0012] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0014] Figure 1 A schematic diagram illustrating the implementation flow of a processor saving and restoring method provided in an embodiment of this application; Figure 2 One of the schematic diagrams of the logic flow of a processor saving and restoring method provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the principle of a processor saving and restoring method provided in an embodiment of this application; Figure 4 A second schematic diagram of the logic flow of a processor saving and restoring method provided in an embodiment of this application; Figure 5 A schematic diagram illustrating the structural composition of a processor storage and recovery device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0017] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0019] This application provides a method for saving and restoring a processor. The method is applied to a processor whose processor core is provided with a block memory. The block memory is composed of multiple physically independent storage units that can be accessed in parallel. The processor is also provided with a software-accessible control status register. The control status register includes a trigger control field for controlling the trigger mode and a register identifier field for identifying the register to be operated.

[0020] In this embodiment, the processor core integrates a block memory. This memory serves as a dedicated high-speed data storage unit for the processor core, used to store instructions and data that require frequent access or fast retrieval, providing physical storage space for subsequent high-speed saving and recovery of field data.

[0021] The processor core's block memory is divided into multiple independent memory blocks at the hardware level. Each memory block is a complete small memory unit. These memory blocks share the same data bit width, but their address space is a subset of the original block memory address space. When a save or restore operation is required, all these memory blocks can be activated simultaneously, and data can be transferred through parallel data channels, thereby achieving a multiple-fold increase in data access speed.

[0022] A specific control status register is configured within the processor. This register is visible and operable to the software running on the processor, and the software can read or configure it using standard control status register access instructions. This register serves as the control center for the entire context saving and recovery mechanism; the software configures it to define the saving and recovery behavior mode and data range. Specific bits within this control status register are designated as trigger control fields. These fields contain multiple bits, each bit or combination of bits corresponding to a specific operation trigger mode, such as automatic stack push, automatic stack pop, semi-automatic stack push, and semi-automatic stack pop. By detecting the values ​​of these bits or software write operations to them, the system determines under what conditions and in what manner the context data saving or recovery process will be initiated.

[0023] Figure 1 This is a schematic diagram illustrating the implementation flow of a processor saving and restoring method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method includes: Step 101: During the operation of the processor core, monitor the occurrence of triggering events associated with field saving or recovery.

[0024] In this embodiment, the processor core is the core computing unit of the central processing unit, responsible for executing instructions and processing data. The running period refers to the time during which the processor core is executing program instructions. Monitoring is the process of continuously checking whether specific signals or conditions are met. A triggering event is a specific condition or signal that can cause the processor to perform a context-saving or restore operation, such as an interrupt, an exception, or the execution of a specific instruction.

[0025] During the execution of program instructions by the processor core, hardware signal lines and instruction flow are continuously monitored. Detected interrupt signals originate from external devices or internal timers, exception signals are generated by illegal operations or error conditions, privilege return instructions are architecture-specific instructions that return from privileged mode, and write operations to specific control status registers are software-initiated configuration instructions. When any of these preset conditions is met, a trigger event is determined to have occurred, and preparations are made to initiate subsequent context processing.

[0026] Step 102: Upon detecting the trigger event, based on the configuration status of the trigger control domain and the specific identifier of the register identifier domain, determine the selected register from the register file of the processor core, and determine whether to perform a save operation or a restore operation.

[0027] In this embodiment, the configuration state refers to the current value of each bit in the trigger control field of the control status register, which defines the operating mode that should be activated. The specific identifier is the correspondence between each bit in the register identifier field and a general-purpose register within the processor core; a bit value of 1 indicates that the register needs to be operated on. The register file is a set of high-speed data storage units within the processor core, used to temporarily store instruction operands. The selected register is the specific register selected based on the bits in the register identifier field that requires data saving or restoration operations. A save operation is the process of writing data from the register file to memory. A restore operation is the process of reading data from memory back to the register file.

[0028] Upon confirmation of the trigger event, the control status register is immediately read. First, the bit values ​​of the trigger control field are parsed to determine whether an automatic push, automatic pop, semi-automatic push, or semi-automatic pop operation should be performed. Next, the N bits of the register identifier field are parsed, where each bit corresponds to a specific register in the register file. All registers corresponding to bits with a value of 1 are marked as selected registers. Based on the operation mode determined by the trigger control field, a final decision is made as to whether to perform a save or restore operation, and the set of selected registers to be processed is locked.

[0029] Step 103: By connecting the register file and the block memory through multiple parallel data channels, the data of the selected register is transferred at high speed to the storage unit in the block memory to complete the saving, or the data stored in the storage unit is transferred at high speed to the selected register to complete the recovery. The high-speed transfer rate is higher than the normal transfer rate of the processor core accessing the block memory through conventional memory access instructions.

[0030] In this embodiment, a parallel data channel is a set of independent physical connections connecting a register file and multiple memory units, capable of transmitting data simultaneously. High-speed transmission refers to the process of data moving in large quantities through a parallel channel per unit time; its rate is determined by the channel width and clock frequency. Block memory is a high-speed static random access memory region tightly connected to the processor core and operating at the same frequency. Regular memory access instructions are standard load-store instructions in the processor instruction set used for reading and writing memory. Low-speed transmission rate refers to the data throughput that the processor core can achieve by serially executing regular memory access instructions to access memory.

[0031] For save operations, data from multiple selected registers is simultaneously transferred to a pre-allocated, currently unused memory cell in the block memory via a dedicated parallel data channel. For restore operations, data saved in the specified memory cell is simultaneously transferred back to the corresponding selected register via the same parallel channel. This parallel transfer mechanism leverages the simultaneous read / write capability of multiple physical memory blocks, completing the data transfer of all selected registers within one or a few clock cycles. This rate is significantly higher than the rate achieved by the processor core, which accesses the same memory region one by one by executing multiple load or store instructions sequentially.

[0032] This application embodiment monitors various trigger events and parses programmable configurations through hardware, enabling automatic or semi-automatic operation initiation. Utilizing segmented tightly coupled memory and parallel direct data channels, it batch transfers register data flexibly specified by the software at speeds several times faster than traditional software stack pushing or conventional hardware access, without requiring modification of the instruction set or compilation toolchain. The saved data is fully visible and accessible to the software, while the hardware implementation cost is low and there are no stack depth limitations, thereby significantly reducing interrupt response time and function call overhead, and improving the overall operating efficiency of the processor.

[0033] Optionally, the triggering event includes automatic triggering events and semi-automatic triggering events; the control status register is configured with an independent triggering control field, and the independent triggering control field has at least one of the following functions: automatic stack push triggering function, automatic stack pop triggering function, semi-automatic stack push triggering function, and semi-automatic stack pop triggering function.

[0034] In the embodiments of this application, a triggering event refers to a condition or signal that can initiate a processor state save or restore operation. Automatically triggered events are conditions that are automatically generated by the processor's operating state, such as interrupts, exceptions, and privilege return instructions. Semi-automatically triggered events are conditions that are actively initiated by software through specific operations.

[0035] During operation, the processor core continuously monitors for two types of triggering events. One type is automatically triggered events, which are closely related to the processor's execution flow. For example, when an interrupt signal or exception signal is generated, or a privilege return instruction is executed, the system automatically identifies these events as trigger conditions. The other type is semi-automatically triggered events, which are actively set by the software program through specific control status register access instructions. For instance, the software writes specific values ​​to the control status register representing semi-automatic push or pop functions, thereby generating a trigger signal.

[0036] The processor core defines and implements a specific control status register within its control status register set. This register has a dedicated area designated as a trigger control domain. This trigger control domain is designed to be readable and writable in hardware, and its state can be directly read by the processor control logic to determine whether to initiate the corresponding context saving or restoring operation.

[0037] Automatic stack push triggering refers to the system automatically saving register contents to memory upon detecting an interrupt or exception. Automatic stack pop triggering refers to the system automatically restoring register contents from memory upon detecting a privilege return instruction. Semi-automatic stack push triggering refers to the software actively writing control bits to initiate the save operation. Semi-automatic stack pop triggering refers to the software actively writing control bits to initiate the restore operation.

[0038] The processor core has explicitly mapped and bound the trigger control domains within the trigger control domain to their functions. The first trigger control domain is defined as the automatic push trigger function; when this function is active, the system should respond to an automatic push event. The second trigger control domain is defined as the automatic pop trigger function, with its active state corresponding to an automatic pop event. The third trigger control domain is defined as the semi-automatic push trigger function; software initiates a push request by setting this bit. The fourth trigger control domain is also defined as the semi-automatic pop trigger function; software initiates a pop request by setting this bit. The processor's control logic continuously monitors the state of these functions to determine which operation to perform.

[0039] Step 102 includes: Step 1021a: When an interrupt signal or an abnormal signal is received, and the automatic stack push triggering function is in an active state, start the on-site save operation for the interrupt signal or abnormal signal.

[0040] In this embodiment, an interrupt signal refers to an electronic signal generated externally or internally to the processor, requiring the processor to suspend the currently executing program and instead execute a specific service routine. An exception signal refers to an internal signal generated by the processor during instruction execution due to unexpected or erroneous events detected by the processor. Automatic stack push triggering refers to a binary bit located in a specific control status register; when this bit is set to a valid state, it indicates that the automatic stack push function is enabled. Context saving operation refers to the process of storing the processor's current running state to a specified memory area.

[0041] The system continuously monitors interrupt and exception signals from the processor core. Upon receiving a valid interrupt or exception signal, it simultaneously checks the status of the preset automatic stack push trigger function in the control status register. If the automatic stack push trigger function is active, it determines that the current conditions meet the trigger requirements for automatic context saving. Subsequently, the context saving operation is immediately initiated. This operation uses another N-bit register in the control status register to identify the register list defined by the control field. Through a multi-channel directly connected to the hardware, the contents of the specified registers are written in parallel to the block TCM, thereby quickly completing the context saving.

[0042] Step 1022a: If a preset instruction returning from privileged mode is detected and the automatic stack popping trigger function is in a valid state, initiate a context recovery operation for the instruction returning from privileged mode.

[0043] In this embodiment, the instruction to return from privileged mode refers to a special instruction defined in the processor instruction set architecture, used to cause the processor to return from a high-privilege mode to a low-privilege mode. The automatic stack pop trigger function refers to a binary bit located in a specific control status register; when this bit is set to a valid state, it indicates that the automatic stack pop function is enabled. The context recovery operation refers to the process of loading the previously saved processor running state from a specified memory region back into the processor.

[0044] During instruction execution, the instruction decoding result is checked. When a pre-defined instruction returning from privileged mode is detected, the status of the pre-defined automatic stack pop trigger function in the control status register is simultaneously checked. If the automatic stack pop trigger function is active, the current conditions are deemed to meet the trigger requirements for automatic context restoration. Subsequently, the context restoration operation is immediately initiated. This operation uses the N-bit register in the control status register to store the register list defined by the identification control domain. Through a multi-channel directly connected to the hardware, data is read in parallel from the block TCM and loaded into the specified registers, thereby quickly completing the context restoration.

[0045] Step 1023a: If a write operation to the control status register is detected, and the write operation sets the semi-automatic push-to-trigger function or the semi-automatic pop-to-trigger function to an active state, then initiate a save-in-time operation or a restore-in-time operation.

[0046] In this embodiment, the control status register refers to a set of dedicated registers in the processor used to record and configure the processor core's operating state. A write operation refers to the operation triggered by the processor executing an instruction to write data to a specific address. The semi-automatic stack push trigger function refers to a binary bit located in a specific control status register, which software can manually trigger a context save operation by writing a 1 to. The semi-automatic stack pop trigger function refers to a binary bit located in a specific control status register, which software can manually trigger a context restore operation by writing a 1 to.

[0047] The system monitors access to specific control status registers. When a write operation to that register is detected, the data written is parsed. If the write operation enables the semi-automatic push function in the register, a context save operation is initiated; if it enables the semi-automatic pop function, a context restore operation is initiated. The specific list of registers processed in both save and restore operations is determined by the N-bit register-stored identifier control field within the same control status register. This process is entirely triggered by standard CSR access instructions, requiring no custom instructions.

[0048] This application embodiment achieves efficient and flexible saving and recovery of the processor context by automatically detecting interrupts, exceptions, privilege return instructions, and software write operations to specific CSRs through hardware, combined with a configurable register selection bitmap.

[0049] Optionally, the number of bits contained in the register identifier field is equal to the total number of general-purpose registers in the register file of the processor core.

[0050] Step 102 includes: Step 1021b: Read the value of each bit in the register identifier field, where the value of each bit corresponds to a general-purpose register with a specific number in the register file.

[0051] In this embodiment, a bit is a single bit in a binary number, the smallest unit of data storage in a computer, and its value can only be 0 or 1. The register identifier field is a control field composed of multiple bits, used to identify a group of registers. The register file is a high-speed storage unit group inside the processor, composed of multiple general-purpose registers, used to temporarily store data and addresses during instruction execution. General-purpose registers are registers in the processor that can be directly accessed and used by program instructions to perform arithmetic and logical operations, data transfer, and other operations.

[0052] Access a specific control status register containing an N-bit register identifier field. Read the binary value of each bit in the identifier field bit by bit. Establish a fixed mapping between the position index of each bit in the identifier field and a general-purpose register with a unique number in the processor register file. For example, bit 0 of the identifier field corresponds to register R0, bit 1 corresponds to register R1, and so on. This operation yields a bitmap of information for subsequent filtering operations.

[0053] Step 1022b: Incorporate general-purpose registers with a bit value of a first logical value into the selected register set, and exclude general-purpose registers with a bit value of a second logical value from the selected register set, wherein the second logical value is the opposite of the first logical value.

[0054] In this embodiment, the first logical value is a predefined binary value used to represent the selected state, such as logic 1. The selected register set is a temporary logical set used to store the identifiers of the registers selected for subsequent operations. The second logical value is a predefined binary value that is the opposite of the first logical value, used to represent the unselected state, such as logic 0.

[0055] Based on the bitmap of the read register identifier field, all general-purpose registers in the register file are filtered. Each bit in the identifier field and its corresponding general-purpose register is traversed. When the value of a bit equals a predefined first logical value, the identifier of the general-purpose register with that specific number is added to a logical set named the selected register set. Conversely, when the value of a bit equals a predefined second logical value, the general-purpose register corresponding to that bit is ignored and not included in the selected register set. Through this process, based on the software-configurable bitmap, a subset of registers that need to participate in subsequent context saving or recovery operations is precisely determined.

[0056] This application's embodiments enable flexible and precise selection of specific register subsets in the processor register file that require context saving or restoration, based on a software-programmable bitmap control field. This method avoids the resource waste of saving all registers required in traditional hardware stack-based schemes and overcomes their lack of flexibility. By parsing the configuration bitmap and generating the selected register set, it lays the foundation for subsequent high-speed parallel data transmission using block-based TCM, thereby achieving an efficient, customizable, and software-visible processor save and restore mechanism, significantly improving interrupt response and function call performance.

[0057] Optionally, step 103 includes: Step 1031a: When starting the field save operation, read the data of X registers in the selected register set simultaneously through the parallel data channel.

[0058] In this embodiment, a parallel data channel refers to a set of physical paths connecting the processor register file and block memory, capable of simultaneously transmitting multiple data units. Reading refers to the process of retrieving data from a source storage location. Data from multiple registers refers to the binary values ​​retrieved from some or all of the registers involved in a single operation within a selected set of registers.

[0059] The selected register set is determined based on configuration information (such as the N-bit register storing the identifier control field in the CSR). The parallel data channel connecting the register file and the context storage hardware is activated. Multiple read operations are simultaneously initiated to multiple registers in the selected register set via multiple data lines of this parallel data channel. The control logic of these registers responds to the read requests, outputting their currently stored data values ​​to the corresponding parallel data channel, thereby enabling the batch acquisition of data from multiple registers at once.

[0060] Step 1032a: If the number of sub-memories Y is greater than or equal to X, write the data of X registers into X sub-memories in parallel; or if the number of sub-memories Y is less than X, write the data of X registers into a block memory in parallel in batches of Y each time. The starting write position of the multiple memory units is a preset starting position, and the block memory is composed of Y sub-memories.

[0061] In the embodiments of this application, parallel writing refers to the operation of simultaneously storing multiple data units to multiple target storage locations. Multiple storage units refer to multiple small blocks of SRAM storage units that are logically storage units, physically independent, and accessible in parallel.

[0062] Data from multiple registers acquired simultaneously via parallel data channels is routed and latched. Based on the starting address of each memory cell, the corresponding write address of each physical memory cell constituting the logical block is calculated. Control logic drives these data to be written simultaneously to a corresponding number of different memory cells through independent write ports. Each memory cell receives and stores the register data, thus completing the batch, high-speed transfer of data from the register file to the block memory.

[0063] This application embodiment pre-allocates contiguous logical storage blocks to prepare a defined space for data storage. Then, it uses parallel data channels to read data from multiple registers at once and writes this data in parallel to multiple physical storage blocks. If the number Y of sub-memories in the block memory is greater than or equal to the amount of data X in the registers, the data from X registers can be directly written to X sub-memories in parallel. If the number Y of sub-memories is less than the amount of data X in the registers, the data from X registers is written to the block memory in batches of Y, with each batch containing Y data units. For example, if the number Y of sub-memories in the block memory is 8 and the amount of data in the registers is 32, the data from the registers can be written to the block memory in four batches of 8 units each.

[0064] This compresses the register saving process, which traditionally requires multiple clock cycles to execute sequentially, into a very small number of clock cycles, achieving an order-of-magnitude improvement in context saving speed. Simultaneously, because the data is stored in the software-visible and flexibly addressable TCM, the saving process is both transparent and accessible to the software, while avoiding the significant hardware overhead and nesting depth limitations associated with using multiple sets of shadow registers. This improves interrupt response and function call efficiency while balancing hardware cost, software compatibility, and usage flexibility.

[0065] Optionally, step 103 includes: Step 1031b: When initiating the field recovery operation, determine the target storage unit previously used to save the field.

[0066] In this embodiment, the context recovery operation refers to reading previously saved processor running state data from memory and writing it back to the processor register, so that the processor can resume execution from the previously interrupted or suspended state. The target memory unit refers to a logical memory unit composed of multiple physically independent small blocks of SRAM, collectively forming part of the processor's block memory, specifically used to store the context data to be recovered.

[0067] When initiating a context recovery operation, the location of the data source must first be determined. Based on the preset address management logic or stack pointer information, the specific logical storage block used during the previous context saving operation is located in the logical address space of the block memory; this is the target storage unit. This target storage unit consists of multiple physically independent and parallel-accessible storage units, which store the register data that needs to be recovered.

[0068] Step 1032b: Read multiple data words in parallel from the multiple storage cells constituting the target storage cell.

[0069] In the embodiments of this application, a storage cell refers to a small-capacity SRAM storage cell that constitutes a logical TCM and is physically independent and individually addressable. Each storage cell has the same data width as the TCM, but its address depth is only 1 / N of the logical TCM. A data word refers to a basic data unit stored in memory, whose bit width matches the register bit width of the processor, such as 32 bits or 64 bits.

[0070] After identifying the target storage unit, a parallel read operation is initiated. Read requests are simultaneously sent to each storage unit constituting the target unit via independent access channels. Each storage unit responds to the request, outputting a single data word stored internally. In this way, multiple data words are retrieved in parallel from multiple storage units, collectively forming the set of on-site data that needs to be recovered.

[0071] Step 1033b: Through the parallel data channel, the multiple data words read in parallel are written in parallel into the corresponding multiple registers in the selected register set.

[0072] In this embodiment, the parallel data channel refers to a dedicated hardware data path with multi-path parallel transmission capability that connects the register file (RegFile) and the block memory (TCM). This channel allows the simultaneous transmission of multiple data words. The selected register set refers to a specific set of registers specified by the register identifier control field in the control status register (CSR) that need to have data restored. This set is a subset of all processor registers.

[0073] Multiple data words read in parallel in step 1032b are transmitted to the register file (RegFile) in parallel via a dedicated parallel data channel. According to a preset mapping relationship, each arriving data word is accurately written to the corresponding specific register in the selected register set. Thus, the saved processor state is restored to the register file in a single, parallel process.

[0074] This application's embodiments, by locating a specific memory block, reading multiple data words in parallel, and writing back to the register in one go via a parallel channel, compress the context recovery operation, which traditionally requires multiple clock cycles to complete serially, into a very short number of clock cycles. This significantly reduces the latency of interrupt returns or function returns, improving the processor's response speed and operating efficiency. Simultaneously, since the recovered data is stored in a software-accessible TCM, and the registers to be recovered can be flexibly selected through configuration, this mechanism improves performance while maintaining software compatibility and flexibility.

[0075] Optionally, the method further includes: Step 201: Each time a field save operation is performed, the starting address of the storage unit used to save the field data is recorded in the stack pointer register or a dedicated address record table.

[0076] In this embodiment, a context save operation refers to the process by which the processor core saves its current running state to the block memory (TCM). A memory cell refers to one of the multiple small blocks of SRAM that logically constitute the TCM, specifically used to store the data generated by a single context save operation. The stack pointer register is a dedicated register in the processor core; its content is a memory address used to indicate the current top position of the stack, i.e., the next available memory cell or the starting position of the most recently stored data. A dedicated address record table is a data structure located in memory or a specific hardware unit, used to sequentially record the starting address of the memory cell used in each context save operation.

[0077] When performing a save operation, a memory location is selected as the storage location for the current data. After the save operation is complete, the starting memory address of that memory location is written to a designated stack pointer register. Alternatively, the starting address is added as a new entry to a hardware table specifically used to record historical save addresses. This recording behavior ensures that the specific storage location of each piece of live data in the TCM can be tracked.

[0078] Step 202: After each execution of the field recovery operation, release the space occupied by the recovered storage unit, and update the stack pointer register or the dedicated address record table accordingly to point to the storage unit used in the previous save operation.

[0079] In this embodiment, after performing a context recovery operation, the storage unit containing the recovered data is marked as available. Next, the stack pointer register, used to record storage locations, is updated to point to the starting address of the storage unit used in the previous context recovery operation. If a dedicated address record table is used, the address entries corresponding to the currently recovered data are removed from the table or marked, making the entries point to previously valid save addresses. This update operation maintains the continuity of the stack pointer or address records, ensuring the correctness of storage space management.

[0080] This application embodiment achieves software visibility and addressability of saved data by accurately recording the data location after each save, and realizes the circular reuse of TCM storage space by timely reclaiming storage resources and updating management pointers after each recovery. This enables the fast context saving and recovery device based on block TCM to support theoretically infinite nested calls, while ensuring flexible access to saved data and efficient utilization of storage resources by the software. Overall, it significantly improves the context switching efficiency of the processor during interrupts, exceptions and function calls.

[0081] Optionally, the method further includes: Step 301: If the remaining available space of the block memory is less than a predetermined threshold, the field data stored in one or more storage units at the bottom of the stack in the block memory is moved to the main memory of the processor through the direct memory access controller.

[0082] In this embodiment, block memory refers to an on-chip static random access memory (SRAM) tightly coupled to the processor core and possessing high access bandwidth. In this invention, this memory is logically divided into multiple small blocks for high-speed storage and retrieval of processor context data. A direct memory access controller (DMC) is a hardware module capable of performing inter-memory data transfer independently of the processor core. It can complete data transfer from a source address to a destination address without consuming processor core computing resources. Main memory refers to external or off-chip memory within the processor, typically with a capacity much larger than block memory, such as dynamic random access memory (DRAM), whose access speed is generally lower than that of block memory.

[0083] The usage of the block memory is continuously monitored. When the remaining available storage space in the block memory is detected to be less than a preset threshold, the Direct Memory Access Controller (DMI) is activated. This controller locates one or more memory cells at the bottom of the block memory stack according to a predefined strategy. Subsequently, the DMI initiates a data transfer operation, moving the current data stored in the located memory cell to a designated area in the processor's main memory via the bus. This process is completed automatically by hardware; the processor core does not need to intervene in the specific data transfer operation.

[0084] Step 302: Update the metadata information used to manage the location of field data storage in the block memory.

[0085] In this embodiment of the application, metadata information refers to data used to describe and manage field data stored in the block memory. Its content includes at least the storage start address of each field data block in the block memory, its valid status, and pointers that may point to backup data in the main memory.

[0086] After migrating the field data from the block storage to main memory, the metadata information maintaining the block storage's usage status needs to be updated. This involves modifying entries in the metadata related to the moved storage units, such as marking these blocks as free or reusable. Simultaneously, the new storage address of the moved data in main memory is recorded in the metadata, establishing a mapping between the logical stack in the block storage and the physical data in main memory. These update operations ensure that subsequent push or pop operations can correctly identify the available space in the block storage and, when it's necessary to recover data that has been moved, can locate the correct position in main memory using the metadata.

[0087] This application's embodiments introduce a direct memory access controller to automatically migrate historical context data from the bottom of the stack to a larger main memory in the background. While maintaining the high-speed access advantage of block memory, it greatly expands the logically supported context saving depth, freeing it from being limited by the physical capacity of block memory. Combined with dynamic updates of metadata information, it achieves transparent management of distributed storage context data, ensuring the correctness and continuity of context saving and recovery mechanisms in ultra-deep nested scenarios, thereby improving the overall reliability and adaptability of the processor in complex task processing.

[0088] Optionally, the original function call process in interrupt or exception scenarios is as follows: Figure 2 As shown. Taking a 32-bit RISC-V single-issue processor as an example, in this embodiment, as... Figure 2 As shown, 31 instructions and at least 31 clock cycles are needed to save the context, and 31 instructions and 31 clock cycles are needed to restore the context (the x0 register does not need to be saved because it is always 0. The specific saving scenarios differ depending on the implementation). However, if an 8-block implementation based on the solution described in this invention is adopted, such as... Figure 3 As shown, saving requires only 0 instructions and 4 clock cycles. If a 16-block scheme is used, saving requires only 0 instructions and 2 clock cycles. The overhead for restoration is similar.

[0089] Optionally, the function call process in a function call scenario is as follows: Figure 4 As shown in the diagram. Taking a 32-bit RISC-V single-issue processor as an example, in this embodiment, the registers that need to be saved are shown in the red box. However, if the 8-block implementation based on the scheme described in this invention is adopted, only one CSR access configuration instruction and 1 / 8 of the original total clock cycle are needed to complete the saving. If a 16-block scheme is adopted, only one CSR access configuration instruction and 1 / 16 of the original total clock cycle are needed to complete the saving. The overhead during restoration is similar.

[0090] Based on the foregoing embodiments, this application provides a processor storage and recovery device, which includes various units and modules included in each unit, and can be implemented by a processor in a computer device; of course, it can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0091] Figure 5 This is a schematic diagram illustrating the structural composition of a processor storage and recovery device provided in an embodiment of this application. The device is applied to a processor, whose processor core includes a block memory composed of multiple physically independent and parallel-accessible storage units. The processor also includes a software-accessible control status register, which contains a trigger control field for controlling the trigger mode and a register identifier field for identifying the register to be operated on. Figure 5 As shown, the device includes: Monitoring module 401 is used to monitor the occurrence of trigger events associated with field saving or recovery during the operation of the processor core; The processing module 402 is used to, upon detecting the triggering event, determine the selected register from the register file of the processor core according to the configuration status of the triggering control domain and the specific identifier of the register identifier domain, and determine whether to perform a save operation or a restore operation. The execution module 403 is used to transfer data from the selected register to a storage unit in the block memory at high speed through multiple parallel data channels connecting the register file and the block memory to complete the saving, or to transfer data stored in the storage unit to the selected register at high speed to complete the recovery. The high-speed transfer rate is higher than the normal transfer rate of the processor core accessing the block memory through conventional memory access instructions.

[0092] Optionally, the triggering event includes automatic triggering events and semi-automatic triggering events; the control status register is configured with at least four independent bits as the triggering control field, and the at least four independent bits correspond to the automatic push-to-stack triggering function, the automatic pop-to-stack triggering function, the semi-automatic push-to-stack triggering function, and the semi-automatic pop-to-stack triggering function, respectively; The processing module 402 is further configured to: Upon receiving an interrupt signal or an abnormal signal, and with the automatic stack push trigger function in an active state, a context saving operation is initiated for the interrupt signal or abnormal signal. If a preset instruction returning from privileged mode is detected, and the automatic stack popping trigger function is in a valid state, a context recovery operation is initiated for the instruction returning from privileged mode. If a write operation to the control status register is detected, and the write operation enables the semi-automatic push-to-trigger function or the semi-automatic pop-to-trigger function, then a save-to-state or restore-to-state operation is initiated.

[0093] Optionally, the number of bits contained in the register identifier field is equal to the total number of general-purpose registers in the register file of the processor core; The processing module 402 is further configured to: Read the value of each bit in the register identifier field, where each bit corresponds to a general-purpose register with a specific number in the register file; A general-purpose register with a bit value of a first logical value is included in the selected register set, and a general-purpose register with a bit value of a second logical value, which is the opposite of the first logical value, is excluded from the selected register set.

[0094] Optionally, the execution module 403 is further configured to: When a save operation is initiated, data from X registers in the selected register set is read simultaneously via the parallel data channel. When the number of sub-memories Y is greater than or equal to X, the data of X registers is written to X sub-memories in parallel; or when the number of sub-memories Y is less than X, the data of X registers is written to the block memory in parallel in batches of Y each time, wherein the starting write position of the multiple memory units is a preset starting position, and the block memory is composed of Y sub-memories.

[0095] Optionally, the execution module 403 is further configured to: When initiating the field recovery operation, a target storage unit previously used to save the field is identified; Multiple data words are read in parallel from multiple storage cells that constitute the target storage unit; Through the parallel data channel, the multiple data words read in parallel are written in parallel into the corresponding registers in the selected register set.

[0096] Optionally, the execution module 403 is further configured to: Each time a save operation is performed, the starting address of the storage unit used to save the save data is recorded in a stack pointer register or a dedicated address record table. After each on-site recovery operation, the space occupied by the recovered storage unit is released, and the stack pointer register or the dedicated address record table is updated accordingly to point to the storage unit used in the previous save operation.

[0097] Optionally, the execution module 403 is further configured to: If the remaining available space of the block memory is less than a predetermined threshold, the field data stored in one or more storage units at the bottom of the stack in the block memory is moved to the main memory of the processor system through the direct memory access controller. Update the metadata information used to manage the location of field data storage in the block memory.

[0098] This application embodiment monitors various trigger events and parses programmable configurations through hardware, enabling automatic or semi-automatic operation initiation. Utilizing segmented tightly coupled memory and parallel direct data channels, it batch transfers register data flexibly specified by the software at speeds several times faster than traditional software stack pushing or conventional hardware access, without requiring modification of the instruction set or compilation toolchain. The saved data is fully visible and accessible to the software, while the hardware implementation cost is low and there are no stack depth limitations, thereby significantly reducing interrupt response time and function call overhead, and improving the overall operating efficiency of the processor.

[0099] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided in this application can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0100] It should be noted that, in the embodiments of this application, if the above-described processor saving and restoring method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0101] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0102] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0103] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0104] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0105] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0106] It should be noted that, Figure 6 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this application, such as... Figure 6 As shown, the hardware entity of the computer device 700 includes: one or more processors 701, a communication interface 702, and a memory 703, wherein: Processor 701 typically controls the overall operation of computer device 700.

[0107] Communication interface 702 enables computer devices to communicate with other terminals or servers over a network.

[0108] The memory 703 is configured to store instructions and applications executable by the processor 701, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 701 and various modules in the computer device 700. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 701, the communication interface 702, and the memory 703 can be performed via bus 704. Only one processor is shown in the figure; each processor 700 includes one or more cores.

[0109] It should be noted that the computer device may include multiple processors 701, and each processor 701 can interact with each other through aggregated communication methods such as all-to-all, all-gather, or all-reduce. The processors 701 may be central processing units (CPUs), graphics processing units (GPUs), embedded neural network processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), accelerated processing units (APUs), floating-point processing units (FPUs), or application-specific integrated circuits (ASICs). The processors may also be single-core or multi-core processors. The processor may consist of a CPU and hardware chips. The hardware chips may be ASICs, PLDs, or combinations thereof. The PLDs may be complex programmable logic devices (CPLDs), FPGAs, generic array logic (GALs), or any combination thereof. The processor can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs).

[0110] The communication interface 702 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0111] Memory 703 can be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 703 can also be volatile memory, which can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synclink dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM), direct rambus DRAM (DRDRAM), and rambus DRAM.

[0112] The 704 bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc.

[0113] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0114] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0116] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0117] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0118] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0119] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0120] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for saving and restoring a processor, characterized in that, The method is applied to a processor, wherein the processor core of the processor is provided with a block memory, the block memory is composed of multiple physically independent memory cells that can be accessed in parallel, and the processor is also provided with a software-accessible control status register, the control status register including a trigger control field for controlling the trigger mode and a register identifier field for identifying the register to be operated; the method includes: During the operation of the processor core, the occurrence of triggering events associated with field saving or recovery is monitored; Upon detecting the triggering event, the selected register is determined from the register file of the processor core based on the configuration status of the trigger control domain and the specific identifier of the register identifier domain, and a save operation or a restore operation is performed. By connecting the register file and the block memory through multiple parallel data channels, the data of the selected register is transferred at high speed to the storage unit in the block memory to complete the saving, or the data stored in the storage unit is transferred at high speed to the selected register to complete the recovery. The high-speed transfer rate is higher than the normal transfer rate of the processor core accessing the block memory through regular memory access instructions.

2. The method according to claim 1, characterized in that, The triggering events include automatic triggering events and semi-automatic triggering events; the control status register is configured with an independent triggering control field, and the independent triggering control field has at least one of the following functions: automatic stack push triggering function, automatic stack pop triggering function, semi-automatic stack push triggering function, and semi-automatic stack pop triggering function; Based on the configuration status of the trigger control field and the specific identifier of the register identifier field, the steps for performing a save or restore operation are determined, including: Upon receiving an interrupt signal or an abnormal signal, and with the automatic stack push trigger function in an active state, a context saving operation is initiated for the interrupt signal or abnormal signal. If a preset instruction returning from privileged mode is detected, and the automatic stack popping trigger function is in a valid state, a context recovery operation is initiated for the instruction returning from privileged mode. If a write operation to the control status register is detected, and the write operation enables the semi-automatic push-to-tap or semi-automatic pop-to-tap function, then a save-to-state or restore-to-state operation is initiated.

3. The method according to claim 2, characterized in that, The number of bits contained in the register identifier field is equal to the total number of general-purpose registers in the register file of the processor core; The step of determining the selected register from the processor core's register file based on the configuration state of the trigger control domain and the specific identifier of the register identifier domain includes: Read the value of each bit in the register identifier field, where the value of each bit corresponds to a general-purpose register with a specific number in the register file; A general-purpose register with a bit value of a first logical value is included in the selected register set, and a general-purpose register with a bit value of a second logical value, which is the opposite of the first logical value, is excluded from the selected register set.

4. The method according to claim 1, characterized in that, The process of transferring data from the selected register to a storage unit in the block memory at high speed via multiple parallel data channels connecting the register file and the block memory to complete the saving includes: When a save operation is initiated, data from X registers in the selected register set is read simultaneously via the parallel data channel. When the number of sub-memories Y is greater than or equal to X, the data of X registers is written to X sub-memories in parallel; or when the number of sub-memories Y is less than X, the data of X registers is written to the block memory in parallel in batches of Y each time, wherein the starting write position of the multiple memory units is a preset starting position, and the block memory is composed of Y sub-memories.

5. The method according to claim 1, characterized in that, The recovery process involves using multiple parallel data channels connecting the register file and the block memory to rapidly transfer data stored in the memory cell to the selected register, including: When initiating a field recovery operation, the target storage unit previously used to save the field is identified; multiple data words are read in parallel from multiple storage units constituting the target storage unit. Through the parallel data channel, the multiple data words read in parallel are written in parallel into the corresponding registers in the selected register set.

6. The method according to claim 1, characterized in that, The method further includes: Each time a save operation is performed, the starting address of the storage unit used to save the save data is recorded in the stack pointer register or a dedicated address record table. After each on-site recovery operation, the space occupied by the recovered storage unit is released, and the stack pointer register or the dedicated address record table is updated accordingly to point to the storage unit used in the previous save operation.

7. The method according to claim 1, characterized in that, The method further includes: If the remaining available space of the block memory is less than a predetermined threshold, the field data stored in multiple storage cells at the bottom of the stack in the block memory is moved to the main memory of the processor system through the direct memory access controller. Update the metadata information used to manage the location of field data storage in the block memory.

8. A processor storage and recovery device, characterized in that, The device is applied to a processor, wherein the processor core of the processor is provided with a block memory, the block memory being composed of multiple physically independent memory cells that can be accessed in parallel; the processor is also provided with a software-accessible control status register, the control status register including a trigger control field for controlling the trigger mode and a register identifier field for identifying the register to be operated; the device includes: A monitoring module is used to monitor the occurrence of triggering events associated with field saving or recovery during the operation of the processor core; The processing module is used to, upon detecting the triggering event, determine the selected register from the register file of the processor core based on the configuration status of the trigger control domain and the specific identifier of the register identifier domain, and determine whether to perform a save operation or a restore operation. The execution module is used to transfer data from the selected register to a storage unit in the block memory at high speed through multiple parallel data channels connecting the register file and the block memory to complete the saving, or to transfer data stored in the storage unit to the selected register at high speed to complete the recovery. The high-speed transfer rate is higher than the normal transfer rate of the processor core accessing the block memory through conventional memory access instructions.

9. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the save and restore method of the processor according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the processor's save and restore method as described in any one of claims 1 to 7.

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