A data model construction method, system, simulation software and computer device

Abstract

This invention provides a data model construction method, system, simulation software, and computer equipment. The method includes: acquiring a target file to be parsed and reading the target file using a preset reading method; during the reading of the target file, whenever a preset section keyword is detected, constructing a section parser corresponding to the section keyword through a factory class; parsing the section content within a preset range corresponding to the section keyword according to the section parser to obtain parsed data; writing the parsed data into an intermediate data model, wherein the intermediate data model integrates the parsed data in a combined field manner; and converting the intermediate data model into a target data model corresponding to the target EDA product. This solution can effectively parse .asc format PCB files and output the parsing results in a unified data model format, thereby supporting various simulation application scenarios.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and more particularly to a data model construction method, system, simulation software, and computer equipment. Background Technology

[0002] With the increasing complexity of electronic systems, PCB-level simulation is becoming increasingly important in signal integrity, power integrity, and system reliability analysis. To perform board-level simulation, it is typically necessary to parse the completed PCB layout file and convert its structural information, network connections, and geometric information into a data model recognizable by simulation tools. PADS Layout is a commonly used PCB design tool, and its exported .asc format files contain overall board information, component information, network information, routing information, via information, and copper pour information. However, there are numerous versions of the .asc file format, with differences in field definitions and data organization between versions, and the format lacks a unified standardized parsing interface.

[0003] In existing technologies, EDA products typically only support PCB files in their own format or a limited number of common formats. For .asc format files exported from PADSLayout, there is a lack of universal and scalable parsing solutions, making it difficult to directly apply these files to board-level simulation scenarios. Therefore, there is an urgent need for a technical solution that can effectively parse .asc format PCB files and output the parsing results in a unified data model format, thereby supporting various simulation application scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a data model construction method, system, simulation software, and computer equipment to effectively parse .asc format PCB files and output the parsing results in a unified data model format, thereby supporting various simulation application scenarios.

[0005] The technical solution provided by this invention is as follows: Firstly, this application provides a data model construction method, including: Obtain the target file to be parsed, and read the target file using a preset reading method; During the reading of the target file, whenever a preset section keyword is detected, a section parser corresponding to the section keyword is constructed through a factory class; The section parser parses the section content within a preset range corresponding to the section keyword to obtain parsed data. The parsed data is written into an intermediate data model, which integrates the parsed data by combining fields. The intermediate data model is then converted into a target data model corresponding to the target EDA product.

[0006] In some implementations, the preset reading method is any one of line-by-line reading, sentence-by-sentence reading, segmented reading, and block reading; When the reading method is line-by-line reading, the preset range corresponding to the section keyword is the content of the line where the section keyword is located; When the reading method is sentence-by-sentence reading, the preset range corresponding to the section keyword is the content of the sentence in which the section keyword is located; When the reading method is segmented reading, the preset range corresponding to the section keyword is the content of the segment where the section keyword is located; When the reading method is block reading, the preset range corresponding to the section keyword is the content of the preset block where the section keyword is located, and the target file is divided into several blocks.

[0007] In some implementations, the target file is divided into several sections according to the preset reading method; When reading the current section content and detecting the preset section keyword, a section parser corresponding to the section keyword is constructed for parsing. After the current parsing is completed, the next section content is read. Alternatively, when reading the current section content and detecting the preset section keyword, a section parser corresponding to the section keyword is constructed for parsing, and the next section content is read in parallel.

[0008] In some implementations, before obtaining the target file to be parsed, the process further includes: The section keywords are preset, and the configuration file of the section parser corresponding to the section keywords is preset. Each section keyword contains several expandable approximations.

[0009] In some implementations, when the same section keyword is read from different section contents, the corresponding parsed data is merged.

[0010] In some implementations, when multiple different section keywords are read in each section, the section parser corresponding to each different section keyword is constructed sequentially for parsing and the association relationship is marked.

[0011] In some implementations, the target file is an ASCII format PCB file.

[0012] Secondly, this application provides a data model construction system, comprising: The parsing controller is used to read the input target file in a preset reading mode; A factory class is used to construct a section parser corresponding to a preset section keyword whenever a preset section keyword is detected during the process of the parsing master reading the target file; The section parser is used to parse the section content within a preset range corresponding to the section keyword to obtain parsed data; An intermediate data model is used to integrate the parsed data obtained by the various section parsers in a combined field manner; The conversion module is used to convert the intermediate data model into a target data model corresponding to the target EDA product.

[0013] Thirdly, this application provides simulation software, including the data model construction system described in the second aspect.

[0014] Fourthly, this application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the data model construction method described in the first aspect.

[0015] The data model construction method, system, simulation software, and computer equipment provided by this invention have at least the following technical effects: 1) This solution can correctly parse .asc format PCB files exported by PADS Layout and completely restore PCB board-level information, providing a reliable data foundation for PCB board-level post-simulation, simulation analysis after net selection, and comparison between pre-simulation and post-simulation. 2) This solution decouples the file parsing logic from the specific EDA product data structure through an intermediate data model, which can improve the parser's versatility and scalability; 3) This solution supports multiple versions of .asc file formats, which facilitates subsequent maintenance and expansion, and is applicable to various simulation application scenarios that require PCB board-level information. Attached Figure Description

[0016] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.

[0017] Figure 1 This is a schematic diagram of the overall process of one embodiment of the present invention; Figure 2 This is a schematic diagram of the target file parsing process according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the parsing state machine according to an embodiment of the present invention; Figure 4 This is a timing diagram of target file parsing according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the system architecture of one embodiment of the present invention. Detailed Implementation

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0019] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0020] With the increasing complexity of electronic systems, PCB-level simulation is becoming increasingly important in signal integrity, power integrity, and system reliability analysis. To perform board-level simulation, it is typically necessary to parse the completed PCB layout file and convert its structural information, network connections, and geometric information into a data model recognizable by simulation tools. PADS Layout is a commonly used PCB design tool, and its exported .asc format files contain overall board information, component information, network information, routing information, via information, and copper pour information. However, there are numerous versions of the .asc file format, with differences in field definitions and data organization between versions, and the format lacks a unified standardized parsing interface.

[0021] In existing technologies, EDA products typically only support PCB files in their own format or a limited number of common formats. For .asc format files exported from PADSLayout, there is a lack of a universal and scalable parsing solution, making it difficult to directly apply these files to board-level simulation scenarios. Furthermore, existing solutions often tightly couple the file parsing logic with the specific product's internal data structure, making it difficult to adapt to different EDA products or simulation application requirements, and also hindering subsequent version expansion and maintenance. Therefore, there is an urgent need for a technical solution that can effectively parse .asc format PCB files and output the parsing results in a unified data model format, thereby supporting various simulation application scenarios.

[0022] This solution addresses the problem of .asc files being difficult to directly use for board-level simulation in existing technologies by performing structured parsing, constructing a unified intermediate data model, and converting this intermediate data model into the data model required by the target EDA product. It enables PCB layout reconstruction, post-simulation analysis after net selection, and comparison between pre-simulation and post-simulation, making it suitable for various board-level simulation application scenarios. The following is a detailed description of this solution with reference to the accompanying drawings: In one embodiment, refer to the appendix to the specification. Figure 5 This application provides a data model construction system. Based on the content structure characteristics of .asc files, the system constructs models using a keyword-based segmented parsing method. The system architecture includes: a parsing controller, a factory class, a section parser, and an intermediate data model.

[0023] The parsing controller is used to read the input target file in a preset reading mode and schedule the parsing process. In this solution, the target file is a PCB file in ASCII format. The preset reading mode can be line-by-line reading, sentence-by-sentence reading, segmented reading, block reading, etc., and this application does not impose any restrictions. In this embodiment, line-by-line reading is used as an example to describe the process of this solution.

[0024] The factory class is used to construct a section parser corresponding to a predefined section key whenever a preset section key is detected during the process of parsing the target file read by the master controller.

[0025] A section parser is used to parse the section content within a preset range corresponding to a section keyword, obtaining parsed data. Each section parser independently parses its corresponding data section content. Different section keywords correspond to different section parsers. The section parsers in this solution may include PCB section parsers, PART section parsers, ROUTE section parsers, VIA section parsers, POUR section parsers, etc.

[0026] An intermediate data model is used to integrate the parsed data obtained from various parsers by combining fields, so as to uniformly carry the parsed PCB board-level information and facilitate subsequent conversion. The data model construction system of this solution also includes a conversion module, used to convert the intermediate data model into a target data model corresponding to the target EDA product. The conversion process from the intermediate data model to the target data model can be determined according to the structural requirements of the target data model, and this application does not impose any restrictions. Through the above architecture, modular parsing of .asc files and decoupling of the parsing results from the specific EDA product data structure can be achieved, enabling accurate parsing of .asc format PCB files and adapting to different EDA products or different simulation application requirements.

[0027] In this solution, an intermediate data model is constructed to uniformly carry the raw board-level information parsed from .asc format PCB files. The intermediate data model includes at least the following fields: *PCB*: Used to describe the overall properties of the circuit board; *REUSE*: Used to describe reusable instances or reference relationships; *TEXT*: Used to describe board-level text annotation information; *LINES*: Used to describe line segment or geometric contour information; *VIA*: Used to describe via structure and its properties; *PARTDECAL*: Used to describe component package information; *PARTTYPE*: Used to describe component type definition information; *PART*: Used to describe component instances and their layout information on the board; *ROUTE*: Used to describe routing information; *POUR*: Used to describe copper-clad area information; *MISC*: Used to describe additional attribute information; *END*: Used to identify the end of a file or parsing unit.

[0028] The intermediate data model described above can completely preserve the structural information, connection relationships, and geometric information related to PCB board-level simulation in the .asc file. Furthermore, the field information of the intermediate data model is adjustable; in other embodiments, it can be added or deleted as needed.

[0029] In one embodiment, refer to the appendix to the specification. Figure 1 This application provides a data model construction method, including the following steps: S100. Obtain the target file to be parsed and read it using a preset reading method. In this solution, the target file to be parsed is a .asc format file. The preset reading method can be line-by-line reading, sentence-by-sentence reading, segmented reading, block reading, etc. This solution uses line-by-line reading as an example for description.

[0030] S200. During the process of reading the target file, whenever a preset section key is detected, a section parser corresponding to the section key is constructed through the factory class.

[0031] Specifically, before parsing the file, several section keywords are preset. During the reading of the target file, whenever a preset section keyword is read, a section parser corresponding to that section keyword is constructed through a factory class. The section parser is then used to parse the section content within the preset range corresponding to the section keyword.

[0032] S300: The section parser parses the section content within the preset range corresponding to the section keyword to obtain parsed data.

[0033] The content of a section within a preset range is associated with the reading method. For example, when the reading method is line-by-line, the preset range corresponding to the section key is the content of the line containing the section key. That is, during the process of reading the target file line by line, whenever the preset section key is detected in a line, a section parser corresponding to the section key is constructed through a factory class, and the section parser parses the content of the line to obtain the parsed data.

[0034] S400: Write the parsed data into the intermediate data model. The intermediate data model integrates the parsed data by combining fields.

[0035] Specifically, the parsed data from each section parser corresponding to a section keyword is written into an intermediate data model. The intermediate data model can integrate the parsed data output by each section parser by combining fields. For example, in one example, there are five section keywords, which are parsed by five corresponding section parsers. The five parsed data are written into the intermediate data model, and these five parsed data are integrated by combining fields to obtain the overall parsed data of the target file.

[0036] S500: Convert the intermediate data model into a target data model corresponding to the target EDA product.

[0037] For details, please refer to the attached instruction manual. Figures 2 to 4 The parsing controller in this scheme reads the contents of the .asc file using a preset reading method (e.g., line-by-line reading). During the reading process, it performs keyword matching on the current line to determine if a preset section keyword is detected. If not, it continues reading the next line. When a predefined section keyword is detected, a section parser corresponding to that keyword is constructed using a factory class. The constructed section parser is used to parse its corresponding section content and writes the parsed data into the intermediate data model. When the parsing controller detects a new section keyword during subsequent readings, it terminates the parsing process of the current section parser and constructs a new section parser to continue parsing subsequent content. This process continues until the entire .asc file is parsed, ultimately generating a complete intermediate data model.

[0038] After generating the intermediate data model, it is converted into the data model required by the target EDA product. The conversion process from the intermediate data model to the target data model can be determined according to the structural requirements of the target data model, and the processing order and dependencies are not limited in this invention. This invention does not involve specific network topology extraction algorithms or simulation calculation processes, but rather provides basic data support for subsequent network selection, topology extraction, and pre- or post-simulation analysis.

[0039] For example, in a specific example, the parser reads the contents of the .asc file line by line in a streaming manner. When the *PCB* keyword is read, a PCB section parser is created using a factory class to parse the overall board attribute information; when the *PART* keyword is read, a component section parser is created to parse component instance information; when the *ROUTE* keyword is read, a trace section parser is created to parse trace data. Each section parser writes the parsing results into an intermediate data model. After completing file parsing, the intermediate data model is converted into the target data model according to the data model structure of the target EDA product for use in PCB board-level simulation, layout display, or other simulation applications.

[0040] In one embodiment, based on the foregoing embodiments, the preset reading method is any one of line-by-line reading, sentence-by-sentence reading, segmented reading, and block reading. When the reading method is line-by-line reading, the preset range corresponding to the section key is the content of the line containing the section key; when the reading method is sentence-by-sentence reading, the preset range corresponding to the section key is the content of the sentence containing the section key; when the reading method is segmented reading, the preset range corresponding to the section key is the content of the segment containing the section key; when the reading method is block reading, the preset range corresponding to the section key is the content of the preset block containing the section key, and the target file is divided into several blocks. In specific use, a suitable reading method and the division of the target file can be selected according to the requirements and factors such as the length of the target file and the number of section keys.

[0041] In one embodiment, based on the foregoing embodiments, the target file is divided into several sections according to a preset reading method; when reading the current section content and detecting a preset section keyword, a section parser corresponding to the section keyword is constructed for parsing, and after the current parsing is completed, the next section content is read; or, when reading the current section content and detecting a preset section keyword, a section parser corresponding to the section keyword is constructed for parsing, and the next section content is read in parallel.

[0042] Preferably, before obtaining the target file to be parsed, the method further includes: pre-setting section keywords and pre-setting a configuration file for the section parser corresponding to the section keywords. Each section keyword contains several expandable approximations. The pre-set section keywords can be adjusted according to usage requirements to cover circuit board attribute information, board-level text annotation information, reusable instances or reference relationships, line segment or geometric contour information, hole structure and its attribute information, component package information, component type definition information, component instances and their layout information on the board, routing information, copper area information, and additional attribute information in the PCB file. In addition, due to user habits or different naming conventions of different software, several expandable approximations corresponding to the section keywords can be set to accurately identify the section keywords.

[0043] Preferably, when the same section keyword is read from different sections, the corresponding parsed data is merged.

[0044] Preferably, when multiple different section keywords are read in each section, a section parser corresponding to each different section keyword is constructed in sequence for parsing, and the relationship is marked so as to integrate the corresponding information.

[0045] In one embodiment, this application provides simulation software, including the data model building system of the foregoing embodiments. The technical concept of this simulation software is the same as that of the data model building system of the foregoing embodiments, and will not be described in detail here.

[0046] In one embodiment, this application provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the data model construction method of the foregoing embodiment.

[0047] The data model construction method, system, simulation software, and computer equipment provided by this invention have at least the following technical effects: 1) This solution can correctly parse .asc format PCB files exported by PADS Layout and completely restore PCB board-level information, providing a reliable data foundation for PCB board-level post-simulation, simulation analysis after net selection, and comparison between pre-simulation and post-simulation. 2) This solution decouples the file parsing logic from the specific EDA product data structure through an intermediate data model, which can improve the parser's versatility and scalability; 3) This solution supports multiple versions of .asc file formats, which facilitates subsequent maintenance and expansion, and is applicable to various simulation application scenarios that require PCB board-level information.

[0048] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A data model construction method, characterized in that, include: Obtain the target file to be parsed, and read the target file using a preset reading method; During the reading of the target file, whenever a preset section keyword is detected, a section parser corresponding to the section keyword is constructed through a factory class; The section parser parses the section content within a preset range corresponding to the section keyword to obtain parsed data. The parsed data is written into an intermediate data model, which integrates the parsed data by combining fields. The intermediate data model is then converted into a target data model corresponding to the target EDA product.

2. The data model construction method according to claim 1, characterized in that, The preset reading method is any one of line-by-line reading, sentence-by-sentence reading, segmented reading, and block reading; When the reading method is line-by-line reading, the preset range corresponding to the section keyword is the content of the line where the section keyword is located; When the reading method is sentence-by-sentence reading, the preset range corresponding to the section keyword is the content of the sentence in which the section keyword is located; When the reading method is segmented reading, the preset range corresponding to the section keyword is the content of the segment where the section keyword is located; When the reading method is block reading, the preset range corresponding to the section keyword is the content of the preset block where the section keyword is located, and the target file is divided into several blocks.

3. The data model construction method according to claim 1, characterized in that, The target file is divided into several sections according to the preset reading method; When reading the current section content and detecting the preset section keyword, a section parser corresponding to the section keyword is constructed for parsing. After the current parsing is completed, the next section content is read. Alternatively, when reading the current section content and detecting the preset section keyword, a section parser corresponding to the section keyword is constructed for parsing, and the next section content is read in parallel.

4. The data model construction method according to claim 1, characterized in that, Before obtaining the target file to be parsed, the process also includes: The section keywords are preset, and the configuration file of the section parser corresponding to the section keywords is preset. Each section keyword contains several expandable approximations.

5. The data model construction method according to claim 3, characterized in that, Also includes: When the same section keyword is read from different sections, the corresponding parsed data will be merged.

6. The data model construction method according to claim 3, characterized in that, Also includes: When multiple different section keywords are read in each section, the section parser corresponding to each different section keyword is constructed in sequence for parsing, and the association relationship is marked.

7. A data model construction method according to any one of claims 1-6, characterized in that, The target file is a PCB file in ASCII format.

8. A data model construction system, characterized in that, include: The parsing controller is used to read the input target file in a preset reading mode; A factory class is used to construct a section parser corresponding to a preset section keyword whenever a preset section keyword is detected during the process of the parsing master reading the target file; The section parser is used to parse the section content within a preset range corresponding to the section keyword to obtain parsed data; An intermediate data model is used to integrate the parsed data obtained by the various section parsers in a combined field manner; The conversion module is used to convert the intermediate data model into a target data model corresponding to the target EDA product.

9. A simulation software, characterized in that, Includes the data model building system as described in claim 8.

10. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the data model construction method according to any one of claims 1-7.

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