A chopping-based operational amplifier circuit

Abstract

The application discloses a kind of based on chopping operational amplifier circuit, the positive and negative input of operational amplifier circuit is connected to operational amplifier unit through a pair of differential pair input, then is output through output stage, operational amplifier unit includes two gain boost operational amplifier, operational amplifier circuit also includes offset voltage adjustment current circuit, chopping switch is equipped at the positive and negative input of operational amplifier circuit, the input of gain boost operational amplifier and inside, gain boost gain boost folded cascode operational amplifier with chopping technology is used, including common-mode voltage control, while improving the output impedance and gain of cascode stage, the offset, drift and 1 / f noise of itself can be eliminated, offset voltage adjustment current circuit reduces the offset voltage caused by transistor size variation in production and manufacture, output stage uses DC bias voltage control circuit, both ensure that output tube is slightly on, improve the output response speed of operational amplifier, and can be controlled at lower static power consumption level.The application realizes effective zero drift technology by independent chopping circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to operational amplifier circuits, specifically a chopper-based operational amplifier circuit. Background Technology

[0002] Ideally, the voltages at the two input terminals of an operational amplifier should be equal, but in reality, there is a small inherent error voltage. In some high-precision amplifier applications, such as instruments, sensors, and DC measurements, the electrical signal itself is very small and weak, and even a small error will be amplified. Therefore, in these applications, the offset voltage of the op-amp should be as small as possible, preferably close to 0. A zero-drift op-amp is a high-precision op-amp specifically designed to eliminate DC or low-frequency errors. It uses chopping, self-stabilization, or a combination of both techniques to eliminate unwanted low-frequency error sources, such as input offset voltage and 1 / f noise.

[0003] Figure 1 This is a schematic diagram of a rail-to-rail amplifier disclosed in Chinese Patent CN105871344A. It adopts a structure combining chopping technology and self-stabilizing zero technology, including automatic zeroing and amplification stages. In the automatic zeroing stage, the input differential pairs are separated from the subsequent stages, and a bias current is determined for automatic zeroing of the input offset voltage. During the amplification stage, the two input differential pairs can be coupled to the subsequent stages for continuous selection, or the selected input differential pairs can be coupled to the subsequent stages for discrete selection.

[0004] However, due to the noise folding of self-stabilizing zero technology and the need for additional channels to support continuous operation, using a separate chopping scheme can reduce circuit complexity and power consumption for independent operational amplifiers. If the chopping scheme can be further improved to reduce the disadvantages of the separate chopping scheme, then the separate chopping scheme will be a better zero-drift technology for independent operational amplifiers.

[0005] For chopper solutions, due to manufacturing mismatches between transistors in the circuit—specifically, dimensional deviations between NMOS and PMOS transistors during actual production—the input offset voltage of the chopper amplifier varies with different transistor configurations, meaning the initial offset voltage is highly discrete and cannot be completely eliminated. Furthermore, the offset voltage changes with temperature and power supply voltage (i.e., "drift"), making it difficult to meet the accuracy requirements at the microvolt (μV) or even nanovolt (nV) level. Additionally, when rail-to-rail op-amps are used in power amplifiers, it is necessary to eliminate crossover distortion from the output power transistors and control the static signal, requiring careful design of the output stage bias.

[0006] In summary, superior chopping technology is more suitable for independent operational amplifiers. It is also necessary to eliminate offset voltage caused by the manufacturing process of transistors. In addition, power amplifiers need to control the bias voltage of the output transistors to achieve low power consumption and eliminate crossover distortion. Summary of the Invention

[0007] The technical problem this invention aims to solve is the noise folding inherent in self-stabilizing zero-amplifier technology and the need for additional channels to support continuous operation, which significantly increases circuit complexity. This invention studies how to further optimize the chopping effect based on an independent chopper operational amplifier, while introducing tuning techniques to minimize the impact of offset and noise.

[0008] The technical solution of this invention is as follows: an operational amplifier circuit based on chopper, wherein the positive and negative inputs of the operational amplifier circuit pass through an input stage chopper switch, a pair of complementary differential input pairs, an output stage chopper switch, an auxiliary gain operational amplifier unit, and then output through an output stage. The auxiliary gain operational amplifier unit includes gain boost operational amplifiers EA1 and EA2. The operational amplifier circuit also includes an offset voltage adjustment current circuit and first to third bias voltage circuits, configured as follows:

[0009] The first bias voltage circuit generates bias voltages VC3 and VC1, where VC1 provides the input common-mode voltage reference for the gain boost operational amplifier EA2, and VC3 provides bias for the N-type cascode transistor. The second bias voltage circuit generates bias voltages VC4 and VC2, where VC2 provides the input common-mode voltage reference for the gain boost operational amplifier EA1, and VC4 provides bias for the P-type cascode transistor. Gain boost operational amplifiers EA1 and EA2 provide gate voltages for the PMOS and NMOS transistors, respectively. The third bias voltage circuit generates bias voltages PC and NC to provide DC bias voltages for the output transistors. BP and BN are the general bias voltages for PMOS and NMOS transistors, respectively.

[0010] The bodies of N1-N13, N31, and output transistor Npower are connected to VSS potential; the bodies of P1-P13, P31, and output transistor Ppower are connected to VDD potential; the sources of P3, P4, P5, P14, P15, P17, P18, and Ppower are connected to VDD potential; the sources of N3, N4, N5, N15, N16, N17, N20, and Npower are connected to VSS potential; among these, the sources of N1 and N2 are connected together and then connected to the drain of N31, the source of N31 is connected to the drain of N3, and the gate of N31 is connected to VC3. The gate of N3 is connected to BN, forming the NMOS differential pair input of the folded cascode op-amp; the sources of P1 and P2 are connected to the drain of P31, the source of P31 is connected to the drain of P3, the gate of P31 is connected to VC4, and the gate of P3 is connected to BP, forming the PMOS differential pair input of the folded cascode op-amp; P4 and P10, P5 and P11, N4 and N10, N5 and N11 form a cascode circuit, and the output stage chopper switches include a high-side chopper switch composed of P6, P7, P8, and P9, and a low-side chopper switch composed of N6, N7, N8, and N9, with the following connection relationships:

[0011] The drain of N1 is connected to the drain of P5, the source of P9, the drain of P6, and the negative input terminal of EA1; the drain of N2 is connected to the drain of P4, the source of P8, the drain of P7, and the positive input terminal of EA1; the gates of P4 and P5 are connected to BP; the drain of P8 is connected to the source of P6 and the source of P10; the drain of P10 is connected to the source of P12 and the drain of N12; the source of N12 is connected to the source of P12, the drain of N10, and the gates of N4 and N5; the source of N10 is connected to the drain of N9 and the drain of N7; the source of N9 is connected to the drain of N6, the drain of P2, and the positive input terminal of EA2; the drain of P9 is connected to the source of P11 and the source of P7; the source of N11 is connected to the drain of N8 and the source of N6; the source of N8 is connected to the drain of N5 and the drain of N7. The source of EA1, the negative input of EA2, and the drain of P1 are connected. The negative output of EA2 is connected to the gate of N10, and the positive output is connected to the gate of N11. The positive output of EA1 is connected to the gate of P11, and the negative output is connected to the gate of P10. The drain of P11 is connected to the drain of N13, the source of P13, the gate of Ppower, and one end of the compensation capacitor C1. The source of N13 is connected to the drain of P13, the drain of N11, the gate of Npower, and one end of the compensation capacitor C2. The other ends of C1 and C2 are connected to the drains of Ppower and Npower, and serve as the output terminal Out of the op-amp circuit. The gates of N12 and N13 are connected to the bias voltage NC, and the gates of P12 and N12 are connected to the bias voltage PC.

[0012] The offset voltage correction current circuit outputs correction currents BA and BB. BA is connected to the drain of N1 and the drain of P5, and BB is connected to the drain of N2 and the drain of P4. The input offset voltage is corrected through a one-time correction.

[0013] The oscillator signal CLK of the operational amplifier circuit is inverted once to generate signal E, and then inverted again to generate signal F. The positive input terminal INP and the negative input terminal INN of the operational amplifier circuit are each equipped with two sets of input stage chopper switches for switching the connection with the differential input. Signals E and F serve as control signals for the chopper switches. In the high-side and low-side chopper switches, the gates of P6, P7, N8, and N9 are connected to signal F, and the gates of P8, P9, N6, and N7 are connected to signal E. When E... When E=0 and F=1, through the input stage chopper switch, INP is output to the gates of N1 and P1, and INN is output to the gates of N2 and P2. P8, P9, N8, and N9 are turned on, while P6, P7, N6, and N7 are turned off. When E=1 and F=0, INP is output to the gates of N2 and P2, and INN is output to the gates of N1 and P1. P8, P9, N8, and N9 are turned off, while P6, P7, N6, and N7 are turned on, completing one cycle of chopping operation of CLK.

[0014] Furthermore, the input stage chopper switch consists of NMOS transistors NS and PMOS transistors PS, including NS1 and PS1, NS2 and PS2, NS3 and PS3, and NS4 and PS4. INP is connected to the source of NS1 and PS1, and the source of NS3 and PS3; INN is connected to the source of NS2 and PS2, and the source of NS4 and PS4; the drain of NS1 and PS1 is connected to the drain of NS2 and PS2, and then to the gate of N1 and P1; the drain of NS3 and PS3 is connected to the drain of NS4 and PS4, and then to the gate of N2 and P2; the body terminals of NS1, NS2, NS3, and NS4 are connected to the VSS voltage, and the body terminals of PS1, PS2, PS3, and PS4 are connected to the VDD voltage; the gates of NS1, PS2, PS3, and NS4 are connected to signal F, and the gates of NS2, PS1, PS4, and NS3 are connected to signal E.

[0015] Furthermore, the first bias voltage circuit includes PMOS transistors P17, NMOS transistors N17, N18, and N19; the second bias voltage circuit includes NMOS transistors N20, PMOS transistors P18, P19, and P20; and the third bias voltage circuit includes PMOS transistors P14, P15, and P16, and NMOS transistors N14, N15, and N16. The body terminals of NMOS transistors N14 to N20 are connected to the VSS potential, and the body terminals of PMOS transistors P14 to P20 are connected to the VDD potential.

[0016] In the first bias voltage circuit, the gate of P17 is connected to BP, the source is connected to VDD potential, and the drain is connected to the drain and gate of N19. A bias voltage VC3 is generated between the drain and gate of N19. The source of N19 is connected in series with the drain of N18 and outputs a bias voltage VC1, which is connected to the VC1 terminal of EA2. The gate of N19 is connected to the gates of N17 and N18. The source of N18 is connected in series with the drain of N17. The source of N17 is connected to VSS.

[0017] In the second bias voltage circuit, the source of P18 is connected to VDD, the gates of P18, P19 and P20 are connected, the drain of P18 is connected to the source of P19, the drain of P19 is connected to the source of P20, the output bias voltage VC2 between the drain of P19 and the source of P20 is connected to the VC2 terminal of EA1, the drain of P20 is connected to the gate and connected to the drain of N20, a bias voltage VC4 is generated between the gate and drain of P20, and the source of N20 is connected to the VSS potential.

[0018] In the third bias voltage circuit, the sources of P14 and P15 are connected to VDD potential, the gate of P14 is connected to BP, and the drain is connected to the drain of N14. The gate and drain of N14 are connected, generating a bias voltage NC between the gate and drain of N14. The drain and gate of P15 are connected and connected to the source of P16. The gate and drain of P16 are connected, generating a bias voltage PC between the gate and drain of P16. The drain of P16 is connected to the drain of N16. The source of N14 is connected to the drain and gate of N15, the gate of N16, and the gate of N20. The sources of N15 and N16 are connected to VSS potential.

[0019] Furthermore, the circuit of the gain boost operational amplifier EA1 is as follows: I+ and I- are the positive and negative input terminals of the gain boost operational amplifier, respectively; VC2 is the common-mode voltage; and O+ and O- are the positive and negative output terminals of the gain boost operational amplifier. The gain boost operational amplifier EA1 is a folded common-source common-gate operational amplifier with three-terminal NMOS input and two-terminal output. The circuit includes NMOS transistors N0A~N11A and N31A, and PMOS transistors P4A~P11A.

[0020] The body terminals of all NMOS transistors are connected to the VSS potential; the body terminals of all PMOS transistors are connected to the VDD potential; the sources of N3A, N4A, and N5A are connected to the VSS potential; the sources of P4A and P5A and the drain of N0A are connected to the VDD potential; the sources of N0A, N1A, and N2A are connected together to the drain of N31A; the source of N31A is connected to the drain of N3A; the gates of N31A, N10A, and N11A are connected to VC3; the gates of N3A, N4A, and N5A are connected to BN; the gates of P4A and P5A are connected to BP; the gates of P10A and P11A are connected to VC4; the gates of P8A, P9A, N6A, and N7A are connected to signal E; the gates of P6A, P7A, N8A, and N9A are connected to signal F; the gate of N0A is connected to signal VC2; and the gate of N1A is connected to I+. The positive input terminal is connected to the gate of N2A (I-), which is the negative input terminal. The drain of N1A is connected to the drain of P5A, the source of P9A, and the source of P6A. The drain of P9A is connected to the source of P7A and the source of P11A. The drain of P11A outputs an O- signal, which is connected to the drain of N11A. The source of N11A is connected to the drain of N8A and the drain of N6A. The source of N8A is connected to N... The drain of N7A and the drain of N5A are connected; the drain of N2A is connected to the drain of P4A, the source of P8A, and the drain of P7A; the drain of P8A is connected to the drain of P6A and the source of P10A; the drain of P10A outputs a O+ signal and is connected to the drain of N10A; the source of N10A is connected to the drain of N9A and the source of N7A; the source of N9A is connected to the drain of N4A and the source of N6A.

[0021] The reference voltage VC2 is introduced at the input terminal of N0A to set the common-mode voltage of I+ and I-. This, combined with the negative feedback gain boost of the cascode op-amp connected to the dual-ended input and output, controls the cascode voltage to meet the set DC operating point. A chopper circuit is introduced in the folded cascode, where P4A and P10A, P5A and P9A, N4A and N9A, and N5A and N8A form cascode, and P6A, P7A, P8A, and P9A form the high-side chopper switch within EA1. N6A, N7A, N8A, and N9A form the low-side chopper switch inside EA1, controlled by signals E and F respectively. When E=0 and F=1, P8A, P9A, N9A, and N8A are turned on, while P6A, P7A, N6A, and N7A are all turned off. When E=1 and F=0, P8A, P9A, N9A, and N8A are turned off, while P6A, P7A, N6A, and N7B are all turned on. The detection signals of I+ and I- switch with the E and F signals, completing the switching of one oscillation cycle.

[0022] Furthermore, the circuit of the gain boost operational amplifier EA2 is as follows: I+ and I- are the positive and negative input terminals of the gain boost operational amplifier, respectively; VC1 is the common-mode voltage; and O+ and O- are the positive and negative output terminals of the gain boost operational amplifier. The gain boost operational amplifier EA2 is a folded common-source common-gate operational amplifier with three-terminal PMOS input and two-terminal output. The circuit includes NMOS transistors N4B~N11B, and PMOS transistors P0B~P11B and P31B.

[0023] The body terminals of all NMOS transistors are connected to the VSS potential; the body terminals of all PMOS transistors are connected to the VDD potential; the sources of N4B and N5B are connected to the VSS potential; the sources of P3B, P4B, and P5B are connected to the drain of P31B, and the source of P31B is connected to the drain of P3B; the drain of P0B is connected to the VSS potential; the gates of N10B and N11B are connected to VC3; the gates of N4B and N5B are connected to BN; the gates of P3B, P4B, and P5B are connected to BP; the gates of P31B, P10B, and P11B are connected to VC4; the gates of P8B, P9B, N6B, and N7B are connected to signal E; the gates of P6B, P7B, N8B, and N9B are connected to signal F; the gate of P0B is connected to VC1, and the gate of P1B is connected to I+, which is the non-inverting input terminal; the gate of P2B... The gate is connected to I-, serving as the negative phase input. The drain of P5B is connected to the source of P9B and the source of P6B. The drain of P9B is connected to the source of P7B and the source of P11B. The drain of P11B outputs an O- signal, which is connected to the drain of N11B. The source of N11B is connected to the drain of N8B and the drain of N6B. The source of N8B is connected to the drain of N7B, the drain of N5B, and the drain of P1B. The drain of P4B is connected to the source of P8B and the drain of P7B. The drain of P8B is connected to the drain of P6B and the source of P10B. The drain of P10B outputs an O+ signal, which is connected to the drain of N10B. The source of N10B is connected to the drain of N9B and the source of N7B. The source of N9B is connected to the drain of N4B, the source of N6B, and the drain of P2B.

[0024] A reference voltage VC1 is introduced at the P0B input terminal to set the common-mode voltage of I+ and I-. This, combined with the dual-ended input and output, forms a negative feedback gain boosting operational amplifier to control the common-source gate voltage to meet the set DC operating point. A chopper circuit is introduced in the folded common-source gate circuit, where P4B and P10B, P5B and P9B, N4B and N9B, and N5B and N8B form common-source gate circuits respectively, and P6B, P7B, P8B, and P9B form the high-side chopper switch within EA2. N6B, N7B, N8B, and N9B form the low-side chopper switch inside EA2, controlled by signals E and F respectively. When E=0 and F=1, P8B, P9B, N9B, and N8B are turned on, while P6B, P7B, N6B, and N7B are all turned off. When E=1 and F=0, P8B, P9B, N9B, and N8B are turned off, while P6B, P7B, N6B, and N7B are all turned on. The detection signals of I+ and I- switch with the E and F signals, completing the switching of one oscillation cycle.

[0025] Furthermore, the offset voltage adjustment current circuit is as follows: A0, A1, and A2 are adjustment control signals, which are generated by an inverter (inv) and a NAND gate (nand) into pairs of inverted adjustment signals Y0 and Y01, Y1 and Y11, Y2 and Y21, Y3 and Y31, Y4 and Y41, Y5 and Y51, Y6 and Y61, and Y7 and Y71. BA and BB are the two output ports of the offset voltage adjustment current circuit, respectively. The current source PMOS transistors include FP1, FP2, FP3, FP4, and FP5, with the following dimensions:

[0026] FP1:FP2:FP3:FP4:FP5=1:2:4:8:16

[0027] The source and body terminals of FP1, FP2, FP3, FP4, and FP5 are connected to VDD; the body terminals of PMOS transistors FP11, FP12, FP21, FP22, FP31, FP32, FP41, FP42, FP51, and FP51 are connected to VDD potential; the drain of FP1 is connected to the source of FP11 and FP12, and the gate of FP11 and the gate of FP12 are connected to adjustment control signals Y0 and Y01, respectively; the drain of FP2 is connected to the source of FP21 and FP22, and the gate of FP21 and the gate of FP22 are connected to adjustment control signals Y1 and Y11, respectively; the drain of FP3 is connected to FP31 and FP32. The source of FP2, the gate of FP31 and the gate of FP32 are connected to adjustment control signals Y2 and Y21 respectively; the drain of FP4 is connected to the source of FP41 and FP42, and the gate of FP41 and the gate of FP42 are connected to adjustment control signals Y3 and Y31 respectively; the drain of FP5 is connected to the source of FP51 and FP52, and the gate of FP51 and the gate of FP52 are connected to adjustment control signals Y4 and Y41 respectively; the drains of FP11, FP21, FP31, FP41 and FP51 are connected together to output the BA signal; the drains of FP12, FP22, FP32, FP42 and FP52 are connected together to output the BB signal.

[0028] Furthermore, in the offset voltage adjustment current circuit, the circuit that generates paired inverted adjustment signals from the adjustment control signals A0, A1, and A2 is specifically as follows:

[0029] A2 connects to the input of inv21, and the output of inv21 connects to the input of inv22, and is also connected to terminal 3 of NAND5, terminal 2 of NAND6 and NAND7, and terminal 1 of NAND8; the outputs of inv22 connect to terminal 1 of NAND1 and NAND4, and terminal 2 of NAND2 and NAND3; A1 connects to the input of inv31, and the output of inv31 connects to the input of inv32, as well as terminal 3 of NAND3 and NAND7, and terminal 4 of NAND8. Terminal 2 of NAND 8; the output of inv32 is connected to terminal 2 of NAND 1, and terminal 1 of NAND 2, NAND 5, and NAND 6; A0 is connected to the input of inv41, the output of inv41 is connected to the input of inv42, and terminal 3 of NAND 2, NAND 4, NAND 6, and NAND 8; the output of NAND 1 is connected to the input of inv23, the output of inv23 is Y71 and connected to the input of inv24, and the output of inv24 is Y7; the output of NAND 2... The output of nand3 is connected to the input of inv33. Inv33 outputs Y61, which is then connected to the input of inv34, causing inv34 to output Y6. The output of nand3 is connected to the input of inv43. Inv43 outputs Y51, which is then connected to the input of inv54, causing inv54 to output Y5. The output of nand4 is connected to the input of inv53. Inv53 outputs Y41, which is then connected to the input of inv54, causing inv54 to output Y4. The output of nand5 is connected to the input of inv63, which outputs Y61... Y31 is output and connected to the input of inv64, inv64 outputs Y3; the output of nand6 is connected to the input of inv73, inv73 outputs Y21 and is connected to the input of inv74, inv74 outputs Y2; the output of nand7 is connected to the input of inv83, inv83 outputs Y11 and is connected to the input of inv84, inv84 outputs Y1; the output of nand8 is connected to the input of inv93, inv93 outputs Y01 and is connected to the input of inv94, inv94 outputs Y0.

[0030] The circuit of this invention has the following beneficial effects;

[0031] First, this invention designs chopper switching circuits for both the input and output stages to eliminate input offset voltage. It also employs a gain-boost folded cascode op-amp with chopping technology. Furthermore, based on the traditional gain-boost op-amp circuit, chopping technology, including common-mode voltage control, is introduced to further enhance the gain-boost op-amp circuit. This not only improves the cascode output impedance and gain but also eliminates its own offset, drift, and 1 / f noise.

[0032] Secondly, an offset voltage adjustment current circuit was designed for the operational amplifier circuit. The bias current adjustment technology was used to adjust the offset voltage caused by the device size difference introduced in the production, thereby significantly reducing the offset voltage caused by the transistor size change in the manufacturing process.

[0033] Finally, the bias voltages PC and NC designed in this invention, combined with N13 and P13, provide DC bias voltages to the output stages Ppower and Npower. The output transistors adopt a DC bias voltage control circuit, which not only ensures that the two output transistors are slightly turned on, improving the output response speed of the op-amp, but also controls the power consumption at a low level.

[0034] Therefore, this invention achieves effective zero-drift technology through an independent chopper circuit, effectively eliminating offset, drift, and 1 / f noise. The circuit is simple and easy to implement. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a rail-to-rail amplifier disclosed in prior art CN105871344.

[0036] Figure 2 This is a circuit diagram of the chopper-based operational amplifier circuit of the present invention.

[0037] Figure 3 This is a circuit diagram of the gain boosting operational amplifier EA1 in the chopper-based operational amplifier circuit of this invention.

[0038] Figure 4 This is a circuit diagram of the gain boosting operational amplifier EA2 in the chopper-based operational amplifier circuit of this invention.

[0039] Figure 5 This is a circuit diagram of the offset voltage adjustment current of the present invention.

[0040] Figure 6 The diagram shows the effect of noise reduction before and after using the chopper circuit of this invention.

[0041] Figure 7 The figure shows the simulation results of offset voltage cancellation after using the chopper circuit design of this invention. Detailed Implementation

[0042] The implementation of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] like Figure 2The diagram shown is a circuit schematic of the present invention. The positive and negative inputs of the operational amplifier circuit pass through an input stage chopper switch, a pair of complementary differential input pairs, an output stage chopper switch, an auxiliary gain operational amplifier unit, and then through an output stage. The auxiliary gain operational amplifier unit includes gain boost operational amplifiers EA1 and EA2. The operational amplifier circuit also includes an offset voltage adjustment current circuit and first to third bias voltage circuits.

[0044] The specific circuit is as follows: CLK is connected to the input of inverter inv1, outputting an E signal which is then connected to the input of inverter inv2. Inv2 outputs an F signal. INP is connected to the sources of NS1 and PS1, and the sources of NS3 and PS3. INN is connected to the sources of NS2 and PS2, and the sources of NS4 and PS4. The drains of NS1 and PS1 are connected to the drains of NS2 and PS2, and then to the gates of N1 and P1. The drains of NS3 and PS3 are connected to the drains of NS4 and PS4, and then to the gates of N2 and P2. The bodies of NS1, NS2, NS3, and NS4 are connected to the VSS voltage, and the bodies of PS1, PS2, PS3, and PS4 are connected to the VDD voltage. The gates of NS1, PS2, PS3, NS4, P6, P7, N8, and N9 are connected to the F signal, and the gates of NS2, PS1, PS4, NS3, P8, P9, N6, and N7 are connected to the E signal.

[0045] The body terminals of N1, N2, N3, N31, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, and Npower are connected to the VSS potential; P1, P2, P3, P31, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, and P18 are connected to the VSS potential. The body terminals of P19, P20, and Ppower are connected to VDD potential; the sources of P3, P4, P5, P14, P15, P17, P18, and Ppower are connected to VDD potential; the sources of N3, N4, N5, N15, N16, N17, N20, and Npower are connected to VSS potential; the source of N1 is connected to the source of N2, and then to the drain of N31; the source of N31 is connected to the drain of N3; the gate of N31 is connected to VC3; the gate of N3 is connected to BN. The drain of N1 is connected to the BA terminal, the drain of P5, the source of P9, the drain of P6, and the negative input terminal of EA1; the drain of N2 is connected to the BB terminal, the drain of P4, the source of P8, and the drain of P7; the drain of P8 is connected to the source of P6 and the source of P10; the drain of P10 is connected to the source of P12 and the drain of N12; the source of N12 is connected to the source of P12, the drain of N10, and the gates of N4 and N5; the source of N10 is connected to the drains of N9 and N7, and the source of N9 is connected to the drain of N6, P... The drain of P2 is connected to the non-inverting input of op-amp EA2; the drain of P9 is connected to the source of P11 and the source of P7; the drain of P11 is connected to the drain of N13, the source of P13, the gate of Ppower, and one end of C1; the source of N13 is connected to the drain of P13, the drain of N11, the gate of Npower, and one end of C2; the other ends of C1 and C2 are connected to the drains of Out, Ppower, and Npower; the source of N11 is connected to the drain of N8 and the source of N6.The source of N8 is connected to the drain of N5, the source of N7, the negative input of EA2, and the drain of P1; the positive output of EA1 is connected to the gate of P11, and the negative output is connected to the gate of P10; the negative output of EA2 is connected to the gate of N10, and the positive output is connected to the gate of N11; the gates of N12 and N13 are connected to the NC signal, the gate and drain of N14, and the drain of P15; the gate of P12 is connected to the gate of P13, the PC signal, the gate and drain of P16, and the drain of N16; the gates of P4, P5, P14, and P17 are connected to the BP signal; the source of N14 is connected to the drain of N15. The source of P16 is connected to the drain and gate of P15; the drain of P17 is connected to the VC3 signal, the drain and gate of N19, and the gates of N17 and N18; the source of N19 is connected in series with the drain of N18 and outputs the VC1 signal, which is connected to the VC1 terminal of EA2; the source of N18 is connected in series with the drain of N17; the drain of N20 is connected to the drain and gate of P20, and the gates of P18 and P19; the source of P20 is connected in series with the drain of P19 and outputs the VC2 signal, which is connected to the VC2 terminal of EA1; the source of P19 is connected to the drain of P18.

[0046] The circuit principle of this invention is as follows.

[0047] CLK is the oscillator signal of a general-purpose ring oscillator; E and F are the output signals of CLK after passing through an inverter, respectively; INP and INN are the positive and negative input terminals of the operational amplifier, respectively; Out is the output terminal of the operational amplifier; BP and BN are the general-purpose bias voltages for PMOS and NMOS transistors, respectively, used to generate bias current; BA and BB are the output signal terminals of the offset voltage trimming current circuit; EA1 and EA2 are gain boost operational amplifiers with chopper technology, providing gate voltages for the PMOS and NMOS common-source common-gate circuits, respectively; VC1, VC2, VC3, and VC4 are the bias voltages generated by the bias circuit; VDD is a high potential, and VSS is a low potential.

[0048] The first bias voltage circuit includes P17, N17, N18, and N19, which are used to generate bias voltages VC3 and VC1, where VC1 is used to provide an input common-mode voltage reference for EA2, and VC3 is used to provide bias for the N-type cascode circuit; the second bias voltage circuit includes N20, P18, P19, and P20, which are used to generate bias voltages VC4 and VC2, where VC2 is used to provide an input common-mode voltage reference for EA1, and VC4 is used to provide bias for the P-type cascode circuit.

[0049] The third bias voltage circuit includes P14, N14, N15, N16, P15, and P16, which generate bias voltages PC and NC. Combined with N13 and P13, these provide DC bias voltages to the output stages Ppower and Npower, thereby enabling Ppower and Npower to conduct slightly, improving the output response speed of the op-amp, while keeping the static power consumption at a low level. N12 and P12 are auxiliary transistors introduced for dual-channel matching.

[0050] Wherein the gate voltage of Ppower is:

[0051] Vsg(Ppower)=Vsg(P15)+Vsg(P16)-Vsg(P13)

[0052] Where the gate voltage of Npower is:

[0053] Vgs(Npower)=Vgs(N15)+Vgs(N14)-Vgs(N13)

[0054] By adjusting the W / L ratio of P15, P16, P13, N15, N14, and N13, suitable gate voltages for Ppower and Npower can be obtained, thereby controlling their on-current.

[0055] The drain current of the NMOS transistor is I N =μ n C ox (Vgs-Vthn) 2 / 2*( W / L), where μ n denoted as NMOS transistor carrier mobility, Cox as gate oxide capacitance per unit area, and W / L as the width-to-length ratio of the NMOS transistor.

[0056] Vgs=[2*I N / (W / L)( μ n C ox )] 1 / 2 + Vthn.

[0057] The dimensions and bias current of N13, N14, and N15 can be designed to obtain a suitable voltage.

[0058] ΔVgs N=Vgs(N15)+Vgs(N14)-Vgs(N13)

[0059] If the size of the N-power transistor is fixed, then the corresponding drain current is:

[0060] I Npower =μ n C ox (ΔVgsN-Vthn)2 / 2*( W / LN)

[0061] It can achieve both low power consumption control and micro-conduction of Npower, thus accelerating the turn-on speed.

[0062] Similarly, the dimensions and bias currents of P13, P15, and P16 can be designed, while the dimensions of the Ppower transistor are fixed, and the corresponding drain current is...

[0063] I Ppower =μ p C ox (ΔVsgP-Vthp) 2 / 2*( W / LP)

[0064] It can achieve both low power consumption control and micro-conduction of Ppower, thus accelerating the turn-on speed.

[0065] NS1 and PS1, NS2 and PS2, NS3 and PS3, NS4 and PS4 are input stage chopper switches used to control the switching of input signals INP and INN. When E=0 and F=1, INP is output to the gates of N1 and P1 through NS1 and PS1, and INN is output to the gates of N2 and P2 through NS4 and PS4. When E=1 and F=0, INP is output to the gates of N2 and P2 through NS2 and PS2, and INN is output to the gates of N1 and P1 through NS3 and PS3.

[0066] The output stage chopper switch includes a high-side chopper switch composed of P6, P7, P8, and P9, and a low-side chopper switch composed of N6, N7, N8, and N9. When E=0 and F=1, P8, P9, N9, and N8 are turned on, and P6, P7, N6, and N7 are turned off. When E=1 and F=0, P8, P9, N9, and N8 are turned off, and P6, P7, N6, and N7 are turned on.

[0067] Therefore, when E=0 and F=1, INP is output to the gates of N1 and P1, INN is output to the gates of N2 and P2, and P8, P9, N9, and N8 are turned on; when E=1 and F=0, INN is output to the gates of N1 and P1, INP is output to the gates of N2 and P2, and P6, P7, N6, and N7 are turned on; thus completing one cycle of chopping operation of CLK.

[0068] N1, N2, N31, and N3 form the NMOS differential input of the folded cascode op-amp; P1, P2, P31, and P3 form the PMOS differential input of the folded cascode op-amp; P4 and P10, P5 and P11, N4 and N10, and N5 and N11 form the cascode circuit; the gain boost amplifier EA1 detects the drain voltages of P4 and P5 respectively, and due to the introduction of the common-mode voltage VC2, the gates of P10 and P11 are controlled through negative feedback, so the drain voltages of P4 and P5 are approximately equal to the VC2 voltage; similarly, the gain boost amplifier EA2 detects the drain voltages of N4 and N5 respectively, and due to the introduction of the common-mode voltage VC1, the gates of N10 and N11 are controlled through negative feedback, so the drain voltages of N4 and N5 are approximately equal to the VC1 voltage.

[0069] C1 and C2 are used as compensation capacitors to introduce Miller compensation in the output stages of Ppower and Npower.

[0070] This invention further improves the gain boost operational amplifiers EA1 and EA2 by introducing chopping technology into the gain boost operational amplifiers to achieve common-mode voltage control.

[0071] As an example, Figure 3 The connection relationship of the gain booster operational amplifier EA1 in the circuit of the present invention is shown.

[0072] BN and VC3, BP and VC4 are bias currents, E and F are chopper-controlled oscillator signals, and VC2 is the reference potential.

[0073] The body terminals of N1A, N2A, N31A, N3A, N10A, N11A, N6A, N7A, N8A, N9A, N4A, and N5A are connected to VSS voltage; the body terminals of P4A, P5A, P6A, P7A, P8A, P9A, P10A, and P11A are connected to VDD; the sources of N3A, N4A, and N5A are connected to VSS voltage; the sources of P4A and P5A and the drain of N0A are connected to VDD; N0A The sources of N1A and N2A are connected together to the drain of N31A; the source of N31A is connected to the drain of N3A; the gates of N31A, N10A, and N11A are connected to the VC3 voltage; the gates of N3A, N4A, and N5A are connected to the BN signal; the gates of P4A and P5A are connected to the BP signal; the gates of P10A and P11A are connected to the VC4 signal; the gates of P8A, P9A, N6A, and N7A are connected to the E signal; the gates of P6A, P7A, and N... The gates of N8A and N9A are connected to the F signal; the gate of N0A is connected to the VC2 signal; the gate of N1A is connected to I+, serving as the positive input terminal; the gate of N2A is connected to I-, serving as the negative input terminal; the drain of N1A is connected to the drain of P5A, the source of P9A, and the source of P6A; the drain of P9A is connected to the source of P7A and the source of P11A; the drain of P11A outputs the O- signal, which is connected to the drain of N11A; the source of N11A is connected to N8A. The drain of N6A is connected to the drain of N8A; the source of N8A is connected to the drain of N7A and the drain of N5A; the drain of N2A is connected to the drain of P4A, the source of P8A, and the drain of P7A; the drain of P8A is connected to the drain of P6A and the source of P10A; the drain of P10A outputs a O+ signal and is connected to the drain of N10A; the source of N10A is connected to the drain of N9A and the source of N7A; the source of N9A is connected to the drain of N4A and the source of N6A.

[0074] The circuit principle of the gain booster op-amp EA1 is explained below.

[0075] I+ and I- are the positive and negative input terminals of the op-amp, respectively; VC2 is the common-mode voltage; O+ and O- are the positive and negative output terminals of the op-amp; BP, VC4, BN, and VC3 are the bias currents; and E and F are the oscillator signals that control the chopper.

[0076] This operational amplifier is a folded cascode operational amplifier with three-terminal NMOS input and two-terminal output. The reference voltage VC2 is introduced at the N0A input terminal to set the common-mode voltage of I+ and I-. After the two-terminal input and two-terminal output are connected to form a negative feedback gain boost of the cascode operational amplifier, the voltage of the cascode is controlled to meet the set DC operating point.

[0077] In the folded common-source common-gate circuit, a chopper circuit is introduced; P4A and P10A, P5A and P9A, N4A and N9A, and N5A and N8A form common-source common-gate circuits respectively; P6A, P7A, P8A, and P9A form the high-side chopper switch within EA1, and N6A, N7A, N8A, and N9A form the low-side chopper switch within EA1, controlled by signals E and F respectively; when E=0 and F=1, P8A, P9A, N9A, and N8A are turned on, and P6A, P7A, N6A, and N7A are all turned off; when E=1 and F=0, P8A, P9A, N9A, and N8A are turned off, and P6A, P7A, N6A, and N7A are all turned on; simultaneously, due to the... Figure 2 In this process, the detection signals I+ and I- also switch with the E and F signals, thus completing the switching of one oscillation cycle.

[0078] As an example, Figure 4 The connection relationship of the gain booster operational amplifier EA2 in the circuit of this invention is shown.

[0079] BN and VC3, BP and VC4 are bias voltages, E and F are chopper-controlled oscillator signals, and VC1 is the reference potential.

[0080] The body terminals of N10B, N11B, N6B, N7B, N8B, N9B, N4B, and N5B are connected to voltage VSS; the body terminals of P3B, P31B, P0B, P1B, P2B, P4B, P5B, P6B, P7B, P8B, P9B, P10B, and P11B are connected to voltage VDD; the sources of N4B and N5B are connected to voltage VSS; the sources of P3B, P4B, and P5B are connected to the source of P31B. The drain of P31 is connected to the drain of P3B; the drain of P0B is connected to VSS; the gates of N10B and N11B are connected to the VC3 voltage; the gates of N4B and N5B are connected to the BN signal; the gates of P3B, P4B, and P5B are connected to the BP signal; the gates of P31B, P10B, and P11B are connected to the VC4 signal; the gates of P8B, P9B, N6B, and N7B are connected to the E signal; the gates of P6B, P7B, N8B, and N9B are connected to the VC4 signal. Connect to the F signal; the gate of P0B is connected to the VC1 signal, the gate of P1B is connected to I+, which is the positive input terminal; the gate of P2B is connected to I-, which is the negative input terminal; the drain of P5B is connected to the source of P9B and the source of P6B; the drain of P9B is connected to the source of P7B and the source of P11B; the drain of P11B outputs the O- signal, which is connected to the drain of N11B; the source of N11B is connected to the drain of N8B and the drain of N6B; N8 The source of B is connected to the drain of N7B, the drain of N5B, and the drain of P1B; the drain of P4B is connected to the source of P8B and the drain of P7B; the drain of P8B is connected to the drain of P6B and the source of P10B; the drain of P10B outputs the O+ signal and is connected to the drain of N10B; the source of N10B is connected to the drain of N9B and the source of N7B; the source of N9B is connected to the drain of N4B, the source of N6B, and the drain of P2B.

[0081] The circuit principle of the gain booster op-amp EA2 is explained below.

[0082] I+ and I- are the positive and negative input terminals of the op-amp, respectively; VC1 is the common-mode voltage; O+ and O- are the positive and negative output terminals of the op-amp; BP, VC4, BN, and VC3 are the bias currents; and E and F control the oscillator signal for the chopper.

[0083] This operational amplifier is a folded cascode operational amplifier with three-terminal PMOS input and two-terminal output. A reference voltage VC1 is introduced at the P0B input terminal to set the common-mode voltage of I+ and I-. After the two-terminal input and two-terminal output are connected to form a negative feedback gain boost of the cascode operational amplifier, the voltage of the cascode is controlled to meet the set DC operating point.

[0084] A chopper circuit is introduced in the folded common-source common-gate circuit. P4B and P10B, P5B and P9B, N4B and N9B, and N5B and N8B form common-source common-gate circuits respectively. P6B, P7B, P8B, and P9B form the high-side chopper switch within EA2, and N6B, N7B, N8B, and N9B form the low-side chopper switch within EA2, controlled by signals E and F respectively. When E=0 and F=1, P8B, P9B, N9B, and N8B are turned on, and P6B, P7B, N6B, and N7B are all turned off. When E=1 and F=0, P8B, P9B, N9B, and N8B are turned off, and P6B, P7B, N6B, and N7B are all turned on. Simultaneously, due to the... Figure 2 In this process, the detection signals I+ and I- also switch with the E and F signals, thus completing the switching of one oscillation cycle.

[0085] As an example, Figure 5 The circuit connection relationship of the offset voltage adjustment current of the present invention is shown.

[0086] The offset voltage trimming current circuit is based on a 3-8 decoder. A0, A1, and A2 are trimming control signals, which are generated by an inverter (inv) and a NAND gate (nand) to produce pairs of inverted trimming signals Y0 and Y01, Y1 and Y11, Y2 and Y21, Y3 and Y31, Y4 and Y41, Y5 and Y51, Y6 and Y61, and Y7 and Y71. These trimming signals control the two outputs BA and BB of the offset voltage trimming current circuit. In this embodiment, only 5 levels are needed, but the 3-8 decoder outputs 8 signals, so 3 sets of output trimming signals are used as backup levels.

[0087] The source and body terminals of PMOS transistors FP1, FP2, FP3, FP4, and FP5 are connected to VDD; the body terminals of PMOS transistors FP11, FP12, FP21, FP22, FP31, FP32, FP41, FP42, FP51, and FP51 are connected to VDD potential; the drain of FP1 is connected to the source of FP11 and FP12, and the gate of FP11 and the gate of FP12 are connected to adjustment control signals Y0 and Y01, respectively; the drain of FP2 is connected to the source of FP21 and FP22, and the gate of FP21 and the gate of FP22 are connected to adjustment control signals Y1 and Y11, respectively; the drain of FP3 is connected to FP31 and FP51. The source of P32, the gate of FP31, and the gate of FP32 are connected to adjustment control signals Y2 and Y21, respectively; the drain of FP4 is connected to the source of FP41 and FP42, and the gate of FP41 and the gate of FP42 are connected to adjustment control signals Y3 and Y31, respectively; the drain of FP5 is connected to the source of FP51 and FP52, and the gate of FP51 and the gate of FP52 are connected to adjustment control signals Y4 and Y41, respectively; the drains of FP11, FP21, FP31, FP41, and FP51 are connected together to output the BA signal; the drains of FP12, FP22, FP32, FP42, and FP52 are connected together to output the BB signal.

[0088] The 3-8 decoder circuit is as follows: A2 is connected to the input of inv21; the output of inv21 is connected to the input of inv22, and is also connected to terminal 3 of nand5, terminal 2 of nand6 and nand7, and terminal 1 of nand8; the outputs of inv22 are connected to terminals 1 of nand1 and nand4, and terminals 2 of nand2 and nand3; A1 is connected to the input of inv31; the output of inv31 is connected to the input of inv32, and is also connected to terminals 3 of nand3 and nand7, and... The output of inv32 is connected to the second terminal of nand1, and the first terminal of nand2, nand5, and nand6; A0 is connected to the input of inv41, the output of inv41 is connected to the input of inv42, and the third terminal of nand2, nand4, nand6, and nand8; the output of nand1 is connected to the input of inv23, the output of inv23 is Y71 and connected to the input of inv24, and the output of inv24 is Y7; The output of nand2 is connected to the input of inv33. Inv33 outputs Y61, which is then connected to the input of inv34, where inv34 outputs Y6. The output of nand3 is connected to the input of inv43. Inv43 outputs Y51, which is then connected to the input of inv54, where inv54 outputs Y5. The output of nand4 is connected to the input of inv53. Inv53 outputs Y41, which is then connected to the input of inv54, where inv54 outputs Y4. The output of nand5 is connected to the input of inv63. The output of nand6 is Y31, which is connected to the input of inv64. Inv64 outputs Y3. The output of nand6 is connected to the input of inv73. Inv73 outputs Y21, which is connected to the input of inv74. Inv74 outputs Y2. The output of nand7 is connected to the input of inv83. Inv83 outputs Y11, which is connected to the input of inv84. Inv84 outputs Y1. The output of nand8 is connected to the input of inv93. Inv93 outputs Y01, which is connected to the input of inv94. Inv94 outputs Y0.

[0089] The circuit principle of the offset voltage adjustment current of this invention is explained as follows.

[0090] FP1~FP5 are all mirror current sources. The current is generated proportionally based on the size of the tube. The current range adjustment setting is based on the size ratio of the current source PMOS tube, as follows:

[0091] FP1:FP2:FP3:FP4:FP5=1:2:4:8:16,

[0092] The adjustment signals A0, A1, and A2 control the gating of adjustment signals Y0-Y7 according to the following truth table, thereby achieving precise gear setting;

[0093]

[0094] Since BA and BB are connected to the drains of the folded common-source and common-gate current sources P4 and P5 respectively, the input offset voltage can be corrected by introducing the adjustment current. Using a one-time initial adjustment technique, the offset voltage caused by transistor size variations during manufacturing can be significantly reduced. Since Y0 / Y01, Y1 / Y11, Y2 / Y21, Y3 / Y31, and Y4 / Y41 are all inversely related during adjustment, the currents of BA and BB are also inversely related, thus achieving a doubling of the adjustment effect. For example, in the initial state, when Y0=1 and Y01=0, FP11 is off and FP12 is on. When adjusting Y0=0 and Y01=1, FP11 is on and FP12 is off. The difference current between BA and BB changes from -1 to +1. For the corresponding output offset voltage, the change in current is X2, thus expanding the adjustment range. In the initial state, A2=A1=A0=1, Y7=Y6=Y5=Y4=T3=Y2=Y1=1.

[0095] When A2=A1=A0=0, corresponding to Y0=0, FP11 is turned on and FP12 is turned off.

[0096] Adjust A2=A1=0, A0=1, corresponding to Y1=0, FP21 is turned on, FP22 is turned off;

[0097] When A2=A0=1 and A1=1 are adjusted, Y2=0 is correspondingly activated, FP31 is turned on, and FP32 is turned off.

[0098] When A2=0, A1=A0=1, corresponding to Y3=1, FP41 is turned on and FP42 is turned off.

[0099] When A2=1, A1=A0=0, corresponding to Y4=1, FP51 is turned on and FP52 is turned off.

[0100] The principle of adjusting the bias current to reduce the initial offset voltage is as follows:

[0101] The input differential pair transistors of an operational amplifier must be identical in size and perfectly matched in circuit and layout design. It is well known that the drain current of an NMOS transistor is I... N =μ n C ox (Vgs-Vthn) 2 / 2*( W / L), where μ n denoted as NMOS transistor carrier mobility, Cox as gate oxide capacitance per unit area, and W / L as the width-to-length ratio of the NMOS transistor.

[0102] Vgs=[2*I N / (W / L)( μ n C ox)] 1 / 2 + Vthn.

[0103] In this invention, the dimensions of N1 and N2 are W / L1 = W / L2, therefore the voltage difference Vgs is simplified to

[0104] ΔVgs=Vgs1- Vgs2={[2*I N1 / (W / L1)( μ n C ox )] 1 / 2 + Vthn}-{[2*I N2 / (W / L2)( μ n C ox )] 1 / 2 + Vthn}=[2 / (W / L1)( μ n C ox )] 1 / 2 *[ (I N1 ) 1 / 2 - (I N2 ) 1 / 2 ]

[0105] The offset voltage Vos is the voltage difference caused by the difference between the two differential pairs of transistors generated during the production process.

[0106] Therefore, from the above formula, we can obtain that by adjusting I... N1 and I N2 The bias current can be used to change the voltage ΔVgs, thereby achieving ΔVgs in the opposite direction to Vos, so that Vos+ΔVgs=0, achieving zero initial offset voltage.

[0107] This invention employs a one-time initial adjustment technique, which adjusts the circuit once before it leaves the factory to obtain the finished circuit.

[0108] Figure 6 The diagram shows the noise reduction effect before and after using the chopper circuit of this invention. The horizontal axis represents frequency, and the vertical axis represents noise voltage, comparing the noise levels across the entire frequency range.

[0109] Red represents the noise before chopping, and green represents the noise after chopping;

[0110] A circuit without choppers, i.e., without chopper switches for NS1 and PS1, NS2 and PS2, NS3 and PS3, NS4 and PS4, and without P6, P7, P8, P9, N8, N9, N10, N11. EA1 and EA2 also do not contain chopper switches, i.e., without P6A, P7A, P8A, P9A, N6A, N7A, N8A, N9A; and without P6B, P7B, P8B, P9B, N6B, N7B, N8B, N9B.

[0111] From the low-frequency range, we can see that f=10 -2 At that time, the noise without the chopper circuit was 35.5mV / sqrt (Hz), while the noise with the chopper circuit of this invention was 5.17uV / sqrt (Hz), which is reduced to 1 / 7000, and the noise is significantly reduced.

[0112] Figure 7 This demonstrates how the offset voltage is canceled after the present invention uses chopping technology.

[0113] Chopping technology modulates the error to a higher frequency, thereby separating offset and low-frequency noise from the signal content. This invention modulates the input signal and 1mV offset voltage into a square wave using an input-stage chopper circuit. This signal is then processed by an amplifier in the amplification unit, and finally demodulated back to a DC signal using an output-stage chopper circuit. Simultaneously, the low-frequency error of the amplifier is modulated into a square wave, canceling out the high and low levels, resulting in an offset voltage effect close to zero. As seen in the output square wave, the high and low levels are approximately equal; after equivalent averaging, the offset voltage approaches zero, achieving an offset voltage much smaller than 1mV.

[0114] In summary, this invention provides a novel amplifier circuit with chopper technology;

[0115] First, in addition to the chopper switch circuits at the input and output terminals, this invention employs a gain-boost folded common-source cascode operational amplifier with chopper technology, which includes common-mode voltage control. While improving the common-source cascode output impedance and gain, it can eliminate its own offset, drift and 1 / f noise.

[0116] Secondly, the use of one-time initial adjustment technology can significantly reduce the offset voltage caused by transistor size changes during manufacturing;

[0117] Finally, the output transistors are controlled by a DC bias voltage control circuit, which ensures that the two output transistors are slightly turned on, thereby improving the output response speed of the op-amp, and also keeps the power consumption at a low level.

[0118] Therefore, this invention achieves effective zero-drift technology through an independent chopper circuit, effectively eliminating offset, drift, and 1 / f noise. The circuit is simple and easy to implement.

Claims

1. A chopping-based operational amplifier circuit, characterized by The positive and negative inputs of the operational amplifier circuit pass through an input stage chopper switch, a pair of complementary differential input pairs, an output stage chopper switch, an auxiliary gain operational amplifier unit, and then through an output stage. The auxiliary gain operational amplifier unit includes gain boost operational amplifiers EA1 and EA2. The operational amplifier circuit also includes an offset voltage adjustment current circuit and first to third bias voltage circuits, configured as follows: The first bias voltage circuit generates bias voltages VC3 and VC1, where VC1 provides the input common-mode voltage reference for the gain boost operational amplifier EA2, and VC3 provides bias for the N-type cascode transistor. The second bias voltage circuit generates bias voltages VC4 and VC2, where VC2 provides the input common-mode voltage reference for the gain boost operational amplifier EA1, and VC4 provides bias for the P-type cascode transistor. Gain boost operational amplifiers EA1 and EA2 provide gate voltages for the PMOS and NMOS transistors, respectively. The third bias voltage circuit generates bias voltages PC and NC to provide DC bias voltages for the output transistors. BP and BN are the general bias voltages for PMOS and NMOS transistors, respectively. The body terminals of NMOS transistors N1-N13, N31, and output transistor Npower are connected to the VSS potential; the body terminals of PMOS transistors P1-P13, P31, and output transistor Ppower are connected to the VDD potential; the sources of P3, P4, P5, P14, P15, P17, P18, and Ppower are connected to the VDD potential; the sources of N3, N4, N5, N15, N16, N17, N20, and Npower are connected to the VSS potential; among these, the sources of N1 and N2 are connected together and then connected to the drain of N31, the source of N31 is connected to the drain of N3, and the gate of N31 is connected to VC3. The gate of N3 is connected to BN, forming the NMOS differential pair input of the folded cascode op-amp; the sources of P1 and P2 are connected to the drain of P31, the source of P31 is connected to the drain of P3, the gate of P31 is connected to VC4, and the gate of P3 is connected to BP, forming the PMOS differential pair input of the folded cascode op-amp; P4 and P10, P5 and P11, N4 and N10, N5 and N11 form a cascode circuit, and the output stage chopper switches include a high-side chopper switch composed of P6, P7, P8, and P9, and a low-side chopper switch composed of N6, N7, N8, and N9, with the following connection relationships: The drain of N1 is connected to the drain of P5, the source of P9, the drain of P6, and the negative input terminal of EA1; the drain of N2 is connected to the drain of P4, the source of P8, the drain of P7, and the positive input terminal of EA1; the gates of P4 and P5 are connected to BP; the drain of P8 is connected to the source of P6 and the source of P10; the drain of P10 is connected to the source of P12 and the drain of N12; the source of N12 is connected to the source of P12, the drain of N10, and the gates of N4 and N5; the source of N10 is connected to the drain of N9 and the drain of N7; the source of N9 is connected to the drain of N6, the drain of P2, and the positive input terminal of EA2; the drain of P9 is connected to the source of P11 and the source of P7; the source of N11 is connected to the drain of N8 and the source of N6; the source of N8 is connected to the drain of N5 and the drain of N7. The source of EA1, the negative input of EA2, and the drain of P1 are connected. The negative output of EA2 is connected to the gate of N10, and the positive output is connected to the gate of N11. The positive output of EA1 is connected to the gate of P11, and the negative output is connected to the gate of P10. The drain of P11 is connected to the drain of N13, the source of P13, the gate of Ppower, and one end of the compensation capacitor C1. The source of N13 is connected to the drain of P13, the drain of N11, the gate of Npower, and one end of the compensation capacitor C2. The other ends of C1 and C2 are connected to the drains of Ppower and Npower, and serve as the output terminal Out of the op-amp circuit. The gates of N12 and N13 are connected to the bias voltage NC, and the gates of P12 and N12 are connected to the bias voltage PC. The offset voltage correction current circuit outputs correction currents BA and BB. BA is connected to the drain of N1 and the drain of P5, and BB is connected to the drain of N2 and the drain of P4. The input offset voltage is corrected through a one-time correction. The oscillator signal CLK of the operational amplifier circuit is inverted once to generate signal E, and then inverted again to generate signal F. The positive input terminal INP and the negative input terminal INN of the operational amplifier circuit are each equipped with two sets of input stage chopper switches for switching the connection with the differential input. Signals E and F serve as control signals for the chopper switches. In the high-side and low-side chopper switches, the gates of P6, P7, N8, and N9 are connected to signal F, and the gates of P8, P9, N6, and N7 are connected to signal E. When E... When E=0 and F=1, through the input stage chopper switch, INP is output to the gates of N1 and P1, and INN is output to the gates of N2 and P2. P8, P9, N8, and N9 are turned on, while P6, P7, N6, and N7 are turned off. When E=1 and F=0, INP is output to the gates of N2 and P2, and INN is output to the gates of N1 and P1. P8, P9, N8, and N9 are turned off, while P6, P7, N6, and N7 are turned on, completing one cycle of chopping operation of CLK. The circuit for gain boost op-amp EA1 is as follows: I+ and I- are the positive and negative input terminals of the gain boost op-amp, respectively; VC2 is the common-mode voltage; and O+ and O- are the positive and negative output terminals of the gain boost op-amp. Gain boost op-amp EA1 is a folded cascode op-amp with three-terminal NMOS input and two-terminal output. The circuit includes NMOS transistors N0A~N11A and N31A, and PMOS transistors P4A~P11A. The body terminals of all NMOS transistors are connected to the VSS potential; the body terminals of all PMOS transistors are connected to the VDD potential; the sources of N3A, N4A, and N5A are connected to the VSS potential; the sources of P4A and P5A and the drain of N0A are connected to the VDD potential; the sources of N0A, N1A, and N2A are connected together to the drain of N31A; the source of N31A is connected to the drain of N3A; the gates of N31A, N10A, and N11A are connected to VC3; the gates of N3A, N4A, and N5A are connected to BN; the gates of P4A and P5A are connected to BP; the gates of P10A and P11A are connected to VC4; the gates of P8A, P9A, N6A, and N7A are connected to signal E; the gates of P6A, P7A, N8A, and N9A are connected to signal F; the gate of N0A is connected to signal VC2; and the gate of N1A is connected to I+. The positive input terminal is connected to the gate of N2A (I-), which is the negative input terminal. The drain of N1A is connected to the drain of P5A, the source of P9A, and the source of P6A. The drain of P9A is connected to the source of P7A and the source of P11A. The drain of P11A outputs an O- signal, which is connected to the drain of N11A. The source of N11A is connected to the drain of N8A and the drain of N6A. The source of N8A is connected to N... The drain of N7A and the drain of N5A are connected; the drain of N2A is connected to the drain of P4A, the source of P8A, and the drain of P7A; the drain of P8A is connected to the drain of P6A and the source of P10A; the drain of P10A outputs a O+ signal and is connected to the drain of N10A; the source of N10A is connected to the drain of N9A and the source of N7A; the source of N9A is connected to the drain of N4A and the source of N6A. The reference voltage VC2 is introduced at the input terminal of N0A to set the common-mode voltage of I+ and I-. This, combined with the negative feedback gain boost of the cascode op-amp connected to the dual-ended input and output, controls the cascode voltage to meet the set DC operating point. A chopper circuit is introduced in the folded cascode, where P4A and P10A, P5A and P9A, N4A and N9A, and N5A and N8A form cascode, and P6A, P7A, P8A, and P9A form the high-side chopper switch within EA1. N6A, N7A, N8A, and N9A form the low-side chopper switch inside EA1, controlled by signals E and F respectively. When E=0 and F=1, P8A, P9A, N9A, and N8A are turned on, while P6A, P7A, N6A, and N7A are all turned off. When E=1 and F=0, P8A, P9A, N9A, and N8A are turned off, while P6A, P7A, N6A, and N7B are all turned on. The detection signals of I+ and I- switch with the E and F signals, completing the switching of one oscillation cycle. The circuit for gain boost op-amp EA2 is as follows: I+ and I- are the positive and negative input terminals of the gain boost op-amp, respectively; VC1 is the common-mode voltage; and O+ and O- are the positive and negative output terminals of the gain boost op-amp. Gain boost op-amp EA2 is a folded cascode op-amp with three-terminal PMOS input and two-terminal output. The circuit includes NMOS transistors N4B~N11B, and PMOS transistors P0B~P11B and P31B. The body terminals of all NMOS transistors are connected to the VSS potential; the body terminals of all PMOS transistors are connected to the VDD potential; the sources of N4B and N5B are connected to the VSS potential; the sources of P3B, P4B, and P5B are connected to the drain of P31B, and the source of P31B is connected to the drain of P3B; the drain of P0B is connected to the VSS potential; the gates of N10B and N11B are connected to VC3; the gates of N4B and N5B are connected to BN; the gates of P3B, P4B, and P5B are connected to BP; the gates of P31B, P10B, and P11B are connected to VC4; the gates of P8B, P9B, N6B, and N7B are connected to signal E; the gates of P6B, P7B, N8B, and N9B are connected to signal F; the gate of P0B is connected to VC1, and the gate of P1B is connected to I+, which is the non-inverting input terminal; the gate of P2B... The gate is connected to I-, serving as the negative phase input. The drain of P5B is connected to the source of P9B and the source of P6B. The drain of P9B is connected to the source of P7B and the source of P11B. The drain of P11B outputs an O- signal, which is connected to the drain of N11B. The source of N11B is connected to the drain of N8B and the drain of N6B. The source of N8B is connected to the drain of N7B, the drain of N5B, and the drain of P1B. The drain of P4B is connected to the source of P8B and the drain of P7B. The drain of P8B is connected to the drain of P6B and the source of P10B. The drain of P10B outputs an O+ signal, which is connected to the drain of N10B. The source of N10B is connected to the drain of N9B and the source of N7B. The source of N9B is connected to the drain of N4B, the source of N6B, and the drain of P2B. The P0B input terminal introduces a reference voltage VC1 to set the common-mode voltage of I+ and I-. Thus, after the dual-ended input and dual-ended output are connected as a pair of common-source cascode negative feedback gain boost op-amps, the voltage of the common-source cascode is controlled to meet the set DC operating point. A chopper circuit is introduced into the folded common-source common-gate circuit, where P4B and P10B, P5B and P9B, N4B and N9B, and N5B and N8B form common-source common-gate circuits respectively, P6B, P7B, P8B, and P9B form the high-side chopper switch within EA2, and N6B, N7B, N8B, and N9B form the low-side chopper switch within EA2, controlled by signals E and F respectively. When E=0 and F=1, P8B, P9B, N9B, and N8B are turned on, and P6B, P7B, N6B, and N7B are all turned off; when E=1 and F=0, P8B, P9B, N9B, and N8B are turned off, and P6B, P7B, N6B, and N7B are all turned on. The detection signals of I+ and I- switch with the E and F signals, completing the switching of one oscillation cycle.

2. The chopper-based operational amplifier circuit of claim 1, wherein The input stage chopper switch consists of an NMOS transistor NS and a PMOS transistor PS, including NS1 and PS1, NS2 and PS2, NS3 and PS3, and NS4 and PS4. INP is connected to the source of NS1 and PS1, and the source of NS3 and PS3. INN is connected to the sources of NS2 and PS2, and the sources of NS4 and PS4; the drains of NS1 and PS1 are connected to the drains of NS2 and PS2, and then to the gates of N1 and P1; the drains of NS3 and PS3 are connected to the drains of NS4 and PS4, and then to the gates of N2 and P2; the body terminals of NS1, NS2, NS3, and NS4 are connected to the VSS voltage, and the body terminals of PS1, PS2, PS3, and PS4 are connected to the VDD voltage; the gates of NS1, PS2, PS3, and NS4 are connected to signal F, and the gates of NS2, PS1, PS4, and NS3 are connected to signal E.

3. The chopper-based operational amplifier circuit of claim 1, wherein The first bias voltage circuit includes PMOS transistors P17, NMOS transistors N17, N18, and N19; the second bias voltage circuit includes NMOS transistors N20, PMOS transistors P18, P19, and P20; and the third bias voltage circuit includes PMOS transistors P14, P15, and P16, and NMOS transistors N14, N15, and N16. The body terminals of NMOS transistors N14 to N20 are connected to the VSS potential, and the body terminals of PMOS transistors P14 to P20 are connected to the VDD potential. In the first bias voltage circuit, the gate of P17 is connected to BP, the source is connected to VDD potential, and the drain is connected to the drain and gate of N19. A bias voltage VC3 is generated between the drain and gate of N19. The source of N19 is connected in series with the drain of N18 and outputs a bias voltage VC1, which is connected to the VC1 terminal of EA2. The gate of N19 is connected to the gates of N17 and N18. The source of N18 is connected in series with the drain of N17. The source of N17 is connected to VSS. In the second bias voltage circuit, the source of P18 is connected to VDD, the gates of P18, P19 and P20 are connected, the drain of P18 is connected to the source of P19, the drain of P19 is connected to the source of P20, the output bias voltage VC2 between the drain of P19 and the source of P20 is connected to the VC2 terminal of EA1, the drain of P20 is connected to the gate and connected to the drain of N20, a bias voltage VC4 is generated between the gate and drain of P20, and the source of N20 is connected to the VSS potential. In the third bias voltage circuit, the sources of P14 and P15 are connected to VDD potential, the gate of P14 is connected to BP, and the drain is connected to the drain of N14. The gate and drain of N14 are connected, generating a bias voltage NC between the gate and drain of N14. The drain and gate of P15 are connected and connected to the source of P16. The gate and drain of P16 are connected, generating a bias voltage PC between the gate and drain of P16. The drain of P16 is connected to the drain of N16. The source of N14 is connected to the drain and gate of N15, the gate of N16, and the gate of N20. The sources of N15 and N16 are connected to VSS potential.

4. The chopper-based operational amplifier circuit of claim 1, wherein the offset is The voltage trimming current circuit is based on a 3-8 decoder. A0, A1, and A2 are trimming control signals, which are generated by an inverter (inv) and a NAND gate (nand) to produce pairs of inverted trimming signals Y0 and Y01, Y1 and Y11, Y2 and Y21, Y3 and Y31, Y4 and Y41, Y5 and Y51, Y6 and Y61, and Y7 and Y71. These trimming signals control the two outputs BA and BB of the offset voltage trimming current circuit. The current source PMOS transistors include FP1, FP2, FP3, FP4, and FP5, with the following dimensions: ​ FP1:FP2:FP3:FP4:FP5=1:2:4:8:16 The source and body terminals of FP1, FP2, FP3, FP4, and FP5 are connected to VDD; the body terminals of PMOS transistors FP11, FP12, FP21, FP22, FP31, FP32, FP41, FP42, FP51, and FP51 are connected to VDD potential; the drain of FP1 is connected to the source of FP11 and FP12, and the gate of FP11 and the gate of FP12 are connected to adjustment control signals Y0 and Y01, respectively; the drain of FP2 is connected to the source of FP21 and FP22, and the gate of FP21 and the gate of FP22 are connected to adjustment control signals Y1 and Y11, respectively; the drain of FP3 is connected to FP31 and FP32. The source of FP2, the gate of FP31 and the gate of FP32 are connected to adjustment control signals Y2 and Y21 respectively; the drain of FP4 is connected to the source of FP41 and FP42, and the gate of FP41 and the gate of FP42 are connected to adjustment control signals Y3 and Y31 respectively; the drain of FP5 is connected to the source of FP51 and FP52, and the gate of FP51 and the gate of FP52 are connected to adjustment control signals Y4 and Y41 respectively; the drains of FP11, FP21, FP31, FP41 and FP51 are connected together to output the BA signal; the drains of FP12, FP22, FP32, FP42 and FP52 are connected together to output the BB signal.

5. The chopper-based operational amplifier circuit according to claim 4, characterized in that the offset... In the voltage trimming current circuit, the circuit that generates pairs of inverted trimming signals from the trimming control signals A0, A1, and A2 is as follows: A2 connects to the input of inv21, and the output of inv21 connects to the input of inv22, and is also connected to terminal 3 of NAND5, terminal 2 of NAND6 and NAND7, and terminal 1 of NAND8; the outputs of inv22 connect to terminal 1 of NAND1 and NAND4, and terminal 2 of NAND2 and NAND3; A1 connects to the input of inv31, and the output of inv31 connects to the input of inv32, as well as terminal 3 of NAND3 and NAND7, and terminal 4 of NAND8. Terminal 2 of NAND 8; the output of inv32 is connected to terminal 2 of NAND 1, and terminal 1 of NAND 2, NAND 5, and NAND 6; A0 is connected to the input of inv41, the output of inv41 is connected to the input of inv42, and terminal 3 of NAND 2, NAND 4, NAND 6, and NAND 8; the output of NAND 1 is connected to the input of inv23, the output of inv23 is Y71 and connected to the input of inv24, and the output of inv24 is Y7; the output of NAND 2... The output of nand3 is connected to the input of inv33. Inv33 outputs Y61, which is then connected to the input of inv34, causing inv34 to output Y6. The output of nand3 is connected to the input of inv43. Inv43 outputs Y51, which is then connected to the input of inv54, causing inv54 to output Y5. The output of nand4 is connected to the input of inv53. Inv53 outputs Y41, which is then connected to the input of inv54, causing inv54 to output Y4. The output of nand5 is connected to the input of inv63, which outputs Y61... Y31 is output and connected to the input of inv64, inv64 outputs Y3; the output of nand6 is connected to the input of inv73, inv73 outputs Y21 and is connected to the input of inv74, inv74 outputs Y2; the output of nand7 is connected to the input of inv83, inv83 outputs Y11 and is connected to the input of inv84, inv84 outputs Y1; the output of nand8 is connected to the input of inv93, inv93 outputs Y01 and is connected to the input of inv94, inv94 outputs Y0.

Images