A split amplifier and electronic device

Abstract

This invention discloses a shunt amplifier and electronic device. By introducing at least one resistor adjustment unit, and defining its connection to at least one resistor branch in a first resistor network and / or a second resistor network, it adjusts the equivalent resistance value of the connected branch. This allows the equivalent resistance value of the resistor branch to be adjusted after circuit molding, thereby compensating for proportional resistor mismatch caused by process deviations and directly solving the proportional resistor mismatch problem caused by process deviations. This invention enables the adjustment unit to actively compensate for the corresponding resistor branch without changing the overall circuit architecture, correcting mismatch errors and improving resistor matching accuracy. Since the common-mode rejection ratio (CMRR) of a shunt amplifier is highly dependent on the accuracy of the resistor ratio, improving resistor matching accuracy directly optimizes the CMRR, enhances the amplifier's robustness to process fluctuations, and makes its performance more stable in high-precision, high-complexity applications.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a shunt amplifier and electronic device. Background Technology

[0002] With the rapid development of electronic products, semiconductor integrated circuits are widely used in various fields such as military and civilian applications. Especially in fields such as computers, multimedia, and digital signal processing, the performance requirements for electronic products are constantly increasing. As one of the core components of electronic systems, the performance of operational amplifiers directly affects the quality of the entire system.

[0003] However, traditional operational amplifiers suffer from proportional resistor mismatch due to manufacturing variations, which directly affects the common-mode rejection ratio (CMRR) of the shunt amplifier. Therefore, the matching accuracy of the resistors directly impacts the overall performance of the operational amplifier. Existing amplifiers struggle to simultaneously meet these requirements, especially in high-precision and high-complexity applications, where amplifier performance still needs improvement. Summary of the Invention

[0004] The purpose of this invention is to provide a shunt amplifier and electronic device that solves the problem of proportional resistor mismatch caused by process deviations, enhances the amplifier's robustness to process fluctuations, and makes its performance more stable in high-precision and high-complexity applications.

[0005] In a first aspect, this application provides a shunt amplifier, comprising: The first-stage amplifier circuit includes a first operational amplifier and a first resistor network connected to the first operational amplifier. The second-stage amplifier circuit includes a second operational amplifier and a second resistor network connected to the second operational amplifier. At least one resistor adjustment unit is provided, which is connected to at least one resistor branch in the first resistor network and / or the second resistor network, for adjusting the equivalent resistance value of the connected resistor branch to adjust the resistance matching accuracy of the shunt amplifier.

[0006] Optionally, the first resistor network includes a first resistor, a second resistor, a third resistor, and a fourth resistor; The first end of the first resistor serves as the first input terminal of the shunt amplifier. The second end of the first resistor is connected to the inverting input terminal of the first operational amplifier and the first end of the second resistor. The second end of the second resistor is connected to the positive output terminal of the first operational amplifier and the first input terminal of the second-stage amplifier circuit. The first end of the third resistor serves as the second input terminal of the shunt amplifier. The second end of the third resistor is connected to the non-inverting input terminal of the first operational amplifier and the first end of the fourth resistor. The second end of the fourth resistor is connected to the negative output terminal of the first operational amplifier and the second input terminal of the second-stage amplifier circuit. The resistor adjustment unit includes at least one of a first adjustment unit and a second adjustment unit; The first adjustment unit is connected to the feedback branch where the second resistor is located, and is used to change the equivalent resistance value of the feedback branch where the second resistor is located; The second adjustment unit is connected to the feedback branch where the fourth resistor is located, and is used to change the equivalent resistance value of the feedback branch.

[0007] Optionally, the first adjustment unit is connected in series between the second end of the second resistor and the first node, where the first node is the connection node between the positive output terminal of the first operational amplifier and the first input terminal of the second stage amplifier circuit. And / or, the second adjustment unit is connected in series between the second end of the fourth resistor and the second node, the second node being the connection node between the negative output terminal of the first operational amplifier and the second input terminal of the second stage amplifier circuit.

[0008] Optionally, the first adjustment unit is connected in parallel with the second resistor; and / or, the second adjustment unit is connected in parallel with the fourth resistor.

[0009] Optionally, the first trimming unit and / or the second trimming unit includes a programmable resistor network; The programmable resistor network includes multiple programmable resistor branches connected in parallel, each programmable resistor branch includes at least one resistor element, and at least some of the programmable resistor branches are provided with branch switches. A switch control module is used to control the on / off state of the branch switch in order to adjust the equivalent resistance value of the programmable resistor network.

[0010] Optionally, the programmable resistor network includes: The first resistor branch includes a reference resistor element and is a normally open branch; At least one fixed resistor branch is connected in series with the first resistor branch; Multiple adjustable resistor branches are connected in parallel with a series branch composed of the first resistor branch or the first resistor branch and the fixed resistor branch, and the resistance values ​​of the resistor elements in each adjustable resistor branch are in a binary proportional relationship. Each of the adjustable resistor branches is equipped with a branch switch to independently control the on / off state of the corresponding branch.

[0011] Optionally, the programmable resistor network may also include multiple master switches; The main switch is connected in series in the corresponding adjustable resistor branch and is used to control whether the multiple adjustable resistor branches enter the programmable state.

[0012] Optionally, the second operational amplifier adopts a Class AB output stage circuit structure with a floating voltage source bias, and the second operational amplifier includes: The input differential pair transistors have their two input terminals connected to the two output terminals of the first-stage amplifier circuit, respectively, to receive and amplify the input signal. The first set of current mirrors in the cascode structure has its input terminals connected to the differential pair transistors and the power supply voltage, respectively, serving as an active load; The second set of current mirrors is connected to the ground terminal and serves as the tail current source; The first linear transconductance loop includes multiple PMOS transistors, which are respectively connected to the first group of current mirrors and the second group of current mirrors; The second linear transconductance ring includes multiple NMOS transistors and is coupled to the first linear transconductance ring.

[0013] Optionally, the second operational amplifier further includes a bias switch; the first set of current mirrors includes a first switch and a second switch; the second set of current mirrors includes a third switch and a fourth switch; the first linear transconductance loop includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; and the second linear transconductance loop includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first terminal of the first switching transistor receives a differential signal output from the first stage amplifier circuit and is connected to the power supply voltage. The first terminal of the second switching transistor receives another differential signal output from the first stage amplifier circuit and is connected to the power supply voltage. The second terminal of the first switching transistor is connected to the first terminal of the bias switching transistor. The second terminal of the bias switching transistor is connected to the first terminal of the third switching transistor and the control terminal of the third switching transistor. The second terminal of the third switching transistor is grounded. The control terminal of the first switching transistor is connected to the control terminal of the second switching transistor. The control terminal of the third switching transistor is connected to the control terminal of the fourth switching transistor. The second terminal of the second switch is connected to the first terminal of the first PMOS transistor, the first terminal of the first NMOS transistor, and the control terminal of the fourth PMOS transistor, respectively; the second terminal of the first PMOS transistor is connected to the first terminal of the fourth switch, the second terminal of the first NMOS transistor, and the control terminal of the fourth NMOS transistor, respectively; and the second terminal of the fourth switch is grounded. The control terminal of the first NMOS transistor is connected to the control terminal of the second NMOS transistor, the first terminal of the second NMOS transistor, and the power supply voltage. The control terminal of the first PMOS transistor is connected to the control terminal of the bias switch transistor, the control terminal of the second PMOS transistor, the second terminal of the second PMOS transistor, and ground. The first terminal of the second PMOS transistor is connected to the control terminal of the third PMOS transistor and the second terminal of the third PMOS transistor. The first terminal of the third PMOS transistor is connected to the power supply voltage. The first terminal of the fourth PMOS transistor is connected to the power supply voltage, the second terminal of the fourth PMOS transistor is connected to the first terminal of the fourth NMOS transistor and serves as the output terminal of the second operational amplifier, and the second terminal of the fourth NMOS transistor is grounded; the second terminal of the second NMOS transistor is connected to the first terminal of the third NMOS transistor and the control terminal of the third NMOS transistor, respectively, and the second terminal of the third NMOS transistor is grounded.

[0014] Optionally, the input differential pair transistors include a first input switch transistor and a second input switch transistor; The control terminal of the first input switch is the first input terminal of the second operational amplifier, and the control terminal of the second input switch is the second input terminal of the second operational amplifier. The first terminals of the first and second input switches are both grounded. The second terminal of the first input switch is connected to the first terminal of the second switch and the power supply voltage, respectively. The second terminal of the second input switch is connected to the first terminal of the first switch and the power supply voltage, respectively.

[0015] Secondly, this application provides an electronic device including the operational amplifier as described above.

[0016] This invention provides a shunt amplifier and electronic device. By introducing at least one resistor adjustment unit and defining its connection to at least one resistor branch in a first resistor network and / or a second resistor network, it adjusts the equivalent resistance value of the connected branch. This allows the equivalent resistance value of the resistor branch to be adjusted after circuit molding, thereby compensating for proportional resistor mismatch caused by process deviations and directly solving the proportional resistor mismatch problem caused by process deviations. This invention enables the adjustment unit to actively compensate for the corresponding resistor branch without changing the overall circuit architecture, correcting mismatch errors and improving resistor matching accuracy. Since the common-mode rejection ratio (CMRR) of a shunt amplifier is highly dependent on the accuracy of the resistor ratio, improving resistor matching accuracy directly optimizes the CMRR, enhances the amplifier's robustness to process fluctuations, and makes its performance more stable in high-precision and high-complexity applications. Attached Figure Description

[0017] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a typical shunt amplifier; Figure 2 A schematic diagram of a shunt amplifier provided by the present invention; Figure 3 A schematic diagram of another shunt amplifier provided by the present invention. Figure 4 A schematic diagram of a first adjustment unit provided by the present invention; Figure 5 A schematic diagram of a second adjustment unit provided by the present invention; Figure 6 This is a schematic diagram of a second operational amplifier provided by the present invention. Detailed Implementation

[0019] The core of this invention is to provide a shunt amplifier and electronic device that solves the problem of proportional resistor mismatch caused by process deviations, enhances the amplifier's robustness to process fluctuations, and makes its performance more stable in high-precision and high-complexity applications.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] like Figure 2 In a first aspect, this application provides a shunt amplifier, comprising: The first-stage amplifier circuit includes a first operational amplifier and a first resistor network connected to the first operational amplifier. The second-stage amplifier circuit includes a second operational amplifier and a second resistor network connected to the second operational amplifier. At least one resistor adjustment unit is connected to at least one resistor branch in the first resistor network and / or the second resistor network, for adjusting the equivalent resistance value of the connected resistor branch to adjust the resistance matching accuracy of the shunt amplifier.

[0022] The shunt amplifier in this embodiment has a core structure consisting of a first-stage amplifier circuit and a second-stage amplifier circuit connected in series. The first-stage amplifier circuit includes a first operational amplifier and its peripheral first resistor network, while the second-stage amplifier circuit includes a second operational amplifier and its peripheral second resistor network. In shunt amplifier structures, the matching accuracy of the resistor network directly determines the overall circuit's ability to suppress common-mode signals. In this embodiment, at least one resistor branch in the first and second resistor networks is selected and connected to a resistor adjustment unit. This adjustment unit does not operate on the entire resistor network, but rather on one or more specific branches within the network. By changing the equivalent resistance values ​​of these branches, it corrects deviations in the resistance ratio from the design value caused by manufacturing process variations.

[0023] The resistor adjustment unit can be connected to the target resistor branch in parallel or series configurations, but is not limited to this. In one implementation of this embodiment, the adjustment unit may contain an adjustable network consisting of multiple resistors and switches. By controlling the on / off state of the switches, the total impedance of the branch can be changed. Since the ratio between the input resistance and the feedback resistance in the first resistor network, and the ratio between the feedback resistors at each stage in the second resistor network, directly affect the signal transmission accuracy, introducing adjustable resistance compensation in any critical branch can provide directional correction of proportional errors without changing the amplifier's main topology.

[0024] From the perspective of common-mode rejection ratio (CMRR), the CMRR capability of a shunt amplifier primarily depends on the balance of the bridge structure formed by the four resistors in the first-stage amplifier circuit. When process variations cause inconsistencies in the resistor ratios of the two input branches and the two feedback branches, the common-mode signal is converted into differential-mode output, directly degrading the amplifier's performance. This embodiment addresses this by setting a trimming unit in the feedback or input branches, effectively introducing an adjustable compensation at the point of resistor ratio mismatch. This allows the final equivalent resistance ratio to be restored to near the design value, thereby ensuring that the common-mode signal is effectively canceled and no longer propagates to subsequent stages.

[0025] This embodiment places the adjustment unit within the first and / or second resistor networks, rather than limiting it to a fixed location. This layout fully considers the differences in mismatch between different batches and devices in actual chip production. In practical applications, adjustment can be performed in a single stage based on test results, or adjustment units can be set in both stages to suppress the mismatch errors of the preceding and following stages within their respective tolerance ranges. This flexible configuration allows the shunt amplifier to effectively control resistor matching accuracy through post-adjustment methods when facing different process fluctuations.

[0026] like Figure 2 In one exemplary embodiment, the first resistor network includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first terminal of the first resistor R1 serves as the first input terminal of the shunt amplifier. The second terminal of the first resistor R1 is connected to the inverting input terminal of the first operational amplifier and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the positive output terminal of the first operational amplifier and the first input terminal of the second-stage amplifier circuit. The first terminal of the third resistor R3 serves as the second input terminal of the shunt amplifier. The second terminal of the third resistor R3 is connected to the non-inverting input terminal of the first operational amplifier and the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the negative output terminal of the first operational amplifier and the second input terminal of the second-stage amplifier circuit. The resistor adjustment unit includes at least one of the first adjustment unit 1 and the second adjustment unit 2; The first adjustment unit 1 is connected to the feedback branch where the second resistor R2 is located, and is used to change the equivalent resistance value of the feedback branch where the second resistor R2 is located. The second adjustment unit 2 is connected to the feedback branch where the fourth resistor R4 is located, and is used to change the equivalent resistance value of the feedback branch.

[0027] This embodiment illustrates a specific connection method for the first-stage amplifier circuit in a shunt amplifier. In the first-stage amplifier circuit, the first resistor R1 and the third resistor R3 serve as input resistors for the two input terminals, respectively, while the second resistor R2 and the fourth resistor R4 serve as feedback resistors for the two output terminals. These four resistors, together with the first operational amplifier, constitute a classic fully differential amplifier structure. In this structure, the amplifier's output signal theoretically depends only on the differential signals at the two input terminals and is independent of the common-mode signal shared by both input terminals. This ability to suppress common-mode signals is achieved through strict matching of the resistor ratios.

[0028] In the ideal case of perfect resistor matching, the second resistor R2 and the fourth resistor R4 have equal resistance values, and the first resistor R1 and the third resistor R3 have equal resistance values. In this case, the first-stage amplifier circuit can be equivalent to a balanced bridge structure. When a common-mode signal is applied to both inputs simultaneously, due to the symmetrical resistor ratios, the common-mode signals cancel each other out at the output and are not propagated to subsequent stages. The common-mode rejection ratio (CMRR), a key performance indicator, is directly related to the resistor matching accuracy. Higher matching accuracy results in a higher CMRR and stronger common-mode interference suppression capability of the amplifier.

[0029] Specifically, such as Figure 1 This is a structure for a shunt amplifier with an added adjustment unit. It mainly includes a first-stage fully differential amplifier AMP1, first-stage amplification resistors R1~R4, a second-stage amplifier AMP2, second-stage amplification resistors R7~R10, a reference voltage VREF, and a power supply voltage AREF. Ideally, under perfectly matched resistor conditions, R2 and R4 are equal, R1 and R3 are equal, R9 and R10 are equal, and R7 and R8 are equal. Its ideal output formula is: However, in the actual circuit fabricated and returned, there is a resistor mismatch, which will lead to a worse common-mode rejection ratio. This is because, in an ideal situation, the output is only related to the differential signal (VSP-VSN) and not to the common-mode signal. The formula for common-mode rejection ratio: Where Ad is the gain of the differential signal and Acm is the gain of the common-mode signal; the higher the CMRR, the better, indicating a stronger ability to suppress common-mode interference.

[0030] Assuming resistor mismatch, i.e. R2 is not equal to R4: As can be seen from the formula, resistance mismatch is inversely proportional to CMRR; As can be seen, the problem lies in the fact that when the resistance values ​​of the second resistor R2 and the fourth resistor R4 are no longer equal, the originally balanced bridge structure is disrupted. At this time, the common-mode signal cannot be completely canceled at the output, but appears as a differential-mode signal between the two outputs of the first operational amplifier. This error signal converted from common-mode signal will be transmitted to the subsequent stage along the signal chain, ultimately causing a significant decrease in the common-mode rejection ratio of the entire shunt amplifier.

[0031] To address this issue, this embodiment includes at least one of a first adjustment unit 1 and a second adjustment unit 2 in the first-stage amplifier circuit. The first adjustment unit 1 is connected in the feedback branch containing the second resistor R2, and the second adjustment unit 2 is connected in the feedback branch containing the fourth resistor R4. Each adjustment unit can be connected to the circuit in series or in parallel with the corresponding resistor, but is not limited to this method. When a mismatch in the equivalent resistance of the two feedback branches is detected during testing, the total equivalent resistance of one of the branches can be changed by the adjustment unit, so that the equivalent resistance of the branch containing the second resistor R2 and the branch containing the fourth resistor R4 are brought back to the same level.

[0032] From the calculation relationship of common-mode rejection ratio (CMRR), it can be seen that CMRR is inversely proportional to the degree of feedback resistor mismatch. The greater the actual resistance deviation between the second resistor R2 and the fourth resistor R4, the lower the CMRR. In this embodiment, by introducing an adjustable trimming unit in the feedback branch, it is equivalent to adding a degree of freedom for correction on the key proportional relationship. By testing the actual resistance matching, the first trimming unit 1 or the second trimming unit 2 can be adjusted to control the equivalent resistance deviation of the two feedback branches within an acceptable range. This method of correction on a single feedback branch does not require changing the entire circuit topology; the bridge balance can be restored simply by local resistance compensation, thereby maintaining the CMRR within the designed specification range.

[0033] like Figure 2 In one exemplary embodiment, the first adjustment unit 1 is connected in series between the second end of the second resistor R2 and the first node, which is the connection node between the positive output terminal of the first operational amplifier and the first input terminal of the second stage amplifier circuit. And / or, the second tuning unit 2 is connected in series between the second end of the fourth resistor R4 and the second node, which is the connection node between the negative output terminal of the first operational amplifier and the second input terminal of the second stage amplifier circuit.

[0034] This embodiment illustrates the specific connection positions of the first trimming unit 1 and the second trimming unit 2 in the circuit. The first trimming unit 1 is connected between the second end of the second resistor R2 and the first node, where the first node is the location where the positive output terminal of the first operational amplifier is connected to the first input terminal of the second-stage amplifier circuit. This connection method is equivalent to connecting the first trimming unit 1 in series in the feedback path where the second resistor R2 is located, that is, the signal travels from the inverting input terminal of the first operational amplifier through the second resistor R2, then through the first trimming unit 1, and finally reaches the positive output terminal. Similarly, the second trimming unit 2 is connected in series between the fourth resistor R4 and the second node. This series structure allows the equivalent resistance of the trimming unit to be directly added to the original feedback resistance, together forming the total impedance of the feedback branch.

[0035] When a deviation in the total impedance of the two feedback branches is detected, this embodiment can change the total resistance of the branch by adjusting the tuning unit connected in series in the branch. For example, if the test finds that the total impedance of the branch containing the second resistor R2 is less than that of the branch containing the fourth resistor R4, the first tuning unit 1 can add an extra series resistor to the second resistor R2 to increase the total resistance of the branch until it is consistent with that of the branch containing the fourth resistor R4. This adjustment method directly affects the total impedance of the feedback path, does not change the connection topology of the first operational amplifier itself, and does not affect the matching relationship on the input resistor side. Therefore, it can restore the balance between the two feedback branches without introducing additional errors.

[0036] From a signal transmission perspective, the closed-loop gain of the first operational amplifier is determined by the ratio of the feedback resistor to the input resistor. In this embodiment, the tuning unit is connected in series at the end of the feedback resistor, which is equivalent to correcting the equivalent resistance of the feedback branch while keeping the input resistance constant. This correction method can be achieved, but is not limited to, through a multi-stage resistor network within the tuning unit in conjunction with switches. By selecting different resistance values ​​connected in the series path, fine resistance compensation can be achieved. Since the common-mode rejection ratio of the first-stage amplifier circuit directly depends on the symmetry of the ratio between the two feedback branches and the two input branches, the series tuning method can effectively suppress the deviation of the feedback branch within an acceptable range.

[0037] like Figure 3 In one exemplary embodiment, the first adjustment unit 1 and the second resistor R2 may be connected in parallel; and / or, the second adjustment unit 2 and the fourth resistor R4 may be connected in parallel.

[0038] This embodiment also provides another implementation method, namely, the first adjustment unit 1 is connected in parallel with the second resistor R2, and / or the second adjustment unit 2 is connected in parallel with the fourth resistor R4. In this parallel structure, the adjustment unit and the original feedback resistor form a parallel relationship, jointly determining the total equivalent impedance of the branch. According to the impedance characteristics of the parallel circuit, when the adjustment unit is connected, the total resistance of the branch will be less than the resistance of the original feedback resistor. By controlling the equivalent resistance of the parallel branch inside the adjustment unit, continuous adjustment from slightly less than the original resistance to much less than the original resistance can be achieved.

[0039] The adjustment principle of the parallel adjustment method differs from that of the series method. When the resistance of the second resistor R2 is found to be too high, causing the total impedance of the feedback branch to be higher than that of the branch containing the fourth resistor R4, the total equivalent impedance of the branch can be reduced by connecting the first adjustment unit 1 in parallel. The formula for calculating the equivalent impedance of the parallel structure is the product of the original resistance and the impedance of the adjustment unit, divided by the sum of the two. Therefore, the smaller the equivalent impedance of the adjustment unit, the more significant the decrease in the total resistance of the branch. This adjustment method has advantages when it is necessary to correct the resistance value downward, and can flexibly compensate for situations where the resistance value is too high due to process deviations.

[0040] The internal implementation of a parallel tuning unit can, but is not limited to, a structure using multiple resistor branches and switches. These branches are connected in parallel, and the overall equivalent impedance of the tuning unit is changed by controlling the switching on and off of different branches. When the tuning unit is connected in parallel with the feedback resistor, the total impedance of the feedback branch will exhibit a non-linear but controllable change. In practical applications, based on the test results after fabrication, a parallel tuning unit can be connected to the feedback branch with a larger resistance value, adjusting the equivalent resistance of that branch downwards to match the other branch. Whether series or parallel tuning, the essence is to restore the proportional balance between the two feedback branches in the first-stage amplifier circuit by changing the equivalent impedance of the feedback branch, thereby ensuring that the common-mode signal is effectively canceled at both outputs and maintaining the common-mode rejection capability of the shunt amplifier within its design specifications.

[0041] In an exemplary embodiment, the first adjustment unit 1 includes a first series adjustment branch and a first parallel adjustment branch; the first series adjustment branch is connected between the second end of the second resistor R2 and the first node, and is used to connect in series with the second resistor R2; the first parallel adjustment branch is connected in parallel with the second resistor R2. And / or, the second adjustment unit 2 includes a second series adjustment branch and a second parallel adjustment branch; the second series adjustment branch is connected between the second end of the fourth resistor R4 and the second node, and is used to connect in series with the fourth resistor R4; the second parallel adjustment branch is connected in parallel with the fourth resistor R4.

[0042] In this embodiment, the series adjustment branch can add an extra resistance value to the original feedback resistor to achieve upward adjustment; the parallel adjustment branch reduces the equivalent resistance value by bypassing part of the current to achieve downward adjustment. When the total impedance of the feedback branch deviates from the design value, the series or parallel branch can be activated, or used in combination, depending on the direction of deviation, to adjust the equivalent resistance value to the target range. This bidirectional adjustment capability has higher adaptability to cope with process deviations in different batches.

[0043] This application does not specify the specific implementation method.

[0044] like Figure 4 or Figure 5 In one exemplary embodiment, the first trimming unit 1 and / or the second trimming unit 2 include a programmable resistor network. The programmable resistor network includes multiple programmable resistor branches connected in parallel. Each programmable resistor branch includes at least one resistor element, and at least some of the programmable resistor branches are provided with branch switches. The switch control module 3 is used to control the on / off state of the branch switch in order to adjust the equivalent resistance value of the programmable resistor network.

[0045] This embodiment illustrates a specific implementation of the tuning unit, namely, using a programmable resistor network to construct either the first tuning unit 1 or the second tuning unit 2. The programmable resistor network contains multiple parallel-connected programmable resistor branches, each branch containing at least one resistive element, and at least some branches also have branch switches. The switch control module 3 is responsible for controlling the on / off states of these branch switches. When a branch switch is closed, the corresponding resistive element is connected to the network, forming a parallel connection with other connected branches; when the switch is open, the branch is disconnected from the network. By selecting different branch combinations, the equivalent resistance value of the entire network can be changed.

[0046] This programmable resistor network is based on the impedance calculation formula for parallel resistors. When multiple resistors are connected in parallel, the reciprocal of the total equivalent resistance is equal to the sum of the reciprocals of the resistances of each branch. Therefore, each time a resistor branch is added, the total equivalent resistance decreases. By designing the resistance values ​​of the resistors in each branch to present a specific proportional relationship, such as a binary weighting relationship, the switch control module 3 can achieve fine-step adjustment within a certain resistance range through different switch combinations. For example, but not limited to, the resistance values ​​of each branch can be designed as powers of 2, so that more resistance levels can be achieved with fewer branches through binary encoding.

[0047] The switch control module 3 in this embodiment can be implemented using, but is not limited to, digital logic circuits. In practical applications, the shunt amplifier is first tested to measure the deviation between the actual equivalent resistance values ​​of the two feedback branches. Based on the measured direction and magnitude of the deviation, the switch control module 3 generates a set of switch control signals to close the branch switches that need to be connected and to open the branch switches that do not need to be connected, causing the programmable resistor network to output a target equivalent resistance value. This target resistance value, when combined with the original feedback resistor in series or parallel, precisely corrects the total impedance of the feedback branches to near the design value, thereby restoring the matching relationship between the two feedback branches.

[0048] This programmable resistor network structure offers flexible and repeatable adjustment. Compared to traditional laser or fuse-based adjustment methods, the switch control module 3 can rewrite the control signal multiple times, achieving programmable reset of the adjustment result. This is particularly suitable for applications requiring dynamic adjustment of resistor matching accuracy under different scenarios. Furthermore, the programmable resistor network can be fully integrated within the chip, eliminating the need for additional external components and reducing post-packaged testing complexity. The cooperation between the switch control module 3 and the branch switch allows the entire adjustment process to be completed via a digital interface, facilitating automated calibration during production testing.

[0049] like Figure 4 or Figure 5 In one exemplary embodiment, the programmable resistor network includes: The first resistor branch includes a reference resistor element and is a normally open branch; At least one fixed resistor branch is connected in series with the first resistor branch; Multiple adjustable resistor branches are connected in parallel with a series branch composed of a first resistor branch or a first resistor branch and a fixed resistor branch, and the resistance values ​​of the resistor elements in each adjustable resistor branch are in a binary proportional relationship. Each adjustable resistor branch is equipped with a branch switch to independently control the on / off state of the corresponding branch.

[0050] This embodiment illustrates the specific internal structure of a programmable resistor network. The structure includes a normally-on first resistor branch, which contains a reference resistor element and is always connected without a switch. At least one fixed resistor branch is connected in series with the first resistor branch, together forming a reference impedance. Multiple adjustable resistor branches are connected in parallel with this reference impedance. The resistance values ​​of the resistor elements in each adjustable resistor branch are designed according to a binary proportional relationship, for example, set to 16 times, 8 times, 4 times, etc., based on a certain base resistance value R5. Each adjustable resistor branch has an independent branch switch. By controlling the on / off state of these switches, it is possible to select which adjustable resistor branches are connected in parallel to the reference impedance, thereby changing the equivalent output resistance value of the entire tuning unit.

[0051] The core of this structure lies in decomposing the equivalent resistance of the adjustment unit into a fixed reference part and a programmable parallel adjustment part. The reference part consists of a first resistor branch and its series-connected fixed resistor branches, determining the minimum or basic resistance value of the adjustment unit. When no adjustable resistor branch is connected, the equivalent resistance of the adjustment unit is equal to the reference impedance. Each time an adjustable resistor branch is connected, its resistive element forms a parallel relationship with the reference impedance. According to the calculation rules for parallel resistance, the smaller the resistance value of the connected branch, the more significant the pull-down effect on the total resistance. By designing the resistance values ​​of each adjustable branch using binary weights, it is possible to obtain a greater number of resistance adjustment levels with fewer branches. The state of each branch switch corresponds to a binary bit, and the switch combinations can cover multiple gradients from the reference resistance value downwards.

[0052] In a more specific implementation, the programmable resistor network employs an eight-parallel branch structure. The first branch includes a sixth resistor (i.e., the reference resistor element described above) and has no switch, serving as a normally-on branch. Branches two through four each contain resistors of 16 times, 8 times, and 4 times R5, respectively. The first, second, third, and fourth branches are connected in parallel to form a first parallel branch, which is then connected in series with an R6. Branches five and six each contain resistors of 8 times and 4 times R5, respectively. These branches are then connected in parallel with (the first parallel branch + R6) to form a second parallel branch, which is then connected in series with a R6 of 2 times. Branches seven and eight each contain resistors of 8 times and 4 times R5, respectively, and are then connected in parallel with (the second parallel branch + R6). Figure 4 and Figure 5 In the middle, the left end serves as the first end of the corresponding adjustment unit, and the right end serves as the second end of the corresponding adjustment unit. In the second to eighth branches, each branch is connected in series with a branch switch (corresponding to S0-S6).

[0053] This multi-layered parallel and series topology achieves a wider range of resistance adjustment capabilities through the combination of resistors at different levels. The first layer consists of the first branch connected in parallel with the second to fourth branches, forming the basic adjustable range. A sixth resistor is then connected in series, shifting the adjustment range towards higher resistance values. The addition of the fifth and sixth branches expands the fineness of adjustment at higher levels. After connecting twice the sixth resistor in series, the seventh and eighth branches further extend the upper and lower limits of adjustment. The switches of each parallel branch can be controlled independently. By combining the switching states of different levels, the entire network can achieve relatively fine step adjustment over a wide resistance range. This layered structure can be used, but is not limited to, in scenarios requiring both a large adjustment range and fine adjustment accuracy, enabling the trim unit to find a suitable equivalent resistance value to compensate for the mismatch in the feedback branch under different process deviations.

[0054] In one exemplary embodiment, the programmable resistor network further includes a plurality of master switches; The main switch is connected in series in the corresponding adjustable resistor branch to control whether multiple adjustable resistor branches enter the programmable state (e.g., Figure 4 S7 in, and Figure 5 (S7' in the middle).

[0055] This embodiment further introduces a master switch into the programmable resistor network. The master switch is connected in series in the adjustable resistor branches, and its function is to control whether multiple adjustable resistor branches enter the programmable state as a whole. Specifically, when the master switch is in the open state, all adjustable resistor branches connected in series with it are disconnected from the network. At this time, the programmable resistor network only retains the reference impedance path composed of the normally open branch and the fixed resistor branch. The entire network is in an unadjustable state, and the equivalent resistance value of the feedback branch is determined by the reference impedance path. When the master switch is closed, each adjustable resistor branch is ready to connect to the network. Then, by independently controlling the on / off state of the corresponding branch through each branch switch, fine adjustment of the resistance value can be achieved.

[0056] This hierarchical control structure, combining a main switch and branch switches, divides the operation of the programmable resistor network into two levels. The first level, determined by the main switch, decides whether to enable the adjustable function; the second level, determined by each branch switch, specifies the resistance setting value. This design can, but is not limited to, bypass the entire adjustable resistor branch in a non-adjustment state, preventing unexpected impacts on the feedback branch due to leakage or coupling interference from branch switches in an unprogrammed state. Simultaneously, the presence of the main switch allows the adjustment unit to isolate the set resistor network from the main circuit by disconnecting the main switch after setting the resistance value, or to maintain the adjustment state by closing the main switch.

[0057] like Figure 6In one exemplary embodiment, the second operational amplifier employs a Class AB output stage circuit structure with a floating voltage source bias. The second operational amplifier includes: The input differential pair transistors have their two input terminals connected to the two output terminals of the first-stage amplifier circuit, respectively, to receive and amplify the input signal. The first set of current mirrors in the cascode structure has its input terminals connected to the differential pair transistors and the power supply voltage, respectively, serving as an active load. The second set of current mirrors is connected to the ground terminal and serves as the tail current source; The first linear transconductance loop includes multiple PMOS transistors, which are respectively connected to the first group of current mirrors and the second group of current mirrors; The second linear transconductance ring includes multiple NMOS transistors and is coupled to the first linear transconductance ring.

[0058] In this embodiment, the second operational amplifier employs a Class AB output stage circuit structure with a floating voltage source bias. This structure achieves stable control of the output stage's quiescent current by introducing two linear transconductance loops. Specifically, the first linear transconductance loop consists of multiple PMOS transistors, and the second linear transconductance loop consists of multiple NMOS transistors, with the two transconductance loops coupled to each other. When the power supply voltage fluctuates, the floating voltage source structure ensures that the quiescent current of the output stage driver transistors remains essentially constant because the presence of the two linear transconductance loops decouples the output stage's bias state from changes in the power supply voltage.

[0059] The advantage of this structure lies in the significant suppression of the output stage quiescent current from power supply voltage fluctuations. In traditional Class AB output stages, the quiescent current of the output stage driver transistors often drifts significantly with power supply voltage changes, leading to a decrease in power supply rejection ratio (PSRR). This embodiment uses a linear transconductance loop to determine the quiescent current, allowing the output stage bias voltage to adaptively adjust with power supply voltage changes, while the driver transistor's operating current remains stable. This relies on the closed-loop characteristics of two linear transconductance loops. When the power supply voltage changes, the transconductance loops automatically adjust the bias point through an internal negative feedback mechanism, ensuring that the output stage driver transistors always operate near the set quiescent current. This allows the shunt amplifier to maintain high common-mode rejection performance and signal amplification accuracy even in complex application environments with fluctuating power supply voltages, enhancing the overall system's robustness under different operating conditions.

[0060] like Figure 6In one exemplary embodiment, the second operational amplifier further includes a bias switch Q5; the input differential pair includes a first input switch Q6 and a second input switch Q7; the first set of current mirrors includes a first switch Q1 and a second switch Q2; the second set of current mirrors includes a third switch Q3 and a fourth switch Q4; the first linear transconductance loop includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3 and a fourth PMOS transistor MP4; and the second linear transconductance loop includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The control terminal of the first input switch Q6 is the first input terminal of the second operational amplifier, and the control terminal of the second input switch Q7 is the second input terminal of the second operational amplifier. The first terminals of the first input switch Q6 and the second input switch Q7 are both grounded. The second terminal of the first input switch Q6 is connected to the first terminal of the second switch Q2 and the power supply voltage, respectively. The second terminal of the second input switch Q7 is connected to the first terminal of the first switch Q1 and the power supply voltage, respectively. The second end of the first switch Q1 is connected to the first end of the bias switch Q5. The second end of the bias switch Q5 is connected to the first end of the third switch Q3 and the control end of the third switch Q3. The second end of the third switch Q3 is grounded. The control end of the first switch Q1 is connected to the control end of the second switch Q2. The control end of the third switch Q3 is connected to the control end of the fourth switch Q4. The second terminal of the second switch Q2 is connected to the first terminal of the first PMOS transistor MP1, the first terminal of the first NMOS transistor MN1, and the control terminal of the fourth PMOS transistor MP4, respectively; the second terminal of the first PMOS transistor MP1 is connected to the first terminal of the fourth switch Q4, the second terminal of the first NMOS transistor MN1, and the control terminal of the fourth NMOS transistor MN4, respectively; and the second terminal of the fourth switch Q4 is grounded. The control terminal of the first NMOS transistor MN1 is connected to the control terminal of the second NMOS transistor MN2, the first terminal of the second NMOS transistor MN2, and the power supply voltage. The control terminal of the first PMOS transistor MP1 is connected to the control terminal of the bias switch Q5, the control terminal of the second PMOS transistor MP2, the second terminal of the second PMOS transistor MP2, and the ground terminal. The first terminal of the second PMOS transistor MP2 is connected to the control terminal of the third PMOS transistor MP3 and the second terminal of the third PMOS transistor MP3. The first terminal of the third PMOS transistor MP3 is connected to the power supply voltage. The first terminal of the fourth PMOS transistor MP4 is connected to the power supply voltage. The second terminal of the fourth PMOS transistor MP4 is connected to the first terminal of the fourth NMOS transistor MN4 and serves as the output terminal of the second operational amplifier. The second terminal of the fourth NMOS transistor MN4 is grounded. The second terminal of the second NMOS transistor MN2 is connected to the first terminal of the third NMOS transistor MN3 and the control terminal of the third NMOS transistor MN3, respectively. The second terminal of the third NMOS transistor MN3 is grounded.

[0061] To obtain an appropriate bias voltage so that the quiescent current of the CLASS AB output stage circuit is not affected by the power supply voltage AREF, a floating voltage source biasing method is adopted. The quiescent current is determined by a linear transconductance loop. The circuit structure mainly includes output stage driver transistors MP4 and MN4, whose bias voltage is provided by a floating voltage source composed of MP1 and MN1. MN2, MN3 and MP2, MP3 are all diodes connected to provide bias voltages for MN4 and MP4 respectively. Iref is the reference current.

[0062] The quiescent current of the output stage driver transistor is controlled by a linear transconductance loop. The circuit shown in the diagram has two linear transconductance loops: one consisting of MN1, MN2, MN3, and MN4, and the other consisting of MP1, MP2, MP3, and MP4. Set the MOSFET size (W / L). MN1 =2(W / L) MN2 (W / L) MN4 =n(W / L) MN3 (W / L) MP1 =2(W / L) MP2 (W / L) MP4 =n(W / L) MP3 Therefore, the MOSFETs in the linear transconductance loop satisfy the following relationship: V GSMN2 +V GSMN3 =V GSMN1 +V GSMN4， (1); V GSMP2 +V GSMP3 =V GSMP1 +V GSMP4， (2); The gate-source voltage VGS of a MOSFET can be expressed as: ; Substituting formula (3) into (2) and (1), we get: ; Simplifying formulas (4) and (5), we get: I DMN4 =I DMP4 =nI ref，The above analysis and calculation of the linear transconductance loop show that the output stage quiescent current is nI. ref Since it is unaffected by the supply voltage AREF, this shunt amplifier has the advantage of a high power supply rejection ratio.

[0063] Secondly, this application provides an electronic device including the operational amplifier as described above.

[0064] For a description of the electronic device, please refer to the above-described embodiment of the shunt amplifier; this application will not repeat it here.

[0065] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0066] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A shunt amplifier, characterized in that, include: The first-stage amplifier circuit includes a first operational amplifier and a first resistor network connected to the first operational amplifier. The second-stage amplifier circuit includes a second operational amplifier and a second resistor network connected to the second operational amplifier. At least one resistor adjustment unit is provided, which is connected to at least one resistor branch in the first resistor network and / or the second resistor network, for adjusting the equivalent resistance value of the connected resistor branch to adjust the resistance matching accuracy of the shunt amplifier.

2. The shunt amplifier as described in claim 1, characterized in that, The first resistor network includes a first resistor, a second resistor, a third resistor, and a fourth resistor; The first end of the first resistor serves as the first input terminal of the shunt amplifier. The second end of the first resistor is connected to the inverting input terminal of the first operational amplifier and the first end of the second resistor. The second end of the second resistor is connected to the positive output terminal of the first operational amplifier and the first input terminal of the second-stage amplifier circuit. The first end of the third resistor serves as the second input terminal of the shunt amplifier. The second end of the third resistor is connected to the non-inverting input terminal of the first operational amplifier and the first end of the fourth resistor. The second end of the fourth resistor is connected to the negative output terminal of the first operational amplifier and the second input terminal of the second-stage amplifier circuit. The resistor adjustment unit includes at least one of a first adjustment unit and a second adjustment unit; The first adjustment unit is connected to the feedback branch where the second resistor is located, and is used to change the equivalent resistance value of the feedback branch where the second resistor is located; The second adjustment unit is connected to the feedback branch where the fourth resistor is located, and is used to change the equivalent resistance value of the feedback branch.

3. The shunt amplifier as described in claim 2, characterized in that, The first adjustment unit is connected in series between the second end of the second resistor and the first node, and the first node is the connection node between the positive output terminal of the first operational amplifier and the first input terminal of the second stage amplifier circuit. And / or, the second adjustment unit is connected in series between the second end of the fourth resistor and the second node, the second node being the connection node between the negative output terminal of the first operational amplifier and the second input terminal of the second stage amplifier circuit.

4. The shunt amplifier according to claim 2, characterized in that, The first adjustment unit is connected in parallel with the second resistor; and / or, the second adjustment unit is connected in parallel with the fourth resistor.

5. The shunt amplifier as described in claim 2, characterized in that, The first trimming unit and / or the second trimming unit includes a programmable resistor network; The programmable resistor network includes multiple programmable resistor branches connected in parallel, each programmable resistor branch includes at least one resistor element, and at least some of the programmable resistor branches are provided with branch switches. A switch control module is used to control the on / off state of the branch switch in order to adjust the equivalent resistance value of the programmable resistor network.

6. The shunt amplifier as described in claim 5, characterized in that, The programmable resistor network includes: The first resistor branch includes a reference resistor element and is a normally open branch; At least one fixed resistor branch is connected in series with the first resistor branch; Multiple adjustable resistor branches are connected in parallel with a series branch composed of the first resistor branch or the first resistor branch and the fixed resistor branch, and the resistance values ​​of the resistor elements in each adjustable resistor branch are in a binary proportional relationship. Each of the adjustable resistor branches is equipped with a branch switch to independently control the on / off state of the corresponding branch.

7. The shunt amplifier as described in claim 6, characterized in that, The programmable resistor network also includes multiple master switches; The main switch is connected in series in the corresponding adjustable resistor branch and is used to control whether the multiple adjustable resistor branches enter the programmable state.

8. The shunt amplifier according to any one of claims 1-7, characterized in that, The second operational amplifier adopts a Class AB output stage circuit structure with a floating voltage source bias. The second operational amplifier includes: The input differential pair transistors have their two input terminals connected to the two output terminals of the first-stage amplifier circuit, respectively, to receive and amplify the input signal. The first set of current mirrors in the cascode structure has its input terminals connected to the differential pair transistors and the power supply voltage, respectively, serving as an active load; The second set of current mirrors is connected to the ground terminal and serves as the tail current source; The first linear transconductance loop includes multiple PMOS transistors, which are respectively connected to the first group of current mirrors and the second group of current mirrors; The second linear transconductance ring includes multiple NMOS transistors and is coupled to the first linear transconductance ring.

9. The shunt amplifier as claimed in claim 8, characterized in that, The second operational amplifier further includes a bias switch; the first set of current mirrors includes a first switch and a second switch; the second set of current mirrors includes a third switch and a fourth switch; the first linear transconductance loop includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the second linear transconductance loop includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first terminal of the first switching transistor receives a differential signal output from the first stage amplifier circuit and is connected to the power supply voltage. The first terminal of the second switching transistor receives another differential signal output from the first stage amplifier circuit and is connected to the power supply voltage. The second terminal of the first switching transistor is connected to the first terminal of the bias switching transistor. The second terminal of the bias switching transistor is connected to the first terminal of the third switching transistor and the control terminal of the third switching transistor. The second terminal of the third switching transistor is grounded. The control terminal of the first switching transistor is connected to the control terminal of the second switching transistor. The control terminal of the third switching transistor is connected to the control terminal of the fourth switching transistor. The second terminal of the second switch is connected to the first terminal of the first PMOS transistor, the first terminal of the first NMOS transistor, and the control terminal of the fourth PMOS transistor, respectively; the second terminal of the first PMOS transistor is connected to the first terminal of the fourth switch, the second terminal of the first NMOS transistor, and the control terminal of the fourth NMOS transistor, respectively; and the second terminal of the fourth switch is grounded. The control terminal of the first NMOS transistor is connected to the control terminal of the second NMOS transistor, the first terminal of the second NMOS transistor, and the power supply voltage. The control terminal of the first PMOS transistor is connected to the control terminal of the bias switch transistor, the control terminal of the second PMOS transistor, the second terminal of the second PMOS transistor, and ground. The first terminal of the second PMOS transistor is connected to the control terminal of the third PMOS transistor and the second terminal of the third PMOS transistor. The first terminal of the third PMOS transistor is connected to the power supply voltage. The first terminal of the fourth PMOS transistor is connected to the power supply voltage, the second terminal of the fourth PMOS transistor is connected to the first terminal of the fourth NMOS transistor and serves as the output terminal of the second operational amplifier, and the second terminal of the fourth NMOS transistor is grounded; the second terminal of the second NMOS transistor is connected to the first terminal of the third NMOS transistor and the control terminal of the third NMOS transistor, respectively, and the second terminal of the third NMOS transistor is grounded.

10. The shunt amplifier as claimed in claim 9, characterized in that, The input differential pair transistors include a first input switch transistor and a second input switch transistor; The control terminal of the first input switch is the first input terminal of the second operational amplifier, and the control terminal of the second input switch is the second input terminal of the second operational amplifier. The first terminals of the first and second input switches are both grounded. The second terminal of the first input switch is connected to the first terminal of the second switch and the power supply voltage, respectively. The second terminal of the second input switch is connected to the first terminal of the first switch and the power supply voltage, respectively.

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