A low-area comparator mismatch calibration circuit suitable for sub-ADCs

Abstract

This invention discloses a low-area comparator offset calibration circuit suitable for sub-ADCs, relating to the field of integrated circuit design technology. The circuit includes a capacitive digital-to-analog converter (DAC) module, a resistive DAC module, a comparator module, and a successive approximation logic module. The capacitive DAC module is a fully differential structure, including a positive-terminal capacitor array and a negative-terminal capacitor array. This invention utilizes a high-area-efficiency R-DAC to replace the traditional large-area capacitor calibration array, and further reduces the number of resistors through a segmented structure. Comparator offset is compensated by injecting an adjustable voltage into the calibration capacitor base plate. This invention significantly reduces circuit area overhead and power consumption while maintaining calibration accuracy, with minimal impact on main circuit performance, making it particularly suitable for area-constrained sub-ADC applications.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a low-area comparator offset calibration circuit suitable for sub-ADCs. Background Technology

[0002] Successive approximation analog-to-digital converters (SAR ADCs) are widely used in various data acquisition systems due to their simple structure, low power consumption, and small area. In a SAR ADC, the comparator is one of the core modules, and its performance directly affects the overall performance of the ADC. The comparator inevitably has offset voltage, which can cause a shift in the ADC's transfer characteristic curve and reduce conversion accuracy. Especially when the SAR ADC is used as a sub-ADC in high-speed scenarios, such as time-interleaved scenarios, the offset voltage can introduce severe spurious and harmonic distortion. Alternatively, when a high-precision ADC is used as a coarse ADC, the offset voltage can lead to reduced system redundancy or even exceed the measurement range. Existing comparator offset calibration methods mainly include: Changing the comparator load: Adding an array of offset calibration capacitors inside the comparator will introduce additional load and reduce the comparator's speed.

[0003] Four-input comparator: Adding two extra comparator inputs consumes offset by adjusting the differential input voltage. However, this method is affected by the comparator common-mode level, and a four-input comparator increases power consumption and noise.

[0004] Input capacitor array method: An offset calibration capacitor array is added to the capacitive digital-to-analog converter (CDAC), and the offset voltage is compensated by adjusting the capacitance ratio. Although this method has good results, it requires a large chip area, and in scenarios involving coarse-quantization and fine-quantization ADCs, the capacitor array used to calibrate the comparator offset is often mismatched with the coarse-quantization ADC due to range issues.

[0005] Therefore, how to design a comparator offset calibration scheme with low area overhead, low impact on main circuit performance, and high calibration accuracy has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide an area-optimized comparator offset calibration circuit and method, which is particularly suitable for sub-ADC applications with limited chip area. While ensuring calibration accuracy, it significantly reduces the area overhead and power consumption of the circuit, and can solve the problems mentioned in the background art.

[0007] To achieve the above objectives, according to one aspect of the present invention, a low-area comparator offset calibration circuit suitable for sub-ADCs is provided, the circuit comprising a capacitive digital-to-analog converter module, a resistive digital-to-analog converter module, a comparator module, and a successive approximation logic module; The capacitive digital-to-analog converter module is a fully differential structure, including a positive terminal capacitor array and a negative terminal capacitor array; the positive terminal capacitor array includes an n-bit capacitor array C. 1_p - C n_p and comparator offset calibration capacitor C os_p The negative terminal capacitor array includes an n-bit capacitor array C. 1_n - C n_n and comparator offset calibration capacitor C os_n ; The n-bit capacitor array C 1_p - C n_p and comparator offset calibration capacitor C os_p The top plate of the capacitor is connected to the common terminal V of the positive capacitor array. cp n-bit capacitor array C 1_p - C n_p The capacitor base plate is connected to n three-way switches S respectively. 1p -S np The aforementioned n three-to-one switches S 1p -S np Connected to the positive input terminal Vip, the positive reference voltage Vrefp, and the negative reference voltage Vrefn respectively; comparator offset calibration capacitor C os_p The capacitor base plate is connected to the positive output terminal of the resistive digital-to-analog converter module; the common terminal V cp Through S tp Connect to the common-mode level Vcm, while the common terminal V cp Connect to the positive input of the comparator; The n-bit capacitor array C 1_n - C n_n and comparator offset calibration capacitor C os_n The top plate of the capacitor is connected to the common terminal V of the negative capacitor array. cn n-bit capacitor array C 1_n - C n_n The capacitor base plates are respectively connected to the three-way selector switch S. 1n -S nn The aforementioned n three-to-one switches are respectively connected to the negative input terminal Vin, the positive reference voltage Vrefp, and the negative reference voltage Vrefn; the comparator offset calibration capacitor C os_n The capacitor base plate is connected to the negative output terminal of the resistive digital-to-analog converter module; common terminal V cn Through S tn Connect to the common-mode level Vcm, while the common terminal Vcn Connect to the negative input of the comparator; The comparator is a differential comparator; its positive input terminal is connected to the common node V of the positive capacitor array. cp The negative input terminal is connected to the common node V of the negative capacitor array. cn The output of the comparator is connected to the successive approximation logic module for outputting a result signal; the successive approximation logic module outputs the final output Dout of the successive approximation analog-to-digital converter and outputs the switching control signal of the capacitive digital-to-analog converter module.

[0008] Preferably, the resistive digital-to-analog converter module is used to generate an adjustable calibration voltage, including an adjustable positive terminal voltage V. RDAC_P and the adjustable voltage V at the negative terminal RDAC_N The positive terminal adjustable voltage V RDAC_P The input is passed to the comparator offset calibration capacitor C through the positive output terminal of the resistive digital-to-analog converter module. os_p The adjustable voltage V at the negative terminal RDAC_N The input is passed to the comparator offset calibration capacitor C through the negative output terminal of the resistive digital-to-analog converter module. os_n .

[0009] Preferably, the resistive digital-to-analog converter module adopts a segmented resistor network structure, including a high-order resistor segment and a low-order resistor segment; The high-order resistance segment contains M series-connected binary weighted resistors R msb<0> -R msb <m-1>< / m-1> The low-position resistor segment contains K resistors R connected in series. lsb<0> -R lsb <k-1>< / k-1> The resistance R of the high-level resistance section msb<0> -R msb <m-1>< / m-1> Connected in series, with the topmost R msb <m-1>< / m-1> The positive terminal of the resistor is connected to Vrefp, and the bottommost R... msb<0> The negative terminal of the resistor is connected to Vrefn; the resistor R in the lower resistor segment... lsb<0> -R lsb <k-1>< / k-1> Connected in series, the whole assembly is connected in parallel to R. msb<0> The resistor has two ends, with R at the very top. lsb <k-1>< / k-1> The positive terminal of the resistor is connected to R msb<0> The positive terminal of the resistor, the bottommost R lsb<0> The negative terminal of the resistor is connected to Vrefn.

[0010] Preferably, the resistive digital-to-analog converter module further includes a first layer switch and a second layer switch; S in the first layer of switches msb <m-1>< / m-1> To S msb<0> The first end is connected to R respectively msb <m-1:0>< / m-1:0>The positive input terminal; S msb <m-1>< / m-1> -S msb<0> The second end is connected to the common point V. rmsb S in the first layer of switches lsb <k>< / k> -S lsb<1> The first end is connected to R respectively lsb <k-1:0>< / k-1:0> The positive input terminal, S lsb<0> Connect to R lsb<0> The negative input terminal; S lsb <k>< / k> -S lsb<0> The second end is connected to the common point V. rlsb ; The second layer of switches contains six switches for outputting an adjustable positive terminal voltage V. RDAC_P and the adjustable voltage V at the negative terminal RDAC_N Adjustable voltage V at the positive terminal RDAC_P Connect to 3 of the switches, the first switch is connected to V. rmsb Its control signal is CTL VP The second switch is connected to V. rlsb Its control signal is CTL VN The third switch is connected to Vrefn, and its control signal is CTL. SMP Adjustable voltage V at the negative terminal RDAC_N Connect to the remaining 3 switches, with the first switch connected to V. rlsb Its control signal is CTL VP The second switch is connected to V. rmsb Its control signal is CTL VN The third switch is connected to Vrefn, and its control signal is CTL. SMP .

[0011] Preferably, the positive terminal adjustable voltage V RDAC_P and the adjustable voltage V at the negative terminal RDAC_N Output Routing CTL VP CTL VN CTL SMP All three factors are involved in the decision; among them, CTL SMP This is the highest priority enable signal; When CTL SMP When =1, both SMP switches are closed, and the adjustable voltage V on the positive terminal... RDAC_P and the adjustable voltage V at the negative terminal RDAC_N All samples were pulled to Vrefn to complete the sampling. When CTL SMP When =0, CTL VP With CTL VN These are complementary control signals; at this time, when CTL VP =1、CTL VNWhen =0, the positive terminal adjustable voltage V RDAC_P Select V rmsb The negative terminal adjustable voltage V RDAC_N Select V rlsb When CTL VP =0、CTL VN When =1, the positive terminal adjustable voltage V RDAC_P Adjustable voltage V at the negative terminal RDAC_N The selection path is interchanged, that is, the positive terminal adjustable voltage V RDAC_P Select V rlsb The negative terminal adjustable voltage V RDAC_N Select V rmsb This enables the polarity switching of the differential output.

[0012] Preferably, the resistive digital-to-analog converter module further includes a control logic module; During operation, the control logic module receives the sampling clock CK. SMP and the J-bit RDAC control signal ctl_rdac <j-1:0>and output the first layer switch S msb <m-1:0>< / m-1:0> S lsb <k:0>< / k:0> and the control signal CTL of the second layer switch VP CTL VN CTL SMP Among them, the J-bit RDAC control signal ctl_rdac <j-1:0>It is decomposed into high-level control bits and low-level control bits to control the switches corresponding to the high-level resistor segment and the low-level resistor segment, respectively.

[0013] Preferably, the switching timing of the control logic module of the resistive digital-to-analog converter module includes: During sampling, CTL SMP =1, causing the comparator offset calibration capacitor C to be 1. os_p C os_n Through V RDAC_P V RDAC_N Connect to Vrefn; After sampling, CTL SMP =0, according to ctl_rdac <j-1:0>Input situation, CTL VP With CTL VN One is high, the other is low, V RDAC_P / V RDAC_N By connecting to V rmsb V rlsb They output different voltages respectively.

[0014] According to another aspect of the present invention, the present invention provides a comparator offset calibration method based on the above-described calibration circuit, characterized by comprising the following steps: During the calibration phase, all differential input terminals of the capacitive digital-to-analog converter module are connected to the common-mode voltage; The output level of the comparator module is detected, and the RDAC control signal ctl_rdac, which is input to the control logic module in the J-bit, is adjusted according to the output result through the successive approximation logic module. <j-1:0>; After the output voltage of the resistive digital-to-analog converter module stabilizes, the RDAC control signal ctl_rdac of the J-bit that causes the comparator module to flip is locked. <j-1:0>Complete calibration; During normal operation, the RDAC control signal ctl_rdac of the locked J-bit is... <j-1:0>Under these conditions, the resistive digital-to-analog converter module continuously outputs an adjustable calibration voltage to offset the offset voltage of the comparator module, and the analog-to-digital converter enters the normal conversion process.

[0015] According to another aspect of the present invention, an analog-to-digital converter is provided that includes a comparator offset calibration circuit.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention is applicable to low-area comparator offset calibration circuits for sub-ADCs and has the following characteristics: Significantly reduced area overhead: Replacing the traditional CDAC calibration array with an R-DAC structure significantly reduces chip area because resistors achieve much higher precision per unit area than capacitors in integrated circuits. Furthermore, the segmented R-DAC structure further reduces the required number of resistors from exponential to linear levels; for example, at 5-bit calibration accuracy, the number of required resistors is reduced from 32 to 8, resulting in a decrease in control logic complexity.

[0017] Minimal impact on main circuit performance: The calibration capacitor is usually close to the least significant bit (LSB) capacitor of the main CDAC, which hardly increases the load on the comparator input and therefore does not affect the comparator's speed and noise performance.

[0018] The calibration range is flexible and controllable: the calibration range is determined by the reference voltage and the ratio of the calibration capacitor to the main capacitor. Designers can flexibly adjust it according to the expected maximum offset voltage, and it is highly adaptable to process, voltage and temperature.

[0019] Good compatibility and portability: The calibration circuit of this invention is an independent module that works by injecting charge, and can be easily integrated into various existing SAR ADC architectures without requiring large-scale modifications to the main CDAC array. Attached Figure Description

[0020] Figure 1 This is an overall structural block diagram of the comparator offset calibration circuit provided in an embodiment of the present invention.

[0021] Figure 2 for Figure 1 A detailed circuit diagram of a medium-resistance digital-to-analog converter (R-DAC) module. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] This invention provides an area-optimized comparator offset calibration circuit suitable for sub-ADCs. It connects an area-optimized resistive digital-to-analog converter (R-DAC) to the offset cancellation capacitor and injects adjustable compensation charge into the comparator input to achieve comparator offset voltage calibration. like Figure 1-2 As shown, the comparator offset calibration circuit of the present invention mainly includes the following functional modules: a capacitive digital-to-analog converter (CDAC) module, a resistive digital-to-analog converter (R-DAC) module, a successive approximation logic module (SAR Logic) and a comparator module (Icmp).

[0024] The CDAC (Capacitive Digital-to-Analog Converter) module adopts a fully differential structure, including a positive capacitor array (P-terminal) and a negative capacitor array (N-terminal). The CDAC module is connected to the differential input of a comparator (Icmp) and implements sampling, holding, and conversion functions through multiple switches.

[0025] The positive terminal capacitor array includes: capacitor C 1_p -C n_p It is an n-bit capacitor array, with its top plate connected to the common terminal V of the positive capacitor array. cp The base plate is connected to n three-way switches S respectively. 1p -S np These n three-way switches S 1p -S np Connect to the positive input terminal respectively V ip Positive reference voltage V refp negative reference voltage V refn C os_p This is the comparator offset calibration capacitor, whose top plate is connected to the common terminal V of the positive capacitor array. cp The capacitor base plate is connected to the adjustable voltage input terminal. V RDAC_P (Positive terminal R-DAC output voltage). Node V cp Through S tp Connect to common mode level Vcm Meanwhile, V cp Connect to the positive input terminal of comparator Icmp. Negative terminal capacitor array connection: Capacitor C 1_n - C n_n It is an n-bit capacitor array, with its top plate connected to the common terminal of the negative capacitor array. V cn The base plate is connected to a three-way selector switch S. 1n -S nn These n three-to-one switches are respectively connected to the negative input terminal. V in Positive reference voltage V refp negative reference voltage V refn C os_n This is the comparator offset calibration capacitor, whose top plate is connected to the common terminal of the negative capacitor array. V cn The capacitor base plate is connected to the adjustable voltage input terminal. V RDAC_N (Negative terminal R-DAC output voltage). Node V cn Through S tn Connect to common mode level Vcm ,at the same time V cn Connect to the negative input of comparator Icmp. Comparator Icmp is a differential comparator. The positive input of comparator Icmp is connected to the common node of the positive capacitor array. V cp The negative input terminal is connected to the common node V of the negative capacitor array. cn The output signal of the comparator Icmp is connected to the successive approximation logic module Ilog. Ilog outputs the final output of the ADC. Dout It also outputs the CDAC's switching control signal.

[0026] The R-DAC module is used to generate an adjustable calibration voltage: the positive terminal adjustable voltage ( V RDAC_P ) and the negative terminal adjustable voltage ( V RDAC_N ).like Figure 2 As shown, the R-DAC module employs a segmented resistor network structure to reduce the number of resistors, control switches, and control logic. The high-order segment (MSB segment) contains M binary-weighted resistors. R msb<0> to R msb <m-1>< / m-1> The low-order segment (LSB segment) contains K resistors connected in series. R lsb<0> to R lsb <k-1>< / k-1> The resistors in the MSB segment are connected in series, with the top one being the... R msb <m-1>< / m-1> The positive terminal of the resistor is connected to V refp The bottom R msb<0> The negative terminal of the resistor is connected to V refn The resistors in the LSB section are connected in series and then connected in parallel to R. msb<0> The resistor has two ends, with R at the very top. lsb <k-1>< / k-1> The positive terminal of the resistor is connected to R msb<0> The positive terminal of the resistor, the bottommost R lsb<0> The negative terminal of the resistor is connected to V refn The R-DAC module has two layers of switches, the first layer being S... msb <m-1>< / m-1> To S msb<0> The first end is connected to R respectively msb <m-1:0>< / m-1:0> The positive input terminal; S msb <m-1>< / m-1> To S msb<0> The second end is connected to the common point. V rmsb S lsb <k>< / k> To S lsb<1> The first end is connected to R respectively lsb <k-1:0>< / k-1:0> The positive input terminal, S lsb<0> Connect to R lsb<0> The negative input terminal. S lsb <k>< / k> To S lsb<0> The second end is connected to a common point. V rlsb The second layer contains six switches to generate an adjustable positive voltage. V RDAC_P Adjustable voltage at the negative terminal V RDAC_N . V RDAC_P Connected to 3 switches, the first switch is connected to V rmsb Its control signal is CTL VP The second switch is connected to V rlsb Its control signal is CTL VN The third switch is connected to V refn Its control signal is CTL SMP . V RDAC_N Connected to 3 switches, the first switch is connected to V rlsb Its control signal is CTL VP The second switch is connected to V rmsb Its control signal is CTL VN The third switch is connected to V refn Its control signal is CTL SMP .

[0027] V RDAC_P and V RDAC_N Output routing CTL VP , CTL VN , CTL SMP The decision is made jointly by all three parties. CTL SMP This is the highest priority enable signal. CTL SMP When =1, both SMP switches are closed. V RDAC_P and V RDAC_N All pulled to V refn Complete sampling; when CTL SMP When =0, CTL VP and CTL VN These are complementary control signals (the two signals have opposite states, and only one of them is active at any given time): When CTL VP =1、 CTL VN When =0, V RDAC_P gating V rmsb , V RDAC_N gating V rlsb ;when CTL VP =0、 CTL VN When =1, V RDAC_P and V RDAC_N Interchange of gating paths — V RDAC_P gating V rlsb , V RDAC_N gating V rmsb This enables polarity switching of the differential output.

[0028] The comparator offset calibration circuit of the present invention also includes a control logic module RDAC logic, which receives the sampling clock as input. CK SMP J-bit RDAC control signal ctl_rdac <j-1:0>Where J = Log2(M) + Log2(K) + 1, the output is S. msb <m-1:0>< / m-1:0> S lsb <k:0>< / k:0> , CTL VP , CTL VN , CTL SMP Here, the J-bit RDAC is split into Log2(M) bits and Log2(K) resistors. For example... Figure 2 Taking a 5-bit input as an example, the traditional structure requires 2^5 = 32 resistors, while the present invention only requires 4 + 4 = 8 resistors, which greatly reduces the complexity and area of ​​the resistors and control logic.

[0029] Switching timing: during sampling CTL SMP =1, causing the comparator offset calibration capacitor C to be 1. os_p C os_n pass V RDAC_P , V RDAC_N Connected to V refn After sampling is completed CTL SMP =0, according to ctl_rdac <j-1:0>Input situation, CTL VP and CTL VN One is high, the other is low. V RDAC_P / V RDAC_N By connecting V rmsb , V rlsb They output different voltages respectively.

[0030] The present invention also provides a comparator offset calibration method based on a comparator offset calibration circuit, comprising the following steps: During the calibration phase: In the offset detection phase, the input terminals of the CDAC module are shorted to the common-mode voltage, theoretically making the voltages at the two input terminals of the comparator equal. At this time, if an offset voltage exists in the comparator, its output will be biased towards a fixed level (high or low). The ctl_rdac is adjusted bit by bit using a successive approximation method. <j-1:0>To find the control code (J-bit RDAC control signal ctl_rdac) corresponding to the compensation voltage (adjustable calibration voltage). <j-1:0>).

[0031] During the normal conversion phase: Under the locked calibration parameters, the SAR ADC enters the normal conversion mode and performs successive approximation analog-to-digital conversion using a compensated comparator.

[0032] Compared with existing technologies, this invention is applicable to low-area comparator offset calibration circuits for sub-ADCs, significantly reducing area overhead: it utilizes the characteristic of R-DAC, which occupies a significantly smaller area compared to capacitor arrays of equivalent precision, to replace the traditional large capacitor array for offset calibration. Furthermore, the J-bit RDAC is split into Log2(M) bits and Log2(K) resistor arrays.

[0033] like Figure 2 For a 5-bit input, a traditional structure requires 2^5 = 32 resistors, while this invention only requires 4 + 4 = 8 resistors, significantly reducing the complexity and area of ​​the resistors and control logic. Furthermore, the R-DAC uses a calibration capacitor C... os_p C os_n The calibration capacitor is introduced into the main capacitor array in a manner similar to that of the least significant bit (LSB) in sub-ADC applications, occupying almost no extra area. Furthermore, the calibration range can be flexibly controlled through the calibration capacitor. The calibration range is stable, determined by the reference level. V refp ,V refn The determination of the calibration capacitor ratio can adapt to offset changes under different process angles, temperature conditions, and power supply voltages.

[0034] Good compatibility: The calibration circuit of this invention can be easily integrated into existing SAR ADC structures without requiring significant modifications to the main CDAC array, resulting in low design migration costs.

[0035] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0036] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A low-area comparator offset calibration circuit suitable for sub-ADCs, characterized in that, The circuit includes a capacitive digital-to-analog converter module, a resistive digital-to-analog converter module, a comparator module, and a successive approximation logic module; The capacitive digital-to-analog converter module is a fully differential structure, including a positive terminal capacitor array and a negative terminal capacitor array; the positive terminal capacitor array includes an n-bit capacitor array C. 1_p - C n_p and comparator offset calibration capacitor C os_p The negative terminal capacitor array includes an n-bit capacitor array C. 1_n - C n_n and comparator offset calibration capacitor C os_n ; The n-bit capacitor array C 1_p - C n_p and comparator offset calibration capacitor C os_p The top plate of the capacitor is connected to the common terminal V of the positive capacitor array. cp n-bit capacitor array C 1_p - C n_p The capacitor base plate is connected to n three-way switches S respectively. 1p -S np The aforementioned n three-to-one switches S 1p -S np Connect to the positive input terminal Vip, the positive reference voltage Vrefp, and the negative reference voltage Vrefn, respectively; Comparator offset calibration capacitor C os_p The capacitor base plate is connected to the positive output terminal of the resistive digital-to-analog converter module; the common terminal V cp Through S tp Connect to the common-mode level Vcm, while the common terminal V cp Connect to the positive input of the comparator; The n-bit capacitor array C 1_n - C n_n and comparator offset calibration capacitor C os_n The top plate of the capacitor is connected to the common terminal V of the negative capacitor array. cn n-bit capacitor array C 1_n - C n_n The capacitor base plates are respectively connected to the three-way selector switch S. 1n -S nn The aforementioned n three-to-one switches are respectively connected to the negative input terminal Vin, the positive reference voltage Vrefp, and the negative reference voltage Vrefn; Comparator offset calibration capacitor C os_n The capacitor base plate is connected to the negative output terminal of the resistive digital-to-analog converter module; common terminal V cn Through S tn Connect to the common-mode level Vcm, while the common terminal V cn Connect to the negative input of the comparator; The comparator is a differential comparator; its positive input terminal is connected to the common node V of the positive capacitor array. cp The negative input terminal is connected to the common node V of the negative capacitor array. cn The output of the comparator is connected to the successive approximation logic module for outputting a result signal; the successive approximation logic module outputs the final output Dout of the successive approximation analog-to-digital converter and outputs the switching control signal of the capacitive digital-to-analog converter module.

2. The low-area comparator offset calibration circuit suitable for sub-ADCs according to claim 1, characterized in that, The resistive digital-to-analog converter module is used to generate an adjustable calibration voltage, including an adjustable positive terminal voltage V. RDAC_P and the adjustable voltage V at the negative terminal RDAC_N The positive terminal adjustable voltage V RDAC_P The input is passed to the comparator offset calibration capacitor C through the positive output terminal of the resistive digital-to-analog converter module. os_p The adjustable voltage V at the negative terminal RDAC_N The input is passed to the comparator offset calibration capacitor C through the negative output terminal of the resistive digital-to-analog converter module. os_n .

3. A low-area comparator offset calibration circuit suitable for a sub-ADC according to claim 1 or 2, characterized in that, The resistive digital-to-analog converter module adopts a segmented resistor network structure, including a high-order resistor segment and a low-order resistor segment; The high-order resistance segment contains M series-connected binary weighted resistors R msb<0> -R msb <m-1>< / m-1> The low-position resistor segment contains K resistors R connected in series. lsb<0> -R lsb <k-1>< / k-1> The resistance R of the high-level resistance section msb<0> -R msb <m-1>< / m-1> Connected in series, with the topmost R msb <m-1>< / m-1> The positive terminal of the resistor is connected to Vrefp, and the bottommost R... msb<0> The negative terminal of the resistor is connected to Vrefn; the resistor R in the lower resistor segment... lsb<0> -R lsb <k-1>< / k-1> Connected in series, the whole assembly is connected in parallel to R. msb<0> The resistor has two ends, with R at the very top. lsb <k-1>< / k-1> The positive terminal of the resistor is connected to R msb<0> The positive terminal of the resistor, the bottommost R lsb<0> The negative terminal of the resistor is connected to Vrefn.

4. A low-area comparator offset calibration circuit suitable for sub-ADCs according to claim 3, characterized in that, The resistive digital-to-analog converter module also includes a first layer switch and a second layer switch; S in the first layer of switches msb <m-1>< / m-1> To S msb<0> The first end is connected to R respectively msb <m-1:0>< / m-1:0> The positive input terminal; S msb <m-1>< / m-1> -S msb<0> The second end is connected to the common point V. rmsb S in the first layer of switches lsb <k>< / k> -S lsb<1> The first end is connected to R respectively lsb <k-1:0>< / k-1:0> The positive input terminal, S lsb<0> Connect to R lsb<0> The negative input terminal; S lsb <k>< / k> -S lsb<0> The second end is connected to the common point V. rlsb ; The second layer of switches contains six switches for outputting an adjustable positive terminal voltage V. RDAC_P and the adjustable voltage V at the negative terminal RDAC_N Adjustable voltage V at the positive terminal RDAC_P Connect to 3 of the switches, the first switch is connected to V. rmsb Its control signal is CTL VP The second switch is connected to V. rlsb Its control signal is CTL VN The third switch is connected to Vrefn, and its control signal is CTL. SMP Adjustable voltage V at the negative terminal RDAC_N Connect to the remaining 3 switches, with the first switch connected to V. rlsb Its control signal is CTL VP The second switch is connected to V. rmsb Its control signal is CTL VN The third switch is connected to Vrefn, and its control signal is CTL. SMP .

5. A low-area comparator offset calibration circuit suitable for sub-ADCs according to claim 4, characterized in that, The positive terminal adjustable voltage V RDAC_P and the adjustable voltage V at the negative terminal RDAC_N Output Routing CTL VP CTL VN CTL SMP All three factors are involved in the decision; among them, CTL SMP This is the highest priority enable signal; When CTL SMP When =1, both SMP switches are closed, and the adjustable voltage V on the positive terminal... RDAC_P and the adjustable voltage V at the negative terminal RDAC_N All samples were pulled to Vrefn to complete the sampling. When CTL SMP When =0, CTL VP With CTL VN These are complementary control signals; at this time, when CTL VP =1、CTL VN When =0, the positive terminal adjustable voltage V RDAC_P Select V rmsb The negative terminal adjustable voltage V RDAC_N Select V rlsb When CTL VP =0、CTL VN When =1, the positive terminal adjustable voltage V RDAC_P Adjustable voltage V at the negative terminal RDAC_N The selection path is interchanged, that is, the positive terminal adjustable voltage V RDAC_P Select V rlsb The negative terminal adjustable voltage V RDAC_N Select V rmsb This enables the polarity switching of the differential output.

6. A low-area comparator offset calibration circuit suitable for a sub-ADC according to claim 5, characterized in that, The resistive digital-to-analog converter module also includes a control logic module; During operation, the control logic module receives the sampling clock CK. SMP and the J-bit RDAC control signal ctl_rdac <j-1:0>and output the first layer switch S msb <m-1:0>< / m-1:0> S lsb <k:0>< / k:0> and the control signal CTL of the second layer switch VP CTL VN CTL SMP Among them, the J-bit RDAC control signal ctl_rdac <j-1:0> It is decomposed into high-level control bits and low-level control bits to control the switches corresponding to the high-level resistor segment and the low-level resistor segment, respectively.< / j-1:0> 7. A low-area comparator offset calibration circuit suitable for sub-ADCs according to claim 5, characterized in that, The switching timing of the control logic module of the resistive digital-to-analog converter module includes: During sampling, CTL SMP =1, causing the comparator offset calibration capacitor C to be 1. os_p C os_n Through V RDAC_P V RDAC_N Connect to Vrefn; After sampling, CTL SMP =0, according to ctl_rdac <j-1:0>Input situation, CTL VP With CTL VN One is high, the other is low, V RDAC_P / V RDAC_N By connecting to V rmsb V rlsb They output different voltages respectively.

8. A comparator offset calibration method based on the circuit according to any one of claims 1 to 7, characterized in that, Includes the following steps: During the calibration phase, all differential input terminals of the capacitive digital-to-analog converter module are connected to the common-mode voltage; The output level of the comparator module is detected, and the RDAC control signal ctl_rdac, which is input to the control logic module in the J-bit, is adjusted according to the output result through the successive approximation logic module. <j-1:0> ；< / j-1:0> After the output voltage of the resistive digital-to-analog converter module stabilizes, the RDAC control signal ctl_rdac of the J-bit that causes the comparator module to flip is locked. <j-1:0> Complete calibration;< / j-1:0> During normal operation, the RDAC control signal ctl_rdac of the locked J-bit is... <j-1:0> Under these conditions, the resistive digital-to-analog converter module continuously outputs an adjustable calibration voltage to offset the offset voltage of the comparator module, and the analog-to-digital converter enters the normal conversion process.< / j-1:0> 9. An analog-to-digital converter, characterized in that, It includes a comparator offset calibration circuit as described in any one of claims 1 to 7.

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