Method for integrally forming large-current thick-copper multilayer PCB

Abstract

This invention discloses a method for the integrated fabrication of high-current, thick copper multilayer PCB circuit boards, belonging to the field of PCB manufacturing technology. The method includes: inner core board fabrication, integrated filling and insulating layer construction, integrated conductive layer construction, multilayer stacking, and integrated lamination. This invention uses vacuum printing to force-fill high thermal conductivity composite resin into the gaps between thick copper lines, forming a flat, coplanar structure, fundamentally eliminating the filling voids and delamination defects caused by insufficient resin flow in traditional lamination processes. The outer layer circuits employ a semi-additive method, electroplating a rectangular cross-section thick copper circuit on an ultra-thin seed layer, with an etching factor ≥6.0, solving the severe side etching problem caused by thick copper etching in traditional subtractive methods. Combined with a stepped vacuum lamination process and a homogeneous resin material system, interlayer thermal stress is significantly reduced, and thermal conductivity is improved. This invention is applicable to fields such as new energy vehicles and high-power power supplies, offering advantages such as high current carrying capacity, high heat dissipation, and high reliability.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board (PCB) manufacturing technology, and in particular to a method for the integrated molding and preparation of high-current thick copper multilayer PCB circuit boards. Background Technology

[0002] With the rapid development of new energy vehicles, electric vehicle charging stations, industrial motor drives, high-power power supply systems, and 5G communication base stations, the requirements for the current carrying capacity, heat dissipation performance, and reliability of PCBs in electronic devices are becoming increasingly stringent. Taking electric vehicle charging stations as an example, their charging power has increased from several kilowatts in the early days to tens of kilowatts or even higher today, with charging currents reaching tens to hundreds of amperes. The current demand of the main drive system of new energy vehicles even exceeds 100A, requiring PCBs to be able to safely carry large currents and effectively manage the heat generated as a result.

[0003] Thick copper multilayer PCBs (typically referring to copper foil thickness ≥ 3 oz, or 105 μm) are the preferred solution for these applications due to their ability to carry high currents and their excellent thermal conductivity. This is based on the current-carrying capacity calculation formula. According to the IPC-2221A standard, the cross-sectional area A of the conductor is the core factor determining its current-carrying capacity. Increasing the copper foil thickness directly increases the cross-sectional area, thereby significantly improving the current-carrying capacity: a 2oz copper thickness can increase the current-carrying capacity by about 70% compared to a 1oz thickness, and a 3oz copper thickness can increase it by about 170% compared to a 1oz thickness.

[0004] Existing thick copper multilayer PCBs face three major technical bottlenecks: 1. Filling Voids and Interface Delamination: Traditional thick copper PCB manufacturing processes rely on the resin flow of prepreg (PP sheet) during lamination to fill the significant height differences (up to hundreds of micrometers) between thick copper traces. Due to the significant height differences on the surface of the thick copper trace pattern (the height difference between the copper foil thickness and the copper-free area), the resin in the prepreg is insufficient to completely fill these recessed areas during lamination. From a materials rheological perspective, the viscosity of traditional PP sheet increases sharply before reaching its gel point, making it impossible to completely fill the deep cavity structure within a limited time.

[0005] The direct consequence of this problem is the formation of "resin voids" or "insufficient adhesive" at the boundary between the bottom of the copper wire and the copper-free area. These voids not only lead to a decrease in local withstand voltage but also become sources of cracks that cause delamination and board breakage during subsequent thermal cycling. According to the IPC-9592 standard, the temperature of copper conductors must not exceed 105°C (Class 3 applications) to avoid degradation of FR-4 resin. The presence of voids significantly reduces local heat dissipation capacity, causing hot spot temperatures to exceed limits and accelerating material aging.

[0006] 2. Issues with Uncontrolled Etching Precision in Thick Copper Circuits: Traditional subtractive etching processes form circuits by etching away excess copper foil. When the copper thickness is ≥3oz, the difference between the lateral (side etching) and longitudinal (biting) etching rates of the etching solution intensifies. According to the etching factor calculation formula... Traditional subtractive etching methods typically have an etching factor of less than 3, making it difficult to control linewidth / line spacing to below 150μm.

[0007] Severe lateral erosion not only reduces the actual cross-sectional area of ​​the line (affecting current-carrying capacity) but also leads to poor impedance consistency, making it difficult to meet the dual requirements of high current and high-speed signals. For high-current applications, the reduction in the line cross-sectional area directly affects the current-carrying capacity, according to Ohm's law. A decrease in cross-sectional area S leads to an increase in resistance R, resulting in Joule heating. It increases by a factor of two.

[0008] 3. Interlayer expansion and contraction mismatch and thermal stress concentration: The coefficient of thermal expansion (CTE) differs significantly between the thick copper core board and the conventional dielectric layer (FR-4). Copper has a CTE of approximately 17 ppm / ℃, while FR-4 has a CTE of approximately 12-16 ppm / ℃ in the X / Y directions and as high as 50-70 ppm / ℃ in the Z direction. During repeated high-temperature lamination processes, this mismatch leads to uneven expansion and contraction of the inner layers, resulting in decreased drilling alignment accuracy.

[0009] Furthermore, the thermal conductivity of traditional FR-4 dielectric layers is low (approximately 0.3-0.8 W / m·K), while copper has a thermal conductivity as high as 398 W / m·K. This significant difference means that the Joule heat generated by thick copper circuitry cannot be effectively conducted to the heat dissipation layer, resulting in localized heat accumulation. According to Fourier's law... The low thermal conductivity of the dielectric layer severely hinders the vertical conduction of heat, causing the hot spot temperature to rise and accelerating material aging.

[0010] To address the above issues, researchers have made several attempts at improvement: 1) Optimization of thick copper subtractive etching: The side etching problem can be improved by adjusting etching parameters and adopting step etching, but due to the limitations of the etching principle itself, the EF value is difficult to break through 4.0, and the process window is narrow and the yield is low.

[0011] 2) Traditional resin plugging technology: Resin is filled into the gaps between circuits using screen printing. However, ordinary resin has poor thermal conductivity (<1.0 W / m·K) and insufficient bonding with the copper interface, making it prone to cracking during thermal cycling.

[0012] 3) Optimization of multi-layer lamination parameters: The filling effect can be improved by adjusting the lamination temperature and pressure curve, but it cannot fundamentally eliminate the filling problem caused by the height difference of the line.

[0013] 4) Copper-embedded heat dissipation technology: Copper blocks are embedded inside the PCB to enhance heat dissipation. However, this process is manufactured separately from the main circuit board, resulting in high interface thermal resistance and the risk of insufficient bonding strength.

[0014] However, none of these improvement attempts have fundamentally solved the core contradiction of thick copper PCBs: how to achieve integrated high-precision circuitry, void-free filling, and efficient heat dissipation while ensuring high current carrying capacity. Summary of the Invention

[0015] To address the shortcomings of existing technologies, this invention proposes an integrated molding and fabrication method for high-current thick copper multilayer PCB circuit boards. The method aims to achieve high-precision molding of thick copper circuits, perfect filling of high-low difference interfaces, and high-reliability interlayer interconnection through an innovative stepped semi-additive method + vacuum resin via plugging and planarization + homogeneous hot pressing technology system. This effectively improves the current carrying capacity, heat dissipation efficiency, and long-term reliability of the product under high-current conditions.

[0016] To achieve the above objectives, the present invention adopts the following technical solution: Current-carrying capacity standards for high-current, thick-copper PCBs: According to the IPC-2221A standard and industry practice, the definition of high-current, thick-copper PCBs needs to comprehensively consider both current rating and temperature rise control. Current rating classification: Low and high current: 10-20A; Medium to high current: 20-50A; High current: 50-100A; Ultra-high current: >100A.

[0017] Relationship between copper thickness and current carrying capacity (ΔT=30℃, linewidth 1mm): 1oz (35μm): outer layer 8-10A, inner layer 6-8A; 2oz (70μm): outer layer 12-15A, inner layer 9-12A; 3oz (105μm): outer layer 16-20A, inner layer 12-16A; 4oz (140μm): outer layer 20-24A, inner layer 15-19A.

[0018] Temperature rise limit standard: According to IPC-9592 standard, the temperature of copper conductors must not exceed 105℃; Typical designs allow for a temperature rise of ΔT = 10-30℃ (based on an ambient temperature of 25℃). Due to poor heat dissipation in the inner layer, a temperature rise of ≤10℃ is recommended. The technical solution of this invention is designed for high current application scenarios with current ≥50A and copper thickness ≥3oz, while also taking into account the medium-to-high current application requirements of 10-50A.

[0019] A method for integrally molding and fabricating high-current, thick-copper, multilayer PCB circuit boards includes the following steps: Step 1: Inner Core Board Fabrication S1.1 Select a double-sided copper-clad laminate with an initial copper foil thickness of 3 oz to 10 oz as the substrate.

[0020] S1.2 Laser direct imaging (LDI) technology is used for pattern transfer, combined with an etch-resistant mask, and a step-by-step etching method is used to process the inner layer circuitry. First, a half-etch is performed to 60%-80% of the target copper thickness to form a pre-circuit pattern. Then, the mask is removed, and a final etching is performed to obtain a thick copper inner layer circuit pattern with a side etching factor ≥5.

[0021] The mechanism of step-by-step etching is to decompose the total etching amount into two stages. The first stage removes most of the copper layer using a faster etching rate, while the second stage performs fine finishing to reduce the impact of side etching. Compared to traditional one-step etching, step-by-step etching can increase the side etching factor from about 2.5 to over 5.0.

[0022] S1.3 The inner layer circuit pattern is subjected to black or brown oxidation treatment to form a rough oxide layer with a thickness of 0.5-2μm to enhance the bonding force with the subsequent filling resin.

[0023] Step 2: Construction of Integrated Filler and Insulation Layer S2.1 Prepare a composite resin filler material with high thermal conductivity and low coefficient of thermal expansion. The filler material comprises, by weight, 40-60 parts of bisphenol A type epoxy resin, 10-20 parts of phenolic epoxy resin, 20-40 parts of spherical alumina filler (average particle size 3-8 μm), and 5-10 parts of latent curing agent.

[0024] Formulation design mechanism of composite resin materials: Bisphenol A type epoxy resin: provides basic mechanical properties and bond strength; Phenolic epoxy resin: Improves heat resistance and crosslinking density, and reduces CTE; Spherical alumina filler: Constructs a thermally conductive network, increasing the thermal conductivity from 0.8 W / m·K to 2.5-4.0 W / m·K, while reducing the CTE of the resin system; Latent curing agent: Enables controlled curing in the B-stage, facilitating subsequent lamination processes.

[0025] S2.2 The composite resin filler material is filled into the line gaps and recessed areas of the inner core board using vacuum printing or vacuum lamination. The process parameters are: pressure 0.5-1.0 MPa, vacuum degree ≤ -0.095 MPa, printing speed 30-80 mm / s. Vacuum assistance is used to remove air bubbles, ensuring complete resin filling.

[0026] Then, pre-baking is performed to bring the resin to a semi-cured state (B-stage), forming a smooth insulating layer surface that is flush with the copper circuit surface, with the height difference controlled within ±5μm.

[0027] S2.3 The semi-cured composite resin layer is subjected to surface plasma treatment to remove surface contaminants and increase surface energy, thereby improving the adhesion to the subsequent conductive layer.

[0028] Step 3: Construction of the integrated conductive layer S3.1 On the smooth insulating layer surface treated in step 2, a thin copper seed layer with a thickness of 1-3 μm is deposited by chemical plating.

[0029] S3.2 Lay a photosensitive permanent medium film or coat a photosensitive resin onto a thin copper seed layer.

[0030] S3.3 By exposure and development, openings are made in the areas where the outer layer of circuitry needs to be formed, creating grooves for the circuit pattern.

[0031] S3.4 A pulse electroplating method is used to deposit a copper layer of the required thickness within the grooves of the circuit pattern. The pulse electroplating parameters are: pulse frequency 500-2000Hz, duty cycle 10%-30%, and copper layer thickness controlled between 105μm and 420μm (3oz to 12oz). The mechanism of pulse electroplating lies in eliminating concentration polarization through periodic reverse current, thereby obtaining a dense, low-stress copper deposition layer.

[0032] S3.5 Remove the photosensitive permanent dielectric film or photosensitive resin, and then use a rapid etching process to remove the remaining thin copper seed layer between the circuit patterns, forming the final outer layer circuit pattern. Since the seed layer thickness is only 1-3μm, the etching time is short, and the lateral etching depth can be controlled to <3μm.

[0033] Step 4: Multi-layer lamination and integrated lamination S4.1 As needed, multiple inner core boards, bonding sheets, and outer copper foils processed in steps 1-3 are stacked. The insulating dielectric layer between adjacent layers is preferably a prepreg made of the same composite resin filler material as in step 2, to ensure the consistency of the material system.

[0034] The formula for calculating the current carrying capacity of multi-layer stacking is: ; I single Let n be the current carrying capacity of a single layer and n be the number of parallel layers. The exponent of 0.85 reflects the current distribution efficiency and thermal coupling effect between parallel layers.

[0035] S4.2 The laminated boards are placed in a vacuum press for integrated lamination, with a vacuum level ≤ -0.098 MPa throughout the process. The lamination parameters are divided into three stages: Phase 1: Increase temperature to 80-110℃, maintain pressure at 10-20 kg / cm² 2 Keep it warm for 10-20 minutes. During this stage, the resin softens and flows fully, expelling internal gases.

[0036] Second stage: Increase the temperature to 120-150℃ and the pressure to 25-35 kg / cm². 2 Keep warm for 20-30 minutes. This stage involves primary curing, during which the resin cross-linking network is formed.

[0037] Third stage: Increase the temperature to 180-200℃, and maintain the pressure at 30-40 kg / cm². 2 Keep warm for 60-90 minutes. After this stage, cure to ensure complete resin cross-linking.

[0038] The mechanism of stepwise temperature and pressure increase is as follows: by controlling the viscosity change of the resin in stages, gas discharge and interface wetting are completed before gelation, high pressure is applied during gelation to eliminate micropores, and finally high temperature curing is used to form a dense bonded interface.

[0039] Step 5: Post-processing S5.1 Perform X-ray target drilling on the laminated multilayer board to drill positioning holes.

[0040] S5.2 Blind holes and through holes are drilled using a combination of laser drilling and mechanical drilling. For thick copper layers, segmented mechanical drilling is used to reduce drill bit wear and hole wall roughness.

[0041] S5.3 performs hole metallization and electroplating to fill the holes, achieving interlayer electrical interconnection. The current carrying capacity of the vias follows: 24 / 12mil vias (24mil inner diameter, 12mil pads) carry approximately 1A of current per via (ΔT=10℃).

[0042] S5.4 Fabricate the solder mask layer, perform surface treatment and molding processes to obtain the finished circuit board.

[0043] Adaptive design mechanism under high current conditions: 1. The current-carrying advantage mechanism of rectangular cross-section lines According to electromagnetic theory, the distribution of current across a conductor's cross-section follows the skin effect and edge effect. For trapezoidal cross-section circuits formed by subtractive methods, the current density concentrates at the bottom two corners, forming local hot spots. Rectangular cross-section circuits have a more uniform current density distribution and higher effective cross-sectional area utilization.

[0044] Joule heating calculation: ,resistance For the same design linewidth, the actual cross-sectional area S of a trapezoidal section is smaller than that of a rectangular section, resulting in a higher resistance R and higher heat generation. The rectangular section of this invention has an actual cross-sectional area 12%-15% larger than that of the trapezoidal section, correspondingly reducing the temperature rise by 20%-30%.

[0045] 2. Thermal conduction mechanism of pre-filled leveling Voids are poor conductors of heat (air's thermal conductivity ≈ 0.026 W / m·K), while the composite resin's thermal conductivity is 2.5-4.0 W / m·K. The presence of voids is equivalent to setting up a "heat insulation layer" in the heat conduction path, preventing the Joule heat generated by the copper wire from being effectively conducted downwards.

[0046] According to Fourier's law When the thermal conductivity k increases from 0.026 to 3.2 W / m·K, the heat flux density q increases by 123 times. The pre-filling process of this invention eliminates voids and constructs a low thermal resistance path of "copper wire → composite resin → heat dissipation layer".

[0047] 3. Cooperative Mechanism of Multi-Layer Parallel Current Carriers In a multi-layer parallel structure, the total current-carrying capacity is not a simple sum of the current-carrying capacities of each layer, but rather follows a certain principle. The relationship. The mechanism of this relationship lies in: Current distribution efficiency: Impedance differences exist in via connections, resulting in uneven current distribution across layers; Thermal coupling effect: The heat generated by adjacent layers affects each other, limiting the overall temperature rise; An index of 0.85 is an engineering experience value recommended by the IPC standard, taking into account the above factors.

[0048] The multilayer stacking design of this invention improves the actual current carrying capacity to 85%-90% of the theoretical value by optimizing the via array (spacing 2-3mm, aperture 0.5mm) and the symmetrical stacking structure.

[0049] Compared with the prior art, the beneficial effects of the present invention are: 1. Completely eliminate the risks of interlayer voids and interface delamination: This invention employs a vacuum printing process to forcibly fill the gaps in thick copper circuits with a high thermal conductivity composite resin and pre-cures it, forming a flat insulating layer coplanar with the copper circuit surface, with a height difference controlled within ±5μm. This process fundamentally solves the problem of voids caused by insufficient resin flow in traditional processes. The void rate of this invention is 0%, while the void rate of the traditional process is as high as 12.5%. In a 288℃ thermal stress test, the product of this invention showed no delamination after three tin-bleaching cycles, while the comparative sample showed severe delamination on the first tin-bleaching cycle. After 1000 temperature cycles from -55℃ to 125℃, the resistance change rate of the product of this invention was only 3.8%, while that of the traditional process was as high as 22.5%, a reduction of 83%. Mechanistically, the vacuum environment effectively eliminates air bubbles inside the resin, and the flat surface formed by pre-curing allows subsequent lamination to achieve only chemical bonding rather than physical filling, completely eliminating the physical basis for void formation and eliminating the blocking effect of the air insulation layer on heat conduction.

[0050] 2. Achieve high-precision thick copper circuit forming: This invention employs a semi-additive method to fabricate a thick outer copper circuit. A rectangular cross-section circuit is formed by electroplating on an ultra-thin seed layer of 1-3 μm, completely avoiding the severe side etching problem caused by thick copper etching in traditional subtractive methods. The etching factor of this invention reaches 6.8, while the traditional subtractive method is only 2.1, representing an improvement of 224%. The linewidth / spacing capability reaches 100 μm / 100 μm, an improvement of 33% compared to the traditional subtractive method. At 150A current, the temperature rise of the product of this invention is 28.5℃, a reduction of 33% compared to the traditional subtractive method. After 1000 high-current cycles, the resistance change rate is 3.8%, a reduction of 79% compared to the traditional subtractive method. Mechanistically, the rectangular cross-section circuit ensures a uniform current density distribution and high effective cross-sectional area utilization, while the trapezoidal cross-section circuit concentrates the current density at the bottom two corners, forming hot spots, and the reduced actual cross-sectional area leads to increased resistance and Joule heating.

[0051] 3. Significantly improves heat dissipation efficiency and thermomechanical reliability: This invention uses a composite resin containing 20-40 wt% spherical alumina filler as the insulating filler material to construct a through-type thermally conductive network. Simultaneously, the filler reduces the coefficient of thermal expansion of the resin system, making it highly compatible with the thermal expansion properties of copper. The thermal conductivity of this invention reaches 3.2 W / m·K, while that of pure epoxy resin is only 0.9 W / m·K, representing an improvement of 256%. At a current of 150 A, the temperature rise of the product of this invention is 28.5 °C, which is 39% lower than that of pure epoxy resin. After 1000 temperature cycles, the resistance change rate is 3.8%, which is 59% lower than that of pure epoxy resin. After 1000 high-current cycles, the resistance change rate is 3.8%, which is 67% lower than that of pure epoxy resin. Mechanistically, the spherical alumina filler forms a thermally conductive network in the resin, reducing thermal resistance by approximately 70%. Simultaneously, the filler reduces the coefficient of thermal expansion of the resin system from approximately 60 ppm / °C to approximately 20 ppm / °C, highly matching that of copper (17 ppm / °C), reducing thermal stress by 93% and effectively preventing interface cracking and via breakage.

[0052] 4. Achieve low temperature rise and high reliability under high current conditions: This invention achieves superior performance under high-current conditions through the synergistic effect of rectangular cross-section circuitry, high thermal conductivity filling material, and zero-void interface. At 150A DC current, the temperature rise of the product using this invention is only 28.5℃, while the traditional process reaches 51.2℃, a reduction of 44%; the hot spot temperature difference is 3.2℃, a 79% reduction compared to the traditional process; the resistance change rate after 1000 high-current cycles is 3.8%, an 87% reduction compared to the traditional process; the resistance change rate after 500 hours of electromigration testing is 4.2%, a 77% reduction compared to the traditional process; and the overall yield reaches 94.5%, a 22.2 percentage point improvement compared to the control. Mechanistically, the rectangular cross-section circuitry reduces resistance by 12-15%, zero voids eliminate interfacial thermal resistance, and the high thermal conductivity resin increases heat flux density by 4 times; the synergy of these three factors reduces total thermal resistance by approximately 70%. The low temperature rise breaks the thermo-electric positive feedback loop; according to the Arrhenius model, a 38℃ reduction in operating temperature theoretically extends the lifespan by approximately 14 times.

[0053] 5. Simplify the process flow and improve production efficiency: The integrated process of this invention combines multiple pressing operations in traditional processes into a single step-by-step pressing operation, reducing the number of thermal processes and minimizing cumulative expansion and contraction. The interlayer alignment accuracy of the product improved from ±75μm to ±50μm, an improvement of 33%; the production cycle was shortened by approximately 30%; and the overall yield increased from 72.3% to 94.5%, an improvement of 22.2 percentage points.

[0054] 6. In summary, this invention, through a technical system of stepped semi-additive method + vacuum resin plugging and homogenized hot pressing, achieves high-precision, high-heat-dissipation, and high-reliability integrated molding of high-current thick copper multilayer PCB circuit boards by synergistically working from three dimensions: circuit cross-section optimization, interface thermal resistance elimination, and material thermal conductivity modification. It can meet the stringent requirements of 50A to 200A current-carrying circuit boards in fields such as new energy vehicles, high-power power supplies, and industrial drives, and has significant technological advancements and industrial application value. Detailed Implementation

[0055] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with existing known technologies. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0056] Experimental Design Fundamentals: Preparation target: 8-layer thick copper PCB board, with inner layer L2-L7 copper thickness of 3oz (105μm) and outer layer L1 / L8 copper thickness of 6oz (210μm).

[0057] Key performance indicators: Filling effect: Metallographic sections were examined under a 50x microscope to check for voids at the bottom of the copper corner of layer L2. The acceptable standard is 100% filling with no voids larger than 5μm.

[0058] Line accuracy: Measure the top and bottom line widths of the outer layer lines and calculate the etching factor. EF>5 is considered optimal.

[0059] Current carrying capacity: Current-carrying temperature rise test, measuring the temperature rise ΔT under different currents.

[0060] Thermal reliability: Delamination was checked after thermal stress test (tinning at 288℃ for 10 seconds, 3 times); resistance change rate ΔR / R0 after temperature cycling test (-55℃~125℃, 1000 times).

[0061] Thermal conductivity: The thermal conductivity of the dielectric layer was measured by laser flare method.

[0062] High current cycle life: 0A→150A→0A cycle, heating and cooling rate 10℃ / min, 1000 cycles, resistance change rate measured.

[0063] Testing equipment: metallurgical microscope, scanning electron microscope (SEM), infrared thermal imager, micro resistance meter, temperature cycling test chamber.

[0064] Preparation process: Step 1: Inner Core Board Fabrication S1.1 Select a double-sided copper-clad laminate with an initial copper foil thickness of 3 oz to 10 oz as the substrate.

[0065] S1.2 Laser direct imaging (LDI) technology is used for pattern transfer, combined with an etch-resistant mask, and a step-by-step etching method is used to process the inner layer circuitry. First, a half-etch is performed to 60%-80% of the target copper thickness to form a pre-circuit pattern. Then, the mask is removed, and a final etching is performed to obtain a thick copper inner layer circuit pattern with a side etching factor ≥5.

[0066] S1.3 The inner layer circuit pattern is subjected to black or brown oxidation treatment to form a rough oxide layer with a thickness of 0.5-2μm to enhance the bonding force with the subsequent filling resin.

[0067] Step 2: Construction of Integrated Filler and Insulation Layer S2.1 Prepare a composite resin filler material with high thermal conductivity and low coefficient of thermal expansion. The filler material comprises, by weight, 40-60 parts of bisphenol A type epoxy resin, 10-20 parts of phenolic epoxy resin, 20-40 parts of spherical alumina filler (average particle size 3-8 μm), and 5-10 parts of latent curing agent.

[0068] S2.2 The composite resin filler material is filled into the line gaps and recessed areas of the inner core board using vacuum printing or vacuum lamination. The process parameters are: pressure 0.5-1.0 MPa, vacuum degree ≤ -0.095 MPa, printing speed 30-80 mm / s. Vacuum assistance is used to remove air bubbles, ensuring complete resin filling.

[0069] Then, pre-baking is performed to bring the resin to a semi-cured state (B-stage), forming a smooth insulating layer surface that is flush with the copper circuit surface, with the height difference controlled within ±5μm.

[0070] S2.3 The semi-cured composite resin layer is subjected to surface plasma treatment to remove surface contaminants and increase surface energy, thereby improving the adhesion to the subsequent conductive layer.

[0071] Step 3: Construction of the integrated conductive layer S3.1 On the smooth insulating layer surface treated in step 2, a thin copper seed layer with a thickness of 1-3 μm is deposited by chemical plating.

[0072] S3.2 Lay a photosensitive permanent medium film or coat a photosensitive resin onto a thin copper seed layer.

[0073] S3.3 By exposure and development, openings are made in the areas where the outer layer of circuitry needs to be formed, creating grooves for the circuit pattern.

[0074] S3.4 A pulse electroplating method is used to deposit a copper layer of the required thickness within the grooves of the circuit pattern. The pulse electroplating parameters are: pulse frequency 500-2000Hz, duty cycle 10%-30%, and copper layer thickness controlled between 105μm and 420μm (3oz to 12oz). The mechanism of pulse electroplating lies in eliminating concentration polarization through periodic reverse current, thereby obtaining a dense, low-stress copper deposition layer.

[0075] S3.5 Remove the photosensitive permanent dielectric film or photosensitive resin, and then use a rapid etching process to remove the remaining thin copper seed layer between the circuit patterns, forming the final outer layer circuit pattern. Since the seed layer thickness is only 1-3μm, the etching time is short, and the lateral etching depth can be controlled to <3μm.

[0076] Step 4: Multi-layer lamination and integrated lamination S4.1 As needed, multiple inner core boards, bonding sheets, and outer copper foils processed in steps 1-3 are stacked. The insulating dielectric layer between adjacent layers is preferably a prepreg made of the same composite resin filler material as in step 2, to ensure the consistency of the material system.

[0077] S4.2 The laminated boards are placed in a vacuum press for integrated lamination, with a vacuum level ≤ -0.098 MPa throughout the process. The lamination parameters are divided into three stages: Phase 1: Increase temperature to 80-110℃, maintain pressure at 10-20 kg / cm² 2 Keep it warm for 10-20 minutes. During this stage, the resin softens and flows fully, expelling internal gases.

[0078] Second stage: Increase the temperature to 120-150℃ and the pressure to 25-35 kg / cm². 2 Keep warm for 20-30 minutes. This stage involves primary curing, during which the resin cross-linking network is formed.

[0079] Third stage: Increase the temperature to 180-200℃, and maintain the pressure at 30-40 kg / cm². 2 Keep warm for 60-90 minutes. After this stage, cure to ensure complete resin cross-linking.

[0080] Step 5: Post-processing S5.1 Perform X-ray target drilling on the laminated multilayer board to drill positioning holes.

[0081] S5.2 Blind holes and through holes are drilled using a combination of laser drilling and mechanical drilling. For thick copper layers, segmented mechanical drilling is used to reduce drill bit wear and hole wall roughness.

[0082] S5.3 performs hole metallization and electroplating to fill the holes, achieving interlayer electrical interconnection. The current carrying capacity of the vias follows: 24 / 12mil vias (24mil inner diameter, 12mil pads) carry approximately 1A of current per via (ΔT=10℃).

[0083] S5.4 Fabricate the solder mask layer, perform surface treatment and molding processes to obtain the finished circuit board.

[0084] Example 1 (Preferred embodiment of the present invention): Based on the above preparation process, and with defined process parameters: Inner core board: 3oz copper thickness, step-by-step etching, EF=5.8; Filler resin: composite high thermal conductivity resin (Al2O3 35%), vacuum printing, pressure 0.8MPa; Outer layer molding: Semi-additive process (SAP), pulse plating, copper thickness 6oz; Lamination parameters: stepped high pressure, maximum pressure 35 kg / cm² 2 The highest temperature is 190℃.

[0085] Example 2 (different Al2O3 content 20%): The difference from Example 1 is that the Al2O3 content in the filling resin is 20%; otherwise, it is the same as Example 1.

[0086] Example 3 (different Al2O3 content 40%): The difference from Example 1 is that the Al2O3 content in the filling resin is 40%; otherwise, it is the same as Example 1.

[0087] Example 4 (Low Lamination Pressure): Difference from Example 1: The highest pressure of stepped lamination is 20 kg / cm². 2 Other aspects are the same as in Example 1.

[0088] Example 5 (High Lamination Pressure): Difference from Example 1: The highest pressure of stepped lamination is 45 kg / cm². 2 Other aspects are the same as in Example 1.

[0089] Example 6 (outer copper layer thickness 3oz): Difference from Example 1: outer copper plating thickness 3oz (105μm); other aspects are the same as Example 1.

[0090] Example 7 (Adding a heat dissipation via array): The difference from Example 1 is that a heat dissipation via array (0.5 mm diameter, 1 mm spacing) is added to the high current path; otherwise, it is the same as Example 1.

[0091] Example 8 (20% wider line): Difference from Example 1: The outer line width is increased by 20%; otherwise, it is the same as Example 1.

[0092] Comparative Example 1 (Traditional process, no prefill): Difference from Example 1: No vacuum prefill in step 2, directly uses traditional FR-4 semi-cured sheet lamination for filling, and the outer layer uses a subtractive method; other aspects are the same as in Example 1.

[0093] Comparative Example 2 (outer layer using subtractive molding): Difference from Example 1: the outer layer circuit is formed using the traditional subtractive molding method; other aspects are the same as in Example 1 (filling and lamination are the same as in this invention).

[0094] Comparative Example 3 (no vacuum printing, only lamination filling): Difference from Example 1: Step 2 uses ordinary screen printing (non-vacuum), and after filling the resin, it is directly laminated without pre-curing; other aspects are the same as Example 1.

[0095] Comparative Example 4 (filled resin without thermally conductive filler): The difference from Example 1 is that the filling resin is pure epoxy resin (without Al2O3 filler); otherwise, it is the same as Example 1.

[0096] Comparative Example 5 (Lamination using traditional one-stage process): Difference from Example 1: Lamination uses a one-stage process (175℃ constant temperature and pressure, 30kg / cm²). 2 ); the rest is the same as in Example 1.

[0097] Comparative Example 6 (Traditional Subtractive Process, EF=2.5, Trapezoidal Cross Section): Difference from Example 1: The 6oz outer layer circuit was fabricated using the traditional subtractive process without prefilling; other aspects were the same as the traditional process.

[0098] Comparative Example 7 (void exists at the bottom of the line): The process of Comparative Example 1 is used, but there is a void rate of 12.5%.

[0099] Comparative Example 8 (pure epoxy filler, low thermal conductivity): Difference from Example 1: The filler resin is pure epoxy resin (λ=0.9W / m·K); other aspects are the same as in Example 1.

[0100] The process differences between Examples 1-9 and Comparative Examples 1-8 are summarized in Table 1 below: Table 1. Differentiated Design of Process Parameters

[0101] The performance differences are shown in Table 2 below: Table 2. Summary of the impact of process parameters on performance

[0102] Note: In Example 6, the outer copper layer thickness was 3 oz, and the test current was 100 A. According to the proportional conversion, the temperature rise at 150 A is approximately 42 °C. The temperature rise at 150 A was not tested separately.

[0103] Perform multi-dimensional analysis on the data in Table 2: 1. Analysis of Filling Effect and Lamination Process (Example 1 vs. Comparative Examples 1, 3, and 5): Table 3. Analysis of Filling Effect and Lamination Process

[0104] In Comparative Example 1, no pre-filling was performed. During lamination, the PP sheet resin needed to flow from the outside to the inside to fill the gaps in the thick copper lines. Due to the large height difference of the thick copper lines (copper thickness 105μm), the resin formed a "shadow area" at the bottom of the copper lines, hindering flow and resulting in a void ratio as high as 12.5%. The presence of voids caused thermal stress concentration, and severe delamination appeared during thermal stress testing.

[0105] Comparative Example 3, although using the same resin, could not completely eliminate air bubbles by relying solely on ordinary screen printing (non-vacuum), and the void rate still reached 8.2%. This demonstrates that the forced filling and air bubble removal functions of vacuum printing are crucial.

[0106] Comparative Example 5 uses a one-stage lamination process. The resin reaches its gel point instantly at high temperature, causing a sharp increase in viscosity. Residual air cannot escape, resulting in 4.5% voids. Example 1 uses a stepped heating and pressurization process: the first stage, at low temperature and low pressure, allows the resin to fully soften and flow; the second stage, at medium temperature and medium pressure, allows the resin to enter the main curing stage and expel gas; and the third stage, at high temperature and high pressure, completes the final cross-linking, achieving zero voids.

[0107] Effect of pressure parameters (Example 1 vs Examples 4 and 5): Example 4: Pressure 20 kg / cm 2 The value is relatively low, the interlayer bonding force is slightly weak, and the microbubbles expand during thermal cycling, causing ΔR / R0 to increase to 5.2%. Example 5: Pressure 45 kg / cm 2 The yield is too high. Although the bonding is good, there is a risk of copper wire crushing (yield drops to 92.5%). Example 1: Pressure 35 kg / cm 2 To achieve the optimal result, zero voids and no risk of collapse are required.

[0108] 2. Line accuracy and cross-sectional shape analysis (Example 1 vs. Comparative Examples 2 and 6): Table 4. Analysis of Line Accuracy and Cross-sectional Shape

[0109] Comparative Example 2 uses a subtractive etching method to fabricate a 6oz (210μm) outer layer circuit. Due to the extremely thick copper layer, the etchant etched vertically downwards while also causing severe lateral etching, resulting in a much wider bottom linewidth than the top, forming a "trapezoidal" cross-section. The calculated EF was only 2.1.

[0110] According to electromagnetic theory, the current distribution on a trapezoidal cross-section is concentrated at the bottom two corners, forming localized hot spots. Joule heating calculation: The actual cross-sectional area S of a trapezoidal cross-section is 12%-15% smaller than that of a rectangular cross-section, therefore the resistance R is greater and the heat generation is higher. The measured temperature rise is 42.6℃ vs 28.5℃, a difference of 14.1℃. A decrease in cross-sectional area S leads to an increase in resistance R, and Joule heating becomes flat. Example 1 employs a semi-additive method, resulting in electroplated circuits with vertical sidewalls (EF=6.8). Subsequently, only a seed layer of <2μm needs to be flash-etched away, leaving almost no change in the circuit morphology. The rectangular cross-section exhibits uniform current density distribution, high effective cross-sectional area utilization, and significantly reduced temperature rise.

[0111] 3. Thermal conductivity and thermal expansion matching analysis (Example 1 vs. Comparative Examples 4 and 8): Table 5. Matching Analysis of Thermal Conductivity and Thermal Expansion

[0112] According to Fourier's law When the thermal conductivity k increases from 0.9 to 3.2 W / m·K, the heat flux density q at the same temperature difference increases by 3.5 times. The spherical alumina constructs a thermally conductive network within the resin, forming a continuous thermal conduction pathway.

[0113] Regarding thermal expansion matching: the CTE of copper is approximately 17 ppm / ℃, while the Z-axis CTE of pure epoxy resin is as high as 55-70 ppm / ℃. Adding Al2O3 filler (CTE approximately 7 ppm / ℃) effectively reduces the CTE of the resin system to approximately 20 ppm / ℃, resulting in better matching with copper. After 1000 temperature cycles, the ΔR / R0 of Comparative Example 4 / 8 reached 9.2%, while Example 1 only showed 3.8%, demonstrating that low CTE matching significantly improves thermomechanical reliability.

[0114] 4. Analysis of heat dissipation structure optimization (Example 1 vs. Examples 7 and 8): Table 6. Analysis of Heat Dissipation Structure Optimization

[0115] Example 7 constructs a low thermal resistance channel in the vertical direction by adding a heat dissipation via array (0.5 mm diameter, 1 mm spacing). The inner wall of the via is plated with copper (average copper thickness ≥ 20 μm) to conduct heat from the outer layer to the inner copper plane -10, increasing the heat flow by about 300% and reducing the temperature rise by 7.2 °C.

[0116] Example 8 increases the cross-sectional area by 20% by widening the line. According to the resistance formula R=ρL / S, the resistance is reduced by approximately 17%, Joule heating is reduced by approximately 17%, and temperature rise is reduced by 4.4℃. However, the increased line width occupies more wiring space, making it an effective solution when space permits.

[0117] 5. Comprehensive performance analysis for high current applications: Table 7. Summary of High Current Performance Tests

[0118] Analysis of high current failure mechanism: 1. Current congestion effect: The trapezoidal cross-section of the subtractive method causes current to concentrate at the bottom two corners, with local current density reaching 2-3 times the average value, forming hot spots. The rectangular cross-section of this invention distributes current evenly, eliminating current congestion.

[0119] 2. Void Insulation Effect: Voids (λ≈0.026W / m·K) block the heat conduction path, leading to heat accumulation. The pre-filling process of this invention eliminates voids and constructs low thermal resistance channels.

[0120] 3. Thermoelectric Positive Feedback: Increased temperature leads to increased resistivity of copper (the temperature coefficient of copper is approximately 0.0039 / ℃), and increased resistance further increases Joule heating, forming a positive feedback loop until burnout. This invention breaks the positive feedback loop by reducing the initial temperature rise and improving heat dissipation.

[0121] Based on the above performance analysis, the products of the present invention, represented by Examples 1 and 7, have the following characteristics: Eliminating interlayer voids: Vacuum prefilling achieves zero voids, eliminating the risk of delamination; High-precision thick copper circuit: Achieve EF≥6.5, rectangular cross-section, and line width / spacing ≤100μm / 100μm using the semi-additive method; High current low temperature rise: Temperature rise at 150A current ≤30℃, which is more than 40% lower than that of traditional processes; High thermal conductivity insulation layer: The thermal conductivity of the composite resin is 2.5-4.0 W / m·K, which is 3-5 times higher; High reliability: After 1000 cycles of high current cycling, ΔR / R0 ≤ 5%, no delamination or cracking.

[0122] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for integrally molding and fabricating a high-current, thick-copper, multilayer PCB circuit board, characterized in that, Includes the following steps: Step 1: Inner layer core board fabrication: Inner layer circuitry is formed on a thick copper clad laminate using a step-by-step etching method, with the etching factor controlled to be ≥5, and surface roughening treatment performed. Step 2, Integrated filling and insulation layer construction: Using vacuum printing technology, composite resin filling material is filled into the gaps of the inner layer circuit and cured to form a flat insulation layer that is coplanar with the surface of the copper circuit. Step 3: Construction of integrated conductive layer: On the flat insulating layer surface, chemically plate a seed layer, apply film, expose and develop to form circuit grooves, electroplat to thicken to the target copper thickness, remove film and flash etch to remove the seed layer to form the outer circuit layer; Step 4, Multi-layer Lamination and Integrated Lamination: Multiple core boards processed in steps one to three are laminated with composite resin bonding sheets and vacuum laminated using a stepped heating and pressurization process to achieve integrated molding.

2. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, The composite resin filler material in step two includes, by weight, 40-60 parts of bisphenol A epoxy resin, 10-20 parts of phenolic epoxy resin, 20-40 parts of spherical alumina filler, and 5-10 parts of latent curing agent.

3. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, The process parameters for vacuum printing in step two are: pressure 0.5-1.0MPa, vacuum degree ≤-0.095MPa, printing speed 30-80mm / s; the height difference between the surface of the cured flat insulating layer and the surface of the copper circuit is controlled within ±5μm.

4. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, In step three, the thickness of the chemically plated seed layer is 1-3 μm; the electroplating thickening adopts pulse electroplating with a pulse frequency of 500-2000 Hz, a duty cycle of 10%-30%, and a copper plating thickness of 105 μm to 420 μm.

5. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, The stepped heating and pressurization process described in step four includes: the first stage, heating to 80-110℃ and pressurizing to 10-20 kg / cm². 2 Hold the temperature for 10-20 minutes; in the second stage, raise the temperature to 120-150℃ and apply a pressure of 25-35 kg / cm². 2 Hold the temperature for 20-30 minutes; in the third stage, raise the temperature to 180-200℃ and apply a pressure of 30-40 kg / cm². 2 Keep warm for 60-90 minutes; vacuum degree throughout the process ≤-0.098MPa.

6. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, The step-by-step etching method is as follows: first, a semi-etch is performed to 60%-80% of the target copper thickness to form a pre-circuit pattern. After removing the resist mask, a final etching is performed to the target copper thickness.

7. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, In step one, the surface roughening treatment is a black oxidation or brown oxidation treatment, and the resulting oxide layer has a thickness of 0.5-2 μm.

8. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, The cross-sectional shape of the outer layer circuit is rectangular or inverted trapezoidal, with an etching factor ≥ 6.

0.

9. The method for integrated fabrication of high-current thick copper multilayer PCB circuit boards according to claim 1, characterized in that, The thermal conductivity of the composite resin filler material is ≥2.5 W / m·K.

10. A high-current thick copper multilayer PCB circuit board, manufactured by the integrated molding method for high-current thick copper multilayer PCB circuit boards according to any one of claims 1 to 9, characterized in that, Its current carrying capacity meets the following requirements: under a DC current of 150A, the line temperature rise is ≤30℃ and the hot spot temperature difference is ≤5℃; after 1000 cycles of a 150A high current, the resistance change rate is ≤5%, and there is no delamination or void expansion at the interface.

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