P-type passivated contact structure and method of making the same

Abstract

This invention provides a P-type passivated contact structure and its preparation method. The P-type passivated contact structure includes a silicon substrate, a first silicon oxide layer, a first polycrystalline silicon layer, a second polycrystalline silicon layer, and a hydrogen-containing dielectric layer. The silicon substrate has a diffusion region near the surface of the first silicon oxide layer. The surface of the first silicon oxide layer near the first polycrystalline silicon layer has a native pinhole defect structure generated by plasma bombardment. The first polycrystalline silicon layer is made of carbon-doped boron-containing polycrystalline silicon, wherein the boron and carbon doping concentrations gradually increase away from the first silicon oxide layer, and the thickness is greater than or equal to 8 nm. The second polycrystalline silicon layer is also made of carbon-doped boron-containing polycrystalline silicon, with a thickness greater than 10 nm. The interfacial silicon oxide surface of this invention has a high density of pinhole defects, and using carbon-doped boron-containing amorphous silicon as the source layer can reduce oxide layer defects caused by interfacial boron enrichment, achieving excellent surface passivation and selective carrier collection, and reducing surface recombination current density.

Description

Technical Field

[0001] This invention relates to the field of crystalline silicon solar cell technology, and more specifically, to a P-type passivated contact structure and its preparation method. Background Technology

[0002] The tunneling oxide passivated contact (TOPCon) structure is a novel passivated contact solar cell structure composed of nano-silicon oxide and doped polycrystalline silicon, designed to improve the passivation of crystalline silicon solar cells. Its core lies in achieving efficient passivation contact through a tunneling oxide layer and a doped polycrystalline silicon layer, thereby enhancing the photoelectric conversion efficiency of the cell.

[0003] TOPCon structures are divided into two types: N-type TOPCon structures based on phosphorus-doped polycrystalline silicon and P-type TOPCon structures based on boron-doped polycrystalline silicon. For tunneling oxide passivation contact technology, since the theoretical limiting efficiency of N-type monofacial TOPCon solar cells is lower than that of N-type bifacial TOPCon solar cells, bifacial TOPCon structures will have greater development potential in the future. The passivation quality of both the electron-collecting n-TOPCon structure and the hole-collecting p-TOPCon structure plays a crucial role.

[0004] Currently, n-TOPCon technology demonstrates superior performance and is widely used in high-efficiency crystalline silicon solar cells. However, the passivation quality of p-TOPCon obtained through various technological approaches is significantly inferior to that of n-TOPCon. Specifically, existing p-TOPCon fabrication techniques can be broadly categorized into three types: 1) Using low-pressure chemical vapor deposition (LPCVD) to prepare interfacial silicon oxide and intrinsic amorphous silicon, followed by boron diffusion to transform the intrinsic amorphous silicon into boron-doped polycrystalline silicon, thus obtaining the p-TOPCon structure. 2) Using LPCVD to prepare interfacial silicon oxide and boron-doped amorphous silicon, followed by high-temperature annealing to form the p-TOPCon structure. 3) Using plasma-enhanced chemical vapor deposition (PECVD) to prepare silicon oxide and boron-doped amorphous silicon, followed by high-temperature annealing to transform the amorphous silicon into boron-doped polycrystalline silicon, forming the p-TOPCon structure. Among these three techniques, the optimal recombination current density J of the p-TOPCon obtained so far is... 0,s Only 6-15 fA / cm 2 This is far from meeting the needs of developing the next generation of high-efficiency batteries. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is how to reduce the surface recombination current density of the P-type TOPCon structure.

[0006] To address the aforementioned technical problems, the first aspect of this invention provides a P-type passivated contact structure, comprising a silicon substrate, and a first silicon oxide layer, a first polysilicon layer, a second polysilicon layer, and a hydrogen-containing dielectric layer disposed on the silicon substrate. The silicon substrate has a diffusion region near the surface of the first silicon oxide layer. The surface of the first silicon oxide layer near the first polysilicon layer has a native pinhole defect structure generated by plasma bombardment. The thickness of the first silicon oxide layer is 1.5 nm to 3.5 nm. The material of the first polysilicon layer is carbon-doped boron-containing polysilicon, wherein the doping concentration of boron and carbon gradually increases along the direction away from the first silicon oxide layer. The thickness of the first polysilicon layer is greater than or equal to 8 nm. The material of the second polysilicon layer is carbon-doped boron-containing polysilicon, and the thickness of the second polysilicon layer is greater than 10 nm.

[0007] The interfacial silicon oxide surface of the present invention has a high density of pinhole defects, and uses boron-doped amorphous silicon containing carbon as the source layer, which can reduce the boron doping concentration in the interfacial silicon oxide, reduce interfacial defects, achieve excellent surface passivation and selective carrier collection, and reduce surface recombination current density.

[0008] Furthermore, the boron doping concentration in the diffusion region is less than 4 × 10⁻⁶. 19 cm -3 Boron activation concentration less than 1×10 19 cm -3 Carbon doping concentration greater than 1×10 18 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

[0009] Furthermore, the boron doping concentration of the first silicon oxide layer is less than 2 × 10⁻⁶. 20 cm -3 Carbon doping concentration greater than 5×10 18 cm -3 Hydrogen doping concentration greater than 5 × 10 19 cm -3 .

[0010] Furthermore, the boron activation concentration at the surface region of the first polycrystalline silicon layer near the first silicon oxide layer is less than 5 × 10⁻⁶. 19 cm -3 Carbon doping concentration greater than 1×10 18 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

[0011] Furthermore, the boron doping concentration in the second polycrystalline silicon layer is greater than 2 × 10⁻⁶. 20 cm -3Boron activation concentration greater than 5×10 19 cm -3 Carbon doping concentration greater than 1×10 20 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

[0012] Furthermore, the material of the hydrogen-containing dielectric layer is selected from one or more stacks of alumina, silicon nitride, silicon oxynitride, and silicon oxide.

[0013] Furthermore, the P-type passivated contact structure also includes a second silicon oxide layer disposed between the first polysilicon layer and the second polysilicon layer, the thickness of the second silicon oxide layer being 0.5 nm to 2.5 nm. The second silicon oxide layer acts as a diffusion barrier, which helps to reduce the thickness of the first polysilicon layer.

[0014] Furthermore, the boron doping concentration of the second silicon oxide layer is greater than 2 × 10⁻⁶. 20 cm -3 Carbon doping concentration greater than 1×10 20 cm -3 .

[0015] This invention also provides a method for preparing the above-mentioned P-type passivated contact structure, comprising the following steps:

[0016] A first silicon oxide layer was prepared on the surface of a silicon substrate using an ion-free bombardment oxidation method.

[0017] Plasma bombardment is used to treat the surface of the first silicon oxide layer, forming a pinhole defect structure.

[0018] An intrinsic amorphous silicon layer was prepared on the first silicon oxide layer using CVD.

[0019] The second silicon oxide layer is prepared on the intrinsic amorphous silicon layer; this step can be omitted.

[0020] A boron source layer was prepared on an intrinsic amorphous silicon layer or a second silicon oxide layer using PECVD. The material was carbon-containing boron-doped amorphous silicon.

[0021] High-temperature annealing is performed to diffuse carbon and boron elements, with a temperature range of 800–1100℃.

[0022] Preparation of hydrogen-containing dielectric layer;

[0023] Perform sintering, light infusion, or dark annealing.

[0024] The first silicon oxide layer is prepared by a two-step method. First, an initial silicon oxide layer is prepared by ion-free bombardment, which can suppress defect states caused by subsequent plasma bombardment. Then, the surface of the oxide layer is bombarded by plasma to generate native pinhole defect structures, which can avoid the accumulation of boron in the oxide layer and prevent silicon oxide defects.

[0025] Furthermore, the first silicon oxide layer is subjected to plasma surface treatment using PECVD.

[0026] Furthermore, the non-ion bombardment oxidation method is selected from one of the following: thermal oxidation, ozone oxidation, and wet chemical oxidation.

[0027] In summary, the present invention has the following advantages over the prior art:

[0028] (1) Significantly reduces the surface recombination current density of the P-type TOPCon structure and improves the surface passivation quality: The P-type passivation contact structure of the present invention has excellent surface passivation quality, and its single-sided saturation current J 0,s As low as 1.5–3 fA / cm 2 The highest implicit open-circuit voltage iV of the double-sided symmetrical passivation sheet oc It is 745–748 mV.

[0029] (2) Simple process flow: The polycrystalline silicon boron source layer can be directly used as part of the passivation contact structure, eliminating the need for operation steps such as etching the source layer.

[0030] (3) Reducing the contact resistivity of the P-type TOPCon structure: The second polysilicon layer has a very high activation concentration, and its contact resistivity with the metal can be lower than 1 mΩcm. 2 .

[0031] (4) The total thickness of the polysilicon layer in the P-type TOPCon structure is significantly reduced: the total thickness of the polysilicon layer using the technology of the present invention can be as low as 20 nm, while the total thickness of the polysilicon layer in the P-type TOPCon structure prepared by the prior art exceeds 200 nm.

[0032] (5) High cost-effectiveness: Compared with the traditional high temperature and high pressure LPCVD process, the present invention adopts PECVD technology, which has the advantages of low temperature deposition, light coating, simple etching, improved performance, reduced tube bursting, and improved yield, thereby reducing the overall cost of battery manufacturing process. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a P-type passivated contact structure according to a specific embodiment of the present invention.

[0034] Figure 2 This is a schematic diagram of another P-type passivated contact structure in a specific embodiment of the present invention.

[0035] Figure 3 This is a surface morphology diagram of the first silicon oxide layer after TAHM etching in Embodiment 1 of the present invention.

[0036] Figure 4 This is a surface morphology diagram of the first silicon oxide layer after TAHM etching in Comparative Example 1 of the present invention.

[0037] Figure 5 This is a comparison chart of the ECV curves of the P-type passivated contact structures prepared in the embodiments and comparative examples of the present invention.

[0038] Figure 6 This is a comparison diagram of boron-based SIMS with P-type passivated contact structures prepared in the embodiments and comparative examples of the present invention.

[0039] Figure 7 This is a comparison diagram of carbon and hydrogen SIMS in the P-type passivated contact structure prepared in the embodiments and comparative examples of the present invention.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1-Silicon substrate, 11-Diffusion region, 2-First silicon oxide layer, 3-First polycrystalline silicon layer, 4-Second silicon oxide layer, 5-Second polycrystalline silicon layer, 6-Hydrogen-containing dielectric layer. Detailed Implementation

[0042] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation methods and typical parameters of the present invention, and are not intended to limit the parameter range described in the present invention. Reasonable variations derived therefrom are still within the protection scope of the claims of the present invention.

[0043] It should be noted that the endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0044] A specific embodiment of the present invention provides a P-type passivated contact structure, a typical structure as follows: Figure 1As shown, the substrate includes a silicon substrate 1, on the surface of which a first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second polycrystalline silicon layer 5, and a hydrogen-containing dielectric layer 6 are sequentially disposed. A diffusion region 11 is present near the surface of the first silicon oxide layer 2 in the silicon substrate 1, wherein the near-surface region refers to a region with a depth less than 5 nm to 10 nm from the surface. The first polycrystalline silicon layer 3 is made of carbon-containing boron-doped polycrystalline silicon, and the second polycrystalline silicon layer 5 is also made of carbon-containing boron-doped polycrystalline silicon.

[0045] In a specific embodiment, the diffusion region 11 contains elements such as carbon, oxygen, and hydrogen, wherein the boron doping concentration is less than 4 × 10⁻⁶. 19 cm -3 Boron activation concentration less than 1×10 19 cm -3 Carbon doping concentration greater than 1×10 18 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

[0046] In a specific embodiment, the thickness of the first silicon oxide layer 2 is 1.5 nm to 3.5 nm, preferably 1.6 nm to 1.8 nm. Its surface near the first polycrystalline silicon layer 3 has a native pinhole defect structure generated by plasma bombardment. This structure can reduce the boron doping concentration in the interface silicon oxide and suppress the generation of boron defects in the interface silicon oxide region. Preferably, the pinhole defect density is greater than 1 × 10⁻⁶. 8 pcs / cm -2 The first silicon oxide layer 2 contains elements such as carbon, boron, and hydrogen, with a boron doping concentration of less than 2 × 10⁻⁶. 20 cm -3 Carbon doping concentration greater than 1×10 18 cm -3 Hydrogen doping concentration greater than 5 × 10 19 cm -3 .

[0047] In a specific embodiment, the thickness of the first polycrystalline silicon layer 3 is greater than or equal to 8 nm, and it contains elements such as carbon, oxygen, boron, and hydrogen. The doping concentrations of boron and carbon gradually increase along the direction away from the first silicon oxide layer 2. The boron activation concentration at the surface of the first polycrystalline silicon layer 3 near the first silicon oxide layer 2 is less than 5 × 10⁻⁶. 18 cm -3 The carbon doping concentration is greater than 1×10 18 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

[0048] In a specific embodiment, the thickness of the second polysilicon layer 5 is generally greater than 10 nm, wherein the boron and carbon doping concentrations are uniformly distributed, and the boron doping concentration of the second polysilicon layer 5 is greater than 2 × 10⁻⁶. 20 cm -3 Boron activation concentration greater than 5×10 19 cm -3 Carbon doping concentration greater than 1×10 20 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

[0049] It should be noted that the diffusion region 11, the first silicon oxide layer 2, the first polycrystalline silicon layer 3, and the second polycrystalline silicon layer 5 may all contain trace elements such as nitrogen and oxygen, which are introduced during the preparation process.

[0050] In a specific embodiment, the material of the hydrogen-containing dielectric layer 7 may be one or more stacks of alumina, silicon nitride, silicon oxynitride, and silicon oxide.

[0051] A typical method for preparing the above-mentioned P-type passivated contact structure includes the following steps:

[0052] (1) A first silicon oxide layer is prepared on the surface of a silicon substrate using an ion-free bombardment oxidation method. The ion-free bombardment oxidation method is selected from one of the following: thermal oxidation, ozone oxidation, and wet chemical oxidation.

[0053] (2) The first silicon oxide layer is surface-treated by plasma bombardment to form a pinhole defect structure. PECVD is preferably used for plasma surface treatment of the first silicon oxide layer; CO2 and N2O are preferably used as oxidizing gases, and H2, Ar, and N2 are used as auxiliary gases. O2, H2O, etc., can also be used as oxidizing gases, and CH4, NH3, HCl, etc., as auxiliary gases.

[0054] (3) An intrinsic amorphous silicon layer was prepared on the first silicon oxide layer by CVD.

[0055] (4) A boron source layer was prepared on the intrinsic amorphous silicon layer by PECVD. The material was carbon-containing boron-doped amorphous silicon.

[0056] (5) High-temperature annealing is carried out to diffuse carbon and boron elements. The typical temperature is 800-1100℃. A diffusion zone is formed on the surface of the silicon substrate, and amorphous silicon is transformed into polycrystalline silicon.

[0057] (6) Prepare a hydrogen-containing dielectric layer.

[0058] (7) Perform sintering, light infusion or dark annealing.

[0059] In other embodiments, the P-type passivated contact structure is as follows: Figure 2As shown, the substrate includes a silicon substrate 1, on the surface of which are sequentially disposed a first silicon oxide layer 2, a first polycrystalline silicon layer 3, a second silicon oxide layer 4, a second polycrystalline silicon layer 5, and a hydrogen-containing dielectric layer 6. A diffusion region 11 is present in the near-surface portion of the silicon substrate 1 adjacent to the first silicon oxide layer 2, wherein the near-surface portion refers to a region at a depth of 10–20 nm from the surface. The first polycrystalline silicon layer 3 is made of carbon-doped boron-doped polycrystalline silicon, and the second polycrystalline silicon layer 5 is also made of carbon-doped boron-doped polycrystalline silicon.

[0060] In a specific embodiment, the thickness of the second silicon oxide layer 4 is 0.5 nm to 2.5 nm. The second silicon oxide layer 4 contains elements such as boron, carbon, and hydrogen, wherein the carbon doping concentration is greater than 1 × 10⁻⁶. 20 cm -3 Commonly exceeding 1×10 21 cm -3 Boron doping concentration exceeding 2×10 20 cm -3 However, the activation concentration of boron is close to or slightly lower than that in the first diffusion region 11. It should be noted that the second silicon oxide layer 4 may contain trace elements such as nitrogen and oxygen, which are introduced during the preparation process.

[0061] In some embodiments, the second silicon oxide layer 4 and the second polycrystalline silicon layer 5 have a sublayer structure, which is typically a stacked structure of one or more silicon oxide films, intrinsic polycrystalline silicon and boron-doped polycrystalline silicon films (all polycrystalline silicon films may contain carbon). The thickness and composition of each silicon oxide film, intrinsic polycrystalline silicon and boron-doped polycrystalline silicon film in the sublayer structure may be the same or different.

[0062] A typical method for preparing the above-mentioned P-type passivated contact structure includes the following steps:

[0063] (1) A first silicon oxide layer is prepared on the surface of a silicon substrate by an ion-free bombardment oxidation method.

[0064] (2) The first silicon oxide layer is surface treated by plasma bombardment to form a pinhole defect structure.

[0065] (3) An intrinsic amorphous silicon layer was prepared on the first silicon oxide layer by CVD.

[0066] (4) A second silicon oxide layer is prepared on the intrinsic amorphous silicon layer.

[0067] (5) A boron source layer was prepared on the second silicon oxide layer by PECVD. The material was carbon-containing boron-doped amorphous silicon.

[0068] (6) High-temperature annealing is carried out to diffuse carbon and boron elements. The typical temperature is 800-1100℃. A diffusion zone is formed on the surface of the silicon substrate, and amorphous silicon is transformed into polycrystalline silicon.

[0069] (7) Prepare a hydrogen-containing dielectric layer.

[0070] (8) Perform sintering, light infusion or dark annealing.

[0071] The technical solution and effects of the present invention will be described below through specific embodiments.

[0072] Example 1

[0073] The fabrication of a double-sided P-type TOPCon passivation wafer follows these steps: An n-type double-sided planar single-crystal silicon substrate is prepared and subjected to RCA cleaning. A first silicon oxide layer is grown on both sides of the n-type silicon substrate using thermal oxidation at 400℃, resulting in an oxide layer thickness of approximately 1.4 nm. Subsequently, the surface of the first silicon oxide layer is subjected to plasma treatment using a mixture of CO2 and H2 gas via PECVD. The surface morphology of the first silicon oxide layer after TMAH etching following plasma treatment is shown below. Figure 3 As shown, it exhibits a high density of pinhole defects, with a density of approximately 2 × 10⁻⁶. 9 pcs / cm -2 The process continues with PECVD deposition of approximately 20 nm thick intrinsic amorphous silicon; followed by deposition of approximately 20 nm thick boron-doped carbon-containing amorphous silicon. After deposition, a high-temperature annealing process is performed at 900°C for 30 min in a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface is etched away using hydrofluoric acid. Alumina is then deposited using ALD and annealed at 490°C for 30 min in a nitrogen atmosphere. Silicon nitride is then deposited using PECVD, followed by annealing at 400°C for 60 min using a mixture of N2 and H2 gases. Finally, photoinjection is performed.

[0074] Example 2

[0075] The following steps were taken to fabricate a double-sided P-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer was grown on both sides of the n-type silicon substrate using thermal oxidation at 500℃, with a thickness of approximately 1.4 nm. Subsequently, the surface of the first silicon oxide layer was subjected to plasma treatment using PECVD with CO2 and H2 gases. An intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD; followed by the deposition of approximately 20 nm of carbon-doped boron-containing amorphous silicon. After deposition, a high-temperature annealing process was performed at 900℃ for 30 min using a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Aluminum oxide was then deposited using ALD and annealed at 490℃ for 30 min under a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400℃ for 60 min using a mixed gas of N2 and H2. Finally, photoinjection was performed.

[0076] Example 3

[0077] The following steps were taken to fabricate a double-sided P-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer was grown on both sides of the n-type silicon substrate using thermal oxidation at 600℃, with a thickness of approximately 1.4 nm. Subsequently, the surface of the first silicon oxide layer was subjected to plasma treatment using PECVD with a mixture of CO2 and H2 gas. An intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD; followed by a deposition of approximately 20 nm of carbon-doped boron-containing amorphous silicon. After deposition, a high-temperature annealing process was performed at 900℃ for 30 min using a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Aluminum oxide was then deposited using ALD and annealed at 490℃ for 30 min under a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400℃ for 60 min using a mixture of N2 and H2 gas. Finally, photoinjection was performed.

[0078] Example 4

[0079] The following steps were taken to fabricate a double-sided P-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer was grown on both sides of the n-type silicon substrate using thermal oxidation at 400℃, with a thickness of approximately 1.4 nm. Subsequently, the surface of the first silicon oxide layer was subjected to plasma treatment using PECVD with a mixture of CO2 and Ar gases. An intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD; followed by the deposition of approximately 20 nm of carbon-doped boron-containing amorphous silicon. After deposition, a high-temperature annealing process was performed at 900℃ for 30 min using a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Aluminum oxide was then deposited using ALD and annealed at 490℃ for 30 min under a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400℃ for 60 min using a mixture of N2 and H2 gases. Finally, photoinjection was performed.

[0080] Example 5

[0081] The following steps were taken to fabricate a double-sided P-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and RCA cleaned. A first silicon oxide layer was grown on both sides of the n-type silicon substrate using thermal oxidation at 400℃, with a thickness of approximately 1.4 nm. Subsequently, the surface of the first silicon oxide layer was subjected to plasma treatment using PECVD with a mixture of N2O and H2 gas. An intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD; followed by a deposition of approximately 20 nm of carbon-doped boron-containing amorphous silicon. After deposition, a high-temperature annealing process was performed at 900℃ for 30 min using a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Aluminum oxide was then deposited using ALD and annealed at 490℃ for 30 min under a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400℃ for 60 min using a mixture of N2 and H2 gas. Finally, photoinjection was performed.

[0082] Example 6

[0083] The following steps were taken to fabricate a double-sided P-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and RCA-cleaned. A first silicon oxide layer was grown on both sides of the n-type silicon substrate using thermal oxidation at 400℃, with a thickness of approximately 1.4 nm. Subsequently, the surface of the first silicon oxide layer was subjected to plasma treatment using PECVD with a mixture of N2O and Ar gases. An intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD; followed by a deposition of approximately 20 nm of carbon-doped boron-containing amorphous silicon. After deposition, a high-temperature annealing process was performed at 900℃ for 30 min using a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Aluminum oxide was then deposited using ALD and annealed at 490℃ for 30 min under a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400℃ for 60 min using a mixture of N2 and H2 gases. Finally, photoinjection was performed.

[0084] Comparative Example 1

[0085] The fabrication of a double-sided P-type TOPCon passivation wafer follows these steps: An n-type double-sided planar single-crystal silicon substrate is prepared and subjected to RCA cleaning. A first silicon oxide layer is grown on both sides of the n-type silicon substrate using thermal oxidation at 600℃, with a layer thickness of approximately 1.8 nm. The surface morphology of the first silicon oxide layer after TMAH etching is shown below. Figure 4As shown, the oxide layer is free of pinhole defects. An intrinsic amorphous silicon layer approximately 20 nm thick was deposited using PECVD; followed by a 20 nm thick layer of boron-doped carbon-containing amorphous silicon. After deposition, a high-temperature annealing process was performed at 900°C for 30 min in a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Alumina was then deposited using ALD and annealed at 490°C for 30 min in a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400°C for 60 min using a mixture of N2 and H2 gases. Finally, photoimplantation was performed.

[0086] Comparative Example 2

[0087] The following steps were taken to fabricate a double-sided P-type TOPCon passivation wafer: An n-type double-sided planar monocrystalline silicon substrate was prepared and RCA-cleaned. A first silicon oxide layer was grown on both sides of the n-type crystalline silicon substrate using thermal oxidation at 600℃, with a thickness of approximately 1.8 nm. An intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD; followed by the deposition of approximately 20 nm of carbon-free boron-doped amorphous silicon. After deposition, a high-temperature annealing process was performed at 900℃ for 30 min in a tube furnace to achieve crystallization of the amorphous silicon and diffusion of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Subsequently, aluminum oxide was deposited using ALD and annealed at 490℃ for 30 min under a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400℃ for 60 min using a mixture of N2 and H2 gases. Finally, photoinjection was performed.

[0088] Comparative Example 3

[0089] The following steps were taken to fabricate a double-sided P-type TOPCon passivation wafer: An n-type double-sided planar monocrystalline silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer was grown on both sides of the n-type crystalline silicon substrate using thermal oxidation at 600℃, with a thickness of approximately 1.8 nm. An intrinsic amorphous silicon layer with a thickness of approximately 5 nm was deposited using PECVD; followed by the deposition of approximately 20 nm of carbon-doped boron-containing amorphous silicon. After deposition, a high-temperature annealing process was performed at 900℃ for 30 min in a tube furnace to achieve crystallization of the amorphous silicon and diffusion of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid. Subsequently, aluminum oxide was deposited using ALD and annealed at 490℃ for 30 min under a nitrogen atmosphere. Silicon nitride was then deposited using PECVD, followed by annealing at 400℃ for 60 min using a mixture of N2 and H2 gases. Finally, photoinjection was performed.

[0090] Comparative Example 4

[0091] The fabrication of a double-sided P-type TOPCon passivation wafer follows these steps: An n-type double-sided planar monocrystalline silicon substrate is prepared and RCA-cleaned. A first silicon oxide layer, approximately 1.6 nm thick, is directly fabricated on both sides of the n-type crystalline silicon substrate using plasma-assisted oxidation. An intrinsic amorphous silicon layer approximately 8 nm thick is deposited using PECVD; followed by a 30 nm thick layer of carbon-doped boron-containing amorphous silicon. After deposition, a high-temperature annealing process is performed at 920 °C for 30 min using a tube furnace to achieve amorphous silicon crystallization and boron diffusion. After annealing, the oxide layer on the polycrystalline silicon surface is etched away using hydrofluoric acid. Aluminum oxide is then deposited using ALD and annealed at 490 °C for 30 min under a nitrogen atmosphere. Silicon nitride is then deposited using PECVD, followed by annealing at 400 °C for 60 min using a mixture of N2 and H2 gases. Finally, photoinjection is performed.

[0092] The boron activation concentration distribution of the P-type passivated contact structures prepared in Example 1 and Comparative Example 1 was tested using ECV, and the results are as follows: Figure 5 As shown, a distinct double activation peak appears near the first silicon oxide layer (interfacial silicon oxide in the figure) without plasma treatment. The double boron activation peak indicates that boron is enriched at the interface and boron defects are generated. The first silicon oxide layer after plasma treatment has a single activation peak, indicating that the process can suppress the generation of boron defects in the interfacial silicon oxide region.

[0093] The boron, hydrogen, and carbon doping concentration distributions of the P-type passivated contact structures prepared in Example 1 and Comparative Example 1 were tested using SIMS, and the results are as follows: Figure 6 and Figure 7 As shown, the interface silicon oxide surface has a high density of pinhole defects, which can reduce the boron doping concentration in the interface silicon oxide and thus suppress interface defects.

[0094] The passivation performance of the double-sided P-type TOPCon structure passivation sheets prepared in Examples 1-6 and Comparative Examples 1-4 was tested using Sinton. The results are shown in Table 1. The test results show that the technology of the present invention can significantly reduce the surface recombination current density of the P-type TOPCon structure and improve the passivation performance.

[0095] Table 1. Comparison of passivation performance of the double-sided P-type TOPCon structure in the embodiments and comparative examples.

[0096] sample <![CDATA[J 0,s (fA / cm 2 )]]> iVoc(mV) <![CDATA[ρ c (Ωcm 2 )]]> Example 1 1.5 748 1.2 Example 2 2.7 745 1.4 Example 3 2.2 746 1.9 Example 4 2.1 746 1.3 Example 5 1.8 747 1.4 Example 6 2.3 746 1.8 Comparative Example 1 6.0 735 1.8 Comparative Example 2 7.6 732 2.3 Comparative Example 3 8.1 730 2.2 Comparative Example 4 18.5 712 1.2

[0097] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A P-type passivated contact structure, characterized in that, The device includes a silicon substrate, and a first silicon oxide layer, a first polycrystalline silicon layer, a second polycrystalline silicon layer, and a hydrogen-containing dielectric layer disposed on the silicon substrate. The silicon substrate has a diffusion region near the surface of the first silicon oxide layer. The surface of the first silicon oxide layer near the first polycrystalline silicon layer has a native pinhole defect structure generated by plasma bombardment. The thickness of the first silicon oxide layer is 1.5 nm to 3.5 nm. The material of the first polycrystalline silicon layer is boron-doped polycrystalline silicon containing carbon, wherein the doping concentration of boron and carbon gradually increases along the direction away from the first silicon oxide layer. The thickness of the first polycrystalline silicon layer is greater than or equal to 8 nm. The material of the second polycrystalline silicon layer is boron-doped polycrystalline silicon containing carbon. The thickness of the second polycrystalline silicon layer is greater than 10 nm.

2. The P-type passivated contact structure according to claim 1, characterized in that, The boron doping concentration in the diffusion region is less than 4 × 10⁻⁶. 19 cm -3 Boron activation concentration less than 1×10 19 cm -3 Carbon doping concentration greater than 1×10 18 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

3. The P-type passivated contact structure according to claim 1, characterized in that, The boron doping concentration of the first silicon oxide layer is less than 2 × 10⁻⁶. 20 cm -3 Carbon doping concentration greater than 5×10 18 cm -3 Hydrogen doping concentration greater than 5 × 10 19 cm -3 .

4. The P-type passivated contact structure according to claim 1, characterized in that, The boron activation concentration at the surface of the first polysilicon layer near the first silicon oxide layer is less than 5 × 10⁻⁶. 19 cm -3 Carbon doping concentration greater than 1×10 18 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

5. The P-type passivated contact structure according to claim 1, characterized in that, The boron doping concentration in the second polycrystalline silicon layer is greater than 2 × 10⁻⁶. 20 cm -3 Boron activation concentration greater than 5×10 19 cm -3 Carbon doping concentration greater than 1×10 20 cm -3 Hydrogen doping concentration greater than 1×10 19 cm -3 .

6. The P-type passivated contact structure according to claim 1, characterized in that, The material of the hydrogen-containing dielectric layer is selected from one or more stacks of alumina, silicon nitride, silicon oxynitride, and silicon oxide.

7. The P-type passivated contact structure according to any one of claims 1-6, characterized in that, It also includes a second silicon oxide layer disposed between the first polysilicon layer and the second polysilicon layer, the thickness of the second silicon oxide layer being 0.5 nm to 2.5 nm.

8. The P-type passivated contact structure according to claim 7, characterized in that, The boron doping concentration of the second silicon oxide layer is greater than 2 × 10⁻⁶. 20 cm -3 Carbon doping concentration greater than 1×10 20 cm -3 .

9. A method for preparing a P-type passivated contact structure as described in any one of claims 1-8, characterized in that, Includes the following steps: A first silicon oxide layer was prepared on the surface of a silicon substrate using an ion-free bombardment oxidation method. Plasma bombardment is used to treat the surface of the first silicon oxide layer, forming a pinhole defect structure. An intrinsic amorphous silicon layer was prepared on the first silicon oxide layer using CVD. The second silicon oxide layer is prepared on the intrinsic amorphous silicon layer; this step can be omitted. A boron source layer was prepared on an intrinsic amorphous silicon layer or a second silicon oxide layer using PECVD. The material was carbon-containing boron-doped amorphous silicon. High-temperature annealing is performed to diffuse carbon and boron elements, with a temperature range of 800°C. ～ 1100℃; Preparation of hydrogen-containing dielectric layer; Perform sintering, light infusion, or dark annealing.

10. The method for preparing the P-type passivated contact structure according to claim 9, characterized in that, The first silicon oxide layer was subjected to plasma surface treatment using PECVD.

11. The method for preparing the P-type passivated contact structure according to claim 9, characterized in that, The non-ion bombardment oxidation method is selected from one of the following: thermal oxidation, ozone oxidation, and wet chemical oxidation.

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