Display device

Abstract

One embodiment of this specification discloses a display device comprising: a substrate including a display area and a non-display area; driving wiring extending from the display area to the non-display area; a planarization layer disposed above the driving wiring; and touch wiring disposed on the planarization layer. The planarization layer includes trenches extending in one direction, and the trenches do not overlap with the touch wirings in a plane.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0189725, filed on December 18, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The implementation plan involves a display device that can prevent moisture penetration. Background Technology

[0004] Electroluminescent display devices can be classified into inorganic light-emitting display devices and organic light-emitting display devices based on the material of the light-emitting layer. Active-matrix organic light-emitting display devices can include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and have advantages such as fast response speed, high luminous efficiency, high brightness, and wide viewing angle. Organic light-emitting display devices can include pixels, each having an OLED (organic light-emitting diode) formed therein. Organic light-emitting display devices can have fast response speed, excellent luminous efficiency, brightness, and viewing angle, and can have excellent contrast and color reproduction because they can represent black grayscale with pure black.

[0005] Such a display device may include a touch sensor that detects whether a user touches the device and detects the coordinates of the touch. The touch sensor may detect the presence of a touch and its coordinates based on changes in capacitance formed at a plurality of touch electrodes. Summary of the Invention

[0006] Display devices have the following problem: the pads lift up in high temperature and high humidity environments, allowing moisture to seep into the display area.

[0007] This manual provides a display device that prevents moisture penetration.

[0008] The problems to be solved in this specification are not limited to those described above, and other problems not mentioned will be clearly understood by those skilled in the art based on the following description.

[0009] A display device according to one or more embodiments of this specification may include: a substrate including a display area and a non-display area; driving wiring extending from the display area to the non-display area; a planarization layer disposed on the driving wiring; and touch wiring disposed on the planarization layer, wherein the planarization layer includes trenches extending in one direction and the trenches do not overlap with the touch wirings in a plane.

[0010] Another embodiment of the present invention provides a display device, comprising: a substrate including a display area and a non-display area; driving wiring extending from the display area to the non-display area; a planarization layer disposed on the driving wiring; and touch wiring including a first touch wiring extending in the display area and a second touch wiring extending in the non-display area, the planarization layer including trenches or openings, and wherein the trenches or openings do not overlap with the first touch wiring in the vertical direction in the display area.

[0011] Another embodiment of the present invention provides a display device, comprising: a substrate including a display area and a non-display area; a first wiring extending from the display area to the non-display area; a planarization layer disposed on the first wiring; and a second wiring disposed on the planarization layer, wherein the planarization layer includes a trench exposing a layer that contacts the planarization layer from below, and the second wiring located in the display area is not located directly above the trench.

[0012] The display device according to one or more embodiments of this specification can prevent moisture from penetrating into the display area even when the pads are warped. Therefore, the lifespan of the display device can be improved, and low-power operation can be achieved.

[0013] The effects of this specification are not limited to those described above, and other effects not mentioned below will be apparent to those skilled in the art to which the technical concept of this specification pertains. Attached Figure Description

[0014] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a conceptual diagram of a display device according to one embodiment of this specification;

[0016] Figure 2 This is a circuit diagram of a display device according to one embodiment of this specification;

[0017] Figure 3 This is a cross-sectional view of pixels according to one embodiment of this specification;

[0018] Figure 4 This is an enlarged view of a portion of the non-display area according to one embodiment of this specification;

[0019] Figure 5 A diagram illustrating the opening region of the planarization layer according to one embodiment of this specification;

[0020] Figure 6 For along Figure 4 A cross-sectional view taken by line A-A';

[0021] Figure 7 For along Figure 4 A cross-sectional view taken from line B-B';

[0022] Figure 8 This is a cross-sectional view of a display device according to one embodiment of this specification;

[0023] Figure 9 A diagram illustrating an opening formed in a planarization layer according to one embodiment of this specification;

[0024] Figure 10 For along Figure 9 A cross-sectional view taken from line C-C'; and

[0025] Figure 11 This is a cross-sectional view of a display device according to another embodiment of this specification. Detailed Implementation

[0026] The advantages and features of this specification, as well as methods for implementing them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed herein, but can be implemented in a wide variety of different forms; rather, these embodiments are provided to ensure the completeness of the disclosure and to enable those skilled in the art to fully understand the scope of this specification.

[0027] The shapes, dimensions, scales, angles, quantities, etc., of the elements shown in the accompanying drawings to illustrate embodiments of this specification are illustrative only and not intended to be limiting. Throughout the description, the same reference numerals may denote the same components. Furthermore, detailed descriptions of relevant known technologies may be omitted in describing this specification to avoid obscuring its essence. Terms such as “comprising,” “including,” “having,” or “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise specifically stated, references to singular nouns of components include the plural of that noun.

[0028] When interpreting components, they are interpreted as including a range of errors, even if not explicitly stated otherwise.

[0029] When describing positional relationships, phrases such as "on top of," "above," "below," or "adjacent to" describe the positional relationship between two components. Unless "immediately next to" or "directly" is used, one or more other components may be positioned between the two components.

[0030] When describing temporal relationships, phrases like "after," "following," "following," or "before" describe preceding or following relationships in time. Unless "immediately following" or "directly" is used, such relationships may not be continuous.

[0031] The terms "first," "second," etc., are used to describe a wide variety of components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the "first component" mentioned below can refer to the "second component."

[0032] Terms such as first, second, A, B, (a), or (b) may be used to describe elements of embodiments of this specification. Such terms are intended only to distinguish one component from another and are not intended to limit the nature, order, sequence, or number of such components. When a component is described as “connected,” “linked,” or “attached” to another component, it should be understood that the component may be directly connected or attached to the other component, but without specific description, other components may also be “inserted” between indirectly connected or attached components.

[0033] It should be understood that the term "at least one" includes all possible combinations of one or more related components. For example, "at least one of the first, second, and third components" can be understood to include not only the first, second, or third component, but also any combination of two or more of the first, second, and third components.

[0034] Each of the features of the various implementation schemes described herein may be connected or combined with each other, either wholly or in part, and may be technically interlocked and operated in a variety of ways, and each of the implementation schemes may be performed independently or in combination with each other.

[0035] The embodiments described herein are illustrated below with reference to the accompanying drawings and examples. The dimensions of the components shown in the drawings are for illustrative purposes only and may not be proportional to the actual components; the actual dimensions are not limited to those shown in the drawings.

[0036] Reference Figure 1 The display device according to this embodiment may include: a display panel DP having a plurality of data lines and a plurality of gate lines thereon and a plurality of pixels P thereon; a data driver 20 connected to the display panel DP and driving the plurality of data lines; a gate driver 30 driving the plurality of gate lines; and a timing controller 10.

[0037] The display panel DP can be a rectangular panel having length in the X-axis direction (or a first direction), width in the Y-axis direction (or a second direction), and thickness in the Z-axis direction (or a third direction), but is not limited thereto. For example, the display panel DP can be a deformed panel in which at least a portion is curved or elliptical. In addition, the display panel DP can be composed of a plurality of physically separated sub-panels.

[0038] The display area DA of the display panel DP includes a pixel array for displaying the input image. The pixel array includes a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixels P arranged in a matrix. The display panel DP may also include power wiring commonly connected to the plurality of pixels P. The power wiring may be commonly connected to pixel circuitry to supply the voltage required to drive the pixels.

[0039] To achieve color, each of the plurality of pixels P can be divided into red sub-pixels, green sub-pixels, and blue sub-pixels. Each of the plurality of pixels may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element can be implemented as an organic light-emitting element such as an OLED or an inorganic light-emitting element such as a micro LED (light-emitting diode), but is not limited thereto. Each pixel circuit can be connected to data lines, gate lines, and power supply wiring. In the following text, a pixel can be interpreted as a sub-pixel.

[0040] The data driver 20 receives pixel data of the input image as a digital signal from the timing controller 10 and outputs a data voltage. The data driver 20 can receive a gamma reference voltage and generate gamma compensation voltages for each grayscale level through a voltage divider circuit. The gamma compensation voltages for each grayscale level can be supplied to a digital-to-analog converter (hereinafter referred to as "DAC") located in each channel of the data driver 20.

[0041] The data driver 20 samples and latches the digital data received from the timing controller 10, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage of the pixel data.

[0042] The gate driver 30 can be formed on the display panel DP together with the circuit elements and wiring of the display area DA. The gate driver 30 can be disposed in at least one of the non-display areas NA on the left and right sides outside the display area DA in the display panel DP, or at least a portion thereof can be disposed within the display area DA.

[0043] The gate driver 30 can be disposed in the non-display areas NA on both sides of the display panel DP, with the display area DA of the display panel DP located therebetween, so as to supply gate pulses to the gate lines from both sides in a double-fed manner. In another embodiment, the gate driver 30 can be disposed on at least one of the left and right non-display areas NA of the display panel DP, so as to supply gate signals to the gate lines in a single-fed manner. The gate driver 30 sequentially outputs gate signal pulses to the gate lines under the control of the timing controller 10. The gate driver 30 can sequentially supply signals to the gate lines by shifting the gate signal pulses using a shift register or an edge-triggered flip-flop.

[0044] The touch sensing unit 50 supplies a drive signal to the first touch electrode TE1 and detects a sensing signal from the second touch electrode TE2. Based on this, it can sense the presence and / or location of a touch (touch coordinates). The touch sensing unit 50 can be implemented as one or two or more components (e.g., an integrated circuit) and can be implemented separately from the data driver 20. However, the embodiments described in this specification are not limited thereto. The data driver 20 and the touch sensing unit 50 can be implemented as a single integrated circuit.

[0045] The timing controller 10 receives digital video data of the input image from the host system and timing signals synchronized with the data. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc. Since the vertical and horizontal periods can be determined by counting the data enable signals, the vertical and horizontal synchronization signals can be omitted. The horizontal synchronization signal and the data enable signal have a period of one horizontal period (1H).

[0046] The timing controller 10 can generate data timing control signals for controlling the operation timing of the data driver 20 and gate timing control signals for controlling the operation timing of the gate driver 30, based on the timing signals received from the host system.

[0047] The data driver 20 and touch sensor 50 can be connected to the bonding pads of the display panel DP via a tape-automated bonding (TAB) method or a chip-on-glass (COG) method. Alternatively, the data driver 20 and touch sensor 50 can be directly disposed on the display panel DP. Alternatively, the data driver 20 and touch sensor 50 can be integrated and disposed on the display panel DP. Furthermore, each integrated circuit can be implemented via a chip-on-film (COF) method. In this case, the integrated circuits acting as the data driver 20 and touch sensor 50 are mounted on a flexible film, wherein one end of the flexible film can be bonded to the source printed circuit board 12, and the other end can be bonded to the display panel DP.

[0048] The source printed circuit board 12 can be located around the display panel DP and can be connected to the control printed circuit board 11 via a flexible flat cable (FFC) 13. The source printed circuit board 12 can receive and process the voltages and signals used to drive the display panel DP from the control printed circuit board 11.

[0049] A timing controller 10 is mounted on a control printed circuit board 11. A power supply 40 may also be mounted on the control printed circuit board 11, which supplies various voltages or currents to the display panel DP, data driver 20, gate driver 30, etc., or controls the various voltages or currents to be supplied.

[0050] The drive wiring SL can have power lines PL (e.g., low-potential voltage lines and high-potential voltage lines) located at the edge of the non-display area NA and data lines DL located in the central part. The power lines PL and data lines DL do not need to overlap and can be spaced apart from each other.

[0051] The touch wiring TL can connect to the touch electrodes TE1 and TE2 of the display area DA and can extend to the non-display area NA. In the non-display area NA, the touch wiring TL can be positioned on the power wiring PL. Therefore, a portion of the touch wiring TL can overlap with the power wiring PL. In this document, overlap can mean being configured to overlap in the thickness direction (or Z-axis direction) of the panel. The touch wiring TL can also be configured not to overlap with the data wiring DL.

[0052] Reference Figure 2 and Figure 3Each pixel driving circuit DC can supply a driving current corresponding to the data signal to the light-emitting element 300 of each pixel P during one frame, based on the gate signal. For example, the pixel driving circuit DC of each pixel P may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. However, the embodiments described in this specification are not limited thereto. For example, the pixel driving circuit may include three or more thin-film transistors.

[0053] Reference Figure 2 and Figure 3 The substrate 100 may contain an insulating material. For example, the substrate 100 may contain glass or plastic.

[0054] Each pixel P's light-emitting element 300 can emit light representing a specific color. For example, each pixel P's light-emitting element 300 may include a first electrode 310, a light-emitting layer 320, and a second electrode 330 sequentially stacked on the substrate 100.

[0055] The first electrode 310 may comprise a conductive material. The first electrode 310 may comprise a material with high reflectivity. For example, the first electrode 310 may comprise metals such as aluminum (Al) and silver (Ag). The first electrode 310 may have a multilayer structure. For example, the first electrode 310 may have a structure in which reflective electrodes made of metal are positioned between transparent electrodes made of transparent conductive materials (e.g., ITO and IZO).

[0056] The light-emitting layer 320 can generate light with a brightness corresponding to the voltage difference between the first electrode 310 and the second electrode 330. For example, the light-emitting layer 320 may include an emission material layer (EML) containing a light-emitting material. The light-emitting material may include organic materials, inorganic materials, or mixed materials. For example, the display device according to the embodiments of this specification may be an organic light-emitting display device containing an organic light-emitting material.

[0057] The light-emitting layer 320 may have a multilayer structure. For example, the light-emitting layer 320 may include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0058] The second electrode 330 may comprise a conductive material. The second electrode 330 may comprise a different material than the first electrode 310. The transmittance of the second electrode 330 may be greater than that of the first electrode 310. For example, the second electrode 330 may be a transparent electrode made of a transparent conductive material such as ITO and IZO. Therefore, in the display device according to the embodiment of this specification, light generated by the light-emitting layer 320 can be emitted to the outside through the second electrode 330.

[0059] The second thin-film transistor T2 may include a second semiconductor pattern 221, a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. The second thin-film transistor T2 can generate a drive current corresponding to a data signal. For example, the second thin-film transistor T2 can be a driving thin-film transistor.

[0060] The second semiconductor pattern 221 may comprise a semiconductor material. For example, the second semiconductor pattern 221 may comprise an oxide semiconductor, such as amorphous silicon (a-Si), polycrystalline silicon (Poly-Si), or IGZO.

[0061] The second gate electrode 223 may contain a conductive material. For example, the second gate electrode 223 may contain metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0062] The second gate electrode 223 may be located on the second semiconductor pattern 221. The second gate electrode 223 may be insulated from the second semiconductor pattern 221.

[0063] The storage capacitor Cst can hold the signal applied to the second gate electrode 223 of the second thin-film transistor T2 during one frame. For example, the storage capacitor Cst can be electrically connected to the second thin-film transistor T2. The storage capacitor Cst can have a stacked structure of capacitor electrodes 231 and 232. For example, the storage capacitor Cst can include a first capacitor electrode 231 and a second capacitor electrode 232. At least one of the capacitor electrodes 231 and 232 can be formed using the same forming process as the first thin-film transistor T1 and the second thin-film transistor T2. For example, the first capacitor electrode 231 can contain the same material as the second gate electrode 223. The second capacitor electrode 232 can contain the same material as the second drain electrode 225 and the second source electrode 227. The second capacitor electrode 232 can be located on the same layer as the second drain electrode 225 and the second source electrode 227. The second capacitor electrode 232 can also be located on a different layer than the second drain electrode 225 and the second source electrode 227.

[0064] A plurality of insulating layers 110, 120, 130, 140, 150, 160, and 180 may be disposed above the substrate 100 to prevent unnecessary electrical connections within each pixel P. For example, a buffer layer 110, a gate insulating layer 120, a lower interlayer insulating layer 130, an upper interlayer insulating layer 140, a device protection layer 150, a planarization layer 160, and a dam layer 180 may be disposed on the substrate 100. The planarization layer 160 may be formed by a lower planarization layer 161 and an upper planarization layer 162, but the embodiments described herein are not limited thereto. For example, the planarization layer 160 may be formed by a single layer.

[0065] The buffer layer 110 may be close to the substrate 100. The buffer layer 110 can prevent contamination caused by the substrate 100 during the formation process of the pixel driving circuit located in each pixel P. For example, the upper surface of the substrate 100 facing the pixel driving circuit of each pixel P can be completely covered by the buffer layer 110.

[0066] The buffer layer 110 may contain an insulating material. For example, the buffer layer 110 may contain an inorganic insulating material, such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer layer 110 may have a multilayer structure. For example, the buffer layer 110 may have a stacked structure of inorganic insulating layers made of silicon oxide (SiOx) and inorganic insulating layers made of silicon nitride (SiNx).

[0067] The gate insulating layer 120 may be located on the buffer layer 110. The gate insulating layer 120 can insulate the semiconductor patterns of each thin-film transistor T1 and T2 from their gate electrodes. The second gate electrode 223 of each pixel P may be located on the gate insulating layer 120. The first capacitor electrode 231 of each pixel P may be located on the gate insulating layer 120. The gate insulating layer 120 may contain an insulating material. For example, the gate insulating layer 120 may contain an inorganic insulating material, such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0068] The lower interlayer insulating layer 130 and the upper interlayer insulating layer 140 can insulate the drain and source electrodes of each thin film transistor T1 and T2 relative to the gate electrodes of the thin film transistor T1 and T2.

[0069] The upper interlayer insulating layer 140 may be located on the lower interlayer insulating layer 130. For example, the lower interlayer insulating layer 130 may cover the second gate electrode 223 of each pixel P.

[0070] The lower interlayer insulating layer 130 and the upper interlayer insulating layer 140 may contain insulating materials. For example, the lower interlayer insulating layer 130 and the upper interlayer insulating layer 140 may contain inorganic insulating materials, such as silicon oxide (SiOx) and silicon nitride (SiNx). The second capacitor electrode 232 of pixel P may be located between the lower interlayer insulating layer 130 and the upper interlayer insulating layer 140.

[0071] The lower interlayer insulation layer 130 and / or the upper interlayer insulation layer 140 can be defined as a first insulation layer. The lower interlayer insulation layer 130 and / or the upper interlayer insulation layer 140 can be formed as a single interlayer insulation layer.

[0072] The lower planarization layer 161 and the upper planarization layer 162 can be sequentially stacked on the upper interlayer insulating layer 140. For example, the lower planarization layer 161 can be located between the device protection layer 150 and the upper planarization layer 162. The lower planarization layer 161 and the upper planarization layer 162 can remove the steps caused by the pixel driving circuit DC of each pixel P. For example, the upper plane of the upper planarization layer 162 facing away from the substrate 100 can be a flat plane.

[0073] The lower planarization layer 161 and the upper planarization layer 162 may contain insulating materials. For example, the lower planarization layer 161 and the upper planarization layer 162 may contain organic insulating materials. The upper planarization layer 162 may contain a different material than the lower planarization layer 161. In this specification, the planarization layer is described as being divided into a lower planarization layer 161 and an upper planarization layer 162, but is not limited thereto. For example, the planarization layer 160 may be formed from a single layer.

[0074] The light-emitting element 300 of each pixel P can be located on the upper planarization layer 162. For example, the first electrode 310, the light-emitting layer 320, and the second electrode 330 of each pixel P can be sequentially stacked on the upper surface of the upper planarization layer 162 located within the pixel P. The first electrode 310 of each pixel P can be in direct contact with the upper surface of the upper planarization layer 162.

[0075] The intermediate electrode 311 may be located between the lower planarization layer 161 and the upper planarization layer 162. The intermediate electrode 311 may contain a conductive material. For example, the intermediate electrode 311 may contain metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first electrode 310 of each pixel P may be electrically connected to the second source electrode 227 of that pixel P through one of the intermediate electrodes 311. For example, each intermediate electrode 311 may pass through the lower planarization layer 161 of each pixel P and directly contact the second source electrode 227 of that pixel P, and the first electrode 310 of each pixel P may pass through the upper planarization layer 162 of that pixel P and directly contact one of the intermediate electrodes 311.

[0076] The dam layer 180 may be located on the upper planarization layer 162. The dam layer 180 may define a light-emitting region within each pixel P. For example, the dam layer 180 may cover the edge of the first electrode 310 located within each pixel P. The light-emitting layer 320 and the second electrode 330 of each pixel P may be sequentially stacked on the portion of the first electrode 310 exposed by the dam layer 180. The dam layer 180 may contain an insulating material. For example, the dam layer 180 may contain an organic insulating material. The dam layer 180 may contain a material different from the upper planarization layer 162.

[0077] At least a portion of the light-emitting layer 320 of each pixel P may extend outside the pixel P. For example, at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) located within each pixel P may extend onto the embankment layer 180. At least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) located within each pixel P may be formed simultaneously with a corresponding layer located within an adjacent pixel P. For example, at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) may be formed over the entire surface of the substrate 100. Therefore, in the display device according to the embodiments of this specification, process efficiency can be improved.

[0078] The encapsulation portion 400 can be located on the light-emitting element 300 of each pixel P. The encapsulation portion 400 can prevent damage to the light-emitting element 300 caused by external moisture and impact. For example, the light-emitting element 300 of each pixel P can be completely covered by the encapsulation portion 400.

[0079] The encapsulation portion 400 may have a multi-layer structure. For example, the encapsulation portion 400 may include a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may contain insulating material.

[0080] The second encapsulation layer 420 may contain a different material than the first encapsulation layer 410 and the third encapsulation layer 430. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may contain inorganic insulating materials, while the second encapsulation layer 420 may contain organic insulating materials. Therefore, in the display device according to the embodiment of this specification, damage to the light-emitting element 300 caused by external moisture and impact can be effectively prevented. Steps caused by the light-emitting element 300 can be removed by the second encapsulation layer 420. For example, in the pixel area, the upper surface of the encapsulation portion 400 facing away from the substrate 100 can be a flat plane.

[0081] A touch sensing layer 500, including a plurality of touch electrodes TE, can be disposed on a package portion 400. The plurality of touch electrodes TE can be electrically connected to a bridging electrode BE. Specifically, the touch sensing layer 500 may include a touch buffer layer 510 disposed on the package portion 400, a bridging electrode BE disposed on the touch buffer layer 510, a touch interlayer insulating layer 520 disposed above the touch buffer layer 510 and the bridging electrode BE, and touch electrodes TE disposed on the touch interlayer insulating layer 520. In this case, the bridging electrode BE and the touch electrode TE may contain the same material.

[0082] The touch buffer layer 510 can prevent chemical solutions (such as developers or etchants) used in the manufacturing process of the touch electrode, or external moisture or foreign matter, from penetrating into the light-emitting element. The touch buffer layer 510 can be defined as a second insulating layer.

[0083] The bridging electrode BE is arranged in the display area DA and is electrically connected to the touch electrode TE on the touch interlayer insulating layer 520.

[0084] An interlayer insulating layer 520 can be disposed on the touch buffer layer 510 to cover the bridging electrode BE, thereby insulating the bridging electrode BE and the touch electrode TE. A portion of the touch electrode TE can be connected to the bridging electrode BE through a via. Furthermore, the interlayer insulating layer 520 can be disposed between the bridging electrodes BE to insulate them from each other.

[0085] The touch buffer layer 510 and / or the touch interlayer insulating layer 520 may be made of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0086] A touch protective layer 530 may be disposed on the touch electrode. The touch protective layer 530 may be used to prevent oxidation, corrosion or damage to the touch electrode and touch wiring. The touch protective layer 530 may be made of at least one or more of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiOx), or organic insulating materials such as benzocyclobutene (BCB), acrylic resins, epoxy resins, phenolic resins, polyamide resins or polyimide resins, but is not limited thereto.

[0087] Figure 4 This is a partial enlarged view of a display device according to one embodiment of this specification. Figure 5 A diagram illustrating the opening region of the planarization layer according to one embodiment of this specification. Figure 6 For along Figure 4 A cross-sectional view taken from line A-A'. Figure 7 For along Figure 4 The cross-sectional view taken by line B-B'.

[0088] Reference Figures 4 to 6 The power supply line PL can extend from the display area DA to the pad portion PD1. The linewidth W1 of the power supply line PL can be relatively wider than the linewidths of the data line DL, gate line GL, and touch line TL. Therefore, when the power supply line PL with a wide linewidth may occupy a large area of ​​the pad portion PD1, the area of ​​the data line DL, gate line GL, and touch line TL connected to the pad portion PD1 may be reduced. With this in mind, the power supply line PL can include a pad connection portion PC1 with a relatively narrow linewidth W2. Since the pad connection portion PC1 of the power supply line PL has a relatively narrow linewidth W2, a separation region SA can be created between multiple pad connection portions PC1. The gate line GL and touch line TL can extend to the separation region SA to connect to the pad portion PD1.

[0089] The planarization layer 160 can be disposed on the power lines PL and data lines DL. The planarization layer 160 can prevent the mask used to form the touch sensing layer on the upper part of the display panel from being damaged due to contact with the power lines PL, etc.

[0090] The planarization layer 160, when formed in the display area DA, can also be formed in a portion of the non-display area NA. For example, the planarization layer 160 can be formed in the area of ​​the non-display area NA where power lines PL and data lines DL are arranged, and may not be formed in the remaining non-display area NA. The planarization layer 160 may not be arranged in the partition area SA between the pad connection portions PC1 of the power lines PL.

[0091] The planarization layer 160 may include an opening region 163 corresponding to the partition region SA between the pad connection portions PC1 of the power wiring PL. This is because if the planarization layer 160 were also disposed within the partition region SA between the pad connection portions PC1 of the power wiring PL, there would be no space for the gate wiring GL extending below the power wiring PL to connect to the pad portion PD1. The gate wiring GL is exposed through the partition region SA and can connect to the pad portion PD1. The opening region 163 may be defined as an aperture, an open region, or a fourth aperture.

[0092] The touch wiring TL can extend from the display area DA to above the power wiring PL and the planarization layer 160. The touch wiring TL and the power wiring PL can be electrically insulated from each other by the planarization layer 160. The end of the touch wiring TL can further extend to a position that does not overlap with the power wiring PL for connection to the pad portion PD1, and can be connected to the pad portion PD1. That is, the touch wiring TL can include a first touch wiring TL1 extending from the display area DA to above the power wiring PL and a second touch wiring TL2 extending to a position that does not overlap with the power wiring PL and is connected to the pad portion PD1.

[0093] The gate wiring GL can extend from the gate driver and can extend below the power wiring PL. The end of the gate wiring GL can further extend to a position that does not overlap with the power wiring PL for connection to the pad portion PD1, and can be connected to the pad portion PD1. That is, the gate wiring GL can include a first gate wiring GL1 extending from the display area below the power wiring PL and a second gate wiring GL2 extending to an opening region 163 that does not overlap with the power wiring PL and connecting to the pad portion PD1. The first gate wiring GL1 extending below the power wiring PL is indicated by a dashed line. The first gate wiring GL1 extending below the power wiring PL can be a connection wiring arranged in different layers.

[0094] According to one embodiment, since the touch wiring TL extends above the power wiring PL and the gate wiring GL extends below the power wiring PL, a large number of wirings can be connected to the pad portion PD1. However, the embodiments described in this specification are not limited to this. For example, the touch wiring TL may extend below the power wiring PL, and the gate wiring GL may extend above the power wiring PL. For example, a portion of the gate wiring GL may extend above the power wiring PL, and a portion of the gate wiring GL may extend below the power wiring PL. In addition to the gate wiring GL, a variety of wirings may extend below or above the power wiring PL and connect to the pad portion PD1.

[0095] The planarization layer 160 may include trenches CT1 to prevent moisture penetration. The trenches CT1 may be formed extending in a first direction (X-axis direction) in a non-display area NA between the display area DA and the pad portion PD1. The trenches CT1 may be disposed between a plurality of power lines PL or touch lines TL. The trenches CT1 may be defined as openings, apertures, or open areas.

[0096] The trench CT1 can be arranged in the area between the plurality of opening regions 163 formed in the planarization layer 160. Since the planarization layer 160 is an organic film, it may be relatively susceptible to moisture. According to this embodiment, since the planarization layer 160 is removed from the trench CT1 and the opening regions 163, moisture can be prevented from penetrating into the display area DA even when the pad portion PD1 is lifted.

[0097] According to this embodiment, a plurality of trenches CT1 and opening regions 163 can be arranged to be spaced apart from each other in a first direction (X-axis direction). The widths of the plurality of trenches CT1 and opening regions 163 can be different from each other. The width of the opening region 163 can be determined by the linewidths W1 and W2 of the power supply wiring PL, and the width of the trenches CT1 can be determined by the distance between the opening regions 163. The width can be the length extending in the first direction (X-axis direction).

[0098] The plurality of trenches CT1 and opening regions 163 may be arranged only in the edge regions where power lines PL are arranged. The trenches CT1 and opening regions 163 may not be formed in the central portion where data lines DL are located. However, the embodiments described herein are not limited to this. For example, the trenches CT1 and / or opening regions 163 may also be formed in the portions where planarization layer 160 is formed, or even in the region where data lines DL are located. Furthermore, a second trench CT2 may be formed between the opening region 163 and the display region DA to further prevent moisture penetration.

[0099] Reference Figure 7 The touch wiring TL can be positioned above the power wiring PL. The trench CT1 may not be formed in the area where the touch wiring TL is located. If the trench CT1 is formed in the area where the touch wiring TL is located, the flatness of the touch wiring TL may be reduced, leading to a break.

[0100] Figure 8 This is a cross-sectional view of a display device according to one embodiment of this specification.

[0101] Reference Figure 8 A plurality of insulating layers 110, 120, 130, 140, 160 and 180 may be located above the substrate. For example, buffer layer 110, gate insulating layer 120, lower interlayer insulating layer 130, upper interlayer insulating layer 140, planarization layer 160 and dam layer 180 may be sequentially located on substrate 100.

[0102] The encapsulation portion 400 can be located in the display area. The encapsulation portion 400 can prevent damage to the light-emitting element 300 due to external moisture and impact. The encapsulation portion 400 can have a multi-layer structure. For example, the encapsulation portion 400 may include a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430 stacked sequentially. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may contain insulating material.

[0103] A touch sensing layer 500, including a plurality of touch electrodes TE, can be disposed on a package portion 400. The plurality of touch electrodes can be connected to bridging electrodes BE disposed on different layers. Specifically, the touch sensing layer 500 may include a touch buffer layer 510 disposed on the package portion 400, bridging electrodes BE disposed on the touch buffer layer 510, a touch interlayer insulating layer 520 disposed above the touch buffer layer 510 and the bridging electrodes BE, and touch electrodes TE disposed on the touch interlayer insulating layer 520. The bridging electrodes BE and the touch electrodes TE may contain the same material.

[0104] A dam 190 that blocks the flow of the second encapsulation layer 420 forming the encapsulation portion 400 can be arranged on the non-display area NA. Specifically, the dam 190 is arranged in a closed curve shape around the display area DA in the non-display area NA, the first encapsulation layer 410 and the third encapsulation layer 430 are arranged above the dam 190, and the flow of the second encapsulation layer 420 can be blocked by the dam 190.

[0105] The dam 190 can be configured to have a height greater than a certain height to block the flow of the second encapsulation layer 420. For this purpose, the dam 190 can be formed by at least one layer made of an organic material. For example, the dam 190 may include a lower layer made of the same material as the planarization layer 160 and an upper layer made of the same material as the dam layer 180, but is not limited thereto. Although the figures show a configuration with two dams 190, one, three, or more dams 190 may be provided.

[0106] The touch buffer layer 510 and the interlayer insulating layer 520 can extend over the dam 190 to the non-display area NA. Therefore, chemical solutions (such as developers or etchants) used in the manufacturing process of the touch electrodes formed over the touch buffer layer 510, or external moisture or foreign matter, can be prevented from penetrating into the light-emitting element.

[0107] The touch electrode TE and touch wiring TL are arranged on the touch interlayer insulating layer 520, and the touch wiring TL can extend along the touch buffer layer 510 to the non-display area NA.

[0108] The touch protection layer 530 can be disposed above the touch wiring TL. The touch protection layer 530 can be used to prevent oxidation, corrosion or damage to the touch electrodes and touch wiring.

[0109] The planarization layer 160 of the display panel can extend into the non-display area NA to cover the power supply wiring PL. The planarization layer 160 extending into the non-display area NA can include a plurality of trenches CT1. Moisture penetration paths can be blocked by the plurality of trenches CT1.

[0110] The power wiring PL extending into the non-display area NA can be exposed through a plurality of trenches CT1. The touch buffer layer 510 extending into the non-display area NA can contact the power wiring PL to improve adhesion. Therefore, peeling of the touch sensing layer can be prevented.

[0111] Figure 9 A diagram illustrating an opening formed in a planarization layer according to one embodiment of this specification. Figure 10 For along Figure 9 The cross-sectional view taken from line C-C'. Figure 11 This is a cross-sectional view of a display device according to another embodiment of this specification.

[0112] Reference Figure 9 On the plane, a plurality of openings H1 can be formed in areas of the planarization layer 160 where no touch wiring TL is provided. The openings H1 can be square in shape, but the embodiments described herein are not limited to this. For example, the openings H1 can have various shapes, such as circular, triangular, and octagonal shapes. The openings H1 may not be formed in areas where touch wiring TL is provided to prevent the touch wiring TL from being disconnected.

[0113] An opening H1 may include a first opening H11 disposed in a region NPA in which there is no power supply wiring PL, and a second opening H12 disposed on the power supply wiring PL. The first opening H11 and the second opening H12 may have the same dimensions, but are not limited to this. For example, the dimensions of the first opening H11 may be different from the dimensions of the second opening H12. For example, the shape of the first opening H11 may be different from the shape of the second opening H12.

[0114] The third opening H13, positioned adjacent to the touch wiring TL, can have a different size and / or shape than the other openings. For example, the third opening H13 positioned closest to the touch wiring TL can have a bevel formed on the side facing the touch wiring TL. Furthermore, the third opening H13 positioned closest to the touch wiring TL can have the smallest size compared to the other openings. In this configuration, a maximum number of openings can be formed to increase the adhesion of the touch sensing layer, while preventing the formation of steps in the touch wiring TL by not forming openings near the area where the touch wiring TL is located.

[0115] Reference Figure 10The drive wiring, including the power supply line PL, can be disposed on the upper interlayer insulating layer 140. The planarization layer 160 can be disposed on the drive wiring, including the power supply line PL. The opening H1 of the planarization layer 160 exposes the upper interlayer insulating layer 140. Therefore, in the process of applying the touch buffer layer 510 onto the planarization layer 160, the touch buffer layer 510 and the touch interlayer insulating layer 520 can be inserted into the opening H1 and can contact the upper interlayer insulating layer 140.

[0116] Since the planarization layer 160 is an organic material, its adhesion to the inorganic touch buffer layer 510 disposed thereon may be relatively weak. However, according to this embodiment, since the inorganic upper interlayer insulating layer 140 and the inorganic touch buffer layer 510 are in contact through the opening H1, the adhesion can be relatively strong. Therefore, the adhesion between the display panel and the touch sensing layer can be improved when subjected to external force or bending. Thus, the phenomenon of touch wiring TL being lifted or peeled off on the touch buffer layer 510 can be improved.

[0117] The opening H1 may include a first opening H11 that exposes the upper interlayer insulating layer 140 of the display panel and a second opening H12 that exposes the power wiring PL.

[0118] The touch buffer layer 510 may include a first contact portion CP1, which is bonded to the upper interlayer insulating layer 140 in a region having a first opening H11 therein, and a second contact portion CP2, which is bonded to the power wiring PL in a region having a second opening H12 therein. Therefore, since the touch buffer layer 510 is bonded to the upper interlayer insulating layer 140 and also to the power wiring PL, adhesion can be improved.

[0119] The first opening H11 and the second opening H12 may have the same shape and / or size, but the embodiments described herein are not limited thereto. For example, the first opening H11 may be larger than the second opening H12. For example, the first opening H11 may be smaller than the second opening H12.

[0120] Reference Figure 11 The planarization layer 160 extending to the non-display area NA may include a plurality of openings H1 and trenches CT1. Moisture penetration paths may be blocked by the plurality of trenches CT1.

[0121] The power wiring PL extending into the non-display area NA can be exposed through a plurality of openings H1 and trenches CT1. The touch buffer layer 510 extending into the non-display area NA can contact the power wiring PL to improve adhesion. Therefore, peeling of the touch sensing layer can be prevented.

[0122] The display device according to various embodiments of this specification can be described as follows.

[0123] A display device according to one or more embodiments of this specification may include: a substrate including a display area and a non-display area; driving wiring extending from the display area to the non-display area; a planarization layer disposed on the driving wiring; and touch wiring disposed above the planarization layer, wherein the planarization layer may include trenches disposed on the driving wiring, and the trenches may not overlap with the touch wiring in a plane.

[0124] The display device according to one or more embodiments of this specification may further include pad portions connected to drive wiring and touch wiring, wherein trenches may be arranged in a non-display area between the display area and the pad portions.

[0125] According to one or more embodiments of this specification, the drive wiring may include a plurality of power wirings and a plurality of data wirings, and trenches may be arranged on the power wirings.

[0126] According to one or more embodiments of this specification, power cabling may include pad connection portions connected to pads arranged in a non-display area, and trenches may be arranged on the pad connection portions.

[0127] The display device according to one or more embodiments of this specification may further include a plurality of partition regions arranged between pad connection portions of power wiring, and the planarization layer may include a plurality of opening regions arranged in the partition regions.

[0128] According to one or more embodiments of this specification, trenches may be arranged between a plurality of open areas.

[0129] According to one or more embodiments of this specification, a plurality of trenches arranged between a plurality of open areas have different lengths.

[0130] According to one or more embodiments of this specification, the touch wiring may include a first touch wiring extending from the display area and disposed above the power wiring, and a second touch wiring connecting the first touch wiring to a pad portion disposed in a non-display area, wherein the second touch wiring may not overlap with the power wiring.

[0131] According to one or more embodiments of this specification, the driving wiring may further include gate wiring, which may include a first gate wiring extending from the display area and disposed under the power supply wiring and a second gate wiring connecting the first gate wiring to a pad portion disposed in a non-display area, and the second gate wiring may not overlap with the power supply wiring.

[0132] According to one or more embodiments of this specification, the second gate wiring can be connected to the pad portion through the opening region.

[0133] According to one or more embodiments of this specification, the planarization layer may include a plurality of openings disposed between the trench and the display area, and the plurality of openings may be arranged in a plane offset from the touch conductors.

[0134] The display device according to one or more embodiments of this specification may further include: a first insulating layer disposed between a drive wiring and a planarization layer; and a second insulating layer disposed between the planarization layer and a touch wiring, wherein the second insulating layer may contact the first insulating layer exposed through an opening.

[0135] According to one or more embodiments of this specification, a plurality of openings may include a first opening that does not overlap with the power wiring and a second opening disposed on the power wiring.

[0136] According to one or more embodiments of this specification, the first opening and the second opening may have different sizes.

[0137] According to one or more embodiments of this specification, the opening arranged closest to the touch wiring in the opening can have the smallest area.

[0138] According to one or more embodiments of this specification, the first insulating layer and the second insulating layer may comprise inorganic materials, and the planarization layer may comprise organic materials.

[0139] The display device according to one or more embodiments of this specification may further include a dam arranged in a non-display area, wherein an opening may be arranged between the dam and the trench.

[0140] The display device according to one or more embodiments of this specification may further include: a data driver configured to apply data signals to pixels in a display area; a gate driver configured to apply gate signals to pixels in a display area; and a touch sensing unit connected to touch wiring to receive touch signals.

[0141] The display device according to one or more embodiments of this specification may further include a timing controller configured to control a data driver, a gate driver, and a touch sensing unit.

[0142] The display device according to one or more embodiments of this specification may further include: a first substrate on which a timing controller is disposed; a second substrate on which a data driver and a touch sensing unit are disposed; and a flexible cable connecting the first substrate and the second substrate.

[0143] 100: Substrate CT1, CT2: Trench

[0144] TL: Touch wiring; SL: Driver wiring

[0145] PL: Power supply wiring

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area; Drive wiring extending from the display area to the non-display area; A planarization layer disposed on the drive wiring; as well as Touch wiring arranged above the planarization layer, The planarization layer includes trenches disposed on the drive wiring, and The groove does not overlap with the touch wiring in a plan view.

2. The display device according to claim 1, further comprising: The pad portion connected to the drive wiring and the touch wiring, The trench is arranged in the non-display area between the display area and the pad portion.

3. The display device according to claim 2, wherein: The drive wiring includes a plurality of power lines and a plurality of data lines, and The trench is arranged on the power supply wiring.

4. The display device according to claim 3, wherein: The power supply cabling includes pad connection portions connected to the pads arranged in the non-display area, and The groove is arranged on the pad connection portion.

5. The display device according to claim 4, further comprising: A plurality of partitioned areas are arranged between the pad connection portions of the power wiring. The planarization layer includes a plurality of open areas arranged in the partitioned area.

6. The display device according to claim 5, wherein the groove is arranged between the plurality of opening regions.

7. The display device according to claim 6, wherein the trench comprises a plurality of trenches, and the plurality of trenches disposed between the plurality of opening regions have different lengths.

8. The display device according to claim 5, wherein: The touch wiring includes a first touch wire extending in the display area and disposed above the power wiring, and a second touch wire connecting the first touch wire to the pad portion disposed in the non-display area, and The second touch wiring does not overlap with the power wiring.

9. The display device according to claim 5, wherein the driving wiring further includes gate wiring. The gate wiring includes a first gate wiring extending from the display area and disposed under the power wiring, and a second gate wiring connecting the first gate wiring to the pad portion disposed in the non-display area, and The second gate wiring does not overlap with the power supply wiring.

10. The display device according to claim 9, wherein the second gate wiring is connected to the pad portion through the opening region.

11. The display device according to claim 3, wherein: The planarization layer includes a plurality of openings disposed between the trench and the display area, and The plurality of openings are arranged on a plane offset from the touch wire.

12. The display device according to claim 11, further comprising: A first insulating layer disposed between the substrate and the planarization layer; as well as A second insulating layer is disposed between the planarization layer and the touch wiring. The second insulating layer is in contact with the first insulating layer exposed through the opening in the planarization layer.

13. The display device of claim 12, wherein the plurality of openings includes a first opening that does not overlap with the power wiring and a second opening disposed on the power wiring.

14. The display device according to claim 13, wherein the first opening and the second opening have different sizes.

15. The display device of claim 13, wherein the opening arranged closest to the touch wiring in the opening has the smallest area.

16. The display device according to claim 12, wherein: The first insulating layer and the second insulating layer comprise inorganic materials, and The planarization layer contains organic materials.

17. A display device, comprising: A substrate, the substrate including a display area and a non-display area; Drive wiring extending from the display area to the non-display area; A planarization layer disposed on the drive wiring; as well as The touch wiring includes a first touch wiring extending in the display area and a second touch wiring extending in the non-display area. The planarization layer includes trenches or openings, and The groove or opening in the display area does not overlap with the first touch wiring in the vertical direction.

18. The display device according to claim 17, wherein, The drive wiring includes a plurality of power lines and a plurality of data lines. The grooves or openings are arranged on the power wiring. The second touch wiring connects the first touch wiring to the pad portion disposed in the non-display area, and The second touch wiring does not overlap with the power wiring.

19. A display device, comprising: A substrate, the substrate including a display area and a non-display area; A first wiring extending from the display area to the non-display area; A planarization layer disposed on the first wiring; as well as The second wiring arranged on the planarization layer, The planarization layer includes trenches that expose a layer that contacts the planarization layer from below. The second wiring located in the display area is not located directly above the trench.

20. The display device according to claim 19, wherein, The first wiring is a driver wiring, and the second wiring is a touch wiring; or the first wiring is a touch wiring, and the second wiring is a driver wiring. The layer that contacts the planarization layer from above the planarization layer is either in contact with the planarization layer in the trench or connected via an intermediate structure to the layer that contacts the planarization layer from below the planarization layer.

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