Pixels and display devices including them

Abstract

The display device includes pixels. Each pixel includes a light-emitting unit and a pixel circuit. In a first mode, the pixel circuit provides a first driving current to the light-emitting unit in a first current flow direction, and in a second mode, the pixel circuit provides a second driving current to the light-emitting unit in a second current flow direction different from the first current flow direction. The light-emitting unit includes: a first electrode and a second electrode spaced apart from each other; a first light-emitting element connected between the first electrode and the second electrode in the first current flow direction; and a second light-emitting element connected between the first electrode and the second electrode in the second current flow direction.

Description

Technical Field

[0001] This disclosure relates to a pixel and a display device including the pixel. Background Technology

[0002] With increasing interest in information display and growing demand for portable information media, the requirements and commercialization of display devices are increasing dramatically. Summary of the Invention

[0003] Technical issues

[0004] An aspect of the embodiments of this disclosure is to provide a pixel capable of improving brightness deviation and / or brightness variation, and a display device including the pixel.

[0005] Another aspect of the embodiments of this disclosure is to provide a display device that can improve lifespan.

[0006] Technical solution

[0007] To implement the features and aspects of the embodiments of this disclosure, a pixel according to an embodiment of this disclosure includes: an emitting unit connected between a first electric field line and a second electric field line; and a pixel circuit for providing a first driving current to the emitting unit in a first current flow direction in a first mode, and for providing a second driving current to the emitting unit in a second current flow direction different from the first current flow direction in a second mode, wherein the emitting unit includes: a first electrode and a second electrode spaced apart from each other; a first light-emitting element connected between the first electrode and the second electrode in the first current flow direction; and a second light-emitting element connected between the first electrode and the second electrode in the second current flow direction.

[0008] According to an embodiment, the pixel circuit may include: a first driving transistor connected between a first power line and a first electrode; a first scanning transistor connected between a data line and the gate electrode of the first driving transistor, the first scanning transistor having a gate electrode connected to the first scan line; and a first storage capacitor connected between the gate electrode of the first driving transistor and the first electrode, wherein a second electrode is connected to a second power line.

[0009] According to an embodiment, the pixel circuit may further include: a first sensing transistor connected between the readout line and the first electrode, the first sensing transistor having a gate electrode connected to the first sensing line.

[0010] According to an embodiment, the pixel circuit may further include: a second driving transistor connected between the first power line and the first electrode; and a second scanning transistor connected between the data line and the gate electrode of the second driving transistor, the second scanning transistor having a gate electrode connected to the second scan line.

[0011] According to an embodiment, the pixel circuit may further include: a second storage capacitor connected between the gate electrode of the second driving transistor and one electrode of the second driving transistor.

[0012] According to an embodiment, the second storage capacitor may be connected between the gate electrode of the second driving transistor and the first electrode.

[0013] According to an embodiment, the second storage capacitor may be connected between the gate electrode of the second driving transistor and the first power line.

[0014] According to an embodiment, in a first mode, the first scanning transistor and the first sensing transistor can be turned on and the second scanning transistor can be turned off, and in a second mode, the second scanning transistor and the first sensing transistor can be turned on and the first scanning transistor can be turned off.

[0015] According to an embodiment, the pixel circuit can be driven alternately in a first time period in a first mode and a second mode, and the first time period can be greater than or equal to one frame.

[0016] According to an embodiment, the voltage level of the first power supply voltage applied to the first power line and the voltage level of the second power supply voltage applied to the second power line can be interchanged during a first time period.

[0017] According to an embodiment, the pixel may further include: a first power control transistor connected between a first power line and a third power line, the first power control transistor having a gate electrode connected to a control line; and a second power control transistor connected between a first power line and a fourth power line, the second power control transistor having a gate electrode connected to a control line, wherein one of the first power control transistor and the second power control transistor may be an n-type transistor, and the other of the first power control transistor and the second power control transistor may be a p-type transistor.

[0018] According to an embodiment, the pixel may further include: a third power control transistor connected between the second power line and the fourth power line, the third power control transistor having a gate electrode connected to the control line; and a fourth power control transistor connected between the second power line and the third power line, the fourth power control transistor having a gate electrode connected to the control line, wherein the third power control transistor may be a transistor of the same type as the first power control transistor, and the fourth power control transistor may be a transistor of the same type as the second power control transistor.

[0019] According to an embodiment, the first end of the first light-emitting element and the second end of the second light-emitting element can be electrically connected to the first electrode, the second end of the first light-emitting element and the first end of the second light-emitting element can be electrically connected to the second electrode, and the first end of the first light-emitting element and the first end of the second light-emitting element can correspond to the same type of semiconductor layer.

[0020] According to an embodiment, the total number of first light-emitting elements in the emitting unit can be substantially equal to the total number of second light-emitting elements in the emitting unit.

[0021] According to an embodiment, the emitting unit may further include a plurality of light-emitting element packages connected between the first electrode and the second electrode. Each of the plurality of light-emitting element packages may include a first lead electrode, a second lead electrode, and a pair of light-emitting elements arranged between the first lead electrode and the second lead electrode in different current flow directions. The pair of light-emitting elements may include a first light-emitting element and a second light-emitting element.

[0022] According to an embodiment, some of the multiple light-emitting element packages can be connected in series between the first electrode and the second electrode.

[0023] To achieve the features and aspects of this disclosure, a display device according to some embodiments of this disclosure includes: a pixel; a scan driver for supplying a scan signal to the pixel via a scan line and for supplying a sensing signal to the pixel via a sensing line; and a data driver for supplying a data signal to the pixel via a data line and for supplying an initialization signal to the pixel via a readout line, wherein each pixel includes: an emitting unit connected between a first power line and a second power line; and a pixel circuit for supplying a first driving current to the emitting unit in a first current flow direction in response to a first scan signal in the scan signal and a first sensing signal in the sensing signal in a first mode, and for supplying a second driving current to the emitting unit in a second current flow direction different from the first current flow direction in response to a second scan signal in the scan signal and the first sensing signal in a second mode, and the emitting unit includes: a first electrode and a second electrode spaced apart from each other; a first light-emitting element connected between the first electrode and the second electrode in the first current flow direction; and a second light-emitting element connected between the first electrode and the second electrode in the second current flow direction.

[0024] According to an embodiment, the total number of first light-emitting elements in the emitting unit can be substantially equal to the total number of second light-emitting elements in the emitting unit.

[0025] According to an embodiment, the display device may further include: a power supply for supplying a first power supply voltage to a pixel via a first power line, and for supplying a second power supply voltage to a pixel via a second power line, wherein the power supply may exchange the voltage level of the first power supply voltage and the voltage level of the second power supply voltage for a first time period.

[0026] According to an embodiment, the display device may further include a power supply for supplying a first power supply voltage to a third power line and for supplying a second power supply voltage to a fourth power line, wherein each pixel may further include: a first power control transistor connected between the first power line and the third power line, the first power control transistor having a gate electrode connected to a control line; and a second power control transistor connected between the first power line and the fourth power line, the second power control transistor having a gate electrode connected to a control line, wherein one of the first power control transistor and the second power control transistor is an n-type transistor, and the other of the first power control transistor and the second power control transistor is a p-type transistor.

[0027] Beneficial effects

[0028] According to embodiments of the present disclosure, a pixel and a display device including the pixel include an emitting unit, and the emitting unit may include at least a pair of first light-emitting elements and second light-emitting elements arranged between a first electrode and a second electrode along different polarity directions. Because the first light-emitting elements and the second light-emitting elements are arranged in pairs, the ratio of the first light-emitting elements and the ratio of the second light-emitting elements are uniformly presented throughout the pixel and the display device, and the brightness deviation of the pixel and the display device can be improved.

[0029] Furthermore, the pixel and display device can provide a first driving current to the emitting unit in a first mode in a first current flow direction, and can provide a second driving current to the emitting unit in a second mode in a second current flow direction. When the first mode and the second mode alternate at specific time intervals, the first light-emitting element and the second light-emitting element in the emitting unit alternately emit light (light emission). Compared to the case where only the first light-emitting element or the second light-emitting element emits light in response to a current direction, the lifespan of the emitting unit can be improved.

[0030] The effects and aspects of the embodiments according to this disclosure are not limited to those described above, and many more effects and aspects are incorporated herein. Attached Figure Description

[0031] Figure 1a This is a perspective view schematically showing a light-emitting element according to an embodiment.

[0032] Figure 1b yes Figure 1a A cross-sectional view of the light-emitting element.

[0033] Figure 2a This is a plan view showing a light-emitting element package according to an embodiment.

[0034] Figure 2b yes Figure 2a The equivalent circuit diagram of the light-emitting element package.

[0035] Figure 2c It is shown Figure 2a A cross-sectional view of an example of a light-emitting element package.

[0036] Figure 3 This is a schematic plan view of a display device according to an embodiment.

[0037] Figure 4a and Figure 4b It is shown that it includes Figure 3 A circuit diagram of an embodiment of pixels in a display device.

[0038] Figure 5a It is shown that it includes Figure 4a and Figure 4b A plan view of an example of an emission unit in a pixel.

[0039] Figure 5b yes Figure 5a The equivalent circuit diagram of the transmitting unit.

[0040] Figure 5c It is shown that it includes Figure 4a and Figure 4b Another example of a plan view of the emission unit in a pixel.

[0041] Figures 6a to 6c It is shown Figure 4a and Figure 4b A diagram illustrating examples of pixel operations.

[0042] Figures 7a to 7c It is shown Figure 4a and Figure 4b Another example of pixel manipulation is shown in the diagram.

[0043] Figure 8 This is a block diagram illustrating a display device according to an embodiment.

[0044] Figure 9a and Figure 9b It is shown that it includes Figure 3 A circuit diagram of another embodiment of pixels in a display device.

[0045] Figure 10a and Figure 10b It is shown Figure 9a and Figure 9b A diagram illustrating examples of pixel operations.

[0046] Figure 11a and Figure 11b It is shown Figure 9a and Figure 9b Another example of pixel manipulation is shown in the diagram. Detailed Implementation

[0047] In the following description, embodiments of the present disclosure will be illustrated in more detail with reference to the accompanying drawings. Identical elements in the drawings are indicated by the same reference numerals, and redundant descriptions thereof are omitted.

[0048] Figure 1a This is a perspective view schematically showing a light-emitting element according to an embodiment. Figure 1b yes Figure 1a A cross-sectional view of the light-emitting element. In embodiments of this disclosure, the type and / or shape of the light-emitting element are not limited to... Figure 1a and Figure 1b The embodiment shown.

[0049] Reference Figure 1a and Figure 1b The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element (LD) may be implemented as a light-emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked along the length direction or extension direction of the light-emitting element (LD).

[0050] The light-emitting element (LD) can be arranged in a shape that extends in one direction. When the extension direction of the light-emitting element (LD) is longitudinal, the LD may include one end (or lower end) and another end (or upper end) in the extension direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at one end (or lower end) of the LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other end (or upper end) of the LD. For example, the first semiconductor layer 11 may be disposed at one end (or lower end) of the LD, and the second semiconductor layer 13 may be disposed at the other end (or upper end) of the LD.

[0051] The light-emitting element (LD) can be arranged in various shapes. For example, the LD can have a rod-like or bar-like shape that is long in the longitudinal direction (i.e., the aspect ratio is greater than 1). In embodiments of this disclosure, the length L of the LD in the longitudinal direction can be greater than its diameter D (or the width of its cross-section). The LD can include, for example, a light-emitting diode (LED) manufactured in a very small size, with a diameter D and / or length L on the order of approximately micrometers or nanometers.

[0052] The diameter D of the light-emitting element (LD) can be from about 0.5 μm to about 5 μm, and the length L of the light-emitting element (LD) can be from about 1 μm to about 10 μm. However, the diameter D and length L of the light-emitting element (LD) are not limited to these, and the size of the light-emitting element (LD) can be changed to meet the requirements (or design conditions) of the lighting device or self-emissive display device to which the light-emitting element (LD) is applied.

[0053] For example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the material forming the first semiconductor layer 11 is not limited to these, and the first semiconductor layer 11 may include various other materials. In embodiments of this disclosure, the first semiconductor layer 11 may include a GaN semiconductor material doped with a first conductive dopant (or n-type dopant). The first semiconductor layer 11 may include an upper surface in contact with the active layer 12 and a lower surface exposed to the outside in the direction of the length L of the light-emitting element LD. The lower surface of the first semiconductor layer 11 may be one end (or lower end) of the light-emitting element LD.

[0054] The active layer 12 can be disposed on the first semiconductor layer 11 and can be formed in a single quantum well structure or a multi-quantum well structure. For example, when the active layer 12 is formed in a multi-quantum well structure, the active layer 12 may include a barrier layer, a strain enhancement layer, and a well layer that are periodically stacked as a unit. Because the strain enhancement layer has a smaller lattice constant than the barrier layer, the strain applied to the well layer (e.g., compressive strain) can be further enhanced. However, the structure of the active layer 12 is not limited to the embodiments described above.

[0055] The active layer 12 can emit light with wavelengths from 400 nm to 900 nm and can use a dual heterostructure. In embodiments of this disclosure, a capping layer doped with a conductive dopant can be formed above and / or below the active layer 12 along the length L of the light-emitting element LD. For example, the capping layer may include an AlGaN layer or an InAlGaN layer. According to embodiments, materials such as AlGaN or InAlGaN can be used to form the active layer 12, and various other materials can be used to form the active layer 12. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0056] When an electric field of appropriate voltage (e.g., set voltage or predetermined voltage) or higher voltage is applied between the two ends of the light-emitting element LD, electron-hole pairs recombine in the active layer 12, causing the light-emitting element LD to emit light. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source (or light source) for various light-emitting devices, including pixels of a display device.

[0057] The second semiconductor layer 13 may be disposed on the second surface of the active layer 12 and may include a semiconductor layer of a different type from the first semiconductor layer 11. As an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For instance, the second semiconductor layer 13 may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the material forming the second semiconductor layer 13 is not limited to this, and the second semiconductor layer 13 may include various other materials. In embodiments of this disclosure, the second semiconductor layer 13 may include a GaN semiconductor material doped with a second conductive dopant (or p-type dopant). The second semiconductor layer 13 may include a lower surface in contact with the second surface of the active layer 12 and an upper surface exposed to the outside in the direction of the length L of the light-emitting element LD. The upper surface of the second semiconductor layer 13 may be the other end (or upper end) of the light-emitting element LD.

[0058] In embodiments of this disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses along the length L of the light-emitting element LD. As an example, along the length L of the light-emitting element LD, the first semiconductor layer 11 may have a relatively larger thickness (e.g., L1) than the thickness (e.g., L2) of the second semiconductor layer 13. Therefore, the active layer 12 of the light-emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11.

[0059] Although each of the first semiconductor layer 11 and the second semiconductor layer 13 is shown as a single layer, this disclosure is not limited thereto. In embodiments of this disclosure, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer (e.g., a capping layer and / or a tensile strain barrier reduction (TSBR) layer) depending on the material of the active layer 12. The TSBR layer may be a strain mitigation layer disposed between semiconductor layers with different lattice structures and serving as a buffer layer for reducing differences in lattice constants. The TSBR layer may include a p-type semiconductor layer (such as p-GaInP, p-AlInP, or p-AlGaInP), but this disclosure is not limited thereto.

[0060] According to an embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light-emitting element LD may further include an additional electrode (hereinafter referred to as the "first additional electrode") disposed on the second semiconductor layer 13 (e.g., the exposed end of the second semiconductor layer 13). In another embodiment, the light-emitting element LD may further include another additional electrode (hereinafter referred to as the "second additional electrode") disposed at one end (e.g., the exposed end) of the first semiconductor layer 11.

[0061] Each of the first and second additional electrodes may be an ohmic contact electrode, but this disclosure is not limited thereto. According to embodiments, the first and second additional electrodes may be Schottky contact electrodes. The first and second additional electrodes may comprise conductive materials. For example, the first and second additional electrodes may comprise chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and opaque metals used alone or in combination with their oxides or alloys, but this disclosure is not limited thereto. According to embodiments, the first and second additional electrodes may comprise transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO).

[0062] The materials included in the first and second additional electrodes can be the same or different materials. The first and second additional electrodes can be substantially transparent or translucent. Therefore, light generated by the light-emitting element LD can be transmitted through each of the first and second additional electrodes and emitted to the outside of the light-emitting element LD. According to an embodiment, when light generated by the light-emitting element LD is emitted to the outside of the light-emitting element LD through a region other than the two ends of the light-emitting element LD without transmitting through the first and second additional electrodes, the first and second additional electrodes can comprise opaque metals.

[0063] In embodiments of this disclosure, the light-emitting element (LD) may further include an insulating film INF. However, according to embodiments, the insulating film INF may be omitted and may be configured to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, in some embodiments, the insulating film INF may cover the outer peripheral surfaces of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0064] The insulating film INF prevents electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13 of the same light-emitting element LD. Furthermore, the insulating film INF reduces or minimizes surface defects in the light-emitting element LD, thereby improving the lifetime and luminous efficiency of the light-emitting element LD. Additionally, when multiple light-emitting elements LD are closely arranged, the insulating film INF prevents unwanted short circuits that may occur between adjacent light-emitting elements LD. The presence or absence of the insulating film INF is not limited as long as it prevents short circuits between the active layer 12 and external conductive materials.

[0065] The insulating film INF can be configured to completely surround the outer peripheral surface of the light-emitting stack comprising the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0066] In the above embodiments, the insulating film INF has been described as completely surrounding the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but this disclosure is not limited thereto. According to an embodiment, when the light-emitting element LD includes a first additional electrode, the insulating film INF may completely surround the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first additional electrode. In another embodiment, the insulating film INF may not completely surround the outer peripheral surface of the first additional electrode, or it may only surround a portion of the outer peripheral surface of the first additional electrode and may not surround the remaining outer peripheral surface of the first additional electrode. In an embodiment, when the first additional electrode is disposed at another end (or upper end) of the light-emitting element LD and the second additional electrode is disposed at one end (or lower end) of the light-emitting element LD, the insulating film INF may expose at least one area of ​​each of the first and second additional electrodes.

[0067] The insulating film INF can include a transparent insulating material. For example, the insulating film INF can include materials selected from silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON), aluminum oxide (AlO) x It is an insulating material composed of at least one of the groups consisting of and titanium dioxide (TiO2). However, this disclosure is not limited thereto, and various materials having insulating properties can be used as materials for the insulating film INF. In embodiments, the insulating film INF may comprise a bilayer.

[0068] The aforementioned light-emitting elements (LDs) can be used as light sources for various display devices. LDs can be manufactured using surface treatment processes. For example, when multiple LDs are mixed with a fluid solution (or solvent) and supplied to each pixel region (e.g., the emitting region of each pixel or the emitting region of each sub-pixel), each of the LDs can be surface-treated so that the LDs can be uniformly injected without unevenly agglomerating in the solution.

[0069] The emitting unit (or light-emitting device) including the aforementioned light-emitting element (LD) can be used in various types of electronic devices (including display devices) that require a light source. For example, when multiple light-emitting elements (LDs) are arranged in the pixel area of ​​each pixel on a display panel, the light-emitting elements (LDs) can serve as the light source for each pixel. However, the application areas of light-emitting elements (LDs) are not limited to the examples described above. For example, light-emitting elements (LDs) can be used in other types of electronic devices that require a light source (such as lighting devices).

[0070] Figure 2a This is a plan view showing a light-emitting element package according to an embodiment. Figure 2b yes Figure 2a The equivalent circuit diagram of the light-emitting element package. Figure 2c It is shown Figure 2a A cross-sectional view of an example of a light-emitting element package.

[0071] Reference Figures 1a to 2c The light-emitting element package (LDP) may include a first light-emitting element LD1, a second light-emitting element LD2, a first lead electrode E_LEAD1, and a second lead electrode E_LEAD2.

[0072] Each of the first light-emitting element LD1 and the second light-emitting element LD2 can be compared with the above reference. Figure 1a and Figure 1b The light-emitting elements (LDs) described are basically the same or similar.

[0073] The first light-emitting element LD1 and the second light-emitting element LD2 can be arranged in different polarity directions (or different current flow directions).

[0074] The first lead electrode E_LEAD1 can be connected to different semiconductor layers of the first light-emitting element LD1 and the second light-emitting element LD2. The first lead electrode E_LEAD1 can be physically or electrically connected to different semiconductor layers of the first light-emitting element LD1 and the second light-emitting element LD2. For example... Figure 2a As shown, the first lead electrode E_LEAD1 can be connected to the p-type semiconductor layer of the first light-emitting element LD1 (i.e., the second semiconductor layer 13, see...). Figure 1b And it can be connected to the n-type semiconductor layer of the second light-emitting element LD2 (i.e., the first semiconductor layer 11, see...). Figure 1b ).

[0075] Similar to the first lead electrode E_LEAD1, the second lead electrode E_LEAD2 can be connected to different semiconductor layers of the first light-emitting element LD1 and the second light-emitting element LD2. For example... Figure 2a As shown, the second lead electrode E_LEAD2 can be connected to the n-type semiconductor layer of the first light-emitting element LD1 (i.e., the first semiconductor layer 11, see...). Figure 1b And it can be connected to the p-type semiconductor layer of the second light-emitting element LD2 (i.e., the second semiconductor layer 13, see...). Figure 1b ).

[0076] In other words, the first light-emitting element LD1 and the second light-emitting element LD2 can be connected between the first lead electrode E_LEAD1 and the second lead electrode E_LEAD2 along different polarity directions (or different current flow directions).

[0077] Because the first lead electrode E_LEAD1 and the second lead electrode E_LEAD2 are related to the above reference. Figure 1a and Figure 1b The first and second additional electrodes are essentially the same or similar, so their redundant descriptions will not be repeated.

[0078] In some embodiments, the first light-emitting element LD1 and the second light-emitting element LD2 may be integrally formed with each other in the light-emitting element package LDP.

[0079] like Figure 2c As shown, the first semiconductor layer 11a, active layer 12a, and second semiconductor layer 13a of the first light-emitting element LD1 can be sequentially stacked on the second lead electrode E_LEAD2. Furthermore, on one side of the first light-emitting element LD1, the second semiconductor layer 13b, active layer 12b, and first semiconductor layer 11b of the second light-emitting element LD2 can be sequentially stacked on the second lead electrode E_LEAD2, and a first insulating film INF1 is placed between the first light-emitting element LD1 and the second light-emitting element LD2. The first lead electrode E_LEAD1 can be disposed on the second semiconductor layer 13a of the first light-emitting element LD1 and the first semiconductor layer 11b of the second light-emitting element LD2. The second insulating film INF2 can be configured to completely surround the outer peripheral surface of the light-emitting stack including the first light-emitting element LD1 and the second light-emitting element LD2.

[0080] In other words, the first light-emitting element LD1 and the second light-emitting element LD2 can be connected or packaged in different directions and connected to the first lead electrode E_LEAD1 and the second lead electrode E_LEAD2 to form a light-emitting element package LDP.

[0081] For reference, in the manufacture of light-emitting elements (LDs) including those with diameters D and / or lengths L on the micrometer or nanometer scale, see Figure 1a and Figure 1b In the case of a display device, light-emitting elements (LDs) are prepared (fabricated) in the form of a dispersion in a solution (e.g., a set solution or a predetermined solution) and supplied onto the substrate (e.g., a pixel area) of the display device by inkjet printing or slot coating. Subsequently, when a voltage (e.g., a set voltage or a predetermined voltage) is applied between alignment electrodes pre-formed on the substrate, an electric field is formed between the alignment electrodes, and the LDs self-align between the alignment electrodes. However, in the process of LD self-alignment, some LDs may not be arranged in the desired direction. For example, some LDs may be arranged in a direction different from the desired direction (i.e., the desired current flow direction), and some LDs (i.e., reverse-emitting elements arranged in different directions) do not contribute to constituting an effective light source. Furthermore, such reverse-emitting elements do not appear uniformly on the substrate but may be concentrated in specific areas of the substrate, or may appear at different ratios for each location. This is identified as brightness deviation and clustered dark spots / smudges, and the display quality of the display device may deteriorate.

[0082] Therefore, since the light-emitting element package (LDP) according to the embodiments of this disclosure is constructed by encapsulating a first light-emitting element LD1 and a second light-emitting element LD2 arranged in different polarity directions, the alignment ratio of the light-emitting element package (LDP) can be uniformly presented throughout the display device. Therefore, the brightness deviation of the display device can be improved.

[0083] Furthermore, the first light-emitting element LD1 and the second light-emitting element LD2 in the light-emitting element package LDP emit light alternately through a bidirectional driving technology (i.e., a pixel structure for bidirectional driving) described later, thereby improving the lifespan of the display device.

[0084] exist Figures 2a to 2c In this context, although a light-emitting element package (LDP) has been described as including a pair of first light-emitting elements LD1 and second light-emitting elements LD2, the LDP is not limited to this. For example, an LDP may include two or more pairs of first light-emitting elements LD1 and second light-emitting elements LD2.

[0085] Figure 3 This is a schematic plan view of a display device according to an embodiment. For example, Figure 3 Is using Figure 1a and Figure 1b The light-emitting element LD shown is... Figures 2a to 2cThe diagram shows a schematic plan view of a display device with a light-emitting element package (LDP) as the light source. Since the light-emitting element package (LDP) includes the light-emitting element (LD), the light-emitting element (LD) and the light-emitting element package (LDP) in a configuration in which the light-emitting element (LD) and the light-emitting element package (LDP) are applied are referred to as the light-emitting element (LD) and will be described below.

[0086] exist Figure 3 For convenience, the structure of the display device DD is schematically shown with the display area DA in which the image is displayed as the center.

[0087] Reference Figures 1a to 3 The display device DD may include: a substrate SUB; a plurality of pixels PXL disposed on the substrate SUB, and each pixel PXL includes at least one light-emitting element LD; a driver disposed on the substrate SUB and driving the pixels PXL; and a line portion connecting the pixels PXL to the driver.

[0088] This disclosure applies as long as the display device DD is an electronic device (such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, medical device, camera, or wearable device) having a display surface applied to at least one surface.

[0089] Based on the method of driving the light-emitting element (LD), the display device (DD) can be classified into passive matrix display devices and active matrix display devices. For example, when the display device (DD) is implemented as an active matrix type, each of the pixels (PXL) may include a driving transistor for controlling the amount of current supplied to the light-emitting element (LD), a switching transistor for transmitting data signals to the driving transistor, etc.

[0090] The display device DD can be arranged in various shapes. For example, the display device DD can be arranged in the shape of a rectangular plate with two pairs of parallel sides, but this disclosure is not limited thereto. When the display device DD is arranged in the shape of a rectangular plate, one pair of sides can be arranged to be longer than the other pair of sides. In the display device DD arranged in the shape of a rectangular plate, the corner where one long side and one short side touch (or meet) each other can have a rounded shape.

[0091] The base SUB can include the display area DA and the non-display area NDA.

[0092] The display area DA can be an area in which pixels PXL for displaying images are configured. The non-display area NDA can be an area in which a driver for driving pixels PXL is configured and a portion of a line portion for connecting pixels PXL to the driver is configured. For convenience, in Figure 3 Only one pixel PXL is shown, but multiple pixels PXL can actually be set in the display area DA of the base SUB.

[0093] The non-display area NDA can be set on at least one side of the display area DA. The non-display area NDA can surround the periphery (or edge) of the display area DA. In the non-display area NDA, a line portion connected to the pixel PXL and a driver connected to the line portion and driving the pixel PXL can be set.

[0094] The line section can electrically connect the driver to the pixel PXL. The line section can be a fan-out line that provides signals to each pixel PXL and is connected to the signal line (e.g., scan line, data line, or transmit control line) of each pixel PXL. Furthermore, the line section can be a fan-out line connected to the signal line (e.g., control line or sensing line) of each pixel PXL to compensate for changes in the electrical characteristics of each pixel PXL in real time.

[0095] The substrate SUB can include a transparent insulating material and therefore can transmit light. The substrate SUB can be a rigid substrate or a flexible substrate.

[0096] One region on the substrate SUB can be set as a display region DA on which pixels PXL are disposed, and the remaining region on the substrate SUB can be set as a non-display region NDA. For example, the substrate SUB may include a display region DA and a non-display region NDA, wherein the display region DA includes a pixel region in which each pixel PXL is disposed, and the non-display region NDA is disposed around (or adjacent to) the display region DA.

[0097] Each of the pixels PXL can be disposed in the display area DA on the substrate SUB. In embodiments of this disclosure, the pixels PXL can be arranged in a strip structure or The arrangement structure is located within the display area DA, but this disclosure is not limited thereto. The arrangement structure can be referred to as an RGBG matrix structure (e.g., Matrix structure or RGBG structure (e.g., structure)). It is a registered trademark of Samsung Display Co., Ltd., Republic of Korea.

[0098] Each pixel PXL may include at least one light-emitting element (LD) driven by a corresponding scan signal and a corresponding data signal. The LD has a size as small as the micrometer or nanometer scale and may be connected in parallel with adjacent LDs, but this disclosure is not limited thereto. The LD may constitute the light source for each pixel PXL.

[0099] Each of the pixels PXL may include at least one light source driven by signals (e.g., setting signals or predetermined signals) (e.g., scan signals and data signals) and / or voltages (e.g., setting voltage or predetermined voltages) (e.g., first driving voltage and second driving voltage). Figure 1a and Figure 1b The light-emitting element LD shown is not limited to this. However, in the embodiments of this disclosure, the type of light-emitting element LD that can be used as the light source for each pixel PXL is not limited to this.

[0100] The driver can provide signals (e.g., set signals or predetermined signals) and voltages (e.g., set voltages or predetermined voltages) to each pixel PXL via line portions, and can control the driving of the pixel PXL accordingly. The driver may include a scan driver, a transmit driver, a data driver, and a timing controller.

[0101] Figure 4a and Figure 4b It is shown that it includes Figure 3 A circuit diagram of an embodiment of pixels in a display device. Figure 4a and Figure 4b Showing includes Figure 3 The electrical connections between elements in a pixel PXL are shown.

[0102] exist Figure 4a and Figure 4b In China, it will not only include Figure 3 Each element in the pixels shown is called a pixel PXL, and the area in which the element is set is also called a pixel PXL.

[0103] Reference Figures 1a to 4b A pixel PXL (hereinafter referred to as a "pixel") may include an emission unit EMU for generating light with a brightness corresponding to the data signal. Additionally, the pixel PXL may optionally include a pixel circuit PXC for driving the emission unit EMU.

[0104] The transmitting unit (EMU) may include multiple light-emitting elements (LDs) connected in parallel between a first power line PL1 and a second power line PL2. A first driving voltage VDD (or a first power supply voltage) may be applied to the first power line PL1, and a second driving voltage VSS (or a second power supply voltage) may be applied to the second power line PL2. The first driving voltage VDD and the second driving voltage VSS may have different potentials. As an example, the first driving voltage VDD may be set to a high potential voltage, and the second driving voltage VSS may be set to a low potential voltage. According to an embodiment, the first driving voltage VDD may be set to a low potential voltage, and the second driving voltage VSS may be set to a high potential voltage.

[0105] For example, the transmitting unit (EMU) may include a first electrode EL1 (or "first orientation electrode") connected to a first driving voltage VDD via a pixel circuit PXC and a first electric field line PL1, a second electrode EL2 (or "second orientation electrode") connected to a second driving voltage VSS via a second electric field line PL2, and a first light-emitting element LD1 and a second light-emitting element LD2 connected in parallel between the first electrode EL1 and the second electrode EL2 in different directions (or polarity direction, current flow direction, etc.). The first light-emitting element LD1 and the second light-emitting element LD2 may be configured as described above. Figures 2a to 2c The light-emitting element package (LDP) is described. In other words, the emitting unit (EMU) may include the light-emitting element package (LDP).

[0106] The first light-emitting element LD1 included in the transmitting unit EMU may include one end connected to the first driving voltage VDD via a first electrode EL1 and the other end connected to the second driving voltage VSS via a second electrode EL2. The second light-emitting element LD2 included in the transmitting unit EMU may include one end connected to the second driving voltage VSS via a second electrode EL2 and the other end connected to the first driving voltage VDD via a first electrode EL1.

[0107] A first light-emitting element LD1 and a second light-emitting element LD2 (or a light-emitting element package LDP) connected in parallel in different directions between a first electrode EL1 and a second electrode EL2, each supplied with a voltage at a different potential, can constitute an effective light source. As described later, the first light-emitting element LD1 can constitute an effective light source in a first mode, and the second light-emitting element LD2 can constitute an effective light source in a second mode. These effective light sources can be combined to form the emission unit (EMU) of the pixel PXL. The first mode can be defined as a mode in which the first light-emitting element LD1 emits light (emits light), and the second mode can be defined as a mode in which the second light-emitting element LD2 emits light.

[0108] The light-emitting element (LD) of the transmitting unit (EMU) can emit light with a brightness corresponding to the driving current supplied through the pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a driving current corresponding to the grayscale value of the corresponding frame data to the transmitting unit (EMU). The driving current supplied to the transmitting unit (EMU) can flow to either the first light-emitting element (LD1) or the second light-emitting element (LD2). When the first light-emitting element (LD1) or the second light-emitting element (LD2) emits light with a brightness corresponding to the current flowing through it, the transmitting unit (EMU) can emit light with a brightness corresponding to the driving current.

[0109] For example, when a drive current flowing in the first current flow direction is supplied to the transmitting unit EMU, the first light-emitting element LD1 can emit light. Even when a drive voltage (e.g., a set drive voltage or a predetermined drive voltage) (e.g., a forward drive voltage) is applied between the first electrode EL1 and the second electrode EL2, the second light-emitting element LD2 remains inactive. Therefore, virtually no current flows through the second light-emitting element LD2. As another example, when a drive current flowing in the second current flow direction is supplied to the transmitting unit EMU, the second light-emitting element LD2 can emit light. Even when a drive voltage (e.g., a set drive voltage or a predetermined drive voltage) (e.g., a reverse drive voltage) is applied between the first electrode EL1 and the second electrode EL2, the first light-emitting element LD1 remains inactive. Therefore, virtually no current flows through the first light-emitting element LD1.

[0110] Please refer to later Figures 5a to 5c To describe a more specific embodiment of the transmitting unit (EMU).

[0111] The pixel circuit PXC can be connected between the first power line PL1 and the transmitting unit EMU. In the first mode, it can provide a first driving current to the transmitting unit EMU in the first current flow direction, and in the second mode, it can provide a second driving current to the transmitting unit EMU in the second current flow direction.

[0112] The pixel circuit PXC can be connected to the first scan line SCL1, the second scan line SCL2, the readout line RL, and the data line DL of the pixel PXL.

[0113] According to an embodiment, the pixel circuit PXC may include a first driving transistor T_D1, a first scanning transistor T_SC1, a first storage capacitor CST1, and a first sensing transistor T_SS1. The pixel circuit PXC may also include a second driving transistor T_D2, a second scanning transistor T_SC2, and a second storage capacitor CST2.

[0114] The first terminal of the first driving transistor T_D1 can be electrically connected to the first power line PL1, and the second terminal of the first driving transistor T_D1 can be electrically connected to the first electrode EL1 of the transmitter unit EMU. The first terminal of the first driving transistor T_D1 can be the drain electrode, and the second terminal of the first driving transistor T_D1 can be the source electrode. The gate electrode of the first driving transistor T_D1 can be connected to the second terminal of the first scan transistor T_SC1. The first driving transistor T_D1 controls the amount of the first driving current (i.e., the driving current flowing in the first current flow direction) supplied to the transmitter unit EMU in response to the voltage applied to the gate electrode of the first driving transistor T_D1.

[0115] The first terminal of the first scan transistor T_SC1 can be electrically connected to the data line DL, and the second terminal of the first scan transistor T_SC1 can be electrically connected to the gate electrode of the first drive transistor T_D1. The first and second terminals of the first scan transistor T_SC1 can be different terminals. For example, when the first terminal is the source electrode, the second terminal can be the drain electrode. The gate electrode of the first scan transistor T_SC1 can be connected to the first scan line SCL1. When a first scan signal with a voltage (e.g., a high voltage) that can turn on the first scan transistor T_SC1 is supplied from the first scan line SCL1, the first scan transistor T_SC1 turns on to electrically connect the data line DL to the gate electrode of the first drive transistor T_D1. In this case, the frame data signal is supplied to the data line DL, and therefore, the data signal is transmitted to the gate electrode of the first drive transistor T_D1.

[0116] The first terminal of the first sensing transistor T_SS1 can be electrically connected to the readout line RL, and the second terminal of the first sensing transistor T_SS1 can be electrically connected to the second terminal of the first driving transistor T_D1 (or the first electrode EL1 of the emitter unit EMU). The gate electrode of the first sensing transistor T_SS1 can be connected to the first sensing line SSL1. When a first scan signal with a voltage (e.g., a high voltage) that can turn on the first sensing transistor T_SS1 is supplied from the first sensing line SSL1, the first sensing transistor T_SS1 turns on to electrically connect the readout line RL to the second terminal of the first driving transistor T_D1. In this case, an initialization voltage is supplied to the readout line RL, and therefore, an initialization voltage is applied to the second terminal of the first driving transistor T_D1. The initialization voltage can be set to a voltage level that prevents the emitter unit EMU from emitting light relative to the second power line PL2.

[0117] The first storage capacitor CST1 can be formed between the gate electrode of the first driving transistor T_D1 and the second terminal. One electrode of the first storage capacitor CST1 can be connected to the gate electrode of the first driving transistor T_D1, and the other electrode of the first storage capacitor CST1 can be connected to the second terminal of the first driving transistor T_D1 (or the first electrode EL1 of the emitter unit EMU).

[0118] The first storage capacitor CST1 is charged with a voltage corresponding to the data signal supplied to the gate electrode of the first driving transistor T_D1 (or stores a charge corresponding to the data signal supplied to the gate electrode of the first driving transistor T_D1) (for example, charged with or stored with a voltage or charge corresponding to the difference between the data voltage and the initialization voltage), and the charged voltage is maintained until the data signal of the next frame is supplied.

[0119] The first terminal of the second driving transistor T_D2 can be electrically connected to the first power line PL1, and the second terminal of the second driving transistor T_D2 can be electrically connected to the first electrode EL1 of the transmitter unit EMU. The first terminal of the second driving transistor T_D2 can be the source electrode, and the second terminal of the second driving transistor T_D2 can be the drain electrode. However, in some embodiments, the first terminal of the second driving transistor T_D2 can be the drain electrode, and the second terminal of the second driving transistor T_D2 can be the source electrode. The gate electrode of the second driving transistor T_D2 can be connected to the second terminal of the second scan transistor T_SC2. The second driving transistor T_D2 controls the amount of the second driving current (i.e., the driving current flowing in the second current flow direction opposite to the first current flow direction) supplied to the transmitter unit EMU in response to the voltage applied to the gate electrode.

[0120] The first terminal of the second scan transistor T_SC2 can be electrically connected to the data line DL, and the second terminal of the second scan transistor T_SC2 can be electrically connected to the gate electrode of the second drive transistor T_D2. The gate electrode of the second scan transistor T_SC2 can be connected to the second scan line SCL2. When a second scan signal with a voltage (e.g., a high voltage) that can turn on the second scan transistor T_SC2 is supplied from the second scan line SCL2, the second scan transistor T_SC2 turns on to electrically connect the data line DL to the gate electrode of the second drive transistor T_D2. In this case, the frame data signal is supplied to the data line DL, and therefore, the data signal is transmitted to the gate electrode of the second drive transistor T_D2.

[0121] The second storage capacitor CST2 can be formed between the gate electrode and the second terminal of the second driving transistor T_D2. One electrode of the second storage capacitor CST2 can be connected to the gate electrode of the second driving transistor T_D2, and the other electrode of the second storage capacitor CST2 can be connected to the second terminal of the second driving transistor T_D2 (or the first electrode EL1 of the emitter unit EMU).

[0122] The second storage capacitor CST2 is charged with a voltage corresponding to the data signal supplied to the gate electrode of the second driving transistor T_D2 (or stores a charge corresponding to the data signal supplied to the gate electrode of the second driving transistor T_D2) (for example, it is charged with or stores a voltage or charge corresponding to the difference between the data voltage and the initialization voltage), and the charged voltage is maintained until the data signal of the next frame is supplied.

[0123] exist Figure 4a In this context, although the second storage capacitor CST2 has been described as being formed between the gate electrode of the second driving transistor T_D2 and the second terminal, the second storage capacitor CST2 is not limited to this. For example... Figure 4b As shown, the second storage capacitor CST2 can be formed between the gate electrode of the second driving transistor T_D2 and the first terminal. In this case, the second storage capacitor CST2 is charged with a voltage corresponding to the data signal supplied to the gate electrode of the second driving transistor T_D2 (or stores a charge corresponding to the data signal supplied to the gate electrode of the second driving transistor T_D2) (for example, charged with or stored with a voltage or charge corresponding to the difference between the data voltage and the voltage applied to the first power line PL1), and the charged voltage is maintained until the data signal of the next frame is supplied.

[0124] exist Figure 4a and Figure 4b In this disclosure, although the transistors included in the pixel circuit PXC (e.g., the first driving transistor T_D1, the first scanning transistor T_SC1, the first sensing transistor T_SS1, the second driving transistor T_D2, and the second scanning transistor T_SC2) are shown as n-type transistors, this disclosure is not limited thereto. That is, at least one of the first driving transistor T_D1, the first scanning transistor T_SC1, the first sensing transistor T_SS1, the second driving transistor T_D2, and the second scanning transistor T_SC2 included in the pixel circuit PXC can be changed to p-type transistors. Furthermore, those skilled in the art will understand any necessary changes to the circuit and the applied voltage when using p-type transistors.

[0125] As described above, the pixel circuit PXC of pixel PXL can provide a first driving current to the emitting unit EMU in a first current flow direction in a first mode, and can provide a second driving current to the emitting unit EMU in a second current flow direction in a second mode. Therefore, in the first mode, the first light-emitting element LD1 in the emitting unit EMU can emit light, and in the second mode, the second light-emitting element LD2 in the emitting unit EMU can emit light. When the first mode and the second mode alternate at specific time intervals, the first light-emitting element LD1 and the second light-emitting element LD2 alternately emit light. Compared to the case where only the first light-emitting element LD1 or the second light-emitting element LD2 emits light in response to a current direction, the lifetime of the emitting unit EMU can be improved.

[0126] Figure 5a It is shown that it includes Figure 4a and Figure 4b A plan view of an example of an emission unit in a pixel. Figure 5b yes Figure 5a The equivalent circuit diagram of the transmitting unit. Figure 5c It is shown that it includes Figure 4a and Figure 4b Another example of a plan view of the emission unit in a pixel.

[0127] Reference Figures 1a to 5b The transmitting unit (EMU) can be formed in a specific area on the substrate (SUB) (see...). Figure 3 For example, the EMU (Emitting Unit) can be formed in the pixel region corresponding to a pixel PXL.

[0128] Pixel PXL may include a first electrode EL1, a second electrode EL2, and a third electrode EL3 (or an intermediate electrode) that are physically separated or spaced apart from each other. The first electrode EL1 and the second electrode EL2 may correspond to the references above. Figure 4a and Figure 4b The first electrode EL1 and the second electrode EL2 are described.

[0129] The first electrode EL1, the third electrode EL3, and the second electrode EL2 can be arranged sequentially along the first direction DR1. That is, the first electrode EL1 and the second electrode EL2 can be spaced apart from each other in the first direction DR1, and the third electrode EL3 can be disposed between the first electrode EL1 and the second electrode EL2.

[0130] Each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may extend in the second direction DR2, which intersects the first direction DR1.

[0131] However, the first electrode EL1, the second electrode EL2, and the third electrode EL3 are not limited thereto. For example, the shape and / or arrangement of the first electrode EL1, the second electrode EL2, and the third electrode EL3 can be varied. For example, the first electrode EL1, the second electrode EL2, and the third electrode EL3 can have a partially curved shape.

[0132] The first electrode EL1 can be connected to the reference above through the first contact hole. Figure 4a The first driving transistor T_D1 and the second driving transistor T_D2 are described, and the second electrode EL2 can be connected to the reference above through the second contact hole. Figure 4a The second power line PL2 (or the second drive voltage VSS) is described.

[0133] According to embodiments, each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 may have a single-layer structure or a multi-layer structure. For example, the first electrode EL1, the second electrode EL2, and the third electrode EL3 may have a multi-layer structure including a reflective electrode and a conductive coating. Furthermore, the reflective electrode may have a single-layer structure or a multi-layer structure. As an example, the reflective electrode may include at least one reflective conductive layer, and may optionally include at least one transparent conductive layer disposed above and / or below the reflective conductive layer.

[0134] The EMU may include at least one pair of first light-emitting elements LD1 and second light-emitting elements LD2. That is, the EMU may include a light-emitting element package LDP.

[0135] The first light-emitting element LD1 and the second light-emitting element LD2 can be disposed in different directions between the first electrode EL1 and the third electrode EL3. Between the first electrode EL1 and the third electrode EL3, the first end of the first light-emitting element LD1 (e.g., a p-type semiconductor layer) can face the first electrode EL1, and the second end of the first light-emitting element LD1 (e.g., an n-type semiconductor layer) can face the third electrode EL3. Similarly, between the first electrode EL1 and the third electrode EL3, the first end of the second light-emitting element LD2 (e.g., a p-type semiconductor layer) can face the third electrode EL3, and the second end of the second light-emitting element LD2 (e.g., an n-type semiconductor layer) can face the first electrode EL1.

[0136] In other words, one electrode of the light-emitting element package LDP (e.g., the first lead electrode E_LEAD1, see...) Figure 2a The first electrode EL1 can be facing the other electrode of the light-emitting element package LDP (e.g., the second lead electrode E_LEAD2, see...). Figure 2a It can face the third electrode EL3.

[0137] When multiple first light-emitting elements LD1 and multiple second light-emitting elements LD2 are provided, the multiple first light-emitting elements LD1 are connected in parallel between the first electrode EL1 and the third electrode EL3 in the direction of first current flow, and the multiple second light-emitting elements LD2 are connected in parallel between the first electrode EL1 and the third electrode EL3 in the direction of second current flow, thereby forming a... Figure 5b The first level SET1 is shown in the figure.

[0138] Furthermore, the first light-emitting element LD1 and the second light-emitting element LD2 can be disposed between the third electrode EL3 and the second electrode EL2 in different directions. The arrangement of the first light-emitting element LD1 and the second light-emitting element LD2 between the third electrode EL3 and the second electrode EL2 is substantially the same as or similar to the arrangement of the first light-emitting element LD1 and the second light-emitting element LD2 between the first electrode EL1 and the third electrode EL3, and its redundant description will not be repeated.

[0139] When multiple first light-emitting elements LD1 and multiple second light-emitting elements LD2 are provided, the multiple first light-emitting elements LD1 are connected in parallel between the third electrode EL3 and the second electrode EL2 in the direction of first current flow, and the multiple second light-emitting elements LD2 are connected in parallel between the third electrode EL3 and the second electrode EL2 in the direction of second current flow, thereby forming a... Figure 5b The second level SET2 is shown in the diagram.

[0140] exist Figure 5a In this illustration, although the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP) are shown aligned between the first electrode EL1, the second electrode EL2 and the third electrode EL3 in the first direction DR1, this disclosure is not limited thereto. For example, the light-emitting elements may also be arranged between the first electrode EL1, the second electrode EL2 and the third electrode EL3 in a diagonal direction.

[0141] The first light-emitting element LD1 and the second light-emitting element LD2 can be electrically connected between the first electrode EL1 and the second electrode EL2.

[0142] In an embodiment, between the first electrode EL1 and the third electrode EL3, the first end of the first light-emitting element LD1 can be electrically connected to the first electrode EL1 via at least one contact electrode (e.g., the first contact electrode CNE1). Similarly, the second end of the second light-emitting element LD2 can be electrically connected to the first electrode EL1 via the first contact electrode CNE1.

[0143] Furthermore, between the first electrode EL1 and the third electrode EL3, the second end of the first light-emitting element LD1 and the first end of the second light-emitting element LD2 can be connected to the third electrode EL3 via the third contact electrode CNE3. Similarly, between the third electrode EL3 and the second electrode EL2, the first end of the first light-emitting element LD1 and the second end of the second light-emitting element LD2 can be connected to the third electrode EL3 via the third contact electrode CNE3. However, this disclosure is not limited thereto. The third contact electrode CNE3 may not be connected to the third electrode EL3.

[0144] Furthermore, between the third electrode EL3 and the second electrode EL2, the second end of the first light-emitting element LD1 and the first end of the second light-emitting element LD2 can be electrically connected to the second electrode EL2 via the second contact electrode CNE2.

[0145] According to an embodiment, the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP) can be prepared in the form of dispersion in a solution (e.g., a set solution or a predetermined solution) and supplied to the pixel area by inkjet printing or slot coating. For example, the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP) can be mixed with a volatile solvent and supplied to the pixel area. In this case, when a voltage (e.g., a set voltage or a predetermined voltage) is applied between the first electrode EL1 and the third electrode EL3 and between the third electrode EL3 and the second electrode EL2, an electric field is formed between the first electrode EL1 and the third electrode EL3 and between the third electrode EL3 and the second electrode EL2, and the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP) are self-aligned between the first electrode EL1, the second electrode EL2, and the third electrode EL3. After the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP) are aligned, the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP) can be stably arranged between the first electrode EL1, the second electrode EL2 and the third electrode EL3 by evaporating the solvent or removing the solvent by any other method.

[0146] When a pair of first light-emitting elements LD1 and second light-emitting elements LD2 constitute a light-emitting element package LDP, the ratio of the first light-emitting elements LD1 arranged in the first current flow direction to the second light-emitting elements LD2 arranged in the second current flow direction can be equal to 1:1. That is, the total number of first light-emitting elements LD1 in the transmitting unit EMU can be substantially the same as the total number of second light-emitting elements LD2.

[0147] Therefore, the brightness of the display device can be presented uniformly throughout the entire display device.

[0148] Furthermore, because the alignment direction (e.g., forward or reverse direction) in the light-emitting element package (LDP) is independent, processes for improving the alignment of each of the light-emitting elements, which only have a specific polarity orientation, are not required when aligning the LDP. In other words, the manufacturing process can be simplified because no construction is needed to increase the alignment of the LDP.

[0149] Furthermore, the brightness of the first light-emitting element LD1, which emits light in the first mode, and the brightness of the second light-emitting element LD2, which emits light in the second mode, can be equal to each other. Therefore, even if pixel PXL operates alternately in the first and second modes, no brightness change will occur when the mode of pixel PXL is switched.

[0150] exist Figure 5a and Figure 5b Although the transmitting unit (EMU) has been described as including a first stage SET1 and a second stage SET2 connected in series, this disclosure is not limited thereto. Figure 5c As shown, the emitting unit EMU_1 may include a first electrode EL1_1 and a second electrode EL2_1, a first light-emitting element LD1 and a second light-emitting element LD2 disposed between the first electrode EL1_1 and the second electrode EL2_1, a first contact electrode CNE1_1 connecting the first end of the first light-emitting element LD1 and the second end of the second light-emitting element LD2 to the first electrode EL1_1, and a second contact electrode CNE2_1 connecting the second end of the first light-emitting element LD1 and the first end of the second light-emitting element LD2 to the second electrode EL2_1. That is, the first light-emitting element LD1 and the second light-emitting element LD2 in the emitting unit EMU can be connected in parallel in different directions. Optionally, the emitting unit EMU may include a light-emitting element package LDP connected in a hybrid series / parallel structure in various ways.

[0151] Figures 6a to 6c It is shown Figure 4a and Figure 4b A diagram illustrating examples of pixel operations. Figures 6a to 6c Accordingly, it shows Figure 4a and Figure 4b The timing diagram of the operation of pixel PXL in the first mode, the circuit diagram of pixel PXL, and the operation of the transmitting unit EMU.

[0152] Reference Figures 4a to 6c This describes how pixel PXL is driven in first mode in an odd number of frames across multiple frames (or frame segments). However, this is only an example, and pixel PXL can be driven in first mode over two or more consecutive frames.

[0153] In the first mode, a first drive voltage VDD with a high level (or high potential) can be applied to the first power line PL1. A second drive voltage VSS with a low level (or low potential) can be applied to the second power line PL2.

[0154] The first scan signal SC1 applied to the first scan line SCL1 can have a high level (or a turn-on voltage level, a gate turn-on voltage level, etc.). In this case, the first scan transistor T_SC1 can be turned on, and the data voltage DV (or image data DATA) applied to the data line DL can be applied to the gate electrode of the first drive transistor T_D1.

[0155] Simultaneously, the first sensing signal SS1 applied to the first sensing line SSL1 can have a high level. In this case, the first sensing transistor T_SS1 can be turned on, and the initialization voltage VINT applied to the readout line RL can be applied to the second terminal (or source electrode) of the first driving transistor T_D1.

[0156] The first storage capacitor CST1 can store the voltage (or charge) corresponding to the difference between the data voltage DV and the initialization voltage VINT. When the data voltage DV is written to the first storage capacitor CST1, the transmitter unit EMU may not emit light due to the initialization voltage VINT.

[0157] When the first scan signal SC1 and the first sensing signal SS1 change from high level to low level, the first driving transistor T_D1 can supply the first driving current ID1 flowing in the first current flow direction to the transmitting unit EMU in response to the voltage (or charge) stored in the first storage capacitor CST1.

[0158] In this case, the first driving current ID1 can flow through the first light-emitting element LD1 arranged in the first current flow direction in the transmitting unit EMU, and the first light-emitting element LD1 can emit light with a brightness corresponding to the first driving current ID1.

[0159] In the first mode, the second scan signal SC2 applied to the second scan line SCL2 can be kept at a low level (or a cutoff voltage level, gate cutoff voltage level, etc.). Therefore, the second scan transistor T_SC2 can remain in the off state, and the data voltage DV is not applied to the gate electrode of the second drive transistor T_D2. Furthermore, because the first drive current ID1 does not flow through the second light-emitting element LD2 arranged in the second current flow direction in the emitter unit EMU, the second light-emitting element LD2 will not emit light.

[0160] like Figure 6cAs shown, because the first light-emitting element LD1 in the emitting unit EMU emits uniform light, clustered dark spots or blemishes can be avoided.

[0161] Figures 7a to 7c It is shown Figure 4a and Figure 4b Another example of pixel manipulation is shown in the diagram. Figures 7a to 7c Accordingly, it shows Figure 4a and Figure 4b The timing diagram of the operation of pixel PXL in the second mode, the circuit diagram of pixel PXL, and the operation of the transmitting unit EMU.

[0162] Reference Figures 4a to 5c as well as Figures 7a to 7c This describes how pixel PXL is driven in second mode during an even number of frames (or frames) across multiple frames (or frames). However, this is just an example, and pixel PXL can be driven in second mode over two or more consecutive frames.

[0163] In the second mode, a first driving voltage VDD with a low level (or low potential) can be applied to the first power line PL1, and a second driving voltage VSS with a high level (or high potential) can be applied to the second power line PL2. Compared to the first mode, the voltage levels applied to the first power line PL1 and the second power line PL2 are interchanged. When the pixel PXL or pixel circuit PXC is driven alternately in the first mode and the second mode for a specific time period (e.g., at least one frame), the voltage levels of the first driving voltage VDD (or first power supply voltage) applied to the first power line PL1 and the voltage levels of the second driving voltage VSS (or second power supply voltage) applied to the second power line PL2 can be interchanged for a specific time period.

[0164] The second scan signal SC2 applied to the second scan line SCL2 can have a high level (or a turn-on voltage level, a gate turn-on voltage level, etc.). In this case, the second scan transistor T_SC2 can be turned on, and the data voltage DV applied to the data line DL can be applied to the gate electrode of the second drive transistor T_D2.

[0165] Simultaneously, the first sensing signal SS1 applied to the first sensing line SSL1 can have a high level. In this case, the first sensing transistor T_SS1 can be turned on, and the initialization voltage VINT applied to the readout line RL can be applied to the second terminal (or drain electrode) of the second driving transistor T_D2. The transmitting unit EMU may not emit light due to the initialization voltage VINT.

[0166] The second storage capacitor CST2 can store the voltage (or charge) corresponding to the difference between the data voltage DV and the initialization voltage VINT. In another embodiment, as... Figure 7b As shown, the second storage capacitor CST2 can store the voltage corresponding to the difference between the data voltage DV and the voltage level of the second drive voltage VSS applied to the second power line PL2.

[0167] When the second scan signal SC2 and the first sensing signal SS1 change from high level to low level, the second driving transistor T_D2 can supply the second driving current ID2 flowing in the second current flow direction to the transmitter unit EMU in response to the voltage stored in the second storage capacitor CST2.

[0168] In this case, the second driving current ID2 can flow through the second light-emitting element LD2 arranged in the second current flow direction in the transmitting unit EMU, and the second light-emitting element LD2 can emit light with a brightness corresponding to the second driving current ID2.

[0169] In the second mode, the first scan signal SC1 applied to the first scan line SCL1 can be kept at a low level (or a cutoff voltage level, gate cutoff voltage level, etc.). Therefore, the first scan transistor T_SC1 can remain in the off state, and the data voltage DV is not applied to the gate electrode of the first drive transistor T_D1. Furthermore, because the second drive current ID2 does not flow through the first light-emitting element LD1 arranged in the first current flow direction in the emitter unit EMU, the first light-emitting element LD1 will not emit light.

[0170] like Figure 7c As shown, because the second light-emitting element LD2 in the emitting unit EMU emits uniform light, clustered dark spots or blemishes can be avoided. Furthermore, with... Figure 6c In contrast, because the second light-emitting element LD2 emits light in the same ratio (or number) as the first light-emitting element LD1, there is no change in the brightness of the emission unit EMU between the first mode and the second mode. Therefore, when the pixel PXL is driven alternately in the first mode and the second mode, the first light-emitting element LD1 and the second light-emitting element LD2 can be used evenly, thereby doubling the lifespan of the display device.

[0171] Figure 8 This is a block diagram illustrating a display device according to an embodiment. According to the embodiment, Figure 8 The display device may include Figure 4a and Figure 4b The pixel count of PXL.

[0172] Reference Figure 8The display device DD may include a display 110 (or display panel), a scan driver 120 (or gate driver), a data driver 130 (or source driver), a sensor driver 140, a timing controller 150, and a power supply 160.

[0173] The display 110 may include first scan lines SCL1-1 to SCL1-n (where n is a positive integer), second scan lines SCL2-1 to SCL2-n (where n is a positive integer), data lines DL1 to DLm (where m is a positive integer), and pixels PXL. Furthermore, the display 110 may also include sensing lines SSL1-1 to SSL1-n and readout lines RL1 to RLm.

[0174] Pixel PXL can be set in a region (e.g., a pixel region) divided by the first scan lines SCL1-1 to SCL1-n, the second scan lines SCL2-1 to SCL2-n, and the data lines DL1 to DLm.

[0175] Pixel PXL can be connected to a corresponding line among the first scan lines SCL1-1 to SCL1-n, a corresponding line among the second scan lines SCL2-1 to SCL2-n, and a corresponding line among the data lines DL1 to DLm. Additionally, pixel PXL can be connected to a corresponding line among the sensing lines SSL1-1 to SSL1-n and a corresponding line among the readout lines RL1 to RLm.

[0176] As shown above (refer to the reference) Figure 4a and Figure 4b As described, the pixel PXL may include a first light-emitting element LD1 and a second light-emitting element LD2, and at least one transistor that provides drive current to the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP) or is configured to provide drive current to the first light-emitting element LD1 and the second light-emitting element LD2 (or the light-emitting element package LDP).

[0177] In the first mode, pixel PXL can emit light with a brightness corresponding to the data voltage (e.g., data signal) provided by a data line (e.g., the j-th data line DLj, where j is a positive integer less than or equal to m) in response to a first scan signal provided by a first scan line (e.g., the 1-i scan line SCL1-i, where i is a positive integer less than or equal to n). Furthermore, in the second mode, pixel PXL can emit light with a brightness corresponding to the data voltage provided by a data line (e.g., the j-th data line DLj) in response to a second scan signal provided by a second scan line (e.g., the 2-i scan line SCL2-i).

[0178] Because the above has already been referenced. Figures 4a to 7cThe detailed construction and operation of pixel PXL are described, so their description will be omitted.

[0179] The scan driver 120 can generate a first scan signal or a second scan signal based on the scan control signal SCS, and can sequentially provide the first scan signal or the second scan signal to the first scan lines SCL1-1 to SCL1-n or the second scan lines SCL2-1 to SCL2-n. The scan control signal SCS may include a scan start signal (or scan start pulse), a scan clock signal, etc., and may be provided from the timing controller 150. For example, the scan driver 120 may include a shift register (or stage) for sequentially generating and outputting the first scan signal or the second scan signal in pulse form corresponding to the pulse form of the scan start signal (e.g., a gate on-voltage level pulse) using the scan clock signal.

[0180] Similar to the first scan signal and the second scan signal, the scan driver 120 can also generate a first sensing signal (or sensing control signal) and can sequentially apply the first sensing signal to sensing lines SSL1-1 to SSL1-n.

[0181] The data driver 130 can generate a data signal (or data voltage) based on the data control signal DCS provided from the timing controller 150 and the image data DATA2, and can provide the data signal to the data lines DL1 to DLm. The data control signal DCS is a signal used to control the operation of the data driver 130, and may include a load signal (or data enable signal) indicating the output of a valid data voltage.

[0182] The sense driver 140 can provide an initialization voltage to the readout lines RL1 to RLm based on a sense control signal CCS. The sense control signal CCS can be provided from the timing controller 150. According to an embodiment, the sense driver 140 can sense the light emission characteristics (light emission characteristics) of the pixel PXL through the readout lines RL1 to RLm.

[0183] The timing controller 150 can receive input image data DATA1 and a control signal CS from an external source (e.g., a graphics processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and convert the input image data DATA1 to generate image data DATA2. The control signal CS may include commonly known vertical synchronization signals, horizontal synchronization signals, clock signals, etc. For example, the timing controller 150 can convert the input image data DATA1 into image data DATA2 with a format that can be used by the data driver 130.

[0184] Furthermore, the timing controller 150 can generate a sensing control signal CCS based on the control signal CS. The sensing control signal CCS can be provided to the sensing driver 140.

[0185] Power supply 160 can provide a first driving voltage VDD (or a first power supply voltage) and a second driving voltage VSS (or a second power supply voltage) to display 110. In an embodiment, power supply 160 can provide the first driving voltage VDD to the first power line PL1 and the second driving voltage VSS to the second power line PL2.

[0186] In an embodiment, the power supply 160 can generate a high-potential first driving voltage VDD and a low-potential second driving voltage VSS in a first mode, and can generate a low-potential first driving voltage VDD and a high-potential second driving voltage VSS in a second mode.

[0187] Power supply 160 can provide drive voltage to at least one of scan driver 120, data driver 130 and sense driver 140.

[0188] exist Figure 8 In this illustration, scan driver 120, data driver 130, sense driver 140, and timing controller 150 are shown constructed independently of each other; however, this is merely an example, and the disclosure is not limited thereto. For example, at least one of scan driver 120, data driver 130, sense driver 140, and timing controller 150 may be formed on display 110, or may be implemented as an integrated circuit (IC) mounted on a flexible circuit board and connected to display 110. For example, scan driver 120 may be formed on display 110. Furthermore, at least two of scan driver 120, data driver 130, sense driver 140, and timing controller 150 may be implemented as a single IC. For example, data driver 130 and sense driver 140 may be implemented as a single IC.

[0189] Figure 9a and Figure 9b It is shown that it includes Figure 3 A circuit diagram of another embodiment of pixels in a display device. Figure 9a and Figure 9b It shows that it includes Figure 3 The electrical connections between elements in a pixel PXL are shown.

[0190] exist Figure 9a and Figure 9b In China, it will not only include Figure 3 Each element in the pixels shown is called a pixel PXL, and the area in which the element is set is also called a pixel PXL.

[0191] Reference Figures 1a to 4b , Figure 9a and Figure 9b Pixel PXL_1 and Figure 4a and Figure 4b The difference in pixel PXL shown is that pixel PXL_1 also includes a first power transistor T_P1, a second power transistor T_P2, a third power transistor T_P3, and a fourth power transistor T_P4 (or first to fourth power control transistors, first to fourth switches, etc.). Because Figure 9a and Figure 9b Pixel PXL_1, except for the first power transistor T_P1, the second power transistor T_P2, the third power transistor T_P3, and the fourth power transistor T_P4, is similar to... Figure 4a and Figure 4b The pixels PXL are basically the same or similar, so their redundant descriptions will not be repeated.

[0192] The first terminal of the first power transistor T_P1 can be electrically connected to the third power line PL3, and the second terminal of the first power transistor T_P1 can be electrically connected to the first power line PL1 (or the first node N1). The first and second terminals of the first power transistor T_P1 can be different terminals. For example, when the first terminal is the source electrode, the second terminal can be the drain electrode. The gate electrode of the first power transistor T_P1 can be connected to the control line CL (or the switch control line). The first drive voltage VDD (or the first power supply voltage) can be applied to the third power line PL3.

[0193] The first terminal of the second power transistor T_P2 can be electrically connected to the first power line PL1, and the second terminal of the second power transistor T_P2 can be electrically connected to the fourth power line PL4. The gate electrode of the second power transistor T_P2 can be connected to the control line CL. The second drive voltage VSS (or the second power supply voltage) can be applied to the fourth power line PL4.

[0194] In some embodiments, the first power transistor T_P1 and the second power transistor T_P2 can be transistors of different types. One of the first power transistor T_P1 and the second power transistor T_P2 can be an n-type transistor, and the other of the first power transistor T_P1 and the second power transistor T_P2 can be a p-type transistor. Figure 9a and Figure 9bAs shown, the first power transistor T_P1 can be an n-type transistor, and the second power transistor T_P2 can be a p-type transistor. In this case, either the first power transistor T_P1 or the second power transistor T_P2 can be turned on in response to a switching control signal provided through the control line CL, and the first drive voltage VDD of the third power line PL3 or the second drive voltage VSS of the fourth power line PL4 can be applied to the first power line PL1.

[0195] To drive Figure 4a and Figure 4b The pixel count of the PXL, power supply 160 (see...) Figure 8 The voltage levels of the first driving voltage VDD and the second driving voltage VSS must be interchanged. According to some embodiments, in... Figure 9a and Figure 9b In pixel PXL_1, the voltage levels of the first driving voltage VDD and the second driving voltage VSS can be fixed at high and low potentials, respectively, and pixel PXL_1 can be driven by controlling the first power transistor T_P1 and the second power transistor T_P2 using only one switch control signal.

[0196] Furthermore, when pixel PXL_1 includes a first power transistor T_P1 and a second power transistor T_P2, the first driving voltage VDD and the second driving voltage VSS applied to pixel PXL_1 can be controlled individually (e.g., for each pixel row).

[0197] The first terminal of the third power transistor T_P3 can be electrically connected to the fourth power line PL4, and the second terminal of the third power transistor T_P3 can be electrically connected to the second power line PL2 (or the second node N2). The gate electrode of the third power transistor T_P3 can be connected to the control line CL.

[0198] The first terminal of the fourth power transistor T_P4 can be electrically connected to the second power line PL2, and the second terminal of the fourth power transistor T_P4 can be electrically connected to the third power line PL3. The gate electrode of the fourth power transistor T_P4 can be connected to the control line CL.

[0199] In some embodiments, the third power transistor T_P3 and the fourth power transistor T_P4 can be transistors of different types. The third power transistor T_P3 can be the same type of transistor as the first power transistor T_P1, and the fourth power transistor T_P4 can be the same type of transistor as the second power transistor T_P2. For example... Figure 9a and Figure 9bAs shown, the third power transistor T_P3 can be an n-type transistor, and the fourth power transistor T_P4 can be a p-type transistor. In this case, either the third power transistor T_P3 or the fourth power transistor T_P4 can be turned on in response to a switching control signal provided via the control line CL, and the second drive voltage VSS of the fourth power line PL4 or the first drive voltage VDD of the third power line PL3 can be applied to the second power line PL2.

[0200] As described above, pixel PXL_1 may further include a first power transistor T_P1, a second power transistor T_P2, a third power transistor T_P3, and a fourth power transistor T_P4 to interchange the first driving voltage VDD and the second driving voltage VSS and apply the first driving voltage VDD and the second driving voltage VSS to the first power line PL1 and the second power line PL2. Therefore, the driving voltage of pixel PXL_1 can be easily controlled by using signals with relatively low voltage levels applied to the first power transistor T_P1, the second power transistor T_P2, the third power transistor T_P3, and the fourth power transistor T_P4 (e.g., the driving voltage of pixel PXL_1 can be easily controlled simply by using signals with relatively low voltage levels applied to the first power transistor T_P1, the second power transistor T_P2, the third power transistor T_P3, and the fourth power transistor T_P4).

[0201] Figure 9a and Figure 9b The pixel PXL_1 can be applied to Figure 8 The display device DD.

[0202] Figure 10a and Figure 10b It is shown Figure 9a and Figure 9b A diagram illustrating examples of pixel operations. Figure 10a and Figure 10b Accordingly, it shows Figure 9a and Figure 9b Timing diagram and circuit diagram of pixel PXL_1 in the first mode.

[0203] Reference Figure 6a , Figure 6b as well as Figures 9a to 10b Because the signal applied to pixel PXL_1, besides the switch control signal EL_SW applied to control line CL, is the same as the one referenced above. Figure 6a and Figure 6b The signals described are basically the same, so their redundant descriptions will not be repeated.

[0204] In the first mode, a high-level switch control signal EL_SW can be applied to the control line CL. In this case, the first power transistor T_P1 can be turned on, and a high-level first drive voltage VDD can be applied to the first power line PL1. Furthermore, the third power transistor T_P3 can be turned on, and a low-level second drive voltage VSS can be applied to the second power line PL2. Therefore, according to the above reference... Figure 4a and Figure 4b The operation of the first driving transistor T_D1 is described, wherein the first driving current ID1 can flow between the first electric field line PL1 and the second electric field line PL2 in the first current flow direction, and the first light-emitting element LD1 can emit light.

[0205] In the first mode, the second power transistor T_P2 and the fourth power transistor T_P4 can remain in the off state in response to a high-level switching control signal EL_SW.

[0206] Figure 11a and Figure 11b It is shown Figure 9a and Figure 9b Another example of pixel manipulation is shown in the diagram. Figure 11a and Figure 11b Accordingly, it shows Figure 9a and Figure 9b Timing diagram and circuit diagram of pixel PXL_1 in the second mode operation.

[0207] In the second mode, a low-level switch control signal EL_SW can be applied to the control line CL. In this case, the second power transistor T_P2 can be turned on, and a low-level second drive voltage VSS can be applied to the first power line PL1. Furthermore, the fourth power transistor T_P4 can be turned on, and a high-level first drive voltage VDD can be applied to the second power line PL2. Therefore, according to the above reference... Figure 4a and Figure 4b The operation of the second driving transistor T_D2 is described, wherein the second driving current ID2 can flow between the second electric field line PL2 and the first electric field line PL1 in the direction of the second current flow, and the second light-emitting element LD2 can emit light.

[0208] In the second mode, the first power transistor T_P1 and the third power transistor T_P3 can remain in the off state in response to a low-level switching control signal EL_SW.

[0209] Although this disclosure has been described with reference to the described embodiments, those skilled in the art will understand that various modifications and changes can be made to this disclosure without departing from the spirit and scope of the disclosure set forth in the appended claims and their equivalents.

[0210] Therefore, the technical scope of this disclosure should not be limited to what is described in the detailed description, but should be determined by the appended claims and their equivalents.

Claims

1. A pixel, the pixel comprising: The transmitting unit is connected between the first power line and the second power line; as well as The pixel circuit is configured to provide a first driving current to the transmitting unit in a first current flow direction in a first mode, and to provide a second driving current to the transmitting unit in a second current flow direction different from the first current flow direction in a second mode. The transmitting unit includes: The first electrode and the second electrode are spaced apart from each other; A first light-emitting element is connected between the first electrode and the second electrode in the direction of the first current flow; A second light-emitting element is connected between the first electrode and the second electrode in the direction of the second current flow; and Multiple light-emitting element packages are connected between the first electrode and the second electrode. Each of the plurality of light-emitting element packages includes a first lead electrode, a second lead electrode, and a pair of light-emitting elements arranged between the first lead electrode and the second lead electrode in different current flow directions. The pair of light-emitting elements includes the first light-emitting element and the second light-emitting element.

2. The pixel of claim 1, wherein, The pixel circuit includes: A first driving transistor is connected between the first power line and the first electrode; A first scan transistor is connected between a data line and the gate electrode of the first driving transistor, the first scan transistor having a gate electrode connected to the first scan line; and A first storage capacitor is connected between the gate electrode of the first driving transistor and the first electrode, wherein the second electrode is connected to the second power line.

3. The pixel of claim 2, wherein, The pixel circuit further includes: a first sensing transistor connected between the readout line and the first electrode, the first sensing transistor having a gate electrode connected to the first sensing line.

4. The pixel of claim 3, wherein, The pixel circuit also includes: A second driving transistor is connected between the first power line and the first electrode; and A second scan transistor is connected between the data line and the gate electrode of the second drive transistor, and the second scan transistor has a gate electrode connected to the second scan line.

5. The pixel of claim 4, wherein, The pixel circuit further includes a second storage capacitor connected between the gate electrode of the second driving transistor and one electrode of the second driving transistor.

6. The pixel of claim 5, wherein, The second storage capacitor is connected between the gate electrode of the second driving transistor and the first electrode.

7. The pixel of claim 5, wherein, The second storage capacitor is connected between the gate electrode of the second driving transistor and the first power line.

8. The pixel of claim 5, wherein, In the first mode, the first scanning transistor and the first sensing transistor are turned on, and the second scanning transistor is turned off. In the second mode, the second scanning transistor and the first sensing transistor are turned on, and the first scanning transistor is turned off.

9. The pixel of claim 8, wherein, The pixel circuit is driven alternately in the first mode and the second mode for a first time period, and The first time period is greater than or equal to one frame.

10. The pixel of claim 9, wherein, The voltage level of the first power supply voltage applied to the first power line and the voltage level of the second power supply voltage applied to the second power line are interchanged during the first time period.

11. The pixel according to claim 1, wherein the pixel further comprises: A first power control transistor is connected between the first power line and the third power line, and the first power control transistor has a gate electrode connected to the control line; as well as A second power control transistor is connected between the first power line and the fourth power line, and the second power control transistor has a gate electrode connected to the control line. In this embodiment, one of the first power control transistor and the second power control transistor is an n-type transistor, and the other of the first power control transistor and the second power control transistor is a p-type transistor.

12. The pixel according to claim 11, wherein the pixel further comprises: A third power control transistor is connected between the second power line and the fourth power line, and the third power control transistor has a gate electrode connected to the control line; as well as A fourth power control transistor is connected between the second power line and the third power line, and the fourth power control transistor has a gate electrode connected to the control line. The third power control transistor is a transistor of the same type as the first power control transistor, and the fourth power control transistor is a transistor of the same type as the second power control transistor.

13. The pixel of claim 1, wherein, The first end of the first light-emitting element and the second end of the second light-emitting element are electrically connected to the first electrode. Wherein, the second end of the first light-emitting element and the first end of the second light-emitting element are electrically connected to the second electrode, and Wherein, the first end of the first light-emitting element and the first end of the second light-emitting element correspond to the same type of semiconductor layer.

14. The pixel of claim 1, wherein, The total number of the first light-emitting elements in the emitting unit is equal to the total number of the second light-emitting elements in the emitting unit.

15. The pixel of claim 1, wherein, Some of the multiple light-emitting element packages are connected in series between the first electrode and the second electrode.

16. A display device, the display device comprising: Pixel; A scan driver is used to supply a scan signal to the pixel via a scan line and to supply a sensing signal to the pixel via a sensing line; as well as A data driver is used to supply data signals to the pixel via data lines and to supply initialization signals to the pixel via readout lines. Each pixel in the pixel includes: The transmitting unit is connected between the first power line and the second power line; and A pixel circuit is configured to provide a first drive current to the transmitting unit in a first current flow direction in response to a first scan signal from the scan signals and a first sensing signal from the sensing signals in a first mode, and to provide a second drive current to the transmitting unit in a second current flow direction different from the first current flow direction in response to a second scan signal from the scan signals and the first sensing signal in a second mode. The transmitting unit includes: The first electrode and the second electrode are spaced apart from each other; A first light-emitting element is connected between the first electrode and the second electrode in the direction of the first current flow; A second light-emitting element is connected between the first electrode and the second electrode in the direction of the second current flow; and Multiple light-emitting element packages are connected between the first electrode and the second electrode. Each of the plurality of light-emitting element packages includes a first lead electrode, a second lead electrode, and a pair of light-emitting elements arranged between the first lead electrode and the second lead electrode in different current flow directions. The pair of light-emitting elements includes the first light-emitting element and the second light-emitting element.

17. The display device of claim 16, wherein, The total number of the first light-emitting elements in the emitting unit is equal to the total number of the second light-emitting elements in the emitting unit.

18. The display device of claim 16, further comprising: A power source is configured to supply a first power supply voltage to the pixel via the first power line, and to supply a second power supply voltage to the pixel via the second power line. The voltage levels of the first power supply voltage and the second power supply voltage are interchanged during a first time period.

19. The display device of claim 18, wherein, The power supply is also configured to supply the first power supply voltage to the third power line and the second power supply voltage to the fourth power line. Each pixel in the pixel further includes: A first power control transistor is connected between the first power line and the third power line, the first power control transistor having a gate electrode connected to a control line; and A second power control transistor is connected between the first power line and the fourth power line, and the second power control transistor has a gate electrode connected to the control line. Wherein, one of the first power control transistor and the second power control transistor is an n-type transistor, and Among them, the other one of the first power control transistor and the second power control transistor is a p-type transistor.

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