A simulation method for PSI5 cardboard

Abstract

This invention provides a simulation method for PSI5 circuit boards, belonging to the field of automotive electronics testing technology. Using an FPGA as the core control unit, it directly generates and parses the PSI5 protocol timing through hardware logic. First, it completes the initial configuration of the circuit board system, then flexibly selects the master / slave dual communication mode and completes the corresponding parameter configuration. Based on a DAC / ADC chip and a differential amplifier constant current circuit, it realizes hardware-level PSI5 protocol signal generation, combined with hardware closed-loop monitoring to complete real-time monitoring of synchronization pulse capture in slave mode and current readback in master mode. Simultaneously, a fault injection module enables controllable triggering of multiple types of faults and supports synchronous simulation of multi-channel independent logic resources. Combined with a dual-mode communication module, it completes remote parameter adjustment and data interaction. This invention achieves nanosecond-level synchronization accuracy, full parameter software adjustability, and full fault injection coverage, improving the real-time performance, reliability, and test coverage of PSI5 circuit board simulation.

Description

Technical Field

[0001] This invention relates to the field of automotive electronic testing technology, and in particular to a simulation method for a PSI5 card board. Background Technology

[0002] PSI5, a digital interface protocol specifically designed for automotive sensors, has become the core standard for communication between sensors and ECUs in automotive electronic systems due to its high reliability, strong anti-interference capabilities, and bidirectional differential signal transmission characteristics. It is widely used in safety-critical components such as wheel speed sensors, pressure sensors, and collision detection sensors. During the R&D, production line testing, and system integration phases of automotive electronic systems, extensive repeatable functional verification, HIL testing, and fault injection experiments are required on the PSI5 communication link, making it a crucial step in ensuring automotive functional safety.

[0003] In existing technologies, the testing of PSI5 communication links mainly uses real PSI5 sensors or traditional PSI5 simulation schemes, which have many technical shortcomings:

[0004] When using real PSI5 sensors for testing, it is difficult to simulate boundary and fault conditions, and it is impossible to flexibly realize key scenarios of ISO 26262 functional safety testing such as signal over-limit, timing errors, short circuit / open circuit, etc.; moreover, the sensor output parameters are fixed and it is impossible to adjust parameters such as sensitivity and bias in real time, resulting in low test coverage; at the same time, there are problems such as high material cost, long test cycle, test conditions that cannot be accurately reproduced, and high safety risks, and it is also difficult to integrate with automated test pipelines.

[0005] Existing PSI5 simulation patent solutions have obvious technical shortcomings. For example, in patent 202510483786.5, the operating current, reference current, synchronization pulse voltage, and detection pulse voltage are all non-adjustable, limiting application scenarios and resulting in a single technology. Patent 202511160973.6 uses a microcontroller as the main control chip for data transmission, which is affected by factors such as interrupts and scheduling, and cannot meet the high-speed and real-time requirements of the PSI5 protocol, resulting in poor timing consistency.

[0006] Existing conventional PSI5 simulation solutions generally lack hardware closed-loop signal monitoring and readback mechanisms, making it difficult to directly observe the internal state and timing details of sensor communication, which is not conducive to in-depth protocol analysis and fault root cause localization. The fault injection types are limited and cannot cover complex fault scenarios such as power supply, line, signal integrity, and multi-sensor collaboration. The synchronization accuracy is low during multi-channel simulation, which cannot meet the testing requirements of parallel sampling of multiple sensors in intelligent driving.

[0007] In summary, existing technologies lack a PSI5 board simulation method that offers high real-time performance, fully adjustable parameters in software, comprehensive fault injection coverage, hardware closed-loop monitoring, and good multi-channel synchronization. This makes it difficult to meet the high reliability, high real-time performance, and high coverage requirements for PSI5 protocol testing during the evolution of current automotive electronic and electrical architectures towards domain control and central computing.

[0008] Therefore, this invention proposes a simulation method for PSI5 cardboard. Summary of the Invention

[0009] This invention provides a simulation method for PSI5 cardboard to solve the aforementioned technical problems.

[0010] This invention provides a simulation method for a PSI5 card board, comprising:

[0011] Step 1: Initialize and configure the PSI5 card system, complete FPGA logic resource allocation, DAC / ADC chip calibration, differential amplifier constant current circuit zeroing, fault injection module reset, and dual-mode communication module communication link establishment;

[0012] Step 2: Select the host communication mode or slave communication mode according to the test requirements, receive remote configuration instructions through the dual-mode communication module, set the key parameters of the corresponding mode in software, and write them into the FPGA register. The key parameters include reference current, operating current, synchronization pulse amplitude, baud rate, encoding method and number of channels.

[0013] Step 3: In slave communication mode, the FPGA generates an encoded signal conforming to the PSI5 protocol, which is then converted from digital to analog by a DAC and conditioned by a differential amplifier constant current circuit before being output to the external ECU. In master communication mode, the hardware acquisition circuit receives the PSI5 protocol signal from the external sensor, which is then conditioned and sent to the FPGA for protocol parsing. The differential amplifier constant current circuit is constructed from operational amplifiers and transistors. The FPGA performs hardware closed-loop correction of the amplification factor of the differential amplifier constant current circuit based on real-time acquired loop current data.

[0014] Step 4: In slave communication mode, the synchronous pulse edge is captured by a comparator and a programmable voltage threshold and sent to the FPGA for high-precision timing analysis; in master communication mode, the voltage change of the series sampling resistor is detected, and the loop current is monitored in real time after being conditioned by an operational amplifier, and the monitoring data is read back to the FPGA.

[0015] Step 5: According to the test requirements, send a trigger command to the fault injection module through the FPGA to realize the controllable injection of multiple types of faults in the PSI5 communication link. The multiple types of faults include at least one of power failure, line failure, signal integrity failure, timing failure, encoding and data failure, and frame structure failure.

[0016] Step 6: Based on the FPGA, the first result generated in Step 3, the second result generated in Step 4, and the third result generated in Step 5 are summarized in real time, and the data is uploaded to the remote control terminal through the dual-mode communication module to complete the visualization and data traceability of the simulation process.

[0017] Preferably, after step 6, the following steps are also included:

[0018] After the test is completed, the FPGA generates a simulation test report, which includes parameter configuration information, signal timing data, fault injection records, and hardware closed-loop monitoring data. The report is then uploaded to the remote control terminal via a dual-mode communication module, enabling the test cases to be reproducible and the data to be traceable.

[0019] Preferably, the triggering method of the triggering instruction of the fault injection module includes at least one of manual single triggering, timed cyclic triggering, and multi-fault combination triggering, and the software configuration of the fault injection parameters includes: fault duration, fault amplitude, and fault triggering sequence.

[0020] Preferably, before completing the FPGA logic resource allocation, the following steps are included:

[0021] Based on the channel number configuration requirements of the PSI5 card, the global logic resource pool of the FPGA is pre-divided, and the global resource pool is divided into a protocol processing sub-resource pool, a timing scheduling sub-resource pool, a data interaction sub-resource pool, and a fault control sub-resource pool according to the functional dimension.

[0022] The test requirements are analyzed and the current priority of each sub-resource pool is obtained. Based on the combination of current priorities, several simulation test cases are matched from the combination-simulation lookup table.

[0023] Real-time monitoring of resource occupancy and channel load status of each sub-resource pool under each simulation test case; combined with the time-series data of resource interaction variables of the corresponding simulation test case, predicting the PSI5 frame period window in which the target channel blockage occurs.

[0024] When it is predicted that the target channel will be blocked within N PSI5 frame periods, a four-dimensional demand vector of protocol processing computing power, timing counting accuracy, data buffer capacity and fault response latency of the target channel is extracted based on the logical resource demand model determined by the test scenario type of the corresponding simulation test case.

[0025] Capture the resource interaction variables between each sub-resource pool and each other sub-resource pool during the simulation of the corresponding simulation test case, and obtain the scheduling threshold of redundant logical resources of the corresponding sub-resource pool and the PSI5 protocol timing alignment window;

[0026] Traverse the FPGA global idle sub-resource pool, divide redundant logic resources into lightweight sequential logic, medium-weight cache logic, and heavyweight protocol processing logic according to their functional types, and prioritize the selection of redundant logic resources that meet the scheduling threshold, have the highest matching degree between their functional type and the four-dimensional demand vector, and whose loading timing falls within the PSI5 protocol timing alignment window, and regard them as the first resource;

[0027] During the idle time slot of the PSI5 frame of the target channel, the first resource is dynamically loaded into the logical area of ​​the target channel;

[0028] After scheduling is completed, the load status of the target channel and the interaction performance of the sub-resource pool are monitored in real time. Based on the monitoring results, the computing power allocation ratio of redundant logical resources is adaptively adjusted. At the same time, the demand vector, resource matching results and timing alignment data of this scheduling are updated to the combination-simulation comparison table.

[0029] Preferably, the scheduling threshold for the redundant logical resources is the upper limit of computing power ratio and the lower limit of cache capacity.

[0030] Preferably, after setting the key parameters for the corresponding mode in software and writing them into the FPGA registers, the process includes:

[0031] The first parameter set is obtained by reading the write parameters of the FPGA registers and comparing the first parameter set with the standard parameter set of the corresponding mode. If they are completely consistent, the software setting is deemed qualified.

[0032] Otherwise, multiple software-based random settings are performed, and the comparison group and the write group written to the FPGA register are obtained for each random setting. The comparison group and the write group are then compared to obtain the first difference group.

[0033] If all first difference groups consist of 0 parameters, then restart the PSI5 card system;

[0034] Otherwise, construct a value difference matrix based on all the first difference groups and perform normalization to obtain a normalized matrix;

[0035] Simultaneously, the process log of each random setting and writing process is captured, and the running sub-logic of each random setting is constructed. The running sub-logic is compared with the standard sub-logic to determine that the running sub-logic is based on at least one sub-difference logic of the standard sub-logic. In this case, the same standard sub-logic is used for each random setting operation.

[0036] The logical attribute pairs of each sub-difference logic are matched with the attribute-logic lookup table to obtain new logic, and the new logic and the corresponding sub-difference logic are preprocessed to obtain sub-coverage logic;

[0037] The sub-overlay logic corresponding to each sub-difference logic is executed sequentially. When the execution bit of the corresponding sub-overlay logic is detected to reach the preset bit, the execution code of the corresponding sub-difference logic is obtained.

[0038] When it is detected that the execution bit of the corresponding sub-coverage logic has not reached the preset bit, the register state of the corresponding sub-coverage logic is read and the status bit of the register state is responded to. The sub-compensation logic that has reached the preset bit from the status bit is retrieved from the historical database, and the execution code of the corresponding sub-difference logic based on the sub-compensation logic and the sub-coverage logic is obtained.

[0039] Extract the new setting description of each key parameter from all executed code under each random setting, and combine them according to the parameter sorting order of the standard parameter group to obtain the current description group under each random setting. Compare the current description group with the standard description group corresponding to the standard parameter group to obtain the second difference group, and construct the description difference matrix.

[0040] Based on the normalized matrix and the description difference matrix, obtain the difference type pairs of each key parameter, determine the abnormal environment object according to the difference type pairs, extract the optimization file that matches the abnormal environment object, and extract the compensation identifier and compensation position of the response difference type pairs from the optimization file.

[0041] The compensation logic is determined based on the compensation identifier, and the insertion point of the compensation logic in the original parameter setting logic is determined according to the compensation position and inserted to obtain the new setting logic. At this time, the PSI5 card system is restarted.

[0042] Preferably, the behavior of the normalization matrix corresponds to the normalization group of the first difference group in the next random setting, and the columns of the normalization matrix are the normalized differences of the corresponding key parameters under different random settings, and the normalized differences are difference values; the behavior of the description difference matrix corresponds to the current description group in the next random setting, and the columns of the description difference matrix are the description differences of the corresponding key parameters under different random settings, and the description differences are functional difference descriptions.

[0043] Preferably, reading the monitoring data back to the FPGA includes:

[0044] The PSI5 card monitoring data is categorized into timing data, current data, and fault status data, and hardware acquisition channels are configured for each type of data.

[0045] After being conditioned by the channel, various monitoring data are directly transmitted to the corresponding internal hierarchical buffer area through the FPGA high-speed parallel interface. Among them, timing data and current data are stored in the high-speed FIFO buffer, and fault status data are stored in the static register.

[0046] The readback data is verified in real time at the hardware level. If the verification passes, the FPGA monitoring data area is updated. If the verification fails, the channel is retransmitted to complete the data readback.

[0047] Compared with the prior art, the beneficial effects of this application are as follows:

[0048] Using FPGA as the core control unit, and through a hardware-level pure logic processing architecture and dynamic scheduling, closed-loop control, and precise verification mechanisms, it fundamentally solves the core defects of existing technologies, such as poor real-time performance, fixed and unadjustable parameters, incomplete fault injection coverage, lack of closed-loop signal monitoring, and low multi-channel synchronization accuracy. It achieves synchronization accuracy, software-based remote adjustability of all parameters, controllable injection of all types of faults, full-dimensional hardware closed-loop monitoring, and full-link data traceability. It can be seamlessly integrated into automotive HIL test systems, adapting to the automotive-grade PSI5 communication test requirements in fields such as intelligent chassis and intelligent driving. It significantly improves the real-time performance, reliability, and test coverage of PSI5 board simulation, shortens the R&D and testing cycle of automotive electronic systems, and reduces testing costs.

[0049] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0050] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0051] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart illustrating a simulation method for a PSI5 cardboard according to an embodiment of the present invention; Figure 2 This is a structural diagram of the hardware system in an embodiment of the present invention. Detailed Implementation

[0053] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0054] This invention provides a simulation method for PSI5 card boards, such as... Figure 1 As shown, it includes:

[0055] Step 1: Initialize and configure the PSI5 card system, complete FPGA logic resource allocation, DAC / ADC chip calibration, differential amplifier constant current circuit zeroing, fault injection module reset, and dual-mode communication module communication link establishment;

[0056] Step 2: Select the host communication mode or slave communication mode according to the test requirements, receive remote configuration instructions through the dual-mode communication module, set the key parameters of the corresponding mode in software, and write them into the FPGA register. The key parameters include reference current, operating current, synchronization pulse amplitude, baud rate, encoding method and number of channels.

[0057] Step 3: In slave communication mode, the FPGA generates an encoded signal conforming to the PSI5 protocol, which is then converted from digital to analog by a DAC and conditioned by a differential amplifier constant current circuit before being output to the external ECU. In master communication mode, the hardware acquisition circuit receives the PSI5 protocol signal from the external sensor, which is then conditioned and sent to the FPGA for protocol parsing. The differential amplifier constant current circuit is constructed from operational amplifiers and transistors. The FPGA performs hardware closed-loop correction of the amplification factor of the differential amplifier constant current circuit based on real-time acquired loop current data.

[0058] Step 4: In slave communication mode, the synchronous pulse edge is captured by a comparator and a programmable voltage threshold and sent to the FPGA for high-precision timing analysis; in master communication mode, the voltage change of the series sampling resistor is detected, and the loop current is monitored in real time after being conditioned by an operational amplifier, and the monitoring data is read back to the FPGA.

[0059] Step 5: According to the test requirements, send a trigger command to the fault injection module through the FPGA to realize the controllable injection of multiple types of faults in the PSI5 communication link. The multiple types of faults include at least one of power failure, line failure, signal integrity failure, timing failure, encoding and data failure, and frame structure failure.

[0060] Step 6: Based on the FPGA, the first result generated in Step 3, the second result generated in Step 4, and the third result generated in Step 5 are summarized in real time, and the data is uploaded to the remote control terminal through the dual-mode communication module to complete the visualization and data traceability of the simulation process.

[0061] Preferably, after step 6, the following steps are also included:

[0062] After the test is completed, the FPGA generates a simulation test report, which includes parameter configuration information, signal timing data, fault injection records, and hardware closed-loop monitoring data. The report is then uploaded to the remote control terminal via a dual-mode communication module, enabling the test cases to be reproducible and the data to be traceable.

[0063] Preferably, the triggering method of the triggering instruction of the fault injection module includes at least one of manual single triggering, timed cyclic triggering, and multi-fault combination triggering, and the software configuration of the fault injection parameters includes: fault duration, fault amplitude, and fault triggering sequence.

[0064] This embodiment focuses on the PSI5 communication link test scenario of automotive intelligent chassis wheel speed sensors. It adapts to the simulation requirements of a 4-channel PSI5 card board, supports dual-mode switching between host (ECU) and slave (sensor), and can be integrated into an automotive hardware-in-the-loop (HIL) test system. The entire process uses an FPGA as the core control unit, employing a hardware-level pure logic processing architecture to eliminate software scheduling delays. This addresses shortcomings in existing technologies such as poor real-time performance, unadjustable parameters, incomplete fault coverage, lack of closed-loop signal monitoring, and low multi-channel synchronization accuracy. In this embodiment, the FPGA is an XC7K325T chip, and the DAC / ADC chips are both 16-bit high-precision automotive-grade chips. The dual-mode communication module adopts a CAN bus + Ethernet bus architecture, and the fault injection module consists of precision relays, digital potentiometers, and a programmable power supply.

[0065] In this embodiment, step 1 is the basic preparation step for simulation testing. The core is to achieve error-free initialization and functional readiness of each hardware module, which solves the problem that the initialization of existing technologies only performs routine resets, without accurate resource allocation and module accuracy calibration.

[0066] FPGA logic resource allocation refers to the functional planning, division, and scheduling of hardware resources such as logic units (CLBs), registers, on-chip RAM, and high-speed interfaces within an FPGA. It is the foundation for achieving multi-channel synchronous simulation. This embodiment adopts a predictive dynamic scheduling and allocation strategy to avoid resource congestion problems in advance.

[0067] In this embodiment, the DAC (Digital-to-Analog Converter) chip is used to convert the digital encoded signal generated by the FPGA into an analog electrical signal, and the ADC (Analog-to-Digital Converter) chip is used to convert the acquired analog current / pulse signal into a digital signal. Calibration refers to eliminating the zero-point error and system error of the chip to ensure conversion accuracy. Specifically, the standard signal source calibration method is adopted. A standard digital value of 0~4095 is input to the DAC chip, and its analog output voltage is acquired by a high-precision multimeter to construct a digital-analog calibration curve and correct the DAC calibration coefficient in the FPGA. A standard analog voltage of 0~5V is input to the ADC chip, and its output digital value is read to construct an analog-digital calibration curve and correct the ADC calibration coefficient. The calibration process is automatically completed by the FPGA, and the calibration coefficient is stored in a dedicated register after calibration. Before calibration using a 16-bit DAC chip, the output voltage was 2.48V (theoretical value 2.5V) when the input digital value was 2048. After calibration, the correction factor was 1.008, the output voltage was accurately 2.5V, and the overall conversion error was ≤0.1%. Before calibration, the ADC chip output a digital value of 2030 when the input analog voltage was 2.5V. After calibration, the correction factor was 1.009, the output digital value was accurately 2048, and the conversion error was ≤0.1%.

[0068] In this embodiment, the differential amplifier constant current circuit, constructed from an operational amplifier and an NPN transistor, is the core circuit for realizing the PSI5 current-type signal output. Zero adjustment refers to eliminating the circuit's static bias current to avoid static errors affecting the current output accuracy. Specifically, the circuit input is grounded, and the static current at the circuit output is monitored using a precision microammeter. The zero-adjustment potentiometer of the operational amplifier is adjusted until the static current is ≤1. After zeroing is completed, the resistance value of the zeroing potentiometer is recorded via the FPGA as a reference for subsequent circuit calibration. For example, if the static current of the differential amplifier constant current circuit before zeroing is 8... After adjusting the zero-adjustment potentiometer, the quiescent current dropped to 0.8. It meets automotive-grade static error requirements.

[0069] In this embodiment, the fault injection module is the core module for simulating various faults in the PSI5 communication link. Reset refers to restoring the precision relays, digital potentiometers, programmable power supplies, and other devices within the module to their fault-free initial state, ensuring the link is normal before fault injection. Specifically, the FPGA sends a reset command to the fault injection module. After receiving the command, the module disconnects the relay (to avoid short-circuit / open-circuit faults), restores the digital potentiometer to its nominal resistance value, and outputs the rated voltage (12V) of the programmable power supply. After completing the reset, the module sends a reset success feedback signal to the FPGA. The FPGA detects the feedback signal and determines that the module is ready. For example, before the fault injection module resets, the relay is in a closed state (simulating a short-circuit fault), and the digital potentiometer resistance is 100Ω. After the reset, the relay disconnects, the digital potentiometer resistance is restored to 50Ω, the programmable power supply outputs the rated voltage of 12V, and the feedback signal is high (3.3V). The FPGA detects the high level and confirms that the reset is complete.

[0070] In this embodiment, the dual-mode communication module adopts a CAN bus + EtherNET bus architecture. Specifically, the FPGA is configured with a CAN bus baud rate of 500kbps and an EtherNET bus IP address of 192.168.1.100, with a transmission baud rate of 100Mbps. The FPGA sends a handshake command to the remote control terminal (host computer), and the remote control terminal receives and responds with a handshake response. If the FPGA receives the response within 1ms, the link is considered successfully established. The EtherNET bus is configured with a hard real-time transmission protocol (based on TSN time-sensitive network) to ensure that the remote command response delay is ≤1μs. The CAN bus serves as a backup link to enable emergency command transmission in case of failure.

[0071] In this embodiment, the PSI5 protocol is a bidirectional communication protocol. In master mode, the card simulates a car ECU, receiving PSI5 signals from external sensors and parsing the protocol. In slave mode, the card simulates a car sensor (such as a wheel speed sensor), sending current-type signals conforming to the PSI5 protocol to the external ECU. The two modes can be flexibly switched via remote commands. Specifically, the remote control terminal sends a mode selection command to the FPGA via the Ethernet bus (master mode command is 0x01, slave mode command is 0x02). After receiving the command, the FPGA configures its internal PSI5 protocol-specific logic, switches to the corresponding operating mode, and sends a successful mode switching signal back to the remote control terminal.

[0072] In this embodiment, the remote control terminal sets key parameters according to test requirements and sends the parameter data packet to the dual-mode communication module via the Ethernet bus. The module sends the data packet to the FPGA, and the FPGA writes the parameters one by one into a dedicated parameter register. After writing is complete, it sends a parameter writing success signal back to the remote control terminal. If the slave mode is selected, the key parameters are set as follows: reference current 8mA, operating current 16mA, synchronization pulse amplitude 5V, baud rate 125kbps (standard bit period 8000ns), encoding method Manchester encoding, number of channels 4, and the parameter data packet is 0x080x100x050x010x010x04. After the FPGA receives the data, it successfully writes it into the register, and the feedback signal is 0x00 (writing successful).

[0073] In this embodiment, the FPGA generates a Manchester-encoded digital signal (with encoding rules conforming to the PSI5 protocol standard) using PSI5 protocol-specific encoding logic based on the key parameters written to the register. The digital signal is then fed into a 16-bit DAC chip to complete the digital-to-analog conversion, converting the digital signal into an analog electrical signal of 0~5V. The analog electrical signal is then fed into a differential amplifier constant current circuit, and after differential amplification by an operational amplifier and constant current control by a transistor, it is converted into a differential current signal that matches the reference current / operating current. The current signal is then output to an external ECU through an electrically isolated output channel. Each channel is opto-isolated (isolation voltage ≥2500V) to avoid interference between channels.

[0074] In this embodiment, the PSI5 differential current signal from the external sensor is input to the hardware acquisition circuit of the card board. It is converted into a voltage signal by a sampling resistor, and then filtered, amplified, and conditioned to become a standard analog voltage signal of 0~5V. The analog voltage signal is sent to a 16-bit ADC chip to complete analog-to-digital conversion and obtain a digital signal. The digital signal is directly sent to the dedicated PSI5 protocol parsing logic of the FPGA. The hardware logic performs Manchester decoding, extracts valid data, and caches the data in the dedicated data area of ​​the FPGA. For example, the 12mA PSI5 current signal from the external wheel speed sensor is converted into a 1.2mV voltage signal by a 0.1Ω sampling resistor, amplified and conditioned to a standard analog voltage of 2.4V, converted into a digital value 0x0F00 by the ADC chip, and parsed by the FPGA to obtain a wheel speed of 40km / h with a parsing delay of ≤10ns.

[0075] In this embodiment, the differential amplifier constant current circuit consists of: the differential input of the operational amplifier connected to the output of the DAC (digital-to-analog converter), the output connected to the base of an NPN transistor, the collector of the transistor connected to a 5V power supply, and the emitter connected to a sampling resistor and a current-limiting resistor before being grounded. The voltage signal across the sampling resistor is fed back to the inverting input of the operational amplifier, forming a negative feedback constant current structure. The specific rules for the FPGA to perform hardware closed-loop correction on the differential amplifier constant current circuit are as follows:

[0076] The FPGA sets the deviation threshold between the measured value and the standard value of the loop current to ±0.1%. If the deviation exceeds this range, the amplification factor correction will be triggered immediately.

[0077] Digital potentiometer adjustment step size and mapping relationship: The adjustment step size of the X9C103S digital potentiometer is 1st order (corresponding to 100Ω). The FPGA sends adjustment commands to the digital potentiometer via the SPI interface. The amplification factor is inversely proportional to the resistance value of the digital potentiometer. The mapping relationship is as follows: Where A is the circuit amplification factor and K is the circuit intrinsic coefficient (fixed to 2.5 after calibration). The total resistance of the digital potentiometer is 10kΩ. This is the current resistance value of the digital potentiometer;

[0078] Correction process: FPGA every 1 Collect the primary loop current and calculate the deviation value. If the deviation is > ±0.1%, calculate the target resistance value according to the mapping relationship. Send adjustment commands via the SPI interface (resistance increases when triggered by rising edge, and decreases when triggered by falling edge). After adjustment, collect the current again to verify if the deviation is ≤ 0.1%. If it does not meet the target, repeat the adjustment until the deviation meets the requirement. The single correction cycle should be ≤ 5 seconds. .

[0079] In this embodiment, the synchronization pulse signal sent by the ECU is fed into a high-speed automotive-grade comparator (response bandwidth ≥100MHz) after passing through a hardware RC filter circuit (filtering out electromagnetic interference noise). The FPGA dynamically adjusts the programmable voltage threshold according to the signal quality (adjustment step size 10mV, threshold and pulse amplitude adaptation ratio 40%~60%). The comparator compares the analog pulse signal with the programmable voltage threshold and converts it into a digital pulse signal. The digital pulse signal is subjected to hardware-level debouncing (debouncing duration is 10ns, matching the PSI5 protocol timing requirements) to avoid noise triggering false edges. The debouncing digital pulse signal is directly transmitted to the high-precision timing sub-logic (driven by a 200MHz independent high-frequency crystal oscillator, timing accuracy 0.1ns) through the FPGA's high-speed differential interface to complete the high-precision timing of the pulse edge. The FPGA's dedicated PSI5 protocol parsing logic extracts timing characteristic parameters such as the period, duty cycle, and edge transition delay of the synchronization pulse based on the timing data, and compares them with the PSI5 protocol standard timing in real time. If there is a deviation, it is fed back to the programmable voltage threshold adjustment model to achieve closed-loop calibration of the capture threshold. If the ECU sends a synchronization pulse with an amplitude of 5V, the FPGA dynamically adjusts the programmable voltage threshold to 2.5V (50% adaptation ratio). The comparator captures the rising edge (3.3V) and falling edge (0V), and after 10ns hardware debouncing, it is sent to the high-precision timing sub-logic. The timing results in a pulse period of 100μs and a duty cycle of 50%, which is consistent with the PSI5 protocol standard timing and requires no calibration. If the pulse duty cycle deviation is 10%, it is fed back to the adjustment model to adjust the voltage threshold to 2.3V, thus achieving closed-loop calibration.

[0080] In this embodiment, a 0.1Ω precision sampling resistor is connected in series in the signal input channel of the host mode to collect the voltage change across the resistor. The voltage change is conditioned by a high dynamic response, low noise operational amplifier (bandwidth ≥ 50MHz, noise ≤ 1μV) and then sent to a 16-bit ADC chip. The ADC chip converts the analog voltage signal into a digital signal and sends it to the FPGA. The FPGA calculates the loop current value according to Ohm's law, realizing 16-bit high-precision real-time monitoring. If the detected current value exceeds the PSI5 protocol standard range (e.g., <5mA or >20mA), the FPGA triggers a hardware-level real-time warning and sends a warning signal to the remote control terminal. For example, if the loop current sent by the external sensor is 10mA, the voltage across the sampling resistor is 1mV, which is conditioned to 2V by the operational amplifier. The ADC chip converts this to a digital value of 0x0CCC, and the FPGA calculates the loop current as 10.0mA, which conforms to the PSI5 protocol standard. If the current suddenly changes to 22mA, the FPGA immediately triggers a hardware warning and sends a warning signal (0xEE) to the remote control terminal.

[0081] In this embodiment, the monitoring data of the PSI5 card is divided into timing data (pulse period, duty cycle), current data (reference current, operating current, loop current), and fault status data (fault type, fault trigger timing), and independent hardware acquisition channels are configured for each type of data. After channel conditioning, the various monitoring data are directly transmitted to the FPGA's internal hierarchical buffer area through the FPGA's high-speed parallel interface (transmission rate ≥1Gbps). The timing data and current data are stored in a high-speed FIFO buffer (adapted to rapidly changing dynamic data), and the fault status data is stored in a static register (adapted to static status data). Hardware-level CRC verification is performed on the readback data. The checksum is 16 bits. If the verification passes, the FPGA monitoring data area is updated. If the verification fails, the FPGA sends a retransmission command to the acquisition channel, triggering the channel to retransmit the data until the verification passes. For example, timing data (pulse period 100... The current data (16mA) and fault status data (0x00 without fault) are conditioned by their respective acquisition channels and then directly transmitted to the FPGA through a high-speed parallel interface. The FIFO buffer stores the timing and current data in real time, and the static register stores the fault-free status. The 16-bit CRC check code is 0x1234. After the check passes, the monitoring data area is updated. There is no data loss or delay during data readback.

[0082] In this embodiment, the faults include power supply faults (over / under voltage, power interruption), line faults (short circuit, open circuit, poor contact), signal integrity faults (signal attenuation, noise interference), timing faults (pulse delay, duty cycle deviation), encoding and data faults (encoding error, data bit flipping), and frame structure faults (missing frame header, incorrect frame length).

[0083] In this embodiment, the remote control terminal sets the fault type and fault parameters according to the test requirements, and sends the fault injection command to the FPGA via the Ethernet bus. After parsing the command, the FPGA sends a hardware-level trigger command to the fault injection module. The transmission delay of the trigger command is ≤1 second. This ensures the precise timing of fault injection.

[0084] In this embodiment, the fault injection module simulates various faults through different hardware devices according to the FPGA's trigger instructions: power supply faults: the programmable power supply adjusts the output voltage (simulating overvoltage / undervoltage) or disconnects the power supply (simulating power interruption); line faults: a precision relay closes (simulating short circuit), opens (simulating open circuit), or adjusts the contact resistance (simulating poor contact); signal integrity faults: a digital signal generator injects noise into the link, or an attenuator adjusts the signal attenuation; timing faults: a digital potentiometer adjusts the delay time of the synchronization pulse, or the FPGA adjusts the encoding timing; encoding and data faults: the FPGA intentionally introduces encoding errors during the encoding process, or flips data bits; frame structure faults: the FPGA adjusts the frame header identifier or frame length parameter of the PSI5 frame. All fault parameters are configured in software, including fault duration, fault amplitude, and fault trigger timing. A custom frame format is used, with a total length of 64 bytes: frame header (4 bytes) + instruction code (1 byte) + parameter segment (56 bytes) + checksum (2 bytes) + frame tail (1 byte).

[0085] Frame header: Fixed at 0x50534935 (corresponding to PSI5), used for frame synchronization;

[0086] Instruction codes: such as 0x01 for master mode selection, 0x02 for slave mode selection, 0x03 for parameter configuration, and 0x04 for fault injection;

[0087] Parameter section: Fill in the parameters in the order of key parameters, such as the slave mode parameters as reference current (2 bytes), operating current (2 bytes), synchronization pulse amplitude (2 bytes), baud rate (1 byte), encoding method (1 byte), number of channels (1 byte), and fill the remaining bytes with 0;

[0088] Checksum: 16-bit CRC checksum, generator polynomial ;

[0089] End of frame: Fixed at 0x00, indicating the end of the frame.

[0090] In this embodiment, to test the functional safety of the wheel speed sensor, a multi-fault combination trigger is selected, and the fault type is set to a line short-circuit fault + timing fault. The fault parameters are: short-circuit fault duration 100ms, timing fault synchronization pulse delay 10ms. The test duration is 200ms, and the trigger timing is 5s after the test starts. 5s after the test starts, the FPGA simultaneously sends two trigger commands to the fault injection module: a relay closes to short-circuit the circuit, and a digital potentiometer adjusts to achieve pulse delay. The fault triggering error is ≤1. The FPGA monitors the fault status in real time and transmits it back to the remote control terminal. After the fault injection is completed, the module automatically recovers to the fault-free state.

[0091] In this embodiment, the FPGA incorporates a multi-channel data fusion sub-logic to integrate, classify, and cache the signal generation / parsing data from step 3, the hardware closed-loop monitoring data from step 4, and the fault injection status data from step 5 in real time. The cache area is the FPGA's on-chip high-speed RAM, ensuring zero data aggregation delay and maintaining the timing synchronization of data from each channel. For example, the 4-channel signal generation data (16mA current, Manchester encoding) and monitoring data (pulse period 100...) are... The circuit current is 16mA), and the fault injection data (short circuit + timing fault, duration 100 / 200ms) are integrated by the data fusion sub-logic and then cached in the on-chip RAM according to the channel classification.

[0092] In this embodiment, the FPGA uploads the aggregated full data to the remote control terminal at high speed via the EtherNET bus (upload rate ≥100Mbps). The test software on the remote control terminal performs real-time analysis and visualization of the data, including signal waveforms, current change curves, fault status indicators, etc. If the EtherNET bus fails, it automatically switches to the CAN bus for emergency data upload to ensure no data loss.

[0093] In this embodiment, once the test is completed, the simulation test report automatically generated by the FPGA includes all configuration parameters of the 4 channels, 1000 sets of signal timing data, detailed records of fault injection (type, parameters, trigger time), and current monitoring data throughout the process. After the report is uploaded to the host computer, it is stored as a PDF and can be directly used for the reproduction of test cases and root cause analysis of faults.

[0094] like Figure 2As shown, this hardware system uses the CPU as the core control hub, working in conjunction with the power supply module, communication module, fault injection module, digital-to-analog converter module, constant current module, and comparator module to form a closed loop for simulation and data interaction on the PSI5 card. The specific logic flow is as follows: The external power supply provides a stable power input for the entire system. After voltage conversion, filtering, and power isolation by the power supply module, it provides compliant power to the CPU, communication module, fault injection module, digital-to-analog converter module, constant current module, and comparator module, ensuring the stable operation of each hardware module. The communication module, as the external interaction interface, receives simulation configuration commands, parameter setting commands, and fault trigger commands from external control terminals (such as host computers or HIL test systems) and transmits the commands to the CPU. The CPU, as the main control core of the system, receives external commands from the communication module, parses and executes various control logics, and distributes control signals to each functional module: On the one hand, the CPU sends data conversion commands to the digital-to-analog converter module according to the external configuration commands. The digital-to-analog converter module converts the digital signals output by the CPU into analog signals and transmits them to the constant current module. On the other hand, the CPU sends control commands to the fault injection module. The fault injection module is triggered to simulate a specified type of fault in the PSI5 communication link (signal path between CH1+ and CH1-). Simultaneously, the CPU receives synchronization pulse monitoring data from the comparator module and loop current monitoring data from the constant current module. The comparator module and constant current module are connected in parallel to the PSI5 signal input path (CH1+). The comparator module performs level comparison and edge capture on the PSI5 synchronization pulse signal input at CH1+, transmitting the captured digital pulse edge signal to the CPU for accurate timing capture and analysis. The constant current module... The system receives the analog signal output from the digital-to-analog converter module, conditions it into a differential current signal conforming to the PSI5 protocol standard, and outputs it to the external ECU through CH1+. At the same time, it collects the loop current signal fed back from CH1- and sends it back to the CPU for current status monitoring. The overall logic forms a complete closed loop of external instruction reception → CPU main control parsing → signal generation / fault injection / monitoring → data feedback to the CPU → external data interaction. It not only realizes the accurate simulation output of PSI5 signals, but also has the ability to simulate faults and monitor in real time, which can meet the automotive-grade testing requirements of the PSI5 protocol for automotive electronics.

[0095] The beneficial effects of the above technical solution are as follows: Using FPGA as the core control unit, through a hardware-level pure logic processing architecture and dynamic scheduling, closed-loop control, and precise verification mechanism, it fundamentally solves the core defects of existing technologies such as poor real-time performance, fixed and unadjustable parameters, incomplete fault injection coverage, lack of closed-loop signal monitoring, and low multi-channel synchronization accuracy. It achieves synchronization accuracy, software-based remote adjustability of all parameters, controllable injection of all types of faults, full-dimensional hardware closed-loop monitoring, and full-link data traceability. It can be seamlessly integrated into automotive HIL test systems, adapting to the automotive-grade PSI5 communication test requirements in fields such as intelligent chassis and intelligent driving. It significantly improves the real-time performance, reliability, and test coverage of PSI5 board simulation, shortens the R&D and testing cycle of automotive electronic systems, and reduces testing costs.

[0096] This invention provides a simulation method for a PSI5 card board, which includes the following steps before FPGA logic resource allocation:

[0097] Based on the channel number configuration requirements of the PSI5 card, the global logic resource pool of the FPGA is pre-divided, and the global resource pool is divided into a protocol processing sub-resource pool, a timing scheduling sub-resource pool, a data interaction sub-resource pool, and a fault control sub-resource pool according to the functional dimension.

[0098] The test requirements are analyzed and the current priority of each sub-resource pool is obtained. Based on the combination of current priorities, several simulation test cases are matched from the combination-simulation lookup table.

[0099] Real-time monitoring of resource occupancy and channel load status of each sub-resource pool under each simulation test case; combined with the time-series data of resource interaction variables of the corresponding simulation test case, predicting the PSI5 frame period window in which the target channel blockage occurs.

[0100] When it is predicted that the target channel will be blocked within N PSI5 frame periods, a four-dimensional demand vector of protocol processing computing power, timing counting accuracy, data buffer capacity and fault response latency of the target channel is extracted based on the logical resource demand model determined by the test scenario type of the corresponding simulation test case.

[0101] Capture the resource interaction variables between each sub-resource pool and each other sub-resource pool during the simulation of the corresponding simulation test case, and obtain the scheduling threshold of redundant logical resources of the corresponding sub-resource pool and the PSI5 protocol timing alignment window;

[0102] Traverse the FPGA global idle sub-resource pool, divide redundant logic resources into lightweight sequential logic, medium-weight cache logic, and heavyweight protocol processing logic according to their functional types, and prioritize the selection of redundant logic resources that meet the scheduling threshold, have the highest matching degree between their functional type and the four-dimensional demand vector, and whose loading timing falls within the PSI5 protocol timing alignment window, and regard them as the first resource;

[0103] During the idle time slot of the PSI5 frame of the target channel, the first resource is dynamically loaded into the logical area of ​​the target channel;

[0104] After scheduling is completed, the load status of the target channel and the interaction performance of the sub-resource pool are monitored in real time. Based on the monitoring results, the computing power allocation ratio of redundant logical resources is adaptively adjusted. At the same time, the demand vector, resource matching results and timing alignment data of this scheduling are updated to the combination-simulation comparison table.

[0105] Preferably, the scheduling threshold for the redundant logical resources is the upper limit of computing power ratio and the lower limit of cache capacity.

[0106] In this embodiment, obtaining the scheduling threshold and PSI5 protocol timing alignment window for redundant logical resources in the corresponding sub-resource pool includes:

[0107] Upper limit of computing power ratio ,in, Let x be the real-time blocking degree of the blocking sub-resource pool, and ; This represents the computing power requirement of the blocked sub-resource pool x. is the interaction coupling coefficient between sub-resource pool x and the other sub-resource pools y;

[0108] Calculate the lower limit of cache capacity ,in, This is the historical scheduling correction coefficient, with a value range of 1.0 to 1.2. It is determined based on the historical scheduling success rate in the combined-simulation comparison table. When the success rate is ≥95%, it is 1.0; when it is 90% to 95%, it is 1.1; and when it is <90%, it is 1.2. For all The maximum value in; This represents the cache requirement value for the blocking sub-resource pool x.

[0109] Calculate the start time of the timing alignment window ,in, The average interaction latency between sub-resource pool x and the other sub-resource pools y; The standard bit period for the PSI5 protocol is determined by the PSI5 baud rate, at 125kbps. =8000ns, 189kbps =5291ns; N1 represents the actual capture duration of the PSI5 synchronization pulse; N1 represents the number of bits in the current frame data field, which is parsed in real time by the FPGA.

[0110] Calculate the duration of the timing alignment window ,in, The duration of the idle time slot following the current PSI5 frame data field; Due to inherent latency in FPGA hardware resource scheduling; The safety factor for timing matching is set to a value of 0.8 to 0.9, which is determined according to the real-time requirements of the test scenario. For high real-time scenarios (such as intelligent driving and emergency braking), a value of 0.8 is used (to reserve more scheduling margin), while for conventional test scenarios (such as static sensor testing), a value of 0.9 is used.

[0111] Based on the start time Duration Obtain the PSI5 protocol timing alignment window.

[0112] In this embodiment, the PSI5 card is a hardware board used to simulate PSI5 protocol communication, adapted for communication testing between automotive sensors and ECUs. The channel number configuration requirement refers to the total number of communication channels set by the user according to the test scenario (e.g., 4-channel wheel speed sensor testing). The FPGA global logic resource pool is the sum of all available hardware logic resources inside the FPGA, including logic units, registers, on-chip storage, etc. After being divided according to functional dimensions, it is divided into four types of sub-resource pools: the protocol processing sub-resource pool is responsible for core protocol operations such as PSI5 protocol encoding and parsing; the timing scheduling sub-resource pool manages timing tasks such as multi-channel timing synchronization and pulse timing; the data interaction sub-resource pool undertakes interactive work such as data caching and instruction and test data transmission; and the fault control sub-resource pool is used for fault-related operations such as fault injection instruction generation and fault status monitoring. Taking a 4-channel test scenario as an example, if the total logic resources of the FPGA are 1000KCLB, 300KCLB of protocol processing sub-resource pool, 200KCLB of timing scheduling sub-resource pool, 250KCLB of data interaction sub-resource pool, and 250KCLB of fault control sub-resource pool can be pre-allocated. Logical isolation boundaries are set between each sub-resource pool to avoid resource crosstalk between functional modules.

[0113] In this embodiment, the test requirements are the user's specific requirements for simulation testing (such as communication stability testing under emergency braking scenarios, functional safety fault testing, etc.). The current priority is the importance assigned to each sub-resource pool based on the current test requirements (values ​​range from 0 to 1, with higher values ​​indicating greater criticality). Then, simulation test cases are matched from the combination-simulation lookup table based on the priority combination. The combination-simulation lookup table is a pre-established mapping table that records typical test processes corresponding to different priority combinations. The simulation test cases are complete simulation processes designed for specific scenarios (including parameter configuration, fault injection, data monitoring, etc.). For example, in the emergency braking scenario, the priority of the parsed protocol processing sub-resource pool is 0.9, the timing scheduling sub-resource pool is 0.85, the fault control sub-resource pool is 0.7, and the data interaction sub-resource pool is 0.65. This combination matches three test cases in the lookup table: 4-channel synchronous communication test under emergency braking, and emergency braking + line fault combination test.

[0114] In this embodiment, resource occupancy rate is the proportion of resources used in a sub-resource pool to the total resources (e.g., the protocol processing sub-resource pool uses 270KCLB out of a total of 300KCLB, resulting in a 90% occupancy rate). Channel load status refers to the load conditions of the target channel, including computing power, cache, and timing processing (e.g., the channel protocol processing computing power occupancy is 85%, and the cache occupancy is 70%). Resource interaction variable timing data records the changes in interaction variables (e.g., interaction latency and bandwidth occupancy rate) between sub-resource pools as a function of the PSI5 frame period. The target channel is the communication channel that needs to be monitored closely. Blocking occurs when the channel resource demand exceeds the allocated resources, resulting in timing delays or data loss. The PSI5 frame period window is the predicted frame period range for blocking. For example, when running the emergency braking test case, the protocol processing sub-resource pool occupancy rate was 90%, and the load rate of the 4th channel was 88%. Extracting the interaction variable timing data revealed that the interaction latency between the protocol processing and timing scheduling sub-resource pools increased from 5ns to 15ns. Linear regression analysis predicted that the 4th channel would be blocked within the 8th-10th PSI5 frame periods.

[0115] In this embodiment, a univariate linear regression model is used to accurately predict PSI5 channel congestion. The PSI5 frame period is used as the horizontal axis (hx, unit: number of frames), and the sub-resource pool resource occupancy rate is used as the vertical axis (zy, unit: %). The specific implementation steps are as follows:

[0116] Real-time acquisition of the resource occupancy rate of the sub-resource pool corresponding to the target channel under each simulation test case, once every 1 PSI5 frame cycle, continuously acquiring no less than 50 sets of data to form a dataset {(hx1,zy1),(hx2,zy2),...,(hxn,zyn)};

[0117] The least squares method is used to fit the linear regression equation zy = ahx + b, where the slope is... ,intercept ;

[0118] When the resource utilization rate zy of the fitted equation is ≥ 95% (the rated load rate of FPGA logic resources, set based on the resource redundancy design requirements of automotive-grade PSI5 simulation, reserving 5% resource redundancy to cope with sudden fault handling needs), it is determined to be a channel blockage. Calculate the corresponding horizontal coordinate hx0 at this time, and the PSI5 frame period window where the blockage occurs is [hx0−N,hx0+N], where N=2 (reserving 2 frame periods of scheduling time).

[0119] A univariate linear regression model based on the validity of the coefficient of determination is used to accurately predict the blockage of the PSI5 channel. The model needs to continuously collect no less than 50 sets of resource usage time series data for fitting, and the model is considered effective when the coefficient of determination after fitting is ≥0.9.

[0120] In this embodiment, N is the predicted number of remaining frame cycles before blocking (e.g., N=8), the test scenario type is the specific scenario corresponding to the simulation (e.g., emergency braking), and the logic resource requirement model is a model that quantifies the resource requirements of the target channel. The four-dimensional requirement vector includes protocol processing computing power (the number of logic units required for processing protocol encoding / parsing, in KCLB), timing counting accuracy (the minimum accuracy of pulse edge timing, in ns), data buffer capacity (the on-chip storage capacity required for buffered data, in Kbit), and fault response latency (the maximum allowable latency for fault trigger response, in μs). For example, if blocking is predicted after 8 frame cycles for the 4th channel, the logic resource requirement model for the emergency braking scenario outputs the following four-dimensional requirement vector: protocol processing computing power 100KCLB, timing counting accuracy 0.1ns, data buffer capacity 512Kbit, and fault response latency ≤1. .

[0121] In this embodiment, resource interaction variables are parameters describing the degree of interaction between sub-resource pools (such as interaction coupling coefficient and average interaction latency). The scheduling threshold is the minimum / maximum amount of redundant resources allowed to be allocated to the target channel (such as a computing power scheduling threshold of 247.5 KCLB and a cache scheduling threshold of 975.872 Kbit). The PSI5 protocol timing alignment window is a safe time interval for loading redundant resources (it must be within the frame idle time slot to avoid interfering with communication). For example, in the emergency braking test case, the interaction coupling coefficient between the protocol processing and timing scheduling sub-resource pools is 0.8, and the average interaction latency is 10 ns. After calculating the scheduling threshold, the starting time of the timing alignment window is 138.05 seconds after the end of the synchronization pulse. Duration: 16.99575 .

[0122] In this embodiment, the global idle sub-resource pool is the sum of unused redundant resources in all sub-resource pools.

[0123] In this embodiment, the four-dimensional feature values ​​of redundant logical resources and the four-dimensional demand vector of the target channel are normalized and converted to a value between 0 and 1. The normalization formula is: (current value - minimum value) / (maximum value - minimum value).

[0124] Based on the priority of the PSI5 test scenario, weights are assigned to the four-dimensional features: the weight of protocol processing computing power is 0.4, the weight of timing counting accuracy is 0.3, the weight of data cache capacity is 0.2, the weight of fault response latency is 0.1, and the sum of the weights is 1.

[0125] The weighted Euclidean distance between the normalized four-dimensional feature values ​​and the target channel four-dimensional demand vector is calculated. When 1 - weighted Euclidean distance ≥ 0.9, it is determined to be the highest matching degree and selected as the first resource.

[0126] In this embodiment, dynamic loading refers to loading resources into their dedicated logical area without interrupting communication of the target channel. For example, the idle time slot of channel 4 is 138. -155 During this period, the first resource is loaded into its logical region with a loading delay of ≤100ns, and communication continues uninterrupted.

[0127] In this embodiment, interaction performance refers to the efficiency and stability of interactions between sub-resource pools (such as interaction latency and bandwidth utilization). Based on monitoring results, the computing power allocation ratio of redundant resources is adaptively adjusted (e.g., 60% for protocol processing, 25% for timing scheduling, and 15% for fault control). Simultaneously, the demand vector, resource matching results, and timing alignment data from this scheduling are updated to the combination-simulation lookup table for subsequent scheduling optimization in similar scenarios, forming a closed-loop learning process. For example, if the load rate of the 4th channel drops to 65% and the interaction latency drops to 8ns after scheduling, the computing power allocation ratio is adjusted, and the relevant data is updated to the lookup table.

[0128] The beneficial effects of the above technical solution are as follows: by pre-dividing the FPGA logic resource pool and classifying it according to function, matching simulation test cases with test requirements, monitoring and predicting channel blocking risks in real time, accurately selecting the optimal redundant resources based on the four-dimensional demand vector and resource interaction variables, completing uninterrupted dynamic loading within the idle time slot of the PSI5 frame, and finally optimizing resource allocation through adaptive adjustment and closed-loop learning, it not only avoids resource waste or insufficiency caused by fixed resource allocation, but also ensures the nanosecond-level synchronization accuracy and real-time performance of multi-channel PSI5 simulation, while improving communication stability under fault scenarios, providing an efficient and reliable resource scheduling solution for automotive electronics PSI5 protocol testing.

[0129] This invention provides a simulation method for a PSI5 card board, which includes software-based setting of key parameters in the corresponding mode and writing them into the FPGA registers, comprising:

[0130] The first parameter set is obtained by reading the write parameters of the FPGA registers and comparing the first parameter set with the standard parameter set of the corresponding mode. If they are completely consistent, the software setting is deemed qualified.

[0131] Otherwise, multiple software-based random settings are performed, and the comparison group and the write group written to the FPGA register are obtained for each random setting. The comparison group and the write group are then compared to obtain the first difference group.

[0132] If all first difference groups consist of 0 parameters, then restart the PSI5 card system;

[0133] Otherwise, construct a value difference matrix based on all the first difference groups and perform normalization to obtain a normalized matrix;

[0134] Simultaneously, the process log of each random setting and writing process is captured, and the running sub-logic of each random setting is constructed. The running sub-logic is compared with the standard sub-logic to determine that the running sub-logic is based on at least one sub-difference logic of the standard sub-logic. In this case, the same standard sub-logic is used for each random setting operation.

[0135] The logical attribute pairs of each sub-difference logic are matched with the attribute-logic lookup table to obtain new logic, and the new logic and the corresponding sub-difference logic are preprocessed to obtain sub-coverage logic;

[0136] The sub-overlay logic corresponding to each sub-difference logic is executed sequentially. When the execution bit of the corresponding sub-overlay logic is detected to reach the preset bit, the execution code of the corresponding sub-difference logic is obtained.

[0137] When it is detected that the execution bit of the corresponding sub-coverage logic has not reached the preset bit, the register state of the corresponding sub-coverage logic is read and the status bit of the register state is responded to. The sub-compensation logic that has reached the preset bit from the status bit is retrieved from the historical database, and the execution code of the corresponding sub-difference logic based on the sub-compensation logic and the sub-coverage logic is obtained.

[0138] Extract the new setting description of each key parameter from all executed code under each random setting, and combine them according to the parameter sorting order of the standard parameter group to obtain the current description group under each random setting. Compare the current description group with the standard description group corresponding to the standard parameter group to obtain the second difference group, and construct the description difference matrix.

[0139] Based on the normalized matrix and the description difference matrix, obtain the difference type pairs of each key parameter, determine the abnormal environment object according to the difference type pairs, extract the optimization file that matches the abnormal environment object, and extract the compensation identifier and compensation position of the response difference type pairs from the optimization file.

[0140] The compensation logic is determined based on the compensation identifier, and the insertion point of the compensation logic in the original parameter setting logic is determined according to the compensation position and inserted to obtain the new setting logic. At this time, the PSI5 card system is restarted.

[0141] Preferably, the behavior of the normalization matrix corresponds to the normalization group of the first difference group in the next random setting, and the columns of the normalization matrix are the normalized differences of the corresponding key parameters under different random settings, and the normalized differences are difference values; the behavior of the description difference matrix corresponds to the current description group in the next random setting, and the columns of the description difference matrix are the description differences of the corresponding key parameters under different random settings, and the description differences are functional difference descriptions.

[0142] In this embodiment, the FPGA register is a hardware storage unit inside the FPGA used to store configuration parameters. The write parameters are the parameter values ​​actually written to the register after being remotely sent. The first parameter group is a set of these actually written parameters concatenated in sequence. The standard parameter group is a set of correct parameters preset in master or slave mode (such as a reference current of 8mA, operating current of 16mA, and synchronization pulse amplitude of 5V in slave mode). If the two sets of parameters are completely consistent, the software setting is deemed qualified, that is, the parameter configuration is accurate. For example, the standard parameter group in slave mode is: [8mA, 16mA, 5V, 125kbps, Manchester encoding, 4 channels]. If the first parameter group obtained by reading the register corresponds one-to-one with it, the setting is deemed qualified.

[0143] In this embodiment, software-based random setting refers to randomly generating parameter configurations within the parameter range allowed by the PSI5 protocol (e.g., a reference current of 5-20mA). The comparison group is the set of target parameters randomly set each time, the write group is the set of parameters actually written to the register, and the first difference group is the difference between the parameters at corresponding positions in the comparison group and the write group (if the parameters are the same, the difference is 0). For example, if the comparison group set for the first random setting is [9mA, 17mA, 5V, 125kbps, Manchester encoding, 4 channels], and the write group is [9mA, 16.8mA, 5V, 125kbps, Manchester encoding, 4 channels], then the first difference group is [0, 0.2mA, 0, 0, 0, 0]. If the first difference group is all 0 for all 5 random settings, it indicates that the parameter setting logic itself is not defective, and restarting the system can eliminate the impact of single transmission interference.

[0144] In this embodiment, normalization is performed by converting the difference values ​​into dimensionless values ​​between 0 and 1, using the range normalization method. Specifically: the normalized difference value of the j1st key parameter in the i1th random setting = |the written value of the j1st parameter in the i1th random setting - the standard value of the jth key parameter| / the absolute value of the maximum permissible deviation of the jth key parameter. The permissible deviations for different key parameters are shown in Table 1.

[0145] Table 1. Allowable Deviation Table for Key Parameters

[0146] It should be noted that the encoding method is an enumeration type (e.g., Manchester encoding is 0x01), with no numerical differences. The normalized difference value is fixed at 0. The row and column definitions of the value difference matrix are as follows: the rows are randomly set multiple times (i1=1,2,...,n), and the columns are key parameters (j1=1,2,...,6).

[0147] In this embodiment, the process log is text data recording the time, instructions, and results of operations such as parameter setting, writing, and register reading. The running sub-logic is the execution logic for writing parameters (e.g., register address mapping, data bit concatenation, etc.) that is randomly set each time. The standard sub-logic is the preset correct parameter writing logic, and the sub-difference logic is the code segment where the running sub-logic differs from the standard sub-logic. For example, in a randomly set running sub-logic, if the register write address for the action current parameter is offset by 1 bit, differing from the address in the standard sub-logic, this code segment is the sub-difference logic.

[0148] In this embodiment, logical attributes are feature tags of sub-difference logic (such as register address offset, data bit length error, etc.), the attribute-logic lookup table is a pre-established mapping table of logical attributes and correction logic, the new logic is the matched logic used to correct the defects of the sub-difference logic, the preprocessing is to perform syntax compatibility processing on the new logic and the sub-difference logic (such as unifying variable names and aligning instruction formats), and the sub-covering logic is the complete correction logic that can cover the defects of the sub-difference logic. For example, if the attribute of the sub-difference logic is a register address offset of 1 bit, the address offset correction logic is matched in the lookup table, and after preprocessing, the sub-covering logic is obtained to correct the address offset problem.

[0149] In this embodiment, the attribute-logic lookup table is a pre-established static mapping table stored in the on-chip ROM of the FPGA. It contains three columns: sub-differential logic attributes, corresponding correction logic, and logic execution instructions, as shown in Table 2.

[0150] Table 2 Attribute-Logical Comparison Table

[0151] In this embodiment, the execution bit is a binary bit that indicates the execution progress of the sub-coverage logic (e.g., shifting the execution bit left by 1 bit and setting it to 1 after each operation). The preset bit is a threshold for determining whether the sub-coverage logic has been fully executed (e.g., 0x0F, i.e., all 4 bits are 1). The executable code is an executable code segment resulting from the combination of the sub-difference logic and the sub-coverage logic. For example, if the sub-coverage logic contains 4 operations, after execution, the execution bit becomes 0x0F, reaching the preset bit, and at this point, the corresponding executable code is extracted.

[0152] In this embodiment, the register status refers to the working state of the register during the execution of the sub-overwrite logic (such as busy, idle, or error). The status bit is a binary bit that identifies the register status (e.g., 0x01 indicates the register is busy, and 0x02 indicates the register is faulty). The historical database stores similar scenarios from the past used to complete the execution logic. The sub-compensation logic is supplementary logic that allows the execution bit to reach a preset value. For example, if the register is busy (status bit 0x01) when the sub-overwrite logic reaches step 2, the sub-compensation logic waiting for the register to become idle is retrieved from the historical database and inserted into the corresponding position of the sub-overwrite logic to obtain the complete execution code.

[0153] In this embodiment, the new setting description is the assignment statement of the corresponding key parameter in the execution code (such as the reference current = 8mA), the current description group is the set of new setting descriptions of all key parameters in a standard order concatenated under each random setting, the standard description group is the set of correct description statements corresponding to the standard parameter group, and the second difference group is the difference between the current description group and the standard description group at the corresponding position (the same description statement is recorded as 0, and different description statements are recorded as 1). For example, if the new setting description of the operating current is operating current = 16.8mA, and the standard description is operating current = 17mA, then the position in the second difference group is recorded as 1, and the corresponding element in the description difference matrix is ​​1.

[0154] In this embodiment, the difference type pair is a combination of the value difference type (e.g., excessive / insignificant deviation) and the description difference type (e.g., incorrect / missing description statement) for each key parameter. The abnormal environment object is the root cause of the parameter setting anomaly (e.g., register write failure, communication link interference). The optimization file is a file storing compensation schemes for different abnormal environment objects. The compensation identifier is a label identifying the type of compensation logic (e.g., register address correction, data verification enhancement). The compensation position is the insertion position of the compensation logic in the original parameter setting logic (e.g., before / after the register write instruction). For example, if the normalized difference value of the operating current is 0.1 (small deviation) and the description difference is 1 (description error), the difference type pair is small deviation + description error. The abnormal environment object is determined to be a register data bit mapping error. The compensation identifier data bit remapping is extracted from the optimization file, and the compensation position is before the register write instruction. The difference type pair is matched in the preset abnormal mapping table to obtain the abnormal environment object; the corresponding optimization file is read, and the compensation identifier and compensation position are parsed out.

[0155] In this embodiment, the compensation logic is the specific correction logic for abnormal environment objects (such as data bit remapping logic), and the new setting logic is the complete parameter setting logic after the insertion of the compensation logic. Restarting the system makes the new setting logic take effect. The compensation logic is inserted into the original parameter setting logic according to the compensation position. The insertion position is divided into before the register write instruction, after the register write instruction, and in the parameter concatenation stage. The insertion rules and syntax requirements all conform to the VerilogHDL hardware description language specification. Specifically:

[0156] Insertion location: before the register write instruction;

[0157] Applicable anomalies: register address offset, data bit length error, parameter concatenation error;

[0158] Insertion rule: The compensation logic acts as preprocessing logic, completing the address / data correction before the parameters are written to the register, and the corrected data is used as the input for the write instruction;

[0159] Syntax requirements: The compensation logic and the original logic are connected using combinational logic with no clock delay, such as assigndata_corr=data+1'b1; (data bits are padded).

[0160] Insertion location: after the register write instruction;

[0161] Applicable anomalies: Register write timing delay, loss of write acknowledgment signal;

[0162] Insertion rules: The compensation logic is used as post-processing logic. After the write command is sent, an acknowledgment signal detection and retransmission mechanism is added.

[0163] Syntax requirements: The compensation logic adopts sequential logic, based on FPGA clock triggering, such as always@posedgeclkbeginif(!ack)wr_en<=1'b1;end.

[0164] Insertion position: during the parameter concatenation stage;

[0165] Applicable exceptions: Parameters in reverse order, encoding method mapping error;

[0166] Insertion rule: The compensation logic adjusts the parameter order or replaces erroneous enumeration values ​​before key parameters are concatenated into a data packet;

[0167] Syntax requirements: Use bit concatenation operations to correct data packets, such as assignpkg={P_base,P_act,V_pulse,baud,8'h01,ch_num}; (replace encoding method).

[0168] The beneficial effects of the above technical solution are as follows: By verifying the consistency of parameter settings through multiple rounds of random settings, and by combining the value difference matrix and the description difference matrix to locate the root cause of the anomaly from both numerical deviation and logical description dimensions, a layered repair mechanism of sub-coverage logic and sub-compensation logic is established. Finally, targeted compensation logic is inserted to generate new setting logic, thereby realizing the automatic identification and accurate repair of parameter setting anomalies. This avoids simulation test failures caused by single parameter setting errors, significantly improves the reliability and stability of PSI5 card parameter configuration, ensures the accuracy and continuity of automotive electronics PSI5 protocol simulation testing, and provides a more robust parameter configuration guarantee for automotive-grade testing.

[0169] This invention provides a simulation method for a PSI5 card board, which reads monitoring data back to the FPGA, including:

[0170] The PSI5 card monitoring data is categorized into timing data, current data, and fault status data, and hardware acquisition channels are configured for each type of data.

[0171] After being conditioned by the channel, various monitoring data are directly transmitted to the corresponding internal hierarchical buffer area through the FPGA high-speed parallel interface. Among them, timing data and current data are stored in the high-speed FIFO buffer, and fault status data are stored in the static register.

[0172] The readback data is verified in real time at the hardware level. If the verification passes, the FPGA monitoring data area is updated. If the verification fails, the channel is retransmitted to complete the data readback.

[0173] In this embodiment, the monitoring data refers to various data reflecting the operating status of the communication link collected by the PSI5 card during simulation testing; the timing data refers to monitoring data related to the timing of the PSI5 protocol, such as the period of the synchronization pulse, the edge transition time, and the frame interval duration, which are the core data to ensure communication synchronization; the current data refers to relevant data under PSI5 current-type communication, including the reference current, the operating current, and the real-time loop current, which reflect the accuracy and stability of the signal output; the fault status data refers to status data that identifies whether there is a fault in the current communication link, the fault type, the fault trigger time, etc., and is used for fault diagnosis and recording; the hardware acquisition channel is a physical hardware acquisition path specifically allocated for each type of data, including signal conditioning circuits, interface pins, etc., to avoid interference between different types of data and ensure the independence and accuracy of acquisition. In a simulation test of a 4-channel wheel speed sensor, the timing data is the rise time of the synchronization pulse for each channel (e.g., the rise time of the synchronization pulse for channel 1 is 100.0001μs), the current data is the real-time output current for each channel (e.g., the operating current for channel 2 is 16mA), and the fault status data is a status indicator such as a short circuit in channel 3 and a trigger time of 5s. Independent hardware acquisition channels are configured for these three types of data. The timing data channel is connected to the pulse capture circuit, the current data channel is connected to the current sampling circuit, and the fault status data channel is connected to the status output pin of the fault injection module.

[0174] In this embodiment, after the timing data is conditioned by the channel, the pulse edge time is converted into a 32-bit digital quantity, and then transmitted directly to the high-speed FIFO cache (address range 0x0000-0x0FFF) inside the FPGA at a rate of 1Gbps through the FPGA's 32-bit high-speed parallel interface; the current data is conditioned and converted into a 16-bit digital quantity, and then stored in different address segments of the same FIFO cache through the same interface; the fault status data is conditioned and converted into an 8-bit status code (e.g., 0x00 indicates no fault, 0x01 indicates a short circuit), and then stored in the FPGA's static register (address 0x1000) through the parallel interface. This register retains its value when the fault status is not updated. Specifically, in the FPGA hardware logic, a corresponding hardware conditioning circuit is designed for each type of data. The timing data channel uses an RC filter circuit to filter out noise, the current data channel uses an instrumentation amplifier to amplify weak current signals, and the fault status data channel uses a level conversion chip to convert the 3.3V level to the FPGA-compatible 1.8V level. The conditioned data is directly connected to the internal storage unit through the FPGA's dedicated parallel I / O interface. The timing and current data are mapped to the FIFO IP core, and the fault status data is mapped to the static register IP core. The storage address and bit width are configured through a hardware description language.

[0175] Hardware-level real-time verification is a data verification mechanism implemented in the FPGA hardware logic that does not rely on software scheduling. Verification uses preset verification algorithms (such as CRC check, parity check, etc.) to verify the integrity and correctness of the readback data and determine whether the data has been lost, tampered with, or has errors during transmission. The FPGA monitoring data area is a dedicated area inside the FPGA for storing valid monitoring data. It is the data source for subsequent data uploading, analysis, and traceability, and only stores valid data that has passed verification.

[0176] The beneficial effects of the above technical solution are as follows: by classifying the types of monitoring data and isolating the hardware channels, interference between different types of data is avoided; by combining hierarchical caching to adapt to the read and write characteristics of different data; by realizing zero-delay direct transmission of data through high-speed parallel interfaces; and by supplementing the hardware-level real-time verification and retransmission mechanism, the real-time performance and integrity of monitoring data readback are guaranteed, while the accuracy and reliability of the data are improved. This provides stable and efficient data support for signal monitoring, fault diagnosis and data traceability in PSI5 simulation testing, and solves the problems of easy data loss and high verification latency in existing technologies.

[0177] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A simulation method for a PSI5 card board, characterized in that, include: Step 1: Initialize and configure the PSI5 card system, complete FPGA logic resource allocation, DAC / ADC chip calibration, differential amplifier constant current circuit zeroing, fault injection module reset, and dual-mode communication module communication link establishment; Step 2: Select the host communication mode or slave communication mode according to the test requirements, receive remote configuration instructions through the dual-mode communication module, set the key parameters of the corresponding mode in software, and write them into the FPGA register. The key parameters include reference current, operating current, synchronization pulse amplitude, baud rate, encoding method and number of channels. Step 3: In slave communication mode, the FPGA generates an encoded signal conforming to the PSI5 protocol, which is then converted from digital to analog by a DAC and conditioned by a differential amplifier constant current circuit before being output to the external ECU. In master communication mode, the hardware acquisition circuit receives the PSI5 protocol signal from the external sensor, which is then conditioned and sent to the FPGA for protocol parsing. The differential amplifier constant current circuit is constructed from operational amplifiers and transistors. The FPGA performs hardware closed-loop correction of the amplification factor of the differential amplifier constant current circuit based on real-time acquired loop current data. Step 4: In slave communication mode, the synchronous pulse edge is captured by a comparator and a programmable voltage threshold and sent to the FPGA for high-precision timing analysis; in master communication mode, the voltage change of the series sampling resistor is detected, and the loop current is monitored in real time after being conditioned by an operational amplifier, and the monitoring data is read back to the FPGA. Step 5: According to the test requirements, send a trigger command to the fault injection module through the FPGA to realize the controllable injection of multiple types of faults in the PSI5 communication link. The multiple types of faults include at least one of power failure, line failure, signal integrity failure, timing failure, encoding and data failure, and frame structure failure. Step 6: Based on the FPGA, the first result generated in Step 3, the second result generated in Step 4, and the third result generated in Step 5 are summarized in real time, and the data is uploaded to the remote control terminal through the dual-mode communication module to complete the visualization and data traceability of the simulation process.

2. The simulation method for the PSI5 card board according to claim 1, characterized in that, After step 6, the following also includes: After the test is completed, the FPGA generates a simulation test report, which includes parameter configuration information, signal timing data, fault injection records, and hardware closed-loop monitoring data. The report is then uploaded to the remote control terminal via a dual-mode communication module, enabling the test cases to be reproducible and the data to be traceable.

3. The simulation method for the PSI5 card board according to claim 1, characterized in that, The triggering methods of the fault injection module triggering command include at least one of manual single triggering, timed cyclic triggering, and multi-fault combination triggering, and the software configuration of fault injection parameters includes: fault duration, fault amplitude, and fault triggering sequence.

4. The simulation method for the PSI5 card board according to claim 1, characterized in that, Before completing the FPGA logic resource allocation, the following steps are included: Based on the channel number configuration requirements of the PSI5 card, the global logic resource pool of the FPGA is pre-divided, and the global resource pool is divided into a protocol processing sub-resource pool, a timing scheduling sub-resource pool, a data interaction sub-resource pool, and a fault control sub-resource pool according to the functional dimension. The test requirements are analyzed and the current priority of each sub-resource pool is obtained. Based on the combination of current priorities, several simulation test cases are matched from the combination-simulation lookup table. Real-time monitoring of resource occupancy and channel load status of each sub-resource pool under each simulation test case; combined with the time-series data of resource interaction variables of the corresponding simulation test case, predicting the PSI5 frame period window in which the target channel blockage occurs. When it is predicted that the target channel will be blocked within N PSI5 frame periods, a four-dimensional demand vector of protocol processing computing power, timing counting accuracy, data buffer capacity and fault response latency of the target channel is extracted based on the logical resource demand model determined by the test scenario type of the corresponding simulation test case. Capture the resource interaction variables between each sub-resource pool and each other sub-resource pool during the simulation of the corresponding simulation test case, and obtain the scheduling threshold of redundant logical resources of the corresponding sub-resource pool and the PSI5 protocol timing alignment window; Traverse the FPGA global idle sub-resource pool, divide redundant logic resources into lightweight sequential logic, medium-weight cache logic, and heavyweight protocol processing logic according to their functional types, and prioritize the selection of redundant logic resources that meet the scheduling threshold, have the highest matching degree between their functional type and the four-dimensional demand vector, and whose loading timing falls within the PSI5 protocol timing alignment window, and regard them as the first resource; During the idle time slot of the PSI5 frame of the target channel, the first resource is dynamically loaded into the logical area of ​​the target channel; After scheduling is completed, the load status of the target channel and the interaction performance of the sub-resource pool are monitored in real time. Based on the monitoring results, the computing power allocation ratio of redundant logical resources is adaptively adjusted. At the same time, the demand vector, resource matching results and timing alignment data of this scheduling are updated to the combination-simulation comparison table.

5. The simulation method for the PSI5 card board according to claim 4, characterized in that, The scheduling threshold for redundant logical resources is the upper limit of computing power ratio and the lower limit of cache capacity.

6. The simulation method for the PSI5 card board according to claim 1, characterized in that, After setting the key parameters for the corresponding mode in software and writing them into the FPGA registers, the following steps are taken: The first parameter set is obtained by reading the write parameters of the FPGA registers and comparing the first parameter set with the standard parameter set of the corresponding mode. If they are completely consistent, the software setting is deemed qualified. Otherwise, multiple software-based random settings are performed, and the comparison group and the write group written to the FPGA register are obtained for each random setting. The comparison group and the write group are then compared to obtain the first difference group. If all first difference groups consist of 0 parameters, then restart the PSI5 card system; Otherwise, construct a value difference matrix based on all the first difference groups and perform normalization to obtain a normalized matrix; Simultaneously, the process log of each random setting and writing process is captured, and the running sub-logic of each random setting is constructed. The running sub-logic is compared with the standard sub-logic to determine that the running sub-logic is based on at least one sub-difference logic of the standard sub-logic. In this case, the same standard sub-logic is used for each random setting operation. The logical attribute pairs of each sub-difference logic are matched with the attribute-logic lookup table to obtain new logic, and the new logic and the corresponding sub-difference logic are preprocessed to obtain sub-coverage logic; The sub-overlay logic corresponding to each sub-difference logic is executed sequentially. When the execution bit of the corresponding sub-overlay logic is detected to reach the preset bit, the execution code of the corresponding sub-difference logic is obtained. When it is detected that the execution bit of the corresponding sub-coverage logic has not reached the preset bit, the register state of the corresponding sub-coverage logic is read and the status bit of the register state is responded to. The sub-compensation logic that has reached the preset bit from the status bit is retrieved from the historical database, and the execution code of the corresponding sub-difference logic based on the sub-compensation logic and the sub-coverage logic is obtained. Extract the new setting description of each key parameter from all executed code under each random setting, and combine them according to the parameter sorting order of the standard parameter group to obtain the current description group under each random setting. Compare the current description group with the standard description group corresponding to the standard parameter group to obtain the second difference group, and construct the description difference matrix. Based on the normalized matrix and the description difference matrix, obtain the difference type pairs of each key parameter, determine the abnormal environment object according to the difference type pairs, extract the optimization file that matches the abnormal environment object, and extract the compensation identifier and compensation position of the response difference type pairs from the optimization file. The compensation logic is determined based on the compensation identifier, and the insertion point of the compensation logic in the original parameter setting logic is determined according to the compensation position and inserted to obtain the new setting logic. At this time, the PSI5 card system is restarted.

7. The simulation method for the PSI5 card board according to claim 6, characterized in that, The normalization matrix is ​​the normalization group corresponding to the first difference group in the random setting. The columns of the normalization matrix are the normalization differences of the corresponding key parameters under different random settings, and the normalization differences are the difference values. The behavior of the description difference matrix corresponds to the current description group set in the next random setting. The columns of the description difference matrix are the description differences corresponding to the key parameters under different random settings, and the description differences are functional difference descriptions.

8. The simulation method for the PSI5 card board according to claim 1, characterized in that, The monitoring data is read back to the FPGA, including: The PSI5 card monitoring data is categorized into timing data, current data, and fault status data, and hardware acquisition channels are configured for each type of data. After being conditioned by the channel, various monitoring data are directly transmitted to the corresponding internal hierarchical buffer area through the FPGA high-speed parallel interface. Among them, timing data and current data are stored in the high-speed FIFO buffer, and fault status data are stored in the static register. The readback data is verified in real time at the hardware level. If the verification passes, the FPGA monitoring data area is updated. If the verification fails, the channel is retransmitted to complete the data readback.

Images