Buck chip and adaptive dead time circuit and dead time acquisition method thereof
By dynamically adjusting the dead time of the BUCK chip using an adaptive dead time circuit, the problem of inaccurate dead time under different load conditions is solved, thus improving efficiency and safety.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BEILING
- Filing Date
- 2026-04-01
- Publication Date
- 2026-06-30
AI Technical Summary
Existing BUCK chips cannot accurately determine the dead time under different load conditions, resulting in an excessively long dead time and significant efficiency loss under heavy load, and an excessively short dead time and minimal efficiency loss under light load, failing to take into account the risk of switch punch-through.
An adaptive dead-time circuit is adopted. By using a sample-and-hold circuit and a constant current source design, load current information is obtained, and the fixed dead time of the upper and lower transistors is dynamically adjusted to achieve adaptive control of the dead time.
It effectively reduces the conduction loss of the body diode, improves the efficiency of the BUCK chip, and takes into account the punch-through risk of the switching transistor, achieving a match between dead time and load current.
Smart Images
Figure CN122316083A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chips, and in particular to a BUCK chip and its adaptive dead-time circuit and dead-time acquisition method. Background Technology
[0002] Traditional ACOT (Constant On-Time) architecture BUCK chips (also known as Buck converters or step-down DC-DC converters, a type of switching power supply integrated circuit used to efficiently convert higher DC voltages to lower DC voltages) typically have a certain dead time to avoid the problem of the upper and lower transistors of the switching transistors passing through. This ensures that one switching transistor is completely turned off before another switching transistor is allowed to turn on.
[0003] However, since the Miller plateau voltage Vm of the switching transistor increases with the increase of load current, the turn-on speed of the switching transistor is not the same under different load conditions. In particular, the turn-on speed of the switching transistor is slower under heavy load, which results in a longer variable dead time td2 under heavy load, and a greater efficiency loss of the body diode freewheeling during the dead time. On the other hand, the turn-on speed of the switching transistor is faster under light load, resulting in a shorter dead time td2, and a smaller efficiency loss of the body diode freewheeling during the dead time. Therefore, it is impossible to determine the precise dead time. Summary of the Invention
[0004] The technical problem to be solved by this disclosure is to overcome the defect in the prior art that the dead time cannot be accurately determined, and to provide a BUCK chip and its adaptive dead time circuit and dead time acquisition method.
[0005] This disclosure solves the above-mentioned technical problems through the following technical solution:
[0006] According to a first aspect of this disclosure, an adaptive dead-time circuit for a BUCK chip is provided, the adaptive dead-time circuit including an upper-side dead-time control branch and a lower-side dead-time control branch;
[0007] The upper-side dead-time control branch includes a first sample-and-hold circuit, a first constant current source, a first current superposition node, a first timing capacitor, and a first inverter;
[0008] The first sample-and-hold circuit is used to sample and hold the valley current and output a first characterizing current proportional to the valley current; the first characterizing current and the first reference current output by the first constant current source are superimposed at the first current superposition node to charge the first timing capacitor when the upper tube pre-drive signal is valid.
[0009] The first inverter is used to output a high-side turn-on signal when the voltage on the first timing capacitor reaches its flip threshold.
[0010] The dead-time control branch of the lower transistor includes a second sample-and-hold circuit, a second constant current source, a second current superposition node, a second timing capacitor, and a second inverter;
[0011] The second sample-and-hold circuit is used to sample and hold the peak current and output a second characteristic current proportional to the peak current; the second characteristic current and the second reference current output by the second constant current source are superimposed at the second current superposition node to charge the second timing capacitor when the lower transistor pre-drive signal is valid;
[0012] The second inverter is used to output a lower transistor turn-on signal when the voltage on the second timing capacitor reaches its flip threshold.
[0013] When the load current of the BUCK chip increases, at least one of the first characterizing current and the second characterizing current increases, so as to shorten the corresponding fixed dead time.
[0014] Optionally, the first characteristic current output by the first sample-and-hold circuit is K1*Ivy, where Ivy is the valley current and K1 is the first proportional coefficient; the second characteristic current output by the second sample-and-hold circuit is K2*Ipk, where Ipk is the peak current and K2 is the second proportional coefficient.
[0015] Optionally, the BUCK chip adaptive dead-time circuit further includes: a signal triggering module; the signal triggering module includes: a first signal triggering module and a second signal triggering module;
[0016] The first signal triggering module is used to output the upper tube pre-drive signal (HS_ON_PRE signal).
[0017] The second signal trigger module is used to output the lower tube pre-drive signal (LS_ON_PRE signal);
[0018] The upper transistor pre-drive signal being valid includes the upper transistor pre-drive signal going high and the lower transistor pre-drive signal going low. The charging current at the first current superposition node is used to charge the first timing capacitor to control the flip-off time of the first inverter, thereby delaying the turn-on of the upper transistor after the lower transistor is turned off.
[0019] And / or,
[0020] The lower transistor pre-drive signal being valid includes the lower transistor pre-drive signal going high and the upper transistor pre-drive signal going low. The charging current at the second current superposition node is used to charge the second timing capacitor to control the flip-flop time of the second inverter, thereby delaying the turn-on of the lower transistor after the upper transistor is turned off.
[0021] Optionally, the fixed dead time corresponding to the upper tube dead time control branch is related to the capacitance value of the first timing capacitor, the flip threshold of the first inverter, and the charging current at the first current superposition node.
[0022] The fixed dead time corresponding to the lower tube dead time control branch is related to the capacitance value of the second timing capacitor, the flip threshold of the second inverter, and the charging current at the second current superposition node.
[0023] Optionally, the fixed dead time td_HS corresponding to the upper pipe dead time control branch satisfies:
[0024] td_HS=C1×Vt1 / (Id1+K1×Ivy);
[0025] The fixed dead time td_LS corresponding to the dead time control branch of the downpipe satisfies:
[0026] td_LS=C2×Vt2 / (Id2+K2×Ipk);
[0027] Wherein, C1 is the capacitance value of the first timing capacitor, C2 is the capacitance value of the second timing capacitor, Vt1 is the toggle threshold of the first inverter, Vt2 is the toggle threshold of the second inverter, Id1 is the first reference current, and Id2 is the second reference current.
[0028] Optionally, the total dead time includes the fixed dead time corresponding to the upper pipe dead time control branch and the fixed dead time corresponding to the lower pipe dead time control branch.
[0029] According to a second aspect of this disclosure, a method for obtaining dead time is provided, characterized in that the method for obtaining dead time is implemented based on the adaptive dead time circuit of the BUCK chip described in the first aspect of this disclosure, and the method includes:
[0030] During the switching cycle, load current information is acquired, and the load current information includes at least valley current and peak current.
[0031] The valley current and the peak current are sampled and held respectively to obtain a first characterizing current proportional to the valley current and a second characterizing current proportional to the peak current.
[0032] The first characterization current is superimposed with the first reference current. When the upper tube pre-drive signal is valid, the first timing capacitor is charged. When the voltage on the first timing capacitor reaches the first inverter flip threshold, the fixed dead time on the upper tube side is obtained.
[0033] The second characterization current is superimposed with the second reference current. When the lower tube pre-drive signal is valid, the second timing capacitor is charged. When the voltage on the second timing capacitor reaches the second inverter flip threshold, the fixed dead time on the lower tube side is obtained.
[0034] Based on the fixed dead time on the upper tube side and the fixed dead time on the lower tube side, the conduction timing of the upper and lower tubes of the BUCK chip is controlled so that the dead time can be adaptively adjusted according to the load change.
[0035] Optionally, obtaining the fixed dead time on the upper pipe side includes:
[0036] When the upper tube pre-drive signal goes high and the lower tube pre-drive signal goes low, the first timing capacitor is charged using the charging current, and the time from the start of charging to the flip of the first inverter is determined as the upper tube side fixed dead time.
[0037] And / or,
[0038] The process of obtaining the fixed dead time on the lower pipe side includes:
[0039] When the pre-drive signal goes high and the upper tube pre-drive signal goes low, the second timing capacitor is charged using the charging current, and the time from the start of charging to the flip of the second inverter is determined as the fixed dead time on the lower tube side.
[0040] Optionally, the fixed dead time on the upper tube side is negatively correlated with the valley current, and the fixed dead time on the lower tube side is negatively correlated with the peak current, so that the fixed dead time is shorter when the load is heavier and longer when the load is lighter.
[0041] According to a third aspect of this disclosure, a BUCK chip is provided, including the BUCK chip adaptive dead-time circuit described in the first aspect of this disclosure.
[0042] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.
[0043] The positive and progressive effects of this disclosure are as follows:
[0044] The adaptive dead-time circuit of the BUCK chip provided in this disclosure dynamically changes the length of the fixed dead time td1 by detecting the load current, and automatically adjusts the length of the total dead time td, thereby effectively reducing the conduction loss of the body diode, improving the BUCK efficiency, and taking into account the risk of switch punch-through. Attached Figure Description
[0045] Figure 1 This is a circuit diagram for obtaining the traditional dead time.
[0046] Figure 2A schematic diagram of the structure to obtain the actual dead time;
[0047] Figure 3 This is a schematic diagram of the adaptive dead-time circuit of the BUCK chip provided in Embodiment 1 of this disclosure;
[0048] Figure 4 This is a flowchart illustrating the method for obtaining dead time provided in Embodiment 2 of this disclosure. Detailed Implementation
[0049] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.
[0050] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not be construed as an unnecessary limitation. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.
[0051] like Figure 1 as well as Figure 2 As shown, the actual dead time td consists of two parts, such as... Figure 2 As shown: one part is the fixed dead time td1 from the issuance of the lower MOSFET turn-off signal (PWM_SHOT) to the start of the upper MOSFET turn-on; the other part is the variable dead time td2 from the start of the upper MOSFET turn-on to the complete transfer of the lower MOSFET current to the upper MOSFET channel.
[0052] The circuit for fixing the dead time td1 of the upper transistor is as follows: When the HS_ON_PRE signal goes high and the LS_ON_PRE signal goes low, the constant current source Id1 charges capacitor C1 to control the toggle time of inverter INV1, ensuring that switching transistor MN is completely off before switching transistor MP can be turned on. The circuit for fixing the dead time of the lower transistor is as follows: When LS_ON_PRE goes high and HS_ON_PRE goes low, the constant current source Id2 charges capacitor C2 to control the toggle time of inverter INV2, ensuring that switching transistor MP is completely off before switching transistor MN can be turned on. The specific expression for the fixed dead time td1 of the upper transistor is as follows:
[0053] td1=C1*Vt / Id1
[0054] Where Vt is the toggling threshold of inverter INV1.
[0055] The variable dead time td2 is more complex and is usually defined as the time from when the switch starts to turn on (gate-source voltage is 0) until the gate-source voltage reaches the Miller plateau voltage Vm. Its expression is:
[0056] td2=Cgs_HS*Vm / Idrv_HS
[0057] Where Cgs_HS is the gate-source capacitance of the upper transistor, and Idrv_HS is the drive current of the upper transistor;
[0058] Since the Miller plateau voltage Vm of the switching transistor increases with the increase of load current, the switching speed of the transistor is not the same under different load conditions. In particular, the switching speed is slower under heavy load, which results in a longer variable dead time td2 under heavy load, and greater efficiency loss of body diode freewheeling during the dead time. On the other hand, the switching speed is faster under light load, resulting in a shorter dead time td2, and less efficiency loss of body diode freewheeling during the dead time.
[0059] In view of this, this disclosure provides an adaptive dead time circuit for a BUCK chip to achieve dynamic adjustment of the dead time.
[0060] Example 1
[0061] like Figure 3 As shown, this embodiment provides an adaptive dead-time circuit for a BUCK chip, which includes an upper transistor dead-time control branch and a lower transistor dead-time control branch.
[0062] The dead-time control branch of the upper tube includes a first sample-and-hold circuit S&H, a first constant current source Id1, a first current superposition node A, a first timing capacitor C1, and a first inverter INV1;
[0063] The first sample-and-hold circuit is used to sample and hold the valley current and output a first characterizing current proportional to the valley current; the first characterizing current is superimposed on the first reference current output by the first constant current source at the first current superposition node to charge the first timing capacitor when the upper tube pre-drive signal is valid.
[0064] The first inverter is used to output the upper transistor turn-on signal when the voltage on the first timing capacitor reaches its flip threshold.
[0065] The dead-time control branch of the lower transistor includes the second sample-and-hold circuit S&H, the second constant current source Id2, the second current superposition node B, the second timing capacitor C2, and the second inverter INV2;
[0066] The second sample-and-hold circuit is used to sample and hold the peak current and output a second characteristic current proportional to the peak current; the second characteristic current is superimposed on the second reference current output by the second constant current source at the second current superposition node to charge the second timing capacitor when the lower transistor pre-drive signal is valid.
[0067] The second inverter is used to output a lower transistor turn-on signal when the voltage on the second timing capacitor reaches its flip threshold.
[0068] When the load current of the BUCK chip increases, at least one of the first characterizing current and the second characterizing current increases, so as to shorten the corresponding fixed dead time.
[0069] The adaptive dead-time circuit of the BUCK chip provided in this disclosure can effectively adapt the length of the dead time to the load current, which reduces the efficiency loss during the conduction stage of the body diode and avoids the risk of power transistor punch-through.
[0070] In this embodiment, the first characteristic current output by the first sample-and-hold circuit is K1*Ivy, where Ivy is the valley current and K1 is the first proportional coefficient; the second characteristic current output by the second sample-and-hold circuit is K2*Ipk, where Ipk is the peak current and K2 is the second proportional coefficient.
[0071] like Figure 3 As shown, the adaptive dead-time circuit of the BUCK chip also includes: a signal triggering module; the signal triggering module includes: a first signal triggering module PWM_SHOT and a second signal triggering module TON_SHOT;
[0072] The first signal triggering module is used to output the upper tube pre-drive signal (HS_ON_PRE signal).
[0073] The second signal triggering module is used to output the lower tube pre-drive signal (LS_ON_PRE signal).
[0074] The upper transistor pre-drive signal being valid includes the upper transistor pre-drive signal going high and the lower transistor pre-drive signal going low. The charging current at the first current superposition node is used to charge the first timing capacitor to control the toggling time of the first inverter, thereby turning on the upper transistor after a delay after the lower transistor is turned off.
[0075] The lower transistor pre-drive signal being valid includes the lower transistor pre-drive signal going high and the upper transistor pre-drive signal going low. The charging current at the second current superposition node is used to charge the second timing capacitor to control the toggle time of the second inverter, thereby turning on the lower transistor after a delay after the upper transistor is turned off.
[0076] In this embodiment, the fixed dead time corresponding to the upper tube dead time control branch is related to the capacitance value of the first timing capacitor, the flip threshold of the first inverter, and the charging current at the first current superposition node.
[0077] The fixed dead time corresponding to the lower tube dead time control branch is related to the capacitance value of the second timing capacitor, the flip threshold of the second inverter, and the charging current at the second current superposition node.
[0078] Among them, the fixed dead time td_HS corresponding to the upper dead time control branch satisfies:
[0079] td_HS=C1×Vt1 / (Id1+K1×Ivy);
[0080] As can be seen from the above formula, under the condition that other parameters remain basically unchanged, the larger the valley current Ivy is, the larger the charging current is, and the shorter the fixed dead time td_HS on the upper side is; the smaller the valley current Ivy is, the smaller the charging current is, and the longer the fixed dead time td_HS on the upper side is.
[0081] Accordingly, the dead-time control branch of the lower transistor includes a second sample-and-hold circuit, a second constant current source Id2, a second current superposition node B, a second timing capacitor C2, and a second inverter INV2. The second sample-and-hold circuit samples and holds the peak current Ipk information and converts the peak current Ipk into a second characteristic current K2×Ipk proportional to it. The second characteristic current K2×Ipk is superimposed on the second constant current source Id2 at the second current superposition node B to form the total charging current for charging the second timing capacitor C2.
[0082] When the LS_ON_PRE signal goes high and the HS_ON_PRE signal goes low, it indicates that the lower transistor is about to turn on while the upper transistor has entered the turn-off process. At this time, the second timing capacitor C2 begins to charge under the action of the total charging current. As the voltage across the second timing capacitor C2 gradually rises, when this voltage reaches the toggling threshold Vt2 of the second inverter INV2, the second inverter INV2 flips and outputs a lower transistor turn-on signal to control the lower transistor to turn on. Therefore, the fixed dead time on the lower transistor side is determined by the charging time of the second timing capacitor C2.
[0083] The fixed dead time td_LS corresponding to the dead time control branch of the lower pipe satisfies:
[0084] td_LS=C2×Vt2 / (Id2+K2×Ipk);
[0085] Wherein, C1 is the capacitance value of the first timing capacitor, C2 is the capacitance value of the second timing capacitor, Vt1 is the toggling threshold of the first inverter, Vt2 is the toggling threshold of the second inverter, Id1 is the first reference current, and Id2 is the second reference current.
[0086] As can be seen from the above formula, under the condition that other parameters remain basically unchanged, the larger the peak current Ipk, the larger the charging current and the shorter the fixed dead time td_LS on the lower MOSFET side; the smaller the peak current Ipk, the smaller the charging current and the longer the fixed dead time td_LS on the lower MOSFET side.
[0087] In this embodiment, the total dead time includes the fixed dead time corresponding to the upper pipe dead time control branch and the fixed dead time corresponding to the lower pipe dead time control branch.
[0088] In this embodiment, by introducing an additional charging current that characterizes the load current into the traditional fixed dead time circuit, the fixed dead time is no longer a constant, but can be automatically adjusted with load changes. Compared with the scheme that only relies on a constant current source and capacitor to determine the fixed dead time, this embodiment achieves adaptive control of the dead time without significantly increasing the control complexity.
[0089] Example 2
[0090] like Figure 4 As shown, this embodiment provides a method for obtaining dead time. The method for obtaining dead time is based on the adaptive dead time circuit of the BUCK chip in Embodiment 1, and the method includes:
[0091] S11: Obtain load current information during the switching cycle. The load current information includes at least the valley current and the peak current.
[0092] S12: Sample and hold the valley current and the peak current respectively to obtain a first characterizing current proportional to the valley current and a second characterizing current proportional to the peak current.
[0093] S13: Superimpose the first characterization current with the first reference current, charge the first timing capacitor when the upper tube pre-drive signal is valid, and obtain the upper tube side fixed dead time when the voltage on the first timing capacitor reaches the first inverter flip threshold.
[0094] S14: Superimpose the second characterization current with the second reference current, charge the second timing capacitor when the lower tube pre-drive signal is valid, and obtain the fixed dead time on the lower tube side when the voltage on the second timing capacitor reaches the second inverter flip threshold.
[0095] S15: Based on the fixed dead time of the upper and lower transistors, control the conduction timing of the upper and lower transistors of the BUCK chip so that the dead time can be adaptively adjusted according to the load change.
[0096] The acquisition of the fixed dead time on the upper pipe side includes:
[0097] When the upper tube pre-drive signal goes high and the lower tube pre-drive signal goes low, the first timing capacitor is charged using the charging current, and the time from the start of charging to the flip of the first inverter is determined as the upper tube side fixed dead time.
[0098] The time to obtain the fixed dead zone on the lower pipe side includes:
[0099] When the pre-drive signal goes high and the upper tube pre-drive signal goes low, the second timing capacitor is charged using the charging current, and the time from the start of charging to the flip of the second inverter is determined as the fixed dead time on the lower tube side.
[0100] Among them, the fixed dead time on the upper tube side is negatively correlated with the valley current, and the fixed dead time on the lower tube side is negatively correlated with the peak current, so that the fixed dead time is shorter when the load is heavier and longer when the load is lighter.
[0101] The method provided in this disclosure designs an adaptive dead-time circuit whose dead time varies with the load by superimposing load current information onto the dead-time circuit, thereby effectively reducing the conduction loss of the body diode freewheeling and effectively improving the efficiency of the BUCK chip.
[0102] Example 3
[0103] This embodiment provides a BUCK chip, including the BUCK chip adaptive dead time circuit in embodiment 1.
[0104] In some implementations, the BUCK chip is an ACOT architecture BUCK chip. When the BUCK chip is working, the adaptive dead-time circuit dynamically adjusts the fixed dead-time of the upper transistor side and the fixed dead-time of the lower transistor side according to the load state, thereby reducing the losses caused by the conduction of the power transistor diodes, improving the conversion efficiency, and taking into account the punch-through protection requirements of the upper and lower transistors.
[0105] It should be noted that the parameters used in the above embodiments, such as the first proportional coefficient K1, the second proportional coefficient K2, the first constant current source Id1, the second constant current source Id2, the first timing capacitor C1, the second timing capacitor C2, and the inverter flip threshold, can be set according to the chip process, target efficiency, switching frequency, driving capability, and safety margin. Their specific values do not constitute a limitation on the scope of protection of this invention.
[0106] The chip provided in this disclosure can superimpose load current information onto the dead time circuit, designing an adaptive dead time circuit that changes with load, thereby effectively reducing the conduction loss of the body diode freewheeling and effectively improving the efficiency of the BUCK chip.
[0107] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.
Claims
1. A BUCK chip adaptive dead-time circuit, characterized in that, The adaptive dead-time circuit includes an upper-side dead-time control branch and a lower-side dead-time control branch; The upper-side dead-time control branch includes a first sample-and-hold circuit, a first constant current source, a first current superposition node, a first timing capacitor, and a first inverter; The first sample-and-hold circuit is used to sample and hold the valley current and output a first characterizing current proportional to the valley current; the first characterizing current and the first reference current output by the first constant current source are superimposed at the first current superposition node to charge the first timing capacitor when the upper tube pre-drive signal is valid. The first inverter is used to output a high-side turn-on signal when the voltage on the first timing capacitor reaches its flip threshold. The dead-time control branch of the lower transistor includes a second sample-and-hold circuit, a second constant current source, a second current superposition node, a second timing capacitor, and a second inverter; The second sample-and-hold circuit is used to sample and hold the peak current and output a second characteristic current proportional to the peak current; the second characteristic current and the second reference current output by the second constant current source are superimposed at the second current superposition node to charge the second timing capacitor when the lower transistor pre-drive signal is valid; The second inverter is used to output a lower transistor turn-on signal when the voltage on the second timing capacitor reaches its flip threshold. When the load current of the BUCK chip increases, at least one of the first characterizing current and the second characterizing current increases, so as to shorten the corresponding fixed dead time.
2. The adaptive dead-time circuit for the BUCK chip according to claim 1, characterized in that, The first characteristic current output by the first sample-and-hold circuit is K1*Ivy, where Ivy is the valley current and K1 is the first proportional coefficient; the second characteristic current output by the second sample-and-hold circuit is K2*Ipk, where Ipk is the peak current and K2 is the second proportional coefficient.
3. The adaptive dead-time circuit for the BUCK chip according to claim 1, characterized in that, The adaptive dead-time circuit of the BUCK chip further includes: a signal triggering module; the signal triggering module includes: a first signal triggering module and a second signal triggering module; The first signal triggering module is used to output the upper tube pre-drive signal; The second signal triggering module is used to output the lower tube pre-drive signal; The upper transistor pre-drive signal being valid includes the upper transistor pre-drive signal going high and the lower transistor pre-drive signal going low. The charging current at the first current superposition node is used to charge the first timing capacitor to control the flip-off time of the first inverter, thereby delaying the turn-on of the upper transistor after the lower transistor is turned off. And / or, The lower transistor pre-drive signal being valid includes the lower transistor pre-drive signal going high and the upper transistor pre-drive signal going low. The charging current at the second current superposition node is used to charge the second timing capacitor to control the flip-flop time of the second inverter, thereby delaying the turn-on of the lower transistor after the upper transistor is turned off.
4. The adaptive dead-time circuit for the BUCK chip according to claim 1, characterized in that, The fixed dead time corresponding to the upper tube dead time control branch is related to the capacitance value of the first timing capacitor, the flip threshold of the first inverter, and the charging current at the first current superposition node. The fixed dead time corresponding to the lower tube dead time control branch is related to the capacitance value of the second timing capacitor, the flip threshold of the second inverter, and the charging current at the second current superposition node.
5. The adaptive dead-time circuit for the BUCK chip according to claim 4, characterized in that, The fixed dead time td_HS corresponding to the upper pipe dead time control branch satisfies: td_HS=C1×Vt1 / (Id1+K1×Ivy); The fixed dead time td_LS corresponding to the dead time control branch of the downpipe satisfies: td_LS=C2×Vt2 / (Id2+K2×Ipk); Wherein, C1 is the capacitance value of the first timing capacitor, C2 is the capacitance value of the second timing capacitor, Vt1 is the toggle threshold of the first inverter, Vt2 is the toggle threshold of the second inverter, Id1 is the first reference current, and Id2 is the second reference current.
6. The adaptive dead-time circuit for the BUCK chip according to claim 5, characterized in that, The total dead time includes the fixed dead time corresponding to the upper pipe dead time control branch and the fixed dead time corresponding to the lower pipe dead time control branch.
7. A method for obtaining dead time, characterized in that, The method for obtaining the dead time is implemented based on the adaptive dead time circuit of the BUCK chip according to any one of claims 1-6, and the method includes: During the switching cycle, load current information is acquired, and the load current information includes at least valley current and peak current. The valley current and the peak current are sampled and held respectively to obtain a first characterizing current proportional to the valley current and a second characterizing current proportional to the peak current. The first characterization current is superimposed with the first reference current. When the upper tube pre-drive signal is valid, the first timing capacitor is charged. When the voltage on the first timing capacitor reaches the first inverter flip threshold, the fixed dead time on the upper tube side is obtained. The second characterization current is superimposed with the second reference current. When the lower tube pre-drive signal is valid, the second timing capacitor is charged. When the voltage on the second timing capacitor reaches the second inverter flip threshold, the fixed dead time on the lower tube side is obtained. Based on the fixed dead time on the upper tube side and the fixed dead time on the lower tube side, the conduction timing of the upper and lower tubes of the BUCK chip is controlled so that the dead time can be adaptively adjusted according to the load change.
8. The method for obtaining dead time according to claim 7, characterized in that, The process of obtaining the fixed dead time on the upper pipe side includes: When the upper tube pre-drive signal goes high and the lower tube pre-drive signal goes low, the first timing capacitor is charged using the charging current, and the time from the start of charging to the flip of the first inverter is determined as the upper tube side fixed dead time. And / or, The process of obtaining the fixed dead time on the lower pipe side includes: When the pre-drive signal goes high and the upper tube pre-drive signal goes low, the second timing capacitor is charged using the charging current, and the time from the start of charging to the flip of the second inverter is determined as the fixed dead time on the lower tube side.
9. The method for obtaining dead time according to claim 8, characterized in that, The fixed dead time on the upper tube side is negatively correlated with the valley current, and the fixed dead time on the lower tube side is negatively correlated with the peak current, so that the fixed dead time is shorter when the load is heavier and longer when the load is lighter.
10. A BUCK chip, characterized in that, The BUCK chip adaptive dead-time circuit includes any one of claims 1 to 6.