A parasitic cancellation gain cell and distributed amplifier

Abstract

This invention discloses a parasitic cancellation gain unit and a distributed amplifier, belonging to the field of amplifier technology. The parasitic cancellation gain unit is a parasitic cancellation common-source cascode gain unit, comprising two groups of small transistors and multiple parallel embedded capacitors. Each group of small transistors includes four small transistors connected in parallel, and the two groups of small transistors respectively replace a single large transistor in the common-source and common-gate stages. The multiple parallel embedded capacitors are embedded in the traces of the connection capacitors and decoupling capacitors of the common-source cascode gain unit to cancel the influence of parasitic inductance generated by the traces. A distributed amplifier is composed of multiple stages of the above-mentioned parasitic cancellation gain units and input / output transmission lines. This invention solves the problems of limited bandwidth, significant parasitic effects, and large size of distributed amplifiers under traditional bulk CMOS technology.

Description

Technical Field

[0001] This invention belongs to the field of amplifier technology, specifically relating to a parasitic cancelling gain unit and a distributed amplifier. Background Technology

[0002] Wideband amplifiers are in high demand in multi-band wireless / wired communications, radar, high-resolution imaging, and optical transmission. Distributed amplifiers, with their significant advantages such as ultra-wideband characteristics, wideband power matching capabilities, and high data transmission rates, have become the ideal technology choice for these applications.

[0003] In existing technologies, distributed amplifiers based on SiGe and InP processes have achieved wide bandwidth and high output power, but they suffer from incompatibility with CMOS processes, high cost, and low yield, limiting their practical applications. Distributed amplifiers using silicon-on-insulator (SOI) processes have developed rapidly in terms of ultra-wide bandwidth and high linearity, but the complex manufacturing process also brings the challenge of increased costs.

[0004] In contrast, traditional bulk CMOS technology offers significant advantages such as excellent scalability, high manufacturing yield, and integration with digital circuits. However, distributed amplifiers based on this technology still face challenges such as limited bandwidth, significant parasitic effects, and limited voltage swing. The gain unit, as the core design element of a distributed amplifier, directly determines the overall performance of the amplifier: stacking multiple transistors can increase supply voltage and output power, but it increases power consumption; complementary NMOS-PMOS structures can reduce amplitude-phase distortion and improve linearity, but at the expense of bandwidth. Therefore, realizing a high-gain distributed amplifier on bulk CMOS technology with an operating bandwidth exceeding 100 GHz, while also possessing high output power, high efficiency, good linearity, and a compact circuit size, remains a formidable challenge.

[0005] Existing technology 1 Existing technology 1, based on 45-nm RF SOI process, employs an in-stage coupled (k1) common-source cascode gain unit in the design of a distributed amplifier. This coupling is used to compensate for the loss of parasitic capacitance between the gate and drain of the transistor, improve the transconductance of the gain unit at high frequencies, and achieve an operating bandwidth of up to 137 GHz.

[0006] The disadvantages of this existing technology are: the presence of on-chip choke coils occupies a large area, which is not conducive to miniaturization integration; and the 45-nm RF SOI process is complex to manufacture and consumes huge costs.

[0007] Existing technology 2 Existing technology two, based on a 22-nm FD SOI process, proposes a pseudo-differential distributed amplifier. It employs complementary NMOS-PMOS cascode gain units, avoiding the use of external biasers (Bias-T) and reducing design cost and area. Simultaneously, by utilizing the opposite amplitude-phase distortion characteristics of NMOS and PMOS, the distortion of the distributed amplifier is reduced, and linearity is improved to support high-speed transmission rates. Experimental results show that this design achieves a small-signal bandwidth of 0.4-31.6 GHz and can support a modulation rate of 96 Gbps 64-QAM at a carrier frequency of 17 GHz.

[0008] The drawbacks of this existing technology are: limited bandwidth, making it difficult to cover higher frequency band requirements; and a modulation average PAE of only 3.9%, indicating that efficiency needs to be improved. Summary of the Invention

[0009] The purpose of this invention is to provide a parasitic cancellation gain unit and a distributed amplifier to solve the above-mentioned technical problems.

[0010] The technical solution adopted in this invention is as follows: To address the aforementioned technical problems, this invention first proposes a parasitic cancellation cascode gain unit. This gain unit effectively reduces parasitic effects and improves high-frequency performance through a dual parasitic cancellation design, as detailed below: A parasitic cancellation gain unit, which is a parasitic cancellation common-source cascode gain unit, includes two sets of small transistor groups and multiple parallel embedded capacitors; One group of small transistors consists of four small transistors connected in parallel, and the two groups of small transistors replace the single large transistors of the common source stage and the common gate stage, respectively. The multiple parallel embedded capacitors are embedded in the traces of the connection capacitor and decoupling capacitor of the common source cascode gain unit to counteract the effects of parasitic inductance generated by the traces.

[0011] Furthermore, the size of the single large transistor is W×L, and the size of each small transistor is (W / 4)×L, with a group of small transistors maintaining the same total size as the single large transistor it replaces.

[0012] A distributed amplifier consists of multiple stages of the aforementioned parasitic cancelling gain units and input / output transmission lines.

[0013] Furthermore, the input / output transmission lines adopt a helical structure, and there is coupling between the helical input / output transmission lines. It is used to compensate for the passive loss of transmission lines.

[0014] Furthermore, the transistor size and output transmission line impedance of each stage of the parasitic cancellation gain unit gradually change along a specified direction to improve the passband flatness of the distributed amplifier.

[0015] Furthermore, the parasitic cancellation gain unit has 6 stages.

[0016] Furthermore, the distributed amplifier is implemented based on a 28-nm bulk CMOS process.

[0017] Furthermore, the core circuit of the distributed amplifier has a size of 0.529 mm × 0.071 mm, a 3-dB bandwidth of up to 108 GHz, a maximum gain of 7.8 dB, and an input-output matching of less than -10 dB throughout the entire operating frequency band.

[0018] In summary, the beneficial effects of this invention are: 1. Compared with a large transistor, the parallel structure of four small transistors has the following advantages: 1) The source-drain parasitic resistance is smaller, which is simply attributed to the influence of a variety of factors, including the increase in the number of contact holes and the smaller metal lead resistance; 2) The current distribution is uniform, avoiding the decrease in reliability caused by heat accumulation. 2. In order to further eliminate parasitics, this invention introduces multiple parallel embedded capacitors, which increases the operating bandwidth of the distributed amplifier and improves stability. 3. Coupling exists between the spiral-shaped input and output transmission lines of this invention. To compensate for the passive losses of the transmission line, further increase the operating bandwidth of the distributed amplifier and achieve miniaturization; 4. The transistor size and output TL impedance of each gain unit in this invention are changed along the arrow direction shown in the respective figure to improve the passband flatness and operating efficiency of the distributed amplifier. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a design diagram of a distributed amplifier, a technology currently in use. Figure 2 This is a design diagram of a distributed amplifier based on existing technology. Figure 3 Design process of cascode gain cell for parasitic cancellation; Figure 4This is a schematic diagram of the parasitic cancellation principle; Figure 5 This is a diagram illustrating the parasitic cancellation effect. Figure 6 This is a diagram of the architecture of a distributed amplifier. Figure 7 This is a design diagram of a distributed amplifier; Figure 8 The graph shows the small-signal test results for the distributed amplifier. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] To highlight the technical effects of this application, the prior art related to this application is described, and the specific prior art is as follows: Prior art related to this invention like Figure 1 As shown, the existing technology is based on a 45-nm RF SOI process and employs an intra-stage coupled (k1) cascode gain unit in the distributed amplifier design. This coupling compensates for the losses caused by parasitic capacitance between the transistor gate and drain, improving the transconductance of the gain unit at high frequencies, thereby achieving an operating bandwidth of up to 137 GHz. However, the presence of the on-chip choke coil occupies a significant area, hindering miniaturization and integration. Furthermore, the 45-nm RF SOI process used in this design is complex to manufacture, resulting in substantial cost.

[0022] Prior art related to this invention Based on the 22-nm FD SOI process, this prior art proposes a pseudo-differential distributed amplifier, such as... Figure 2As shown, the complementary NMOS-PMOS cascode gain unit avoids the use of an external bias resistor (Bias-T), reducing design cost and area. Furthermore, this complementary unit effectively reduces the distortion of the distributed amplifier by utilizing the opposite amplitude-phase distortion characteristics of NMOS and PMOS, improving linearity to better support high-speed transmission rates. Experimental results show that this design achieves a small-signal bandwidth of 0.4–31.6 GHz, while supporting a modulation rate of 96 Gbps 64-QAM at a carrier frequency of 17 GHz. However, compared to other existing distributed amplifier designs, this design has limited bandwidth, making it difficult to cover higher frequency band requirements. Additionally, the average modulation output efficiency (PAE) is 3.9%, indicating room for improvement.

[0023] Example 1

[0024] This embodiment provides a parasitic cancellation gain unit, which is a parasitic cancellation common-source cascode gain unit, such as... Figure 3 As shown in (a) to (c), the design process is as follows: S1. Complete the first part of the parasitic cancellation design: ... Figure 3 (a) The single large transistor with size W×L is replaced with Figure 3 (b) consists of four small transistors, each with a size of (W / 4)×L, connected in parallel to maintain the same overall size as a single large transistor, ensuring comparable amplification capability. Compared to a single large transistor, the parallel structure of four small transistors has the following advantages: lower source-drain parasitic resistance, which can be simply attributed to the influence of a number of factors, including the increased number of contact holes and lower metal lead resistance; and more uniform current distribution, avoiding reliability degradation caused by heat accumulation. The second step is to complete the second part of the parasitic cancellation design: such as Figure 3 As shown in (b) to (c), in order to further eliminate parasites, [a specific substance] was introduced. Figure 3 (c) contains multiple embedded capacitors.

[0025] Specific diagrams and effect images of the parasitic cancellation principle are as follows: Figure 4 (a) to (c) and Figure 5 As shown; Figure 4 As shown in (a), in a traditional gain unit, a single capacitor C1 is connected to a decoupling capacitor (decap) via a trace. The transformer within the stage, composed of inductors L1 and L2 and a coupling coefficient kc, is used to compensate for current leakage caused by the transistor's parasitic capacitance. However, as the frequency increases, as... Figure 4 As shown in (b), the parasitic inductance Lpar caused by the trace connecting C1 and decap continuously increases, which is equivalent to increasing the inductance value in the transformer, thus causing it to malfunction. Therefore, in order to reduce Lpar, multiple capacitors are embedded in the trace, such as... Figure 4As shown in (c). From Figure 5 As shown, the operating bandwidth of the distributed amplifier is increased and the stability is improved by using multiple embedded parallel capacitors.

[0026] in, Figure 4 (a) is a traditional cascode gain cell without considering parasitic inductance Lpar; Figure 4 (b) For a traditional common-source cascode gain unit that takes into account the parasitic inductance Lpar, as the frequency increases, Lpar increases, causing abnormal operation of the transformer; Figure 4 (c) is the common-source cascode gain unit with dual parasitic cancellation proposed in this invention, which reduces Lpar through embedded capacitors; Figure 5 A comparison of the frequency response of two gain units applied to a distributed amplifier shows that the gain unit of the present invention can significantly broaden the operating bandwidth and improve stability.

[0027] Example 2

[0028] Implementation of a distributed amplifier based on parasitic cancelling gain units: The distributed amplifier in this embodiment, such as... Figure 6 As shown, the parasitic cancellation cascode gain unit described in Embodiment 1 has the following specific architecture: This distributed amplifier consists of a six-stage parasitic cancelling cascode gain unit and input / output transmission lines (TLs). The input and output TLs adopt a spiral structure, and there is coupling between the spiral input and output TLs. It is used to compensate for the passive loss of TL, thereby achieving bandwidth improvement and miniaturization design.

[0029] To further improve passband flatness and operating efficiency, the transistor size and output TL impedance of each gain unit are designed to gradually change along the arrow direction shown in the respective figure, so that the amplifier can maintain stable performance throughout the entire operating frequency band.

[0030] The distributed amplifier in this embodiment is implemented using a 28-nm bulk CMOS process. A physical design diagram of the distributed amplifier is shown below. Figure 7 As shown, the core circuit dimensions are 0.529 mm × 0.071 mm; small signal test results are as follows. Figure 8 As shown, the 3-dB bandwidth is up to 108 GHz, the maximum gain is 7.8 dB, and the input and output matching is almost less than -10 dB throughout the entire operating frequency band, which fully meets the application requirements of ultra-wideband, miniaturization and high efficiency.

[0031] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A parasitic cancellation gain unit, characterized in that, The parasitic cancellation gain unit is a parasitic cancellation common-source cascode gain unit, which includes two sets of small transistor groups and multiple parallel embedded capacitors. One group of small transistors consists of four small transistors connected in parallel, and the two groups of small transistors replace the single large transistors of the common source stage and the common gate stage, respectively. The multiple parallel embedded capacitors are embedded in the traces of the connection capacitor and decoupling capacitor of the common source cascode gain unit to counteract the effects of parasitic inductance generated by the traces.

2. The parasitic cancellation gain unit according to claim 1, characterized in that, The size of the single large transistor is W×L, and the size of each small transistor is (W / 4)×L. A group of small transistors maintains the same total size as the single large transistor it replaces.

3. A distributed amplifier including the parasitic cancellation gain unit as described in claim 1 or 2, characterized in that, It consists of a multi-stage parasitic cancellation gain unit and input / output transmission lines.

4. The distributed amplifier according to claim 3, characterized in that, The input and output transmission lines adopt a helical structure, and there is coupling between the helical input and output transmission lines. It is used to compensate for the passive loss of transmission lines.

5. The distributed amplifier according to claim 3, characterized in that, The transistor size and output transmission line impedance of each stage of the parasitic cancellation gain unit gradually change along a specified direction to improve the passband flatness of the distributed amplifier.

6. The distributed amplifier according to claim 3, characterized in that, The parasitic cancellation gain unit has 6 stages.

7. The distributed amplifier according to claim 3, characterized in that, Implemented using 28-nm bulk CMOS technology.

8. The distributed amplifier according to claim 7, characterized in that, The core circuit of the distributed amplifier measures 0.529 mm × 0.071 mm, has a 3-dB bandwidth of up to 108 GHz, a maximum gain of 7.8 dB, and input-output matching of less than -10 dB throughout the entire operating frequency band.

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