Hardware-implemented sequencing method, apparatus, computer device, readable storage medium and program product

Abstract

This application relates to a hardware-implemented sorting method, apparatus, computer device, readable storage medium, and program product. The method includes: acquiring a first data sequence to be sorted, where each data element in the first data sequence contains a key value and its position index within the sequence; concatenating the key value and position index of each data element according to a preset sorting direction to obtain the first data elements to be sorted; and performing hardware parallel sorting on the first data elements using a bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence retains the relative positional relationships in the first data sequence. This allows the primary sorting order to be determined based on the key value, and the relative order of data with the same key value to be determined based on the positional information. While maintaining sorting stability, it inherits the hardware parallel advantages of bitonic merge sort, resulting in fast sorting speed suitable for real-time video decoding requirements.

Description

Technical Field

[0001] This application relates to the field of video encoding and decoding technology, and in particular to a hardware-implemented sorting method, apparatus, computer device, readable storage medium, and program product. Background Technology

[0002] AV1 (AO Media Video 1) is an open-source, royalty-free next-generation video codec format introduced by the Alliance for Open Media. The AV1 standard stipulates an important constraint: if multiple motion vectors have the same weight, it must be ensured that the relative positions of these motion vectors with the same weight remain unchanged after sorting. That is, the motion vector that enters the motion vector list first should have a higher priority to maintain the stability of the sorting.

[0003] The traditional bitonic merge sort algorithm is a divide-and-conquer algorithm, similar to traditional merge sort. It progressively divides a large sequence into smaller sequences, sorts the smaller sequences, and then merges the sorted subsequences to obtain the final sorted sequence. The key characteristic of bitonic merge sort is that the subsequences are sorted in reverse order; that is, the final merge combines two subsequences with different monotonicity.

[0004] However, the traditional bitonic merge sort algorithm has significant shortcomings when applied to the AV1 standard: when multiple data have the same key value (weight), the algorithm cannot guarantee that the relative positions of these data remain unchanged. Summary of the Invention

[0005] Therefore, it is necessary to provide a hardware-implemented sorting method, apparatus, computer device, readable storage medium, and program product that can meet the constraints of the AV1 standard and maintain sorting stability in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a hardware-implemented sorting method, the method comprising:

[0007] Obtain a first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the index of the key value in the sequence;

[0008] According to the preset sorting direction, the key value and position index of each data element are concatenated to obtain the first data element to be sorted;

[0009] The first data element is sorted in parallel using a bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence preserves the relative positional relationship in the first data sequence.

[0010] In one embodiment, the step of concatenating the key value and position index of each data element according to a preset sorting direction to obtain the first data element to be sorted includes:

[0011] When the preset sorting direction is descending, bit concatenation is performed according to the first rule;

[0012] If the preset sorting direction is ascending, the bits are concatenated according to the second rule;

[0013] The first rule includes: bit concatenation according to W = (w << n) | p, and the second rule includes: bit concatenation according to W = (w << n) | (2 n - p) performs bit concatenation, where w represents the key value, p represents the position index, and n is the preset bit width, satisfying 2 n The length of the sequence to be sorted is greater than or equal to the length of the sequence to be sorted, and W represents the first data element.

[0014] In one embodiment, the hardware parallel sorting process of the first data element according to the bitone merge sort network includes:

[0015] The unsorted sequence containing the first data element is recursively divided into several parts of length 2. n The sorting unit is a natural number greater than 2;

[0016] The sorting module is invoked to sort each of the sorting units;

[0017] According to the merging rules of bitonic merge sort, the sorted sequences are merged level by level until the second sorted data sequence is obtained.

[0018] In one embodiment, the sorting module includes a comparison network consisting of multiple comparison exchange stages, the comparison network comprising:

[0019] The first comparison-swapping level is used to perform comparison-swapping operations on data pairs consisting of adjacent elements;

[0020] The second comparison-swapping level is used to perform comparison-swapping operations on data pairs consisting of elements separated by one position.

[0021] The third comparison-exchange level is used to compare and exchange data pairs consisting of elements at adjacent positions.

[0022] The fourth comparison-swapping level is used to perform comparison-swapping operations on data pairs consisting of elements spaced three positions apart.

[0023] The fifth comparison-swapping level is used to perform comparison-swapping operations on data pairs consisting of elements separated by one position.

[0024] The sixth comparison-exchange level is used to perform comparison-exchange processing on data pairs consisting of adjacent elements;

[0025] The comparison and exchange process refers to deciding whether to exchange the sorting positions based on the data size determined after the comparison.

[0026] In one embodiment, each of the comparison switching stages includes four two-input comparators, which are used to compare input data pairs according to preset comparison logic and output data to a designated port according to the comparison result.

[0027] In one embodiment, when the preset sorting direction is descending, the two-input comparators in the first comparison exchange stage are configured from left to right as greater than, less than, greater than, less than comparison logic; in the second comparison exchange stage to the sixth comparison exchange stage, all the two-input comparators are configured as greater than comparison logic.

[0028] In one embodiment, when the preset sorting direction is ascending, the two-input comparators in the first comparison exchange stage are configured from left to right as less than, greater than, less than, and greater than comparison logic; in the second to the sixth comparison exchange stages, all the two-input comparators are configured as less than comparison logic.

[0029] Secondly, this application also provides a hardware-implemented sorting device, the device comprising:

[0030] The acquisition module is used to acquire a first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the position index of the key value in the sequence;

[0031] The splicing module is used to splice the key value and position index of each data element according to a preset sorting direction to obtain the first data element to be sorted.

[0032] The sorting module is used to perform hardware parallel sorting on the first data elements according to the bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence retains the relative positional relationship in the first data sequence.

[0033] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0034] Obtain a first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the index of the key value in the sequence;

[0035] According to the preset sorting direction, the key value and position index of each data element are concatenated to obtain the first data element to be sorted;

[0036] The first data element is sorted in parallel using a bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence preserves the relative positional relationship in the first data sequence.

[0037] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0038] Obtain a first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the index of the key value in the sequence;

[0039] According to the preset sorting direction, the key value and position index of each data element are concatenated to obtain the first data element to be sorted;

[0040] The first data element is sorted in parallel using a bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence preserves the relative positional relationship in the first data sequence.

[0041] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0042] Obtain a first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the index of the key value in the sequence;

[0043] According to the preset sorting direction, the key value and position index of each data element are concatenated to obtain the first data element to be sorted;

[0044] The first data element is sorted in parallel using a bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence preserves the relative positional relationship in the first data sequence.

[0045] The aforementioned hardware-implemented sorting method, apparatus, computer device, computer-readable storage medium, and computer program product acquire a first data sequence to be sorted, where each data element contains a key value and its position index within the sequence. This preserves the original data's positional information, allowing the original data order to be traced during the sorting process. By concatenating the key value and position index of each data element according to a preset sorting direction, the first data elements to be sorted are obtained. This allows the primary sorting order to be determined based on the key value, and the relative order of data with the same key value to be determined based on the positional information, achieving hardware-friendly encoding for sorting stability. Following a bitonemic merge sort network, the first data elements are processed in parallel hardware to obtain a sorted second data sequence, where the sorting order of data elements retains the relative positional relationships in the first data sequence. Thus, while maintaining sorting stability, it inherits the hardware parallel advantages of bitonemic merge sort, offering fast sorting speed suitable for real-time video decoding requirements. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a flowchart illustrating a hardware-implemented sorting method in one embodiment;

[0048] Figure 2 A schematic diagram of the circuit structure of the comparison network in a sorting module provided in one embodiment of this application;

[0049] Figure 3 This is a structural block diagram of a hardware-implemented sorting device in one embodiment;

[0050] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0053] AV1 is an open-source, royalty-free next-generation video codec format developed by the Open Media Consortium. Compared to its predecessor, HEVC, AV1 offers a 20% to 30% improvement in compression efficiency, significantly enhancing video transmission quality and user experience without increasing bandwidth consumption. In AV1 video decoding, to improve motion vector encoding efficiency, AV1 employs a more complex motion vector candidate list construction method compared to traditional standards like HEVC and H.264. This method utilizes motion vector information from numerous spatially adjacent blocks and temporally referenced blocks to construct the candidate list, assigning weights based on the size of the prediction block to which each motion vector belongs. Finally, the candidate motion vectors in the list are sorted according to their weights, with higher-weighted motion vectors appearing earlier in the list and thus receiving higher priority.

[0054] The motion vector list is constructed on a unit-by-unit basis. In the AV1 standard, the minimum size of a prediction unit can be 4x4 pixels. In extreme cases, such as when most prediction units are very small, the motion vector list construction process will be executed frequently, potentially significantly impacting decoding speed. Therefore, a fast sorting circuit is needed to sort candidate motion vectors in the motion vector list according to their weights. Simultaneously, the AV1 standard specifies an important constraint: if multiple motion vectors have the same weight, it must be ensured that their relative positions remain unchanged after sorting; that is, the motion vector that enters the motion vector list first should have a higher priority to maintain sorting stability.

[0055] For example, Table 1 shows the motion vectors and their weights in the motion vector list before sorting, and Table 2 shows the motion vectors and their weights in the list after sorting.

[0056] Table 1

[0057]

[0058] Table 2

[0059]

[0060] As shown in Tables 1 and 2, the motion vectors mv2 and mv4 have the same weight value, and after sorting, the relative position relationship of mv2 before mv4 should still be maintained.

[0061] Traditional bitonic merge sort is a divide-and-conquer algorithm, similar to traditional merge sort. It progressively divides a large sequence into smaller sequences, sorts the smaller sequences, and then merges the sorted subsequences to obtain the final sorted sequence. A key characteristic of bitonic merge sort is that the subsequences are sorted in reverse order; that is, the final merge combines two subsequences with different monotonicities. However, traditional bitonic merge sort has a significant drawback when applied to the AV1 standard: when multiple data points have the same key value (weight), the algorithm cannot guarantee that the relative positions of these data points remain unchanged. For example, when sorting the input sequence "3, 2, 6, 8, 9, 10, 6, 7" from largest to smallest, the relative positions of two data points with the value "6" change before and after sorting. If it's simply a simple numerical sort, this won't affect the result, but in the AV1 standard, movement vectors with the same weight may be different, and the standard requires maintaining the original relative positional relationship. Therefore, if the motion vector list is simply sorted according to its weight using the traditional bitonic merge sort algorithm, it may not conform to the standard and affect the correctness of the decoding.

[0062] To address the problems existing in the above-mentioned technologies, this application aims to provide a hardware-implemented sorting method that ensures that data with the same key value maintains its original relative position after sorting, thus meeting the stringent requirements of the AV1 standard.

[0063] In one exemplary embodiment, such as Figure 1 As shown, a hardware-implemented sorting method is provided. The method in this embodiment may include the following steps S101 to S103. Wherein:

[0064] Step S101: Obtain the first data sequence to be sorted. Each data element in the first data sequence contains a key value and the index of the key value in the sequence.

[0065] The method in this embodiment can be applied to AV1 video decoding. During AV1 decoding, the maximum length of the motion vector list is 8, and the minimum size of the prediction unit is 4x4. For example, the weight value of the motion vector can be represented by the key value, which ranges from 0 to 255 (8 bits), and the position index can be represented by the position of the motion vector in the original list, which ranges from 0 to 7 (3 bits).

[0066] Step S102: According to the preset sorting direction, the key value and position index of each data element are concatenated to obtain the first data element to be sorted.

[0067] In this embodiment, according to the preset sorting direction, the key value and position index of each data element are concatenated, so that the original position information can be encoded into the high bit (key value) and low bit (position) of the data to be sorted.

[0068] Step S103: The first data elements are sorted in parallel using a bitonic merge sort network to obtain the sorted second data sequence.

[0069] The sorting order of data elements in the second data sequence preserves the relative positional relationship in the first data sequence.

[0070] As an optional example, with the preset sorting direction being descending, bit concatenation is performed according to the first rule. The first rule includes: bit concatenation is performed according to W = (w << n) | p; w represents the key value, p represents the position index, n is the preset bit width, and satisfies 2... n The length of the sequence to be sorted is greater than or equal to the length of the sequence to be sorted, and W represents the first data element.

[0071] In this embodiment, (w << n) means shifting the key value left by n bits, occupying the high-order bits; | p means appending the original position index p to the low-order bits. For example, if w = 85 (binary 01010101), p = 3 (binary 0011), and n = 4, then w << 4 = 010101010000; W = 01010101 0000 | 0011 = 01010101 0011.

[0072] As another alternative example, assuming the preset sorting direction is ascending, bit concatenation is performed according to the second rule. The second rule includes: following W = (w << n) | (2 n - p) performs bit concatenation, where w represents the key value, p represents the position index, and n is the preset bit width, satisfying 2 n The length of the sequence to be sorted is greater than or equal to the length of the sequence to be sorted, and W represents the first data element.

[0073] In this embodiment, (w << n) means shifting the key value n positions to the left to occupy the high-order bits; | (2 n - p) means that (2 n -p) is appended to the lower-order bits. For example, when n is 3, (2 n - p) represents the transformation value of the position index; the smaller p is, the larger the value; the larger p is, the smaller the value. For example, if w=10 and p=2, then 2n - p = 8-2=6, w << 3 = 10 × 8 = 80, corresponding to binary 1010000; W = 80 + 6 = 86, corresponding to binary 1010110.

[0074] In the above sorting process, when comparing two W values, the higher 3 bits (key value) are compared first. The key value is smaller, and the W value is smaller, so it ranks first in ascending order. If the key values ​​are the same, the lower 3 bits (2...) are compared next. n -p), the smaller the W value, the higher it ranks in ascending order. Because (2 n -p) is inversely proportional to p, the larger p is (2) n - p) is smaller, therefore, when the key values ​​are the same, (2 n - The smaller the p value, the smaller the W value, that is, the larger the p value, the smaller the W value. Therefore, when sorting in ascending order, the smaller the W value, the earlier the p value (originally at the back) is placed in the first position.

[0075] In the above embodiments, the unsorted sequence containing the first data element can be recursively divided into several segments of length 2. n The sorting unit is defined by n, where n is a natural number greater than 2. The sorting module is called to sort each sorting unit. According to the merging rules of bitonic merge sort, the sorted sequences are merged level by level until the second sorted data sequence is obtained.

[0076] In this embodiment, a data sequence of length 32 is used as an example to illustrate the specific hardware implementation of recursive segmentation and merging. First, the sequence to be sorted with a length of 32 is recursively segmented: the first level is segmented into two subsequences of length 16; the second level is segmented into two subsequences of length 8 each; finally, four sorting units of length 8 are obtained.

[0077] The sorting module includes a comparison network consisting of multiple comparison and exchange levels. The comparison network includes: a first comparison and exchange level for comparing and exchanging data pairs consisting of adjacent elements; a second comparison and exchange level for comparing and exchanging data pairs consisting of elements separated by one position; a third comparison and exchange level for comparing and exchanging data pairs consisting of adjacent elements; a fourth comparison and exchange level for comparing and exchanging data pairs consisting of elements separated by three positions; a fifth comparison and exchange level for comparing and exchanging data pairs consisting of elements separated by one position; and a sixth comparison and exchange level for comparing and exchanging data pairs consisting of adjacent elements. The comparison and exchange process refers to determining whether to exchange the sorting positions based on the size of the data determined after the comparison.

[0078] It should be understood that there is no limit to the number of sorting modules. For example, four sorting modules can work in parallel to output four ordered sequences of length 8 simultaneously. In hardware implementation, four identical sorting modules can be instantiated, or a single module can be time-division multiplexed.

[0079] For example, the merging process includes two levels of merging. In the first level, two adjacent ordered sequences of length 8 are merged. The merging circuit uses a bi-tone merge rule, requiring three levels of comparisons, each containing eight two-input comparators. The result is two ordered sequences of length 16. In the second level, two ordered sequences of length 16 are merged. The merging circuit requires four levels of comparisons, each containing 16 two-input comparators. The result is a final ordered sequence of length 32. In this embodiment, recursive partitioning and step-by-step merging extend the small-scale sorting module to sort sequences of arbitrary lengths. The hardware architecture is well-structured and easily expandable. Latency and throughput can be balanced by increasing the number of pipeline stages or parallelism to meet the needs of different application scenarios.

[0080] For example, taking n as a value of 3, the 8 data points are used as a sorting unit of length 8. The sorting module is directly called, and the sorted key-value sequence is obtained by using the six-level comparison and exchange stages in the sorting module. Since the sorting result retains the original position information, the original motion vectors can be directly mapped back according to the position index, and a sorted list of motion vectors is output, which satisfies the requirement of maintaining the original order when the weights are the same.

[0081] It should be understood that this embodiment retains the encoding method of position information (inverting the value in descending order and keeping the original value in ascending order), ensuring that data with the same key value are arranged in the original order, meeting the strict requirements of the AV1 standard. Furthermore, no additional stability control logic is required; stable sorting can be achieved solely through data preprocessing, resulting in low hardware overhead. In addition, it can inherit the parallel comparison network structure of bitoneic merge sort, offering fast sorting speed, suitability for real-time decoding, and applicability to any 2D algorithm. n Sequence sorting by length is not limited to AV1 application scenarios.

[0082] In the aforementioned hardware-implemented sorting method, a first data sequence to be sorted is obtained. Each data element in the first data sequence contains a key value and its position index within the sequence. This preserves the original data's positional information, allowing the original data order to be traced during the sorting process. By concatenating the key value and position index of each data element according to a preset sorting direction, the first data element to be sorted is obtained. This allows the primary sorting order to be determined based on the key value, and the relative order of data with the same key value to be determined based on the positional information, achieving hardware-friendly encoding for sorting stability. Following a bitonemic merge sort network, the first data element is processed in parallel hardware to obtain a sorted second data sequence. The sorting order of the data elements in the second data sequence retains the relative positional relationships in the first data sequence. Thus, while maintaining sorting stability, it inherits the hardware parallel advantages of bitonemic merge sort, resulting in fast sorting speed suitable for real-time video decoding requirements.

[0083] The following explanation will be based on a specific application of AV1, using an example of sorting 8 data points in descending order.

[0084] Table 3 shows the sequence W0~W7 consisting of 8 data elements to be sorted.

[0085] Table 3

[0086]

[0087] For example, Figure 2 This is a schematic diagram of the circuit structure of the comparison network in a sorting module provided in one embodiment of this application, as shown below. Figure 2 As shown, input 8 data points to be sorted, denoted as w0, w1, w2, w3, w4, w5, w6, w7, each with its original index (N, 2, 0); after six levels of sorting, the 8 data points arranged from largest to smallest will be output to the registers corresponding to w0, w1, w2, w3, w4, w5, w6, w7 respectively.

[0088] See also Figure 2As shown, stage 0 is the first comparison-swapping stage, used to compare and swap data pairs consisting of adjacent elements: (w0,w1), (w2,w3), (w4,w5), (w6,w7). Stage 1 is the second comparison-swapping stage, used to compare and swap data pairs consisting of elements separated by one position: (w0',w2'), (w1',w3'), (w4',w6'), (w5',w7'). Stage 2 is the third comparison-swapping stage, used to compare and swap data pairs consisting of adjacent elements: (w0'',w1''), (w2'',w3''), (w4'',w5''), (w6'',w7''). Stage 3 is the fourth comparison-swapping stage, used to compare and swap data pairs consisting of elements separated by three positions: (w0''',w4'''), (w1''',w5'''), (w2''',w6'''), (w3''',w7'''). Stage 4 is the fifth comparison-swapping stage, used to compare and swap data pairs consisting of elements separated by one position: (w0'''',w2''''), (w1'''',w3''''), (w4'''',w6''''), (w5'''',w7''''). Stage 5 is the sixth comparison and swapping stage, used to perform comparison and swapping on data pairs consisting of adjacent elements: (w0''''',w1'''''), (w2''''',w3'''''), (w4''''',w5'''''), (w6'''',w7'''''). Where w0', w1', w2', w3', w4', w5', w6', w7' represent the sorted data after the first comparison and exchange stage; w0'', w1'', w2'', w3'', w4'', w5'', w6'', w7'' represent the sorted data after the second comparison and exchange stage; w0''', w1''', w2''', w3''', w4''', w5''', w6''', w7''' represent the sorted data after the third comparison and exchange stage; w0'''', w1'''', w2'''', w3'''', w4'''', w5'''', w6''', w7''' represent the sorted data after the fourth comparison and exchange stage; w0'''', w1'''', w2''''' w3''''', w4''''', w5''''', w6''''', w7''''' represent the sorted data after the fifth comparison and exchange level.

[0089] Here, Swap represents a two-input comparator. Each comparison switching stage includes four two-input comparators. The two-input comparators are used to compare the input data pairs according to the preset comparison logic and output the data to the specified port according to the comparison result.

[0090] For example, when the preset sorting direction is descending, the two-input comparators in the first comparison exchange stage are configured from left to right as greater than, less than, greater than, less than comparison logic; in the second to sixth comparison exchange stages, all two-input comparators are configured as greater than comparison logic.

[0091] For example, when the preset sorting direction is ascending, the two-input comparators in the first comparison exchange stage are configured from left to right as less than, greater than, less than, greater than comparison logic; in the second to sixth comparison exchange stages, all two-input comparators are configured as less than comparison logic.

[0092] Combination Figure 2 As shown, stage0, stage1, and stage2 are two monotonic sequences, where W0'''~W3''' is a monotonically decreasing sequence and W4'''~W7''' is a monotonically increasing sequence. Figure 2 Stages 3, 4, and 5 are the comparison and merging processes. For sorting eight numbers, this process requires a total of three comparison circuits, with each stage requiring four two-input comparators. Observing the final sorting result, we can see that although w3 and w4 have the same value, the motion vector corresponding to w3 is still located before the motion vector corresponding to w4 after sorting.

[0093] In this embodiment, while retaining the performance of the traditional bitonic merge sort algorithm, position information is superimposed on the input data for sorting, so that the original relative positional relationship of each data item can be preserved after sorting.

[0094] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0095] Based on the same inventive concept, this application also provides a hardware-implemented sorting apparatus for implementing the sorting method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations of one or more hardware-implemented sorting apparatus embodiments provided below can be found in the limitations of the hardware-implemented sorting method described above, and will not be repeated here.

[0096] In one exemplary embodiment, such as Figure 3 As shown, a hardware-implemented sorting device is provided, comprising: an acquisition module 301, a splicing module 302, and a sorting module 303, wherein:

[0097] The acquisition module 301 is used to acquire the first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the index of the key value in the sequence;

[0098] The splicing module 302 is used to splice the key value and position index of each data element according to the preset sorting direction to obtain the first data element to be sorted;

[0099] The sorting module 303 is used to perform hardware parallel sorting on the first data elements according to the bitonic merge sort network to obtain the sorted second data sequence, wherein the sorting order of the data elements in the second data sequence retains the relative positional relationship in the first data sequence.

[0100] For example, the splicing module 302 is specifically used to: splice bits according to the first rule when the preset sorting direction is descending;

[0101] If the preset sorting direction is ascending, the bits are concatenated according to the second rule;

[0102] The first rule includes: bit concatenation according to W = (w << n) | p, and the second rule includes: bit concatenation according to W = (w << n) | (2 n - p) performs bit concatenation, where w represents the key value, p represents the position index, and n is the preset bit width, satisfying 2 n The length of the sequence to be sorted is greater than or equal to the length of the sequence to be sorted, and W represents the first data element.

[0103] For example, sorting module 303 is specifically used to: recursively divide the unsorted sequence containing the first data element into several segments of length 2. n The sorting unit is defined by n, where n is a natural number greater than 2. The sorting module is called to sort each sorting unit. According to the merging rules of bitonic merge sort, the sorted sequences are merged level by level until the second sorted data sequence is obtained.

[0104] For example, the sorting module includes a comparison network consisting of multiple comparison exchange levels. The comparison network includes: a first comparison exchange level for comparing and exchanging data pairs consisting of adjacent elements; a second comparison exchange level for comparing and exchanging data pairs consisting of elements separated by one position; a third comparison exchange level for comparing and exchanging data pairs consisting of adjacent elements; a fourth comparison exchange level for comparing and exchanging data pairs consisting of elements separated by three positions; a fifth comparison exchange level for comparing and exchanging data pairs consisting of elements separated by one position; and a sixth comparison exchange level for comparing and exchanging data pairs consisting of adjacent elements. The comparison exchange process refers to determining whether to exchange the sorting positions based on the data size determined after the comparison.

[0105] For example, each comparison switching stage includes four two-input comparators, which are used to compare input data pairs according to preset comparison logic and output data to a specified port according to the comparison result.

[0106] For example, when the preset sorting direction is descending, the two-input comparators in the first comparison exchange stage are configured from left to right as greater than, less than, greater than, less than comparison logic; in the second to sixth comparison exchange stages, all two-input comparators are configured as greater than comparison logic.

[0107] For example, when the preset sorting direction is ascending, the two-input comparators in the first comparison exchange stage are configured from left to right as less than, greater than, less than, greater than comparison logic; in the second to sixth comparison exchange stages, all two-input comparators are configured as less than comparison logic.

[0108] Each module in the above-described hardware-implemented sorting device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0109] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a hardware-implemented sequencing method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0110] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0111] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0112] Obtain a first data sequence to be sorted. Each data element in the first data sequence contains a key value and the position index of the key value in the sequence. According to the preset sorting direction, the key value and position index of each data element are concatenated to obtain the first data element to be sorted. The first data element is then sorted in parallel using a bitonic merge sorting network to obtain a sorted second data sequence. The sorting order of the data elements in the second data sequence retains the relative positional relationship in the first data sequence.

[0113] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0114] If the preset sorting direction is descending, the bits are concatenated according to the first rule;

[0115] If the preset sorting direction is ascending, the bits are concatenated according to the second rule;

[0116] The first rule includes: bit concatenation according to W = (w << n) | p, and the second rule includes: bit concatenation according to W = (w << n) | (2 n - p) performs bit concatenation, where w represents the key value, p represents the position index, and n is the preset bit width, satisfying 2 n The length of the sequence to be sorted is greater than or equal to the length of the sequence to be sorted, and W represents the first data element.

[0117] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0118] The unsorted sequence containing the first data element is recursively divided into several parts of length 2. n The sorting unit is defined by n, where n is a natural number greater than 2. The sorting module is called to sort each sorting unit. According to the merging rules of bitonic merge sort, the sorted sequences are merged level by level until the second sorted data sequence is obtained.

[0119] In one embodiment, the sorting module includes a comparison network consisting of multiple comparison exchange levels. The comparison network includes: a first comparison exchange level for comparing and exchanging data pairs consisting of adjacent elements; a second comparison exchange level for comparing and exchanging data pairs consisting of elements separated by one position; a third comparison exchange level for comparing and exchanging data pairs consisting of adjacent elements; a fourth comparison exchange level for comparing and exchanging data pairs consisting of elements separated by three positions; a fifth comparison exchange level for comparing and exchanging data pairs consisting of elements separated by one position; and a sixth comparison exchange level for comparing and exchanging data pairs consisting of adjacent elements. The comparison exchange process refers to determining whether to exchange the sorting positions based on the data size determined after comparison.

[0120] In one embodiment, each comparison switching stage includes four two-input comparators, which are used to compare input data pairs according to preset comparison logic and output data to a specified port according to the comparison result.

[0121] In one embodiment, when the preset sorting direction is descending, the two-input comparators in the first comparison exchange stage are configured from left to right as greater than, less than, greater than, less than comparison logic; in the second to sixth comparison exchange stages, all two-input comparators are configured as greater than comparison logic.

[0122] In one embodiment, when the preset sorting direction is ascending, the two-input comparators in the first comparison exchange stage are configured from left to right as less than, greater than, less than, and greater than comparison logic; in the second to sixth comparison exchange stages, all two-input comparators are configured as less than comparison logic.

[0123] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method steps of the various embodiments described above.

[0124] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the method steps of the various embodiments described above.

[0125] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0127] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A hardware-implemented sorting method, characterized in that, The method includes: Obtain a first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the index of the key value in the sequence; According to the preset sorting direction, the key value and position index of each data element are concatenated to obtain the first data element to be sorted; The first data element is sorted in parallel using a bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence preserves the relative positional relationship in the first data sequence.

2. The method according to claim 1, characterized in that, The step of concatenating the key value and position index of each data element according to a preset sorting direction to obtain the first data element to be sorted includes: When the preset sorting direction is descending, bit concatenation is performed according to the first rule; If the preset sorting direction is ascending, the bits are concatenated according to the second rule; The first rule includes: bit concatenation according to W = (w << n) | p, and the second rule includes: bit concatenation according to W = (w << n) | (2 n - p) performs bit concatenation, where w represents the key value, p represents the position index, and n is the preset bit width, satisfying 2 n The length of the sequence to be sorted is greater than or equal to the length of the sequence to be sorted, and W represents the first data element.

3. The method according to claim 1, characterized in that, The hardware parallel sorting process for the first data element according to the bitonic merge sort network includes: The unsorted sequence containing the first data element is recursively divided into several parts of length 2. n The sorting unit is a natural number greater than 2; The sorting module is invoked to sort each of the sorting units; According to the merging rules of bitonic merge sort, the sorted sequences are merged level by level until the second sorted data sequence is obtained.

4. The method according to claim 3, characterized in that, The sorting module includes a comparison network composed of multiple comparison exchange stages, the comparison network including: The first comparison-exchange level is used to perform comparison-exchange processing on data pairs consisting of adjacent elements; The second comparison-swapping level is used to perform comparison-swapping operations on data pairs consisting of elements separated by one position. The third comparison-exchange level is used to compare and exchange data pairs consisting of elements at adjacent positions. The fourth comparison-swapping level is used to perform comparison-swapping operations on data pairs consisting of elements spaced three positions apart. The fifth comparison-swapping level is used to perform comparison-swapping operations on data pairs consisting of elements separated by one position. The sixth comparison-exchange level is used to perform comparison-exchange processing on data pairs consisting of adjacent elements; The comparison and exchange process refers to deciding whether to exchange the sorting positions based on the data size determined after the comparison.

5. The method according to claim 4, characterized in that, Each of the comparison switching stages includes four two-input comparators, which are used to compare input data pairs according to preset comparison logic and output data to a designated port according to the comparison result.

6. The method according to claim 5, characterized in that, When the preset sorting direction is descending, the two-input comparators in the first comparison exchange stage are configured from left to right as greater than, less than, greater than, less than comparison logic; in the second to the sixth comparison exchange stages, all the two-input comparators are configured as greater than comparison logic.

7. The method according to claim 5, characterized in that, When the preset sorting direction is ascending, the two-input comparators in the first comparison exchange stage are configured from left to right as less than, greater than, less than, and greater than comparison logic; in the second to the sixth comparison exchange stages, all the two-input comparators are configured as less than comparison logic.

8. A hardware-implemented sorting device, characterized in that, The device includes: The acquisition module is used to acquire a first data sequence to be sorted, wherein each data element in the first data sequence contains a key value and the position index of the key value in the sequence; The splicing module is used to splice the key value and position index of each data element according to a preset sorting direction to obtain the first data element to be sorted. The sorting module is used to perform hardware parallel sorting on the first data elements according to the bitonic merge sort network to obtain a sorted second data sequence, wherein the sorting order of the data elements in the second data sequence retains the relative positional relationship in the first data sequence.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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