Pixel binning processing method, pixel binning circuit and related device

Abstract

This disclosure provides a pixel merging processing method, pixel merging circuit, and related equipment, relating to the field of image acquisition technology. The method includes: providing a pixel circuit that groups a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit as a pixel group; firstly acquiring the first pixel signal of the first pixel unit and the third pixel signal of the third pixel unit; then acquiring the second pixel signal of the second pixel unit and the fourth pixel signal of the fourth pixel unit; and then generating a merged signal for the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal obtained after analog-to-digital conversion of the first pixel signal, the second pixel signal, the third pixel signal, and the fourth pixel signal. This disclosure enables pixel merging over a larger pixel range without introducing new analog circuitry.

Description

Technical Field

[0001] This disclosure relates to the field of image acquisition technology, and in particular to a pixel merging processing method, pixel merging circuit and related equipment. Background Technology

[0002] With the continuous development of image sensor technology, pixel binning technology has become an important means to improve the performance of image sensors. Traditional pixel binning methods usually require the introduction of new analog circuits to process the analog signals of multiple pixels, which not only increases the complexity of the circuit, but may also introduce additional noise.

[0003] Therefore, how to achieve pixel merging without adding analog circuitry is a technical problem that urgently needs to be solved in this field.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a pixel merging processing method, a pixel merging circuit, and related equipment, which at least to some extent overcomes the technical problem that pixel merging processing schemes in related technologies require the addition of analog circuits to process pixel signals, resulting in complex circuits and the potential introduction of additional noise.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.

[0007] According to one aspect of this disclosure, a pixel merging processing method is provided, the method comprising: providing a pixel circuit, the pixel circuit including at least one pixel group, the pixel group including at least a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit; acquiring a first pixel signal of the first pixel unit and a third pixel signal of the third pixel unit, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in a first column of a target image; acquiring a second pixel signal of the second pixel unit and a fourth pixel signal of the fourth pixel unit, wherein the second pixel unit and the fourth pixel unit are two adjacent pixel units in a second column of the target image, and the first pixel unit and the second pixel unit are adjacent in a first row, the third pixel unit and the fourth pixel unit are adjacent in a second column of the target image, and the first pixel unit and the second pixel unit are adjacent in a first row, the third pixel unit and the fourth pixel unit are adjacent in a second column of the target image, the first pixel unit and the second pixel unit are adjacent in a first row, the third pixel unit and the fourth pixel unit are adjacent in a second column of the target image, the first pixel unit and the second pixel unit are adjacent in a first row, the third pixel unit and the fourth pixel unit are adjacent in a second column of the target image, the first pixel unit and the second pixel unit are adjacent in a first column of the target image ... second column of the target image, the first pixel unit and the second pixel unit are adjacent in a second column of the target image, the third pixel unit and the fourth pixel unit are adjacent in a third column of the target image, the first pixel unit and the second pixel unit are adjacent in a second column of the target image, the first pixel unit and the second pixel unit are adjacent The second row and the first column are adjacent to each other, and the second row and the first row are adjacent to each other; read the first digital signal, the second digital signal, the third digital signal and the fourth digital signal, wherein the first digital signal is a digital signal obtained by analog-to-digital conversion of the first pixel signal, the second digital signal is a digital signal obtained by analog-to-digital conversion of the second pixel signal, the third digital signal is a digital signal obtained by analog-to-digital conversion of the third pixel signal, and the fourth digital signal is a digital signal obtained by analog-to-digital conversion of the fourth pixel signal; generate a merged signal of the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal and the fourth digital signal.

[0008] In some embodiments, generating a combined signal of the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal includes: calculating the signal mean of the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal; and determining the signal mean as the signal value of the combined signal.

[0009] According to another aspect of this disclosure, a pixel merging circuit is also provided, comprising: a pixel circuit, a signal acquisition module, an analog-to-digital conversion module, and a data processing module; wherein, the pixel circuit comprises: at least one pixel group, the pixel group comprising at least a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit; the signal acquisition module is respectively connected to the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit on the pixel circuit, and is used to acquire the first pixel signal of the first pixel unit, the second pixel signal of the second pixel unit, the third pixel signal of the third pixel unit, and the fourth pixel signal of the fourth pixel unit, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in a first column of the target image, and the second pixel unit and the fourth pixel unit are two adjacent pixel units in a second column of the target image. The first pixel unit and the second pixel unit are adjacent in the first row, and the third pixel unit and the fourth pixel unit are adjacent in the second row. The second column and the first column are adjacent to each other, and the second row and the first row are adjacent to each other. The analog-to-digital conversion module is connected to the signal acquisition module and is used to convert the first pixel signal, the second pixel signal, the third pixel signal and the fourth pixel signal into corresponding first digital signal, second digital signal, third digital signal and fourth digital signal. The data processing module is connected to the analog-to-digital conversion module and is used to generate a combined signal of the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal and the fourth digital signal.

[0010] In some embodiments, the signal acquisition module includes: a first pixel signal acquisition circuit for acquiring the first pixel signal, a second pixel signal acquisition circuit for acquiring the second pixel signal, a third pixel signal acquisition circuit for acquiring the third pixel signal, and a fourth pixel signal acquisition circuit for acquiring the fourth pixel signal; the analog-to-digital conversion module includes: a first analog-to-digital conversion circuit for converting the first pixel signal into a first digital signal, a second analog-to-digital conversion circuit for converting the third pixel signal into a third digital signal, a third analog-to-digital conversion circuit for converting the second pixel signal into a second digital signal, and a fourth analog-to-digital conversion circuit for converting the fourth pixel signal into a fourth digital signal; wherein the first analog-to-digital conversion circuit is connected to the first pixel signal acquisition circuit, the second analog-to-digital conversion circuit is connected to the third pixel signal acquisition circuit, the third analog-to-digital conversion circuit is connected to the second pixel signal acquisition circuit, and the fourth analog-to-digital conversion circuit is connected to the fourth pixel signal acquisition circuit.

[0011] According to another aspect of this disclosure, an image sensor is also provided, the image sensor including: the pixel merging circuit of any of the above embodiments.

[0012] According to another aspect of this disclosure, an image acquisition device is also provided, which includes the image sensor described above.

[0013] According to another aspect of this disclosure, a pixel merging processing apparatus is also provided. The apparatus is used to merge pixel signals of at least one pixel unit on a pixel circuit. The pixel circuit includes: at least one pixel group, the pixel group including at least a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit. The apparatus includes: a first signal acquisition module for acquiring a first pixel signal of the first pixel unit and a third pixel signal of the third pixel unit, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in a first column of a target image; a second signal acquisition module for acquiring a second pixel signal of the second pixel unit and a fourth pixel signal of the fourth pixel unit, wherein the second pixel unit and the fourth pixel unit are two adjacent pixel units in a second column of the target image, and the first pixel unit and the second pixel unit are adjacent in a first row. The three-pixel unit and the fourth-pixel unit are adjacent in the second row, the second column and the first column are adjacent columns, and the second row and the first row are adjacent rows; the digital signal reading module is used to read the first digital signal, the second digital signal, the third digital signal and the fourth digital signal, wherein the first digital signal is a digital signal obtained by analog-to-digital conversion of the first pixel signal, the second digital signal is a digital signal obtained by analog-to-digital conversion of the second pixel signal, the third digital signal is a digital signal obtained by analog-to-digital conversion of the third pixel signal, and the fourth digital signal is a digital signal obtained by analog-to-digital conversion of the fourth pixel signal; the pixel merging module is used to generate a merged signal of the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit according to the first digital signal, the second digital signal, the third digital signal and the fourth digital signal.

[0014] According to another aspect of this disclosure, an electronic device is also provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the pixel merging processing method described in any of the preceding claims by executing the executable instructions.

[0015] According to another aspect of this disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the pixel merging processing method described in any one of the preceding claims.

[0016] According to another aspect of this disclosure, a computer program product is also provided, comprising: a computer program or instructions that, when executed by a processor, implement the pixel merging processing method described in any one of the preceding claims.

[0017] The pixel merging processing method, pixel merging circuit, and related equipment provided in this disclosure embodiment provide a pixel circuit including at least one pixel group, each pixel group including at least a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit. When performing pixel merging, the first pixel signal of the first pixel unit and the third pixel signal of the third pixel unit are first acquired, then the second pixel signal of the second pixel unit and the fourth pixel signal of the fourth pixel unit are acquired, and then a merged signal of the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit is generated based on the first digital signal obtained by analog-to-digital conversion of the first pixel signal, the second digital signal obtained by analog-to-digital conversion of the second pixel signal, the third digital signal obtained by analog-to-digital conversion of the third pixel signal, and the fourth digital signal obtained by analog-to-digital conversion of the fourth pixel signal.

[0018] The embodiments disclosed herein can achieve the merging of multiple pixels in a larger pixel area by means of an analog circuit for pixel merging in a small pixel area without introducing new analog circuits.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 A circuit diagram of a 2×2 pixel unit is shown in an embodiment of this disclosure;

[0022] Figure 2 This diagram illustrates an image acquisition process in a conventional mode within the relevant technology.

[0023] Figure 3 This diagram illustrates another conventional mode of image acquisition in related technologies.

[0024] Figure 4 This diagram illustrates an image acquisition process in a 2×2 Binning mode within the relevant technology.

[0025] Figure 5 This diagram illustrates a pixel merging circuit in a 4×4 Binning mode according to an embodiment of the present disclosure.

[0026] Figure 6 This diagram illustrates a 4×4 Binning mode image acquisition process according to an embodiment of the present disclosure.

[0027] Figure 7 This diagram illustrates a pixel merging circuit according to an embodiment of the present disclosure.

[0028] Figure 8 This diagram illustrates an image sensor according to an embodiment of the present disclosure;

[0029] Figure 9 This diagram illustrates an image acquisition device according to an embodiment of the present disclosure.

[0030] Figure 10 This diagram illustrates a pixel merging processing method according to an embodiment of the present disclosure.

[0031] Figure 11 This diagram illustrates a pixel merging processing apparatus according to an embodiment of the present disclosure;

[0032] Figure 12 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0033] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0034] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0035] To facilitate understanding, before introducing the embodiments of this disclosure, the following explanations are provided for several terms involved in the embodiments of this disclosure:

[0036] Analog circuits: Circuits that process analog signals (such as optical signals).

[0037] Digital circuits: Circuits that process digital signals (such as binary numbers).

[0038] Binning: In image sensors, it refers to the process of merging multiple pixels into a larger pixel. Pixel merging can improve light sensitivity and reduce data volume.

[0039] The specific implementation methods of the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0040] Pixel binning is a technique commonly used in image sensor processing that improves the signal-to-noise ratio (SNR) or reduces the amount of data in an image by combining adjacent pixels together.

[0041] A pixel is the smallest photosensitive unit on an image sensor, capable of sensing light intensity and converting it into an electrical signal. Pixel merging adds the electrical signals of multiple pixels together to form a single signal.

[0042] Pixel merging has the following three types:

[0043] ① Horizontal Binning: Merges adjacent pixels in the same row;

[0044] ② Vertical Binning: Merges adjacent pixels in the same column;

[0045] ③ Full Binning: Performs both horizontal and vertical merging simultaneously.

[0046] The pixel merging process includes the following steps:

[0047] ① Select the merging region: Determine the size of the pixel region to be merged. Common methods include 2×2 Binning (merging 2×2 pixel regions into a larger pixel), 3×3 Binning (merging 3×3 pixel regions into a larger pixel), 4×4 Binning (merging 4×4 pixel regions into a larger pixel), and 5×5 Binning (merging 5×5 pixel regions into a larger pixel). Each binning technique has its specific application scenarios and advantages. The choice of binning method depends on factors such as the required image quality, sensitivity, data rate, and processing power. Generally, a larger binning size results in lower image resolution but higher sensitivity and signal-to-noise ratio.

[0048] ② Signal accumulation: In the analog domain, the electrical signals of all pixels in the selected pixel area are added together to obtain the merged signal.

[0049] ③ Signal transmission: The merged signal is transmitted to an analog-to-digital converter (ADC). Pixel merging can reduce the number of ADCs required.

[0050] ④ Analog-to-digital conversion: After passing through the ADC, the merged analog signal is converted into a digital signal, which is used to characterize the average light intensity of all pixels in the merged area.

[0051] ⑤ Data Output: The digital signal processor (DSP) or image processor receives the digital signal from the merged area and outputs it as the new pixel value. Taking 2×2 Binning as an example, if the resolution of the original image sensor is 2M×2N, after 2×2 Binning, the resolution of the output image will become M×N.

[0052] It should be noted that although pixel binning reduces resolution and may cause images to appear blurry, it achieves the following technical effects: ① Improved signal-to-noise ratio: By merging multiple pixels, more photons can be collected, thereby reducing the impact of random noise; ② Increased frame rate: Due to the reduced output data volume, the image reading speed can be accelerated, increasing the frame rate; ③ Reduced data volume: The amount of data in the merged image is reduced, reducing the resource consumption for subsequent image processing and image storage.

[0053] Pixel binning is widely used in low-light conditions or when high frame rate is more important than high resolution. Examples include surveillance cameras, motion capture, and certain scientific imaging applications.

[0054] 2×2 Binning is a common type of binding in image sensors, which merges 2×2 pixel areas into a single larger pixel. Here are the simplified steps for 2×2 Binning:

[0055] ① Select a 2×2 pixel area.

[0056] ② Add the analog signals of the four pixels in the selected pixel area to obtain the merged signal.

[0057] ③ The merged signal is converted into a corresponding digital signal through an ADC.

[0058] ④ Output digital signals as the merged pixel values.

[0059] Figure 1 This diagram illustrates a circuit diagram of a 2×2 pixel unit according to an embodiment of the present disclosure, as shown below. Figure 1As shown, icons 101a, 101b, 101c, and 101d represent four photodiodes, and PIX_TX1, PIX_TX2, PIX_TX3, and PIX_TX4 represent the switches of these four photodiodes. Adjacent rows share a row selector, and adjacent columns share a column output (PIXOUT). Assuming the image sensor has 2N pixels per row and a total of 2M rows, the 2×2 pixel units on this image sensor constitute M rows and N columns, meaning there are N column outputs (PIXOUT). Each column is connected to an ADC (Analog-to-Digital Converter) for analog-to-digital conversion, requiring a total of 2N ADCs.

[0060] Figure 2 The process of acquiring a line of images in normal mode is shown, which includes: first, buffering N odd-numbered pixels into the lower ADC; then buffering N even-numbered pixels into the upper ADC; then, performing analog-to-digital conversion on both the upper and lower ADCs simultaneously; and then reading the converted data from each column in sequence.

[0061] Similarly, the process of acquiring the next row of images is as follows: Figure 3 As shown, N odd-numbered pixels are buffered in the lower ADC; N even-numbered pixels are buffered in the upper ADC; the upper and lower ADCs perform analog-to-digital conversion simultaneously; and the converted data is read from each column in sequence.

[0062] Figure 4 This illustrates an image acquisition process in a 2×2 Binning mode from related technologies, such as... Figure 5 As shown, in 2×2 Binning mode, pixels 1, 2, 3, and 4 are connected together by a switch, which is equivalent to a single pixel. The acquisition process is as follows: first, N 2×2 Binning pixels are buffered in the ADC below; then, the ADC below performs analog-to-digital conversion; and finally, the converted data is read from each column in sequence.

[0063] In this embodiment, the 4×4 Binning function is achieved by modifying the digital circuitry without adding new analog circuitry, based on the 2×2 Binning mode. The implementation principle is as follows: the analog section operates in 2×2 Binning mode, simultaneously acquiring two signals each time and transmitting them to the upper and lower ADCs. The upper and lower ADCs operate and acquire signals simultaneously. During column readout, two data points are output from each of the two addresses, for a total of four data points. The average of these four data points yields the 4×4 Binning pixel.

[0064] Figure 5 This illustrates a 4×4 Binning mode pixel merging circuit, such as... Figure 5 As shown in the figure, the left part indicated by icon 500 is the analog part that is no different from that of a conventional sensor. In this embodiment of the present disclosure, an adder and a one-dimensional digital filter are added to the right side to achieve digital merging without additional row buffering.

[0065] The 4×4 Binning mode image acquisition process is as follows: Figure 6 As shown, the specific steps include: first, caching the N 2×2 Binning pixels of the first two rows to the lower ADC; then caching the N 2×2 Binning pixels of the adjacent two rows to the upper ADC; the upper and lower ADCs simultaneously perform analog-to-digital conversion to produce 2N data points; and averaging the two ADCs for every two adjacent data points, i.e., every four data points, to achieve 4×4 Binning.

[0066] It should be noted that the above-mentioned 2×2 Binning mode pixel merging circuit to achieve 4×4 Binning is only an example. In specific implementations, the 4×4 Binning mode pixel merging circuit can also be used to achieve 16×16 Binning; or the 3×3 Binning mode pixel merging circuit can be used to achieve 9×9 Binning.

[0067] Based on the above-described inventive concept, this disclosure provides a pixel merging circuit, such as... Figure 7 As shown, the pixel merging circuit 70 includes: a pixel circuit 700, a signal acquisition module 701, an analog-to-digital conversion module 702, and a data processing module 703.

[0068] The pixel circuit 700 includes: at least one pixel group, the pixel group including at least a first pixel unit 700a, a second pixel unit 700b, a third pixel unit 700c, and a fourth pixel unit 700c; and a signal acquisition module 701, respectively connected to the first pixel unit 700a, the second pixel unit 700b, the third pixel unit 700c, and the fourth pixel unit 700c on the pixel circuit, for acquiring the first pixel signal of the first pixel unit 700a, the second pixel signal of the second pixel unit 700b, the third pixel signal of the third pixel unit 700c, and the fourth pixel signal of the fourth pixel unit 700c, wherein the first pixel unit 700a and the third pixel unit 700c are two adjacent pixel units in the first column of the target image, and the second pixel unit 700b and the fourth pixel unit 700c are two adjacent pixel units in the second column of the target image. The first pixel unit 700a and the second pixel unit 700b are adjacent in the first row, and the third pixel unit 700c and the fourth pixel unit 700c are adjacent in the second row. The second column and the first column are adjacent columns, and the second row and the first row are adjacent rows. The analog-to-digital conversion module 702, connected to the signal acquisition module 701, is used to convert the first pixel signal, the second pixel signal, the third pixel signal and the fourth pixel signal into corresponding first digital signal, second digital signal, third digital signal and fourth digital signal. The data processing module 703, connected to the analog-to-digital conversion module 702, is used to generate a combined signal of the first pixel unit 700a, the second pixel unit 700b, the third pixel unit 700c and the fourth pixel unit 700c based on the first digital signal, the second digital signal, the third digital signal and the fourth digital signal.

[0069] Taking pixel merging in 4×4 Binning mode as an example, the first pixel unit 700a, the second pixel unit 700b, the third pixel unit 700c, and the fourth pixel unit 700c are all 2×2 pixel areas; the first pixel signal is the merged signal of the four pixels in the first pixel unit 700a; the second pixel signal is the merged signal of the four pixels in the second pixel unit 700b; the third pixel signal is the merged signal of the four pixels in the third pixel unit 700c; and the fourth pixel signal is the merged signal of the four pixels in the fourth pixel unit 700c.

[0070] In some embodiments, the signal acquisition module 701 may specifically include: a first pixel signal acquisition circuit 701a for acquiring a first pixel signal, a second pixel signal acquisition circuit 701b for acquiring a second pixel signal, a third pixel signal acquisition circuit 701c for acquiring a third pixel signal, and a fourth pixel signal acquisition circuit 701d for acquiring a fourth pixel signal; the analog-to-digital conversion module 702 may specifically include: a first analog-to-digital conversion circuit 702a for converting the first pixel signal into a first digital signal, and a second analog-to-digital conversion circuit 702c for converting the third pixel signal into a third digital signal. The circuit comprises a second analog-to-digital converter (ADC) 702b, a third ADC 702c for converting a second pixel signal into a second digital signal, and a fourth ADC 702d for converting a fourth pixel signal into a fourth digital signal; wherein, the first ADC 702a is connected to the first pixel signal acquisition circuit 701a, the second ADC 702b is connected to the third pixel signal acquisition circuit 701c, the third ADC 702c is connected to the second pixel signal acquisition circuit 701b, and the fourth ADC 702d is connected to the fourth pixel signal acquisition circuit 701d.

[0071] It should be noted that since the first pixel signal acquisition circuit 701a and the third pixel signal acquisition circuit 701c are located in the first column, the signals acquired by the first pixel signal acquisition circuit 701a and the third pixel signal acquisition circuit 701c are stored in the two analog-to-digital converter circuits in the first column, respectively. The first analog-to-digital converter circuit 702a is the ADC above the first column (used for ADC); the first analog-to-digital converter circuit 702b is the ADC below the first column. Similarly, the signals acquired by the second pixel signal acquisition circuit 701b and the fourth pixel signal acquisition circuit 701d are stored in the two analog-to-digital converter circuits in the second column, respectively. The third analog-to-digital converter circuit 702c is the ADC above the second column; the fourth analog-to-digital converter circuit 702d is the ADC below the second column.

[0072] Based on the same inventive concept, this disclosure also provides an image sensor, such as... Figure 8 As shown, the image sensor 80 includes the pixel merging circuit 70 in any of the above embodiments.

[0073] In one embodiment, the image sensor 80 in this disclosure may be, but is not limited to, a CMOS (Complementary Metal-Oxide-Semiconductor Image Sensor). CMOS image sensors are widely used in digital cameras, mobile phones, surveillance equipment, and other electronic devices that require image capture.

[0074] It's important to note that most image sensors acquire images line by line. This line-by-line acquisition method allows the image sensor to operate in a pipeline manner, improving acquisition efficiency. While acquiring one line of data, the next line can begin integration, allowing the entire image to be acquired in a shorter time. This is particularly important for video applications because it enables higher frame rates.

[0075] For CMOS image sensors, during exposure, each pixel on the sensor accumulates light and generates a charge. After exposure, the sensor selects pixels row by row, typically starting from the top and working downwards. The charge in the selected pixel row is sequentially converted into a voltage signal and processed by analog signal processing circuitry. The analog signal is then converted into a digital signal by an analog-to-digital converter (ADC). The converted digital signal is stored in a buffer or directly transmitted to the image processing unit. This process is repeated for each row until all rows of the entire image have been acquired.

[0076] In some cases, different readout modes may be used to improve readout speed or achieve specific functions (such as pixel merging), for example, skipping certain rows or columns, or reading data from multiple rows or columns simultaneously. However, the basic acquisition process remains row-by-row.

[0077] Based on the same inventive concept, this disclosure also provides an image acquisition device, such as... Figure 9 As shown, the image acquisition device 90 includes the image sensor 80 in any of the above embodiments. The image acquisition device 90 can be any device capable of acquiring images, including but not limited to various cameras, video cameras, etc.

[0078] Based on the same inventive concept, this disclosure also provides a pixel merging processing method, which can be executed by any electronic device with computing power.

[0079] Figure 10 This diagram illustrates a pixel merging processing method according to an embodiment of the present disclosure, such as... Figure 10 As shown, the method includes the following steps:

[0080] S100, a pixel circuit is provided, the pixel circuit includes at least one pixel group, the pixel group includes at least a first pixel unit, a second pixel unit, a third pixel unit and a fourth pixel unit;

[0081] S102, acquire the first pixel signal of the first pixel unit and the third pixel signal of the third pixel unit, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in the first column of the target image;

[0082] S104, acquire the second pixel signal of the second pixel unit and the fourth pixel signal of the fourth pixel unit, wherein the second pixel unit and the fourth pixel unit are two adjacent pixel units in the second column of the target image, and the first pixel unit and the second pixel unit are adjacent in the first row, the third pixel unit and the fourth pixel unit are adjacent in the second row, the second column and the first column are two adjacent columns, and the second row and the first row are two adjacent rows;

[0083] S106, Read the first digital signal, the second digital signal, the third digital signal and the fourth digital signal, wherein the first digital signal is a digital signal obtained by performing analog-to-digital conversion on the first pixel signal, the second digital signal is a digital signal obtained by performing analog-to-digital conversion on the second pixel signal, the third digital signal is a digital signal obtained by performing analog-to-digital conversion on the third pixel signal, and the fourth digital signal is a digital signal obtained by performing analog-to-digital conversion on the fourth pixel signal;

[0084] S108, generate a merged signal for the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

[0085] It should be noted that the pixel circuit in the embodiments of this disclosure can be any circuit containing multiple pixel units. The pixel circuit includes at least one pixel group, and each pixel group includes: a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit. The first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit in the embodiments of this disclosure can be a unit containing one or more pixels. When the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are units containing multiple pixels, the number of pixels contained in the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit can be the same or different. In one embodiment, when the pixel merging method provided in the embodiments of this disclosure implements 4×4 Binning with a 2×2 Binning pixel merging circuit, the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are all 2×2 pixel areas. In an image sensor, since each column has two analog-to-digital converters (ADCs), the signal acquired by S102 can be stored in one ADC of the corresponding column (such as the ADC below), and the signal acquired by S104 can be stored in the other ADC of the corresponding column (such as the ADC above).

[0086] In some embodiments, the above-described S108 can be implemented by the following steps: calculating the signal average of the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal; and determining the signal average as the signal value of the combined signal.

[0087] It should be noted that there are multiple ways to calculate the merging of digital signals. The above calculation of the signal mean is only an example. In specific implementation, other calculation methods can be used to obtain the signal value of the merged signal (e.g., summation or weighted average).

[0088] The pixel merging processing method provided in this embodiment of the present disclosure enables the merging of multiple pixels in a larger pixel area without introducing new analog circuits, by using an analog circuit for pixel merging in a small pixel area.

[0089] Based on the same inventive concept, this disclosure also provides a pixel merging processing apparatus, as described in the following embodiments. Since the principle by which this apparatus solves the problem is similar to that of the method embodiments described above, the implementation of this apparatus embodiment can refer to the implementation of the method embodiments described above, and repeated details will not be repeated.

[0090] Figure 11 This diagram illustrates a pixel merging processing apparatus according to an embodiment of the present disclosure, such as... Figure 11 As shown, the device includes: a first signal acquisition module 111, a second signal acquisition module 112, a digital signal reading module 113, and a pixel merging module 114.

[0091] The first signal acquisition module 111 is used to acquire the first pixel signal of the first pixel unit and the third pixel signal of the third pixel unit, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in the first column of the target image; the second signal acquisition module 112 is used to acquire the second pixel signal of the second pixel unit and the fourth pixel signal of the fourth pixel unit, wherein the second pixel unit and the fourth pixel unit are two adjacent pixel units in the second column of the target image, and the first pixel unit and the second pixel unit are adjacent in the first row, the third pixel unit and the fourth pixel unit are adjacent in the second row, the second column and the first column are adjacent columns, and the second row and the first row are adjacent rows; The character signal reading module 113 is used to read a first digital signal, a second digital signal, a third digital signal, and a fourth digital signal, wherein the first digital signal is a digital signal obtained by analog-to-digital conversion of a first pixel signal, the second digital signal is a digital signal obtained by analog-to-digital conversion of a second pixel signal, the third digital signal is a digital signal obtained by analog-to-digital conversion of a third pixel signal, and the fourth digital signal is a digital signal obtained by analog-to-digital conversion of a fourth pixel signal; the pixel merging module 114 is used to generate a merged signal of the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

[0092] In some embodiments, the pixel merging module 114 is further configured to: calculate the signal average of the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal; and determine the signal average as the signal value of the merged signal.

[0093] It should be noted that the examples and application scenarios implemented by the modules in the above device embodiments and the corresponding steps in the method embodiments are the same, but are not limited to the content disclosed in the above method embodiments. It should also be noted that the above modules, as part of the device, can be executed in a computer system such as a set of computer-executable instructions.

[0094] Those skilled in the art will understand that various aspects of this disclosure can be implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which can be collectively referred to herein as a "circuit", "module" or "system".

[0095] Based on the same inventive concept, this disclosure also provides an electronic device, which includes: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the pixel merging processing method described above by executing the executable instructions. Since the principle by which this electronic device solves the problem is similar to that of the above method embodiments, the implementation of this electronic device embodiment can refer to the implementation of the above method embodiments, and repeated details will not be described again.

[0096] The following reference Figure 12 To describe an electronic device 1200 according to such an embodiment of the present disclosure. Figure 12 The electronic device 1200 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0097] like Figure 12 As shown, the electronic device 1200 is manifested in the form of a general-purpose computing device. The components of the electronic device 1200 may include, but are not limited to: at least one processing unit 1210, at least one storage unit 1220, and a bus 1230 connecting different system components (including storage unit 1220 and processing unit 1210).

[0098] The storage unit stores program code, which can be executed by the processing unit 1210 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 1210 can perform the following steps of the above method embodiment: acquiring a first pixel signal of a first pixel unit and a third pixel signal of a third pixel unit, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in a first column of the target image; acquiring a second pixel signal of a second pixel unit and a fourth pixel signal of a fourth pixel unit, wherein the second pixel unit and the fourth pixel unit are two adjacent pixel units in a second column of the target image, and the first pixel unit and the second pixel unit are adjacent in a first row, the third pixel unit and the fourth pixel unit are adjacent in a second row, the second column and the first column are adjacent columns, and the second row... The two rows adjacent to the first row; read the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal, wherein the first digital signal is a digital signal obtained by analog-to-digital conversion of the first pixel signal, the second digital signal is a digital signal obtained by analog-to-digital conversion of the second pixel signal, the third digital signal is a digital signal obtained by analog-to-digital conversion of the third pixel signal, and the fourth digital signal is a digital signal obtained by analog-to-digital conversion of the fourth pixel signal; generate a merged signal of the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

[0099] Storage unit 1220 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 12201 and / or cache memory 12202, and may further include a read-only memory (ROM) 12203.

[0100] Storage unit 1220 may also include a program / utility 12204 having a set (at least one) of program modules 12205, such program modules 12205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0101] Bus 1230 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0102] Electronic device 1200 can also communicate with one or more external devices 1240 (e.g., keyboard, pointing device, Bluetooth device, etc.), one or more devices that enable a user to interact with electronic device 1200, and / or any device that enables electronic device 1200 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1250. Furthermore, electronic device 1200 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1260. As shown, network adapter 1260 communicates with other modules of electronic device 1200 via bus 1230. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0103] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0104] Based on the same inventive concept, this disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the pixel merging processing method described above. Since the principle by which this computer-readable storage medium solves the problem is similar to that of the above method embodiments, the implementation of this computer-readable storage medium embodiment can refer to the implementation of the above method embodiments, and repeated details will not be elaborated further.

[0105] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0106] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.

[0107] Optionally, the program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0108] In practical implementation, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0109] Based on the same inventive concept, this disclosure also provides a computer program product, including a computer program or instructions, which, when executed by a processor, implements the pixel merging processing method of any one of the above method embodiments. Since the principle by which this computer program product embodiment solves the problem is similar to that of the above method embodiments, the implementation of this computer program product embodiment can refer to the implementation of the above method embodiments, and repeated details will not be elaborated further.

[0110] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0111] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0112] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0113] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A pixel binning processing method characterized by, include: A pixel circuit is provided, the pixel circuit including at least one pixel group, the pixel group including at least a first pixel unit, a second pixel unit, a third pixel unit and a fourth pixel unit; The first pixel signal of the first pixel unit and the third pixel signal of the third pixel unit are acquired, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in the first column of the target image; The second pixel signal of the second pixel unit and the fourth pixel signal of the fourth pixel unit are acquired, wherein the second pixel unit and the fourth pixel unit are two adjacent pixel units in the second column of the target image, and the first pixel unit and the second pixel unit are adjacent in the first row, the third pixel unit and the fourth pixel unit are adjacent in the second row, the second column and the first column are two adjacent columns, and the second row and the first row are two adjacent rows; Read a first digital signal, a second digital signal, a third digital signal, and a fourth digital signal, wherein the first digital signal is a digital signal obtained by performing analog-to-digital conversion on a first pixel signal, the second digital signal is a digital signal obtained by performing analog-to-digital conversion on a second pixel signal, the third digital signal is a digital signal obtained by performing analog-to-digital conversion on a third pixel signal, and the fourth digital signal is a digital signal obtained by performing analog-to-digital conversion on a fourth pixel signal; A combined signal for the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit is generated based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

2. The pixel binning processing method according to claim 1, characterized in that, Based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal, a merged signal for the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit is generated, including: Calculate the signal average of the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal; The mean value of the signal is determined as the signal value of the merged signal.

3. A pixel binning circuit, characterized by, include: Pixel circuit, signal acquisition module, analog-to-digital conversion module, and data processing module; The pixel circuit includes at least one pixel group, wherein the pixel group includes at least a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit; The signal acquisition module is connected to the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit on the pixel circuit, respectively, and is used to acquire the first pixel signal of the first pixel unit, the second pixel signal of the second pixel unit, the third pixel signal of the third pixel unit, and the fourth pixel signal of the fourth pixel unit. The first pixel unit and the third pixel unit are two adjacent pixel units in the first column of the target image, the second pixel unit and the fourth pixel unit are two adjacent pixel units in the second column of the target image, and the first pixel unit and the second pixel unit are adjacent in the first row, the third pixel unit and the fourth pixel unit are adjacent in the second row, the second column and the first column are two adjacent columns, and the second row and the first row are two adjacent rows. The analog-to-digital conversion module is connected to the signal acquisition module and is used to convert the first pixel signal, the second pixel signal, the third pixel signal and the fourth pixel signal into corresponding first digital signal, second digital signal, third digital signal and fourth digital signal; The data processing module is connected to the analog-to-digital conversion module and is used to generate a combined signal of the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

4. The pixel merging circuit according to claim 3, characterized in that, The signal acquisition module includes: a first pixel signal acquisition circuit for acquiring the first pixel signal, a second pixel signal acquisition circuit for acquiring the second pixel signal, a third pixel signal acquisition circuit for acquiring the third pixel signal, and a fourth pixel signal acquisition circuit for acquiring the fourth pixel signal; The analog-to-digital conversion module includes: a first analog-to-digital conversion circuit for converting a first pixel signal into a first digital signal, a second analog-to-digital conversion circuit for converting a third pixel signal into a third digital signal, a third analog-to-digital conversion circuit for converting a second pixel signal into a second digital signal, and a fourth analog-to-digital conversion circuit for converting a fourth pixel signal into a fourth digital signal; The first analog-to-digital conversion circuit is connected to the first pixel signal acquisition circuit, the second analog-to-digital conversion circuit is connected to the third pixel signal acquisition circuit, the third analog-to-digital conversion circuit is connected to the second pixel signal acquisition circuit, and the fourth analog-to-digital conversion circuit is connected to the fourth pixel signal acquisition circuit.

5. An image sensor, characterized by, include: The pixel merging circuit according to claim 3 or 4.

6. An image acquisition device, characterized in that, include: The image sensor according to claim 5.

7. A pixel binning processing apparatus characterized by comprising: The apparatus is used to merge pixel signals of at least one pixel unit on a pixel circuit, the pixel circuit comprising: at least one pixel group, the pixel group comprising at least a first pixel unit, a second pixel unit, a third pixel unit, and a fourth pixel unit; the apparatus comprises: The first signal acquisition module is used to acquire the first pixel signal of the first pixel unit and the third pixel signal of the third pixel unit, wherein the first pixel unit and the third pixel unit are two adjacent pixel units in the first column of the target image; The second signal acquisition module is used to acquire the second pixel signal of the second pixel unit and the fourth pixel signal of the fourth pixel unit, wherein the second pixel unit and the fourth pixel unit are two adjacent pixel units in the second column of the target image, and the first pixel unit and the second pixel unit are adjacent in the first row, the third pixel unit and the fourth pixel unit are adjacent in the second row, the second column and the first column are two adjacent columns, and the second row and the first row are two adjacent rows; A digital signal reading module is used to read a first digital signal, a second digital signal, a third digital signal, and a fourth digital signal, wherein the first digital signal is a digital signal obtained by analog-to-digital conversion of a first pixel signal, the second digital signal is a digital signal obtained by analog-to-digital conversion of a second pixel signal, the third digital signal is a digital signal obtained by analog-to-digital conversion of a third pixel signal, and the fourth digital signal is a digital signal obtained by analog-to-digital conversion of a fourth pixel signal. The pixel merging module is used to generate a merged signal for the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

8. An electronic device, comprising: include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the pixel merging processing method of claim 1 or 2 by executing the executable instructions.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the pixel merging processing method according to claim 1 or 2.

10. A computer program product, comprising: A computer program or instruction, characterized in that, when executed by a processor, the computer program or instruction implements the pixel merging processing method according to claim 1 or 2.

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