MOS device and method of manufacturing the same

Abstract

This invention provides a MOS device and its fabrication method. The MOS device includes at least one cell structure, each cell structure comprising at least one body region and at least one source region. The body region is of a second conductivity type and is located in a substrate. The source regions are located in the substrate, with one source region corresponding to one body region and positioned above the corresponding body region. The source regions are connected to their corresponding body regions and are of a first conductivity type opposite to the second conductivity type. Specifically, a portion of the source regions in all cell structures of the MOS device is a high-concentration doped region of the first conductivity type, and another portion is a low-concentration doped region of the first conductivity type. This allows for self-negative feedback adjustment of the source region potential of the MOS device, significantly improving the safe operating area of ​​the MOS device in linear operating mode with minimal sacrifice in on-resistance. The fabrication method of the MOS device can fabricate the aforementioned MOS device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a MOS device and its fabrication method. Background Technology

[0002] In typical MOSFET applications, the transistor operates in a switching state. The drive voltage (VGS) is much higher than the threshold voltage (Vth). Because the on-resistance (Rds-on) of a MOSFET is very small, in the mΩ range, the on-state voltage drop (VDS) is also very small, resulting in a power dissipation of only around 10mW. Soft-start power MOSFETs need to remain on for extended periods under linear mode conditions exceeding 100W, which places extremely high demands on their performance and reliability. Currently, most power devices, especially low-to-medium voltage shielded gate trench (SGT) MOSFETs, require increasingly smaller cell pitches to achieve even lower specific on-resistance (Ron-sp), inevitably leading to higher power densities. Due to thermal instability, higher power densities result in greater current accumulation and temperature concentration, narrowing the safe operating area (SOA) and reducing performance in linear mode. Therefore, a lower specific on-resistance and a larger SOA are inherently mutually restrictive (trade-off). Due to their higher power density, SGT MOS devices are more difficult to improve in terms of SOA compared to ordinary trench MOS devices. Furthermore, improving SOA while maintaining a lower specific on-resistance is even more challenging.

[0003] Therefore, the problem of how to significantly improve the safe operating area of ​​MOS devices in linear operating mode with less sacrifice of specific on-resistance still needs to be solved. Summary of the Invention

[0004] One of the objectives of this invention is to significantly improve the safe operating area of ​​MOS devices in linear operating mode with less sacrifice than on-resistance.

[0005] To achieve the above objectives, the present invention provides a MOS device. The MOS device includes at least one cell structure, each cell structure including at least one body region and at least one source region; the body region is of a second conductivity type and is located in a substrate; the source region is located in the substrate, with one source region corresponding to one body region and located above the corresponding body region, the source region being connected to the corresponding body region, and the source region being of a first conductivity type opposite to the second conductivity type; wherein, a portion of all source regions in all cell structures of the MOS device is a high-concentration doped region of the first conductivity type and another portion is a low-concentration doped region of the first conductivity type, the doping concentration of the high-concentration doped region being greater than the doping concentration of the low-concentration doped region.

[0006] Optionally, the MOS device has multiple cell structures, with the source region of some of the cell structures being the high-concentration doped region and the source region of another portion of the cell structures being the low-concentration doped region.

[0007] Optionally, a number of the cell structures are grouped together; in each pair of adjacent cell structures, the source region of one group of cell structures is the high-concentration doped region, and the source region of the other group of cell structures is the low-concentration doped region.

[0008] Optionally, the MOS device has a plurality of the cell structures; the source region of some of the cell structures includes the high-concentration doped region and the low-concentration doped region, and the source region of another portion of the cell structures is either the high-concentration doped region or the low-concentration doped region.

[0009] Optionally, a portion of the source region of each cell structure is the high-concentration doped region and another portion is the low-concentration doped region.

[0010] Optionally, each of the cell structures includes two body regions and two source regions, one of the two source regions being a high-concentration doped region and the other being a low-concentration doped region; or, a portion of each source region is a high-concentration doped region and another portion is a low-concentration doped region.

[0011] Optionally, each of the cell structures has a gate electrode, and each of the gate electrodes has a body region in the substrate on both sides of the body region and a source region located on the body region.

[0012] Optionally, each cell structure has a trench in its substrate, the gate electrode is located in the trench, the gate electrode is located at the upper part of the trench, the lower part of the trench has a shielding gate, and the shielding gate and the gate electrode are isolated by an isolation oxide layer; or, the gate electrode is located above the substrate, and the two ends of the gate electrode respectively cover at least a portion of the source region on both sides of the gate electrode.

[0013] Optionally, the source region is located on top of the substrate; the MOS device further includes a source contact structure and a drain metal, the source contact structure is located on the top side of the substrate and electrically connected to the body region, and the drain metal is located on the bottom side of the substrate and electrically connected to the substrate.

[0014] Optionally, the MOS device can be a shielded gate trench MOS device, a trench MOS device, a VDMOS device, or a superjunction MOS device.

[0015] Another aspect of the present invention provides a method for fabricating a MOS device. The method includes: providing a substrate; forming at least one body region in the substrate, the body region being a second conductivity type; forming at least one source region on top of the substrate, one source region corresponding to one body region and located above the corresponding body region, the source region being connected to the corresponding body region, and the source region being a first conductivity type opposite to the second conductivity type; wherein the MOS device has at least one cell structure, each cell structure having at least one body region and at least one source region; a portion of all source regions of all cell structures is a high-concentration doped region of the first conductivity type and another portion is a low-concentration doped region of the first conductivity type, the doping concentration of the high-concentration doped region being greater than the doping concentration of the low-concentration doped region.

[0016] Optionally, forming at least one source region in the substrate includes: forming the low-concentration doped region above the body region; forming a mask layer on the substrate; and, under the masking of the mask layer, performing ion implantation on a portion of the low-concentration doped region to form the high-concentration doped region.

[0017] Optionally, the positions and areas of the high-concentration doped region and the low-concentration doped region are set according to the hot spot distribution of the MOS device chip before adjustment.

[0018] Optionally, the method for fabricating the MOS device further includes: forming at least one trench on the top of the substrate before forming at least one body region in the substrate; forming a trench oxide layer in the trench, the trench oxide layer covering the inner surface of the trench; forming a shielding gate at the lower part of the trench, the shielding gate being located on the trench oxide layer; forming an isolation oxide layer in the trench, the isolation oxide layer covering the shielding gate but not filling the trench; forming a gate oxide layer in the trench, the gate oxide layer covering the sidewall of the upper part of the trench; and forming a gate electrode at the upper part of the trench.

[0019] Optionally, the method for fabricating the MOS device further includes: after forming at least one source region in the substrate, forming an interlayer dielectric layer on top of the substrate, the interlayer dielectric layer covering the substrate; etching away a portion of the interlayer dielectric layer and a portion of the substrate to form a contact hole exposing the body region; forming a source contact metal on the interlayer dielectric layer, the source contact metal partially filling the contact hole as a source contact structure; and forming a drain metal at the bottom of the substrate, the drain metal being electrically connected to the substrate.

[0020] The MOS device and its fabrication method provided by this invention have at least one body region and at least one source region in the substrate. A portion of the source region is a high-concentration doped region of a first conductivity type, and another portion is a low-concentration doped region of the same first conductivity type. The doping concentration of the high-concentration doped region is greater than that of the low-concentration doped region. In other words, the entire source region of the MOS device includes both high-concentration and low-concentration doped regions. This allows for self-negative feedback adjustment of the source potential (Vs) of the MOS device; that is, as the temperature increases, the source potential also increases, for example, Vs > 0.7V. This suppresses the activation of parasitic NPN transistors and achieves the effect that the positive feedback of the device gradually decreases as the temperature or current increases. This allows for temperature control of various regions of the chip. Temperature and current distribution adjustment avoids temperature and current concentration, reduces uneven temperature distribution inside the chip, and reduces the probability of MOS device burnout. This significantly improves the safe operating area of ​​MOS devices (especially shielded gate trench type MOS devices) in linear operating mode. By flexibly adjusting the distribution of high-concentration doped and low-concentration doped regions in the source region, the current-temperature distribution in the active region of the MOS device can be flexibly adjusted, which is conducive to improving SOA in linear operating mode. Moreover, this method maximizes the preservation of channel width without sacrificing cell size and power density. Although a large source region resistance Rs is introduced in some areas, the parallel effect between the source region resistances of the chip as a whole ensures that the final Rds-on will not increase significantly, which is less than the sacrifice of the on-resistance. Attached Figure Description

[0021] Figure 1 This is a cross-sectional schematic diagram of a shielded gate trench MOS device.

[0022] Figure 2 This is a schematic diagram of the hot spot on a shielded gate trench MOS device.

[0023] Figure 3 This is a cross-sectional schematic diagram of a shielded gate trench MOS device provided in an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram showing the distribution of high-concentration doped regions and low-concentration doped regions in the source region of a MOS device chip provided in an embodiment of the present invention.

[0025] Figure 5 This is a schematic diagram showing the distribution of high-concentration doped regions and low-concentration doped regions in the source region of a MOS device chip provided in another embodiment of the present invention.

[0026] Figure 6 This is a cross-sectional schematic diagram of a conventional trench MOS device provided in an embodiment of the present invention.

[0027] Figure 7 This is a cross-sectional schematic diagram of a VDMOS device provided in an embodiment of the present invention.

[0028] Figure 8 This is a cross-sectional schematic diagram of a superjunction MOS device provided in an embodiment of the present invention.

[0029] Figures 9 to 22 This is a schematic diagram illustrating the fabrication process of a shielded gate trench MOS device according to an embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures: 100-substrate; 101-trench; 102-trench oxide layer; 103-shielding gate; 104-isolation oxide layer; 105-gate oxide layer; 106-gate electrode; 107-P-type well region; 108-source region; 109-interlayer dielectric layer; 110-contact hole; 111-metal layer;

[0031] 200-Substrate; 200a-Substrate; 200b-Epipolar layer; 201a-Hard mask material layer; 201-Hard mask layer; 202-Trench; 203-Trench oxide layer; 204a-Shielding gate material layer; 204-Shielding gate; 205a-Isolation material layer; 205-Isolation oxide layer; 206-Gate oxide layer; 207-Gate electrode; 208-Bulk region; 209a-Low concentration doped region; 209b-High concentration doped region; 210-Interlayer dielectric layer; 211-Second conductivity type enriched region; 212-Source metal; 212a-Source contact structure; 213-Drain metal; 214-N-pillar; 215-P-pillar. Detailed Implementation

[0032] Figure 1 This is a schematic cross-sectional view of a shielded gate trench MOS device. (Reference) Figure 1 As shown, the fabrication process of this shielded gate trench MOS device includes: etching a substrate 100 to form a trench 101; forming a trench oxide layer 102 covering the inner surface of the trench 101; forming a shielding gate 103 in the lower part of the trench 101 and on the trench oxide layer 102; forming an isolation oxide layer 104 in the trench 101 and on the shielding gate 103, and removing the trench oxide layer 102 on the upper sidewall of the trench 101 to expose the upper sidewall of the trench 101; forming a gate oxide layer 105 on the upper sidewall of the trench 101; forming a gate electrode 106 in the trench 101; and forming a gate electrode 106 in the trench 101. A P-type well region 107, serving as a P-type body region, is formed on the top of the substrate on the side of the trench 101. N-type ion implantation and annealing are performed to form a source region 108 located on the P-type well region 107. An interlayer dielectric layer (ILD) 109 is formed on the substrate 100. The interlayer dielectric layer 109 and part of the substrate 100 are etched to form a contact hole 110, the bottom of which is located within the P-type well region 107. A metal layer 111 is formed on the interlayer dielectric layer 109, with the metal layer 111 partially located on the interlayer dielectric layer 109 and partially filling the contact hole 110 as a source contact structure.

[0033] In this process, only one high-dose N-type ion implantation is performed to form the low-resistance source region 108. This method makes the source region resistance the same throughout the chip, but due to the differences in conductivity and heat dissipation capabilities at different parts of the chip, a current and temperature accumulation point will inevitably appear at some point in the chip during linear operation. Figure 2 This is a schematic diagram of the hot spot on a shielded gate trench MOS device. Figure 2 As shown, due to the continuous positive feedback between thermo-electricity, thermally unstable regions (regions where DI / DT>0) will appear in the active area of ​​the chip, eventually leading to hot spots in the thermally unstable region of the device, which in turn leads to device failure. The more uneven the heat dissipation capacity inside the chip, the weaker the safe operating area capability of the device will be.

[0034] In order to significantly improve the safe operating area of ​​MOS devices in linear operating mode with less sacrifice of on-resistance, this invention provides a MOS device and its fabrication method.

[0035] The MOS device and its fabrication method provided by this invention have at least one body region and at least one source region in the substrate. A portion of the source region is a high-concentration doped region of a first conductivity type, and another portion is a low-concentration doped region of the same first conductivity type. The doping concentration of the high-concentration doped region is greater than that of the low-concentration doped region. In other words, the entire source region of the MOS device includes both high-concentration and low-concentration doped regions. This allows for self-negative feedback adjustment of the source potential (Vs) of the MOS device; that is, as the temperature increases, the source potential also increases, for example, Vs > 0.7V. This suppresses the activation of parasitic NPN transistors and achieves the effect that the positive feedback of the device gradually decreases as the temperature or current increases. This allows for temperature control of various regions of the chip. Temperature and current distribution adjustment avoids temperature and current concentration, reduces uneven temperature distribution inside the chip, and reduces the probability of MOS device burnout. This significantly improves the safe operating area of ​​MOS devices (especially shielded gate trench type MOS devices) in linear operating mode. By flexibly adjusting the distribution of high-concentration doped and low-concentration doped regions in the source region, the current-temperature distribution in the active region of the MOS device can be flexibly adjusted, which is conducive to improving SOA in linear operating mode. Moreover, this method maximizes the preservation of channel width without sacrificing cell size and power density. Although a large source region resistance Rs is introduced in some areas, the parallel effect between the source region resistances of the chip as a whole ensures that the final Rds-on will not increase significantly, which is less than the sacrifice of the on-resistance.

[0036] The MOS device and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0037] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, "upper / upper layer" and / or "lower / lower layer," and similar terms are for ease of description only and are not limited to a location or spatial orientation. "Comprising" or "including," and similar terms mean that the element or structure preceding "comprising" or "including" encompasses the element or structure listed following "comprising" or "including" and its equivalents, and do not exclude other elements or structures. "Connected," or similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0038] Figure 3 This is a schematic cross-sectional view of a shielded gate trench MOS device according to an embodiment of the present invention. (See reference) Figure 3 As shown, the MOS device provided in this application includes at least one cell structure ( Figure 3 (The area within the dashed box represents a single cell structure). A single cell structure includes at least one body region 208 and at least one source region. The body region 208 is of the second conductivity type and is located in the substrate 200. The source region is located in the substrate 200, with one source region corresponding to one body region 208 and located above the corresponding body region 208. The source region is connected to the corresponding body region 208 and is of the first conductivity type, which is opposite to the second conductivity type. Among these, a portion of all source regions in all cell structures of the MOS device is a high-concentration doped region 209b of the first conductivity type, and another portion is a low-concentration doped region 209a of the first conductivity type. The doping concentration of the high-concentration doped region 209b is greater than the doping concentration of the low-concentration doped region 209a.

[0039] In this embodiment, the substrate 200 may include a substrate 200a and an epitaxial layer 200b located on the substrate 200a, and the body region 208 and the source region may be formed in the epitaxial layer 200b. For example, the substrate 200a may be an N+ substrate and the epitaxial layer 200b may be an N- epitaxial layer, but it is not limited thereto.

[0040] In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the body region 208 is a P-type doped region, and the source region is an N-type doped region, but it is not limited to these.

[0041] In this application, the position and area of ​​the low-concentration doped region 209a and the high-concentration doped region 209b in the source region can be flexibly adjusted according to the original hot spot distribution of the MOS device chip before adjustment, so as to make the current-temperature distribution of the chip more uniform and improve the safe operating area range of the MOS device in linear operating mode.

[0042] Figure 4 This is a schematic diagram illustrating the distribution of high-concentration doped and low-concentration doped regions in the source region of a MOS device chip according to an embodiment of the present invention. (For...) Figure 2 The hotspot distribution of the chip shown is illustrated in one embodiment of this application, with reference to... Figure 4 As shown, the source region in the area where hot spots are prone to occur in the MOS device chip can be set as a low-concentration doped region 209a, and the source region in the remaining areas can be set as a high-concentration doped region 209b. This can improve the problem of hot spots appearing in local areas of the chip.

[0043] In one embodiment of this application, as Figure 3 As shown, a portion of the source region in each cell structure is a highly doped region 209b, and another portion is a low-doped region 209a. For more details, see [reference needed]. Figure 3 As shown, each cell structure includes two body regions 208 and two source regions. One source region is located above one body region 208, and the bottom surface of the source region is connected to the top surface of the corresponding body region 208. One of the two source regions is a high-concentration doped region 209b, and the other is a low-concentration doped region 209a. In adjacent cell structures, the low-concentration doped region 209a in the source region is close to each other, but this is not a limitation. In other embodiments, depending on the actual hotspot distribution of the chip, a portion of each source region can be set as a high-concentration doped region 209b, and another portion as a low-concentration doped region 209a.

[0044] In one embodiment of this application, the MOS device has multiple cell structures, with the source region of some cell structures being a high-concentration doped region 209b and the source region of another portion of cell structures being a low-concentration doped region 209a.

[0045] Figure 5This is a schematic diagram illustrating the distribution of high-concentration doped and low-concentration doped regions in the source region of a MOS device chip according to another embodiment of the present invention. For more details, please refer to... Figure 5 As shown, several cellular structures form a group, for example... Figure 5 In a rectangular strip, a unit cell structure is formed. In each pair of adjacent unit cell structures, the source region of one unit cell structure is a high-concentration doped region 209b, and the source region of the other unit cell structure is a low-concentration doped region 209a. The number of unit cell structures in a unit cell structure can be 1, 2, or 3, etc.

[0046] In some embodiments of this application, the MOS device may have multiple cell structures; the source region of some cell structures includes a high-concentration doped region 209b and a low-concentration doped region 209a, and the source region of other cell structures is either a high-concentration doped region 209b or a low-concentration doped region 209a, which can be set according to the actual situation.

[0047] In this application, the MOS device can be a shielded gate trench MOS device, a trench MOS device, a VDMOS device, or a superjunction MOS device, etc.

[0048] Figure 6 This is a cross-sectional schematic diagram of a conventional trench MOS device provided in an embodiment of the present invention. Figure 7 This is a cross-sectional schematic diagram of a VDMOS device provided in an embodiment of the present invention. Figure 8 This is a schematic cross-sectional view of a superjunction MOS device according to an embodiment of the present invention. Figures 6 to 8 In the image, the area within the dashed box represents a single cell structure.

[0049] refer to Figure 3 , Figures 6 to 8 As shown, each cell structure in the MOS device has a gate electrode 207, and each gate electrode 207 has a body region 208 in the substrate on both sides and a source region located above the body region.

[0050] For shielded gate trench MOS devices and ordinary trench MOS devices, refer to Figure 3 and Figure 6 As shown, each cell structure has a trench 202 in its substrate, and the gate electrode 207 is located within the trench 202. For a shielded gate trench MOS device, the gate electrode 207 is located at the upper part of the trench 202, and the lower part of the trench 202 also has a shielded gate 204. The shielded gate 204 and the gate electrode 207 are isolated by an isolation oxide layer 205.

[0051] For VDMOS devices and superjunction MOS devices, refer to Figure 7 and Figure 8As shown, the gate electrode 207 is located above the substrate 200. Both ends of the gate electrode 207 cover at least part of the source regions on both sides of the gate electrode 207. For example, one end of the gate electrode 207 covers part of the low-concentration doped region 209a and the other end covers part of the high-concentration doped region 209b. The body region 208 can wrap the corresponding source region, that is, the bottom surface and side walls of the source region are connected to the corresponding body region 208.

[0052] For a superjunction MOS device, as Figure 8 shown, the substrate 200 includes a substrate 200a, N columns 214 and P columns 215 located on the substrate 200a. The N columns 214 and P columns 215 are arranged alternately, and the top end of the P column 215 protrudes towards the N column 214. Thus, the cross-section of the N column can be "convex" and the cross-section of the P column can be an inverted "convex". The top end of the P column 215 is the body region 208.

[0053] In the MOS device provided in this application, referring to Figure 3 、 Figures 6 to 8 shown, the body region 208 and the source region are located at the top of the substrate 200; the MOS device may further include a source contact structure 212a and a drain metal 213; the source contact structure 212a is located on one side of the top of the substrate 200 and is electrically connected to the corresponding body region 208. The source contact structure 212a is also in direct contact with the corresponding source region (low-concentration doped region 209a or high-concentration doped region 209b); the drain metal 213 is located on one side of the bottom of the substrate 200 and is electrically connected to the substrate 200. The drain metal 213 can cover the bottom surface of the substrate 200. Among them, the body region 208 has a second-conductivity-type enhanced region 211 in direct contact with the source contact structure 212a. The second-conductivity-type enhanced region 211 is, for example, a P+ doped region. The doping concentration of the second-conductivity-type enhanced region 211 is greater than the doping concentration of the body region 208. The source contact structure 212a is in direct contact with the second-conductivity-type enhanced region 211 to electrically connect the body region 208, so as to reduce the contact resistance between the source contact structure 212a and the body region 208.

[0054] For a shielded-gate trench MOS device, referring to Figure 3 shown, a source metal 212 is provided above the top of the substrate 200 on the interlayer dielectric layer 210. The source metal 212 partially fills the contact hole in the interlayer dielectric layer 210 and serves as the source contact structure 212a. Another part of the source metal 212 is located above the interlayer dielectric layer 210 and connects multiple source contact structures 212a.

[0055] The present invention also provides a method for fabricating a MOS device. The method includes: providing a substrate; forming at least one body region in the substrate, the body region being a second conductivity type; forming at least one source region on the top of the substrate, one source region corresponding to one body region and located above the corresponding body region, the source region being connected to the corresponding body region, and the source region being a first conductivity type opposite to the second conductivity type; wherein the MOS device has at least one cell structure, each cell structure having at least one body region and at least one source region; a portion of all source regions in all cell structures is a high-concentration doped region of the first conductivity type, and another portion is a low-concentration doped region of the first conductivity type, the doping concentration of the high-concentration doped region being greater than the doping concentration of the low-concentration doped region.

[0056] Specifically, the step of forming at least one source region in the substrate includes: after forming a body region in the substrate, performing a first first conductivity type ion implantation to form a low-concentration doped region above the body region; forming a mask layer on the substrate; and, under the mask layer, performing a second first conductivity type ion implantation on a portion of the low-concentration doped region to form a high-concentration doped region. The dose of the first first conductivity type ion implantation is less than the dose of the second first conductivity type ion implantation. Thus, by adding a mask layer and using two first conductivity type ion implantations with different doses, a source region including both high-concentration and low-concentration doped regions can be formed. This significantly improves the safe operating area of ​​the MOS device in linear operating mode with less sacrifice compared to on-resistance. Furthermore, by adjusting the pattern of the mask layer, the distribution of the high-concentration and low-concentration doped regions can be flexibly adjusted, thereby allowing for flexible adjustment of the chip's temperature and current distribution. For example, the dose of the first first conductivity type ion implantation is, for instance, 13–14 cm⁻¹. -2 The dose of the second first-conductivity ion implantation is, for example, 14–15 cm⁻¹. -2 .

[0057] For example, based on the hotspot distribution of the MOS device chip before adjustment, the positions and areas of high-concentration doped regions and low-concentration doped regions can be set. This can effectively improve the temperature and current distribution of the chip, avoid temperature and current concentration, reduce uneven temperature distribution inside the chip, reduce the probability of MOS device burnout, and significantly improve the safe operating area of ​​the MOS device in linear operating mode. For instance, the source region in the area where hotspots appeared before adjustment of the MOS device chip can be set as a low-concentration doped region, and the source regions in other areas can be set as high-concentration doped regions, but this is not limited to this.

[0058] Figures 9 to 22 This is a schematic diagram illustrating the fabrication process of a shielded gate trench MOS device according to an embodiment of the present invention. The following is in conjunction with... Figure 3 , Figures 9 to 22Taking the shielded gate trench type MOS device as an example, the fabrication method of the MOS device of this application will be specifically described. The fabrication methods of other types of MOS devices can be adapted accordingly.

[0059] like Figure 9 As shown, a substrate 200 is provided. The substrate 200 may include a substrate 200a and an epitaxial layer 200b located on the substrate 200a. Exemplarily, the substrate 200a may be an N+ substrate and the epitaxial layer 200b may be an N- epitaxial layer, but is not limited thereto.

[0060] like Figure 10 As shown, a hard mask material layer 201a is formed on the substrate 200, and the hard mask material layer 201a covers the epitaxial layer 200b in the substrate 200.

[0061] refer to Figure 10 and Figure 11 As shown, a patterned photoresist layer (not shown) is formed on the hard mask material layer 201a. Using the patterned photoresist layer as a mask, the hard mask material layer 201a is etched to form a patterned hard mask layer 201. Using the hard mask layer 201 as a mask, the substrate 200 is etched to form at least one trench 202 in the substrate 200.

[0062] In this embodiment, multiple trenches 202 can be formed in the substrate 200. For example... Figure 11 As shown, in this embodiment, the hard mask layer 201 is a multilayer structure comprising multiple layers of different materials. For example, the hard mask layer 201 may include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially, but is not limited thereto. In other embodiments, the hard mask layer 201 may also be a single-layer structure comprising a single material layer.

[0063] like Figure 12 As shown, a trench oxide layer 203 is formed within the trench 202, covering the inner surface of the trench 202. Exemplarily, a thermal oxidation process can be used to form the trench oxide layer 203, but it is not limited thereto. The material of the trench oxide layer 203 includes, but is not limited to, silicon oxide.

[0064] like Figure 13 As shown, a shielding grid material layer 204a is formed on the substrate 200, the shielding grid material layer 204a covers the substrate 200, the trench oxide layer 203 and fills the trench 202.

[0065] like Figure 14As shown, the shielding gate material layer 204a is etched back, retaining the shielding gate material layer 204a at the bottom of the trench 202 as the shielding gate 204. For example, the material of the shielding gate 204 includes, but is not limited to, polysilicon. After forming the shielding gate 204, the trench oxide layer 203 at the top of the trench 202 can be removed, exposing the sidewalls at the top of the trench 202.

[0066] like Figure 15 As shown, an isolation material layer 205a is formed on the substrate 200. The isolation material layer 205a can cover the substrate 200. Part of the isolation material layer 205a can be removed by grinding until the hard mask layer 201 is exposed. It should be noted that during the grinding of the isolation material layer 205a and the etching of the shielding gate material layer 204a, a portion of the hard mask layer 201 will inevitably be lost.

[0067] like Figure 16 As shown, a portion of the isolation material layer 205a is etched away, leaving a portion of the remaining isolation material layer 205a within the trench 202, which serves as an isolation oxide layer 205. This isolation oxide layer 205 covers the shielding gate 204 but does not completely fill the trench 202. Exemplarily, the material of the isolation oxide layer 205 includes, but is not limited to, silicon oxide. After etching away a portion of the isolation material layer 205a to form the isolation oxide layer 205, the upper sidewalls of the trench 202 are exposed, and the remaining hard mask layer 201 on the substrate 200 can also be removed.

[0068] like Figure 17 As shown, a gate oxide layer 206 is formed within the trench 202, covering the upper sidewall of the trench 202. Exemplarily, the gate oxide layer 206 can be formed by a thermal oxidation process. The thickness of the gate oxide layer 206 can be set according to the performance requirements of the device.

[0069] like Figure 18 As shown, a gate electrode 207 is formed on the upper part of the trench 202, and the gate electrode 207 is isolated from the shielding gate 204 by an isolation oxide layer 205. For example, the material of the gate electrode 207 includes, but is not limited to, polysilicon.

[0070] like Figure 19 As shown, at least one body region 208 is formed in the substrate 200 by ion implantation. In this embodiment, the body region 208 is of a second conductivity type, which is P-type. In this embodiment, body regions 208 are formed on the top of the substrate on both sides of the gate electrode 207, or on both sides of the trench 202.

[0071] like Figure 20As shown, a low-concentration doped region 209a of a first conductivity type is formed above the body region 208. Specifically, a low-concentration doped region 209a is formed on the top of each body region 208, and the bottom surface of each low-concentration doped region 209a is connected to the corresponding body region 208.

[0072] refer to Figure 21 As shown, a mask layer (not shown) is formed on the substrate 200. Under the mask layer, a portion of the low-concentration doped region 209a is implanted with ions of the first conductivity type to form a high-concentration doped region 209b. In this embodiment, the low-concentration doped region 209a and the high-concentration doped region 209b together serve as the source region of the MOS device. The distribution of the low-concentration doped region 209a and the high-concentration doped region 209b in the source region of the MOS device can refer to the above description and will not be repeated here.

[0073] refer to Figure 22 As shown, an interlayer dielectric layer 210 is formed on top of the substrate 200, and the interlayer dielectric layer 210 covers the substrate 200 and the gate electrode 207. The material of the interlayer dielectric layer 210 includes, but is not limited to, silicon oxide.

[0074] refer to Figure 3 As shown, etching removes part of the interlayer dielectric layer 210 and part of the substrate 200 to form a contact hole exposing the body region 208. A second conductivity type enrichment region 211 can be formed in the body region at the bottom of the contact hole. A source contact metal 212 is formed on the interlayer dielectric layer 210. The source contact metal 212 partially fills the contact hole as a source contact structure 212a. The source contact structure 212a is electrically connected to the body region 208. A drain metal 213 is formed at the bottom of the substrate 200. The drain metal 213 is electrically connected to the substrate 200.

[0075] In the MOS device and its fabrication method provided by this invention, the substrate 200 of the MOS device has at least one body region 208 and at least one source region. A portion of the source region is a high-concentration doped region 209b of a first conductivity type, and another portion is a low-concentration doped region 209a of the first conductivity type. The doping concentration of the high-concentration doped region 209b is greater than the doping concentration of the low-concentration doped region 209a. In other words, the entire source region of the MOS device includes both the high-concentration doped region 209b and the low-concentration doped region 209a. This allows for self-negative feedback adjustment of the source region potential (Vs) of the MOS device; that is, as the temperature increases, the source region potential also increases, for example, Vs > 0.7V, thereby suppressing the turn-on of parasitic NPN transistors and achieving the effect that the positive feedback of the device gradually decreases as the temperature or current increases. As a result, the temperature and current distribution in different areas of the chip can be adjusted, avoiding the concentration of temperature and current, reducing the uneven temperature distribution inside the chip, and reducing the probability of MOS device burnout. This significantly improves the safe operating area of ​​MOS devices (especially shielded gate trench type MOS devices) in linear operating mode. By flexibly adjusting the distribution of high-concentration doped and low-concentration doped regions in the source region, the current-temperature distribution in the active region of the MOS device can be flexibly adjusted, which is conducive to improving SOA in linear operating mode. Moreover, this method maximizes the preservation of channel width without sacrificing cell size and power density. Although a large source resistance Rs is introduced in some areas, the parallel effect between the source resistances of the chip as a whole ensures that the final Rds-on will not increase significantly, i.e., less than the sacrifice of the on-resistance.

[0076] It should be noted that this instruction manual uses a progressive approach, with later descriptions focusing on the differences from earlier descriptions. Similarities and similarities between different sections can be found by referring to each other.

[0077] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A MOS device, characterized by, The device includes at least one cell structure, each cell structure comprising at least one body region and at least one source region; the body region is of a second conductivity type and is located in a substrate; the source region is located in the substrate, one source region is disposed corresponding to one body region and is located above the corresponding body region, the source region is connected to the corresponding body region, and the source region is of a first conductivity type opposite to the second conductivity type; wherein, a portion of all source regions of all cell structures in the MOS device is a high-concentration doped region of the first conductivity type and another portion is a low-concentration doped region of the first conductivity type, the doping concentration of the high-concentration doped region is greater than the doping concentration of the low-concentration doped region.

2. The MOS device of claim 1, wherein, The MOS device has multiple cell structures, with the source region of some of the cell structures being the high-concentration doped region and the source region of another portion of the cell structures being the low-concentration doped region.

3. The MOS device of claim 2, wherein, A number of the aforementioned cell structures form a group; in each pair of adjacent groups of cell structures, the source region of one group of cell structures is the high-concentration doped region, and the source region of the other group of cell structures is the low-concentration doped region.

4. The MOS device of claim 1, wherein, The MOS device has a plurality of the cell structures; the source region of some of the cell structures includes the high-concentration doped region and the low-concentration doped region, and the source region of another portion of the cell structures is either the high-concentration doped region or the low-concentration doped region.

5. The MOS device of claim 1, wherein, A portion of the source region of each cell structure is the high-concentration doped region and another portion is the low-concentration doped region.

6. The MOS device of claim 5, wherein, Each of the cell structures includes two body regions and two source regions, one of the two source regions being a high-concentration doped region and the other being a low-concentration doped region, or a portion of each source region being a high-concentration doped region and another portion being a low-concentration doped region.

7. The MOS device as claimed in claim 1, characterized in that, Each of the cell structures has a gate electrode, and each of the two sides of the gate electrode has a body region in the substrate and a source region located on the body region.

8. The MOS device as described in claim 7, characterized in that, Each cell structure has a trench in its substrate, the gate electrode is located in the trench, the gate electrode is located at the upper part of the trench, the lower part of the trench has a shielding gate, and the shielding gate and the gate electrode are isolated by an isolation oxide layer; or, the gate electrode is located above the substrate, and the two ends of the gate electrode respectively cover at least a portion of the source region on both sides of the gate electrode.

9. The MOS device as claimed in claim 1, characterized in that, The source region is located on top of the substrate; the MOS device further includes a source contact structure and a drain metal, the source contact structure is located on the top side of the substrate and electrically connected to the body region, and the drain metal is located on the bottom side of the substrate and electrically connected to the substrate.

10. The MOS device as claimed in claim 1, characterized in that, The MOS device is a shielded gate trench MOS device, a trench MOS device, a VDMOS device, or a superjunction MOS device.

11. A method for fabricating a MOS device, characterized in that, include: Provide a base; At least one body region is formed in the substrate, the body region being of a second conductivity type; At least one source region is formed on the top of the substrate, one source region is disposed corresponding to one body region and located above the corresponding body region, the source region is connected to the corresponding body region, and the source region is a first conductivity type opposite to the second conductivity type; The MOS device has at least one cell structure, and each cell structure has at least one body region and at least one source region. A portion of the source regions of all the cell structures is a high-concentration doped region of a first conductivity type and another portion is a low-concentration doped region of a first conductivity type, wherein the doping concentration of the high-concentration doped region is greater than the doping concentration of the low-concentration doped region.

12. The method for fabricating a MOS device as described in claim 11, characterized in that, The formation of at least one source region in the substrate includes: The low-concentration doped region is formed above the body region; A mask layer is formed on the substrate; and Under the cover of the mask layer, ion implantation is performed on a portion of the low-concentration doped region to form the high-concentration doped region.

13. The method for fabricating a MOS device as described in claim 11, characterized in that, Based on the hotspot distribution of the MOS device chip before adjustment, the positions and areas of the high-concentration doped region and the low-concentration doped region are set.

14. The method for fabricating a MOS device as described in claim 11, characterized in that, Also includes: Before forming at least one body region in the substrate, at least one trench is formed on the top of the substrate; A trench oxide layer is formed in the trench, and the trench oxide layer covers the inner surface of the trench; A shielding grid is formed at the lower part of the trench, and the shielding grid is located on the oxide layer of the trench; An isolation oxide layer is formed in the trench, the isolation oxide layer covering the shielding grid but not filling the trench; A gate oxide layer is formed in the trench, and the gate oxide layer covers the upper sidewall of the trench; as well as A gate electrode is formed at the upper part of the trench.

15. The method for fabricating a MOS device as described in claim 11, characterized in that, Also includes: After forming at least one source region in the substrate, an interlayer dielectric layer is formed on top of the substrate, the interlayer dielectric layer covering the substrate; Etching removes part of the interlayer dielectric layer and part of the substrate to form contact holes that expose the body region; A source contact metal is formed on the interlayer dielectric layer, and the source contact metal partially fills the contact hole as a source contact structure. as well as A drain metal is formed at the bottom of the substrate, and the drain metal is electrically connected to the substrate.

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