High-frequency reliability test circuits and semiconductor reliability test equipment

Abstract

This application discloses a high-frequency reliability testing circuit and a semiconductor reliability testing device. The high-frequency reliability testing circuit includes: a signal input terminal for receiving a high-frequency sinusoidal signal; a DC blocking capacitor, one end of which is coupled to the signal input terminal; a self-biased inverter unit, its input terminal coupled to the other end of the DC blocking capacitor, for converting the high-frequency sinusoidal signal into a quasi-square wave signal; a buffer unit, its input terminal coupled to the output terminal of the self-biased inverter unit, for shaping and amplifying the quasi-square wave signal to generate a shaped square wave signal; and a signal output terminal coupled to the output terminal of the buffer unit for outputting the shaped square wave signal. The signal output terminal is coupled to the device under test (DUT) to apply the shaped square wave signal as AC electrical stress to the DUT. This application solves the problem of high-frequency test signals being limited by external bandwidth in the prior art, enabling accurate assessment of the reliability and lifetime of devices in high-frequency application scenarios.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a high-frequency reliability testing circuit and a semiconductor reliability testing device. Background Technology

[0002] Current wafer foundries primarily use DC stress for time-dependent dielectric breakdown (TDDB) reliability testing of gate oxide devices. However, numerous industry studies have shown that device lifetime under AC TDDB is longer than that under DC TDDB. Therefore, AC TDDB testing is crucial for accurately assessing device reliability under real-world operating conditions.

[0003] Although the operating frequencies of active devices vary from tens of MHz to tens of GHz depending on the application, most wafer foundries currently use DC test architectures for AC TDDB testing. This limitation restricts current test frequencies to below 1 MHz, failing to meet the testing requirements of high-frequency applications.

[0004] Therefore, existing testing methods cannot provide TDDB lifetime data at high frequencies (e.g., above 100MHz), which limits the operating voltage of devices. How to overcome these frequency limitations and achieve high-frequency reliability testing is a problem that the industry needs to solve. Summary of the Invention

[0005] The purpose of this application is to provide a high-frequency reliability test circuit and a semiconductor reliability test device to solve the problem that the existing AC breakdown reliability test uses a DC test architecture, which causes the test signal to be limited by the external transmission bandwidth and cannot maintain a high-frequency square wave waveform inside the chip, and the test frequency is limited to within 1MHz, making it impossible to accurately evaluate the reliability life of the device in high-frequency (such as 100MHz) application scenarios.

[0006] To achieve the above objectives, this application adopts the following technical solution.

[0007] According to a first aspect of this application, embodiments of this application provide a high-frequency reliability test circuit, comprising: The signal input terminal is used to receive high-frequency sine wave signals; A DC blocking capacitor, one end of which is coupled to the signal input terminal; The self-biased inverter unit, whose input terminal is coupled to the other end of the DC blocking capacitor, is used to convert the high-frequency sine wave signal into a quasi-square wave signal. A buffer unit, the input of which is coupled to the output of the self-biased inverter unit, is used to shape and amplify the quasi-square wave signal to generate a shaped square wave signal. The signal output terminal is coupled to the output terminal of the buffer unit and is used to output the shaped square wave signal; The signal output terminal is coupled to the device under test (DUT) to apply the shaped square wave signal as AC electrical stress to the DUT.

[0008] In some possible implementations, the self-biased inverter unit includes: a first inverter and a first resistor; the input terminal of the first inverter is coupled to the other end of the DC blocking capacitor, and the output terminal of the first inverter is coupled to the buffer unit; the first resistor is coupled to the input terminal and the output terminal of the first inverter respectively, for providing a bias voltage.

[0009] In some possible implementations, the capacitance of the DC blocking capacitor is 50pF to 200pF, and the resistance of the first resistor is 100kΩ to 500kΩ.

[0010] In some possible implementations, the buffer unit includes at least two cascaded buffers; the output of the self-biased inverter unit is coupled to the input of the first-stage buffer, the output of the first-stage buffer is coupled to the input of the second-stage buffer, and the output of the second-stage buffer is coupled to the signal output.

[0011] In some possible implementations, the buffer includes an inverter.

[0012] In some possible implementations, the signal input terminal includes a first pad having two ground terminals and a signal terminal for receiving high-frequency sinusoidal signals.

[0013] In some possible implementations, the high-frequency reliability test circuit further includes: a signal detection terminal for coupling the signal output terminal and an external test device to monitor the waveform of the shaped square wave signal through the external test device.

[0014] In some possible implementations, the high-frequency reliability test circuit further includes: a DC power supply terminal coupled to the self-biased inverter unit and the buffer unit, wherein the amplitude of the shaped square wave signal is determined based on the voltage of the DC power supply terminal.

[0015] In some possible implementations, the device under test is a gate oxide capacitor.

[0016] According to a second aspect of this application, embodiments of this application provide a semiconductor reliability testing apparatus, comprising: A signal source used to generate high-frequency sine wave signals; A DC power supply is used to provide DC voltage. The semiconductor chip under test includes a high-frequency reliability test circuit and a device under test as described in any embodiment of this application. The signal source is coupled to the signal input terminal of the high-frequency reliability test circuit, the DC power supply is coupled to the DC power supply terminal of the high-frequency reliability test circuit, and the device under test is coupled to the signal output terminal of the high-frequency reliability test circuit.

[0017] This application provides a high-frequency reliability testing circuit and a semiconductor reliability testing apparatus. The testing circuit is integrated on a semiconductor chip and includes a DC blocking capacitor, a self-biased inverter unit, and a buffer unit. Utilizing the ease of transmission of high-frequency sinusoidal signals, the testing circuit receives an externally input high-frequency sinusoidal signal at its signal input terminal. This signal is then converted into a quasi-square wave signal via the DC blocking capacitor and the self-biased inverter unit. The buffer unit further shapes and amplifies the signal into a shaped square wave signal to generate a high-frequency AC electrical stress to be applied to the device under test (DUT). This application effectively solves the ripple interference caused by the loss of high-order harmonics due to the transmission of the external square wave signal via cable in existing testing methods and enables high-frequency AC TDDB testing.

[0018] Furthermore, this application enables high-frequency square wave stress testing using a conventional signal source and DC power supply. The test frequency is determined by the signal source, and the amplitude of the shaped square wave signal is determined by the voltage of the DC power supply. This application not only reduces reliance on high-frequency pulse generators but also allows for arbitrary adjustment of the square wave amplitude based on the DC power supply settings, thereby enabling high-frequency TDDB testing and modeling.

[0019] Furthermore, in this application, the output square wave amplitude can be entirely dependent on the voltage of the external DC power supply. If a conventional on-chip high-frequency waveform generator circuit is used, microfarad-level decoupling capacitors must be integrated on-chip to suppress power supply fluctuations during high-frequency switching and maintain ideal square wave edges, which would occupy a large chip area. This application, however, by shifting the requirement for waveform amplitude stability externally, allows any power supply fluctuations to be avoided in the simplest way (e.g., by connecting a bias-T at the power supply terminal). Therefore, this application avoids the problem of a significant increase in area caused by large on-chip capacitors.

[0020] Furthermore, in this application, the GSG pad (i.e., the first pad) is used as the signal input and cooperates with the internal self-biased inverter unit to ensure that the signal integrity can still be maintained when entering the high frequency band, so that the voltage applied to the device under test (such as the gate oxide capacitor) is close to the ideal square wave shape. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a circuit diagram of a high-frequency reliability test circuit provided in an embodiment of this application.

[0023] Figure 2 Another circuit diagram of the high-frequency reliability test circuit provided in the embodiments of this application.

[0024] Figure 3 for Figure 2 A schematic diagram of the simulation waveform of the high-frequency reliability test circuit.

[0025] Figure 4 This is a schematic diagram of the architecture of a semiconductor reliability testing device provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] TDDB (Time Dependent Dielectric Breakdown) refers to the gradual increase in leakage current under bias conditions, leading to oxide layer breakdown and loss of insulation function. Currently, major wafer foundries primarily conduct DC stress tests on gate oxide TDDB reliability. Industry research has explored AC TDDB, showing that device lifetime under AC TDDB is significantly longer than under DC TDDB. However, current research and foundry testing typically employs DC test architectures for AC TDDB, limiting test frequencies to below 1MHz.

[0028] Further research by the researchers revealed that the reason why high-frequency TDDB testing cannot be performed using a conventional DC test architecture is that square wave signals have infinite harmonics. To generate and transmit a 1GHz high-frequency square wave externally via cable, its higher harmonics (e.g., the 20th harmonic, i.e., 20GHz) also need to be able to be transmitted and amplified normally. Otherwise, the waveform will produce large ripples, causing significant interference to the test results. Therefore, wafer foundries cannot provide high-frequency TDDB lifetime data, resulting in limitations on the operating voltage of devices.

[0029] In view of this, embodiments of this application provide a high-frequency reliability testing circuit (hereinafter referred to as the test circuit) and a semiconductor reliability testing apparatus. By integrating a circuit design that converts a high-frequency sine wave signal into a square wave signal and applying it to a reliability testing scenario, high-frequency square wave stress can be directly generated on-chip. It should be noted that "on-chip" in this document refers to integration within or on top of a semiconductor chip.

[0030] refer to Figures 1 to 4 The test circuit 100 of this application embodiment includes: a signal input terminal 110, a DC blocking capacitor 120, a self-biased inverter unit 130, a buffer unit 140, and a signal output terminal 150. The signal input terminal 110 is used to receive a high-frequency sine wave signal. One end of the DC blocking capacitor 120 is coupled to the signal input terminal 110. The input terminal of the self-biased inverter unit 130 is coupled to the other end of the DC blocking capacitor 120, used to convert the high-frequency sine wave signal into a quasi-square wave signal. The input terminal of the buffer unit 140 is coupled to the output terminal of the self-biased inverter unit 130, used to shape and amplify the quasi-square wave signal to generate a shaped square wave signal. The signal output terminal 150 is coupled to the output terminal of the buffer unit 140, used to output the shaped square wave signal. In actual testing, the signal output terminal 150 is coupled to the device under test 200, used to apply the shaped square wave signal as AC electrical stress to the device under test 200.

[0031] Through the circuit design described above, this application can receive external high-frequency sine wave signals at the input terminal and convert them into square waves internally within the chip. Based on this test circuit, only conventional signal sources and DC sources are needed to achieve square wave signals with near-ideal shapes above 100MHz, and the square wave swing can be arbitrarily adjusted according to the DC power supply settings to realize the testing and modeling of high-frequency TDDB.

[0032] The test circuit 100 of this application will be described in further detail below.

[0033] refer to Figure 1 In this embodiment of the application, on the signal input side, the test circuit 100 is provided with a signal input terminal 110 for receiving a high-frequency sine wave signal provided by an external signal source.

[0034] In this embodiment of the application, the input signal is a small sinusoidal signal with a frequency in the range of 100MHz to 2GHz, in order to meet the requirements of high-frequency testing.

[0035] In actual chip layout design, the signal input terminal includes a first pad 111. Exemplarily, the first pad 111 can be a ground-signal-ground (GSG) pad with two ground terminals and one signal terminal. The signal terminal is used to receive a high-frequency sinusoidal signal.

[0036] In high-frequency environments above 100MHz, high-frequency signals entering ordinary DC pads via RF probes are prone to severe signal reflection and loss due to parasitic inductance, parasitic capacitance, and impedance mismatch. In this embodiment, the GSG pad, as a coplanar waveguide structure suitable for high-frequency signals, can cooperate with external high-frequency RF probes to provide shielding, reduce parasitic inductance, and achieve good impedance matching. Therefore, the use of GSG pads in this application reduces reflection and loss when high-frequency signals are input, ensuring the integrity of the high-frequency signal entering the chip.

[0037] In this embodiment, the signal input terminal 110 is coupled to one end of the DC blocking capacitor 120. The DC blocking capacitor 120 is used to transmit externally input AC signals and prevents the DC bias of subsequent circuits from being fed back to the external signal source. The high-frequency sine wave signal is transmitted to the self-biased inverter unit 130 after passing through the DC blocking capacitor 120.

[0038] In this embodiment, the input terminal of the self-biased inverter unit 130 is coupled to the other end of the DC blocking capacitor 120. Specifically, the self-biased inverter unit 130 may include a first inverter 131 and a first resistor 132. The input terminal of the first inverter 131 is also the input terminal of the self-biased inverter unit 130, and the output terminal of the first inverter 131 outputs a signal to the subsequent circuit. The first resistor 132 is coupled to both the input terminal and the output terminal of the first inverter 131. Through the coordinated operation of the DC blocking capacitor 120 and the self-biased inverter unit 130, the input high-frequency sine wave signal (small signal) can be amplified into a quasi-square wave signal close to the power supply voltage. In some embodiments, the capacitance value of the DC blocking capacitor 120 can be set to 50pF to 200pF, and the resistance value of the first resistor 132 can be 100kΩ to 500kΩ to achieve good biasing and preliminary shaping effects.

[0039] Since the waveform edges and driving capability of the quasi-square wave signal may not be sufficient for direct use in highly reliable testing, in this embodiment, the output of the bias inverter unit 130 is coupled to the input of the buffer unit 140. The buffer unit 140 is used to shape and amplify the quasi-square wave signal output from the previous stage to generate a shaped square wave signal. The buffer unit 140 includes at least two cascaded buffers, with the output of the bias inverter unit 130 coupled to the input of the first-stage buffer, the output of the first-stage buffer coupled to the input of the second-stage buffer, and the output of the second-stage buffer coupled to the signal output terminal 150. In a specific embodiment, the above-mentioned at least two cascaded buffers may include a second inverter 141 and a third inverter 142 connected in series. Correspondingly, the input terminal of the second inverter 141 is coupled to the output terminal of the self-biased inverter unit 130, and the output terminal of the second inverter 141 is coupled to the input terminal of the third inverter 142. The output terminal of the third inverter 142 outputs a signal to the subsequent circuit. The quasi-square wave signal, after being driven and amplified by the aforementioned buffer, will be further shaped into a shaped square wave signal. In some embodiments, the aspect ratio of the internal transistors (MOS transistors) of the first inverter 131 in the self-biased inverter unit 130, the second inverter 141 in the buffer unit 140, and the third inverter 142 can be set to 64μm / 30nm to ensure current driving capability. Further, in some embodiments, the ratio of the internal transistor area (i.e., W×L) of the buffer unit output stage to the area of ​​the subsequent device under test can be configured to 3:1 to avoid distortion of the output waveform of the last stage due to insufficient driving capability.

[0040] In this embodiment, the shaped square wave signal output by the buffer unit 140 is transmitted to the signal output terminal 150. That is, the signal output terminal 150 is coupled to the output terminal of the buffer unit 140. In practical applications, the signal output terminal 150 is coupled to the device under test 200. In this embodiment, the device under test 200 is a gate oxide capacitor to be tested for time breakdown (TDDB). In this way, the test circuit 100 can directly apply the shaped square wave signal generated inside the circuit as AC electrical stress to the device under test 200.

[0041] In some embodiments, the test circuit 100 may further include a signal detection terminal 160. The signal detection terminal 160 is coupled to the signal output terminal 150 and an external test device (such as an oscilloscope) to monitor the waveform of the shaped square wave signal via the external test device. In this embodiment, the signal detection terminal 160 is similar to the signal input terminal 110, and includes a second pad 161. Exemplarily, the second pad 161 may be a ground-signal-ground (GSG) pad having two ground terminals and one signal terminal.

[0042] In some embodiments, the test circuit 100 may further include a DC power supply terminal 170. The active devices within the test circuit 100 (the self-biased inverter unit 130 and the buffer unit 140) can all be coupled to the DC power supply terminal 170 to obtain power. It is worth noting that the amplitude (i.e., the full-swing size) of the shaped square wave signal applied to the device under test 200 is determined based on the voltage of the DC power supply terminal 170. This design ensures that the square wave amplitude depends entirely on the voltage value of the external DC power supply, avoiding the need for large-area decoupling capacitors on the chip.

[0043] In addition, it should be noted that, such as Figure 1 As shown, the grounding terminals of all devices in the test circuit 100 (including each pad, the self-biased inverter unit 130, and the buffer unit 140, etc.) are all coupled to the common ground line 180, which is used to provide a reference ground potential for the entire circuit.

[0044] Figure 2 and Figure 3 The following are specific circuit diagrams and corresponding waveform diagrams of the high-frequency reliability test circuit provided in the embodiments of this application. (Reference) Figure 2 and Figure 3 As shown, the signal transmission process at each node within the circuit is clearly visible. The externally input high-frequency sine wave signal arrives at node in on the signal input side, where the waveform is a standard sine wave. After passing through the DC blocking capacitor 120, the high-frequency sine wave signal reaches node a, where the AC component of the signal is transmitted and superimposed with the DC bias voltage of the internal self-biased inverter unit. Subsequently, the signal is amplified by the high gain of the self-biased inverter unit 130 (i.e., the first inverter 131), and is initially shaped into a quasi-square wave signal with a certain swing at node b. Then, this quasi-square wave signal passes through the cascaded inverters in the buffer unit 140 (such as...). Figure 2 The second inverter 141, the third inverter 142, and the fourth inverter 143 shown in series are driven and shaped in stages. Figure 3 As can be seen from the waveform, the signal edges become steeper at nodes c and d. An ideal shaped square wave signal is generated at the output of buffer unit 140, i.e., node out.

[0045] refer to Figure 4 and combined Figure 1As shown in the figure, this application embodiment also provides a semiconductor reliability testing apparatus 1000. The semiconductor reliability testing apparatus 1000 (hereinafter referred to as the testing apparatus) may include a signal source 300, a DC power supply 400, and a semiconductor chip under test 10. The signal source 300 is used to generate and output a high-frequency sine wave signal. The DC power supply 400 is used to provide a stable DC voltage. The semiconductor chip under test 10 includes the aforementioned high-frequency reliability testing circuit 100 and a device under test 200. The signal source 300 is coupled to the signal input terminal 110 of the high-frequency reliability testing circuit 100, the DC power supply 400 is coupled to the DC power supply terminal 170 of the high-frequency reliability testing circuit 100, and the device under test 200 inside the semiconductor chip under test 10 is coupled to the signal output terminal 150 of the high-frequency reliability testing circuit 100. It should be noted that the specific structure and function of the high-frequency reliability testing circuit 100 are detailed in the above description and will not be repeated here.

[0046] Throughout the entire testing workflow, only a standard signal source 300 and a DC power supply 400 are needed to configure the high-frequency test. During testing, a high-frequency sine wave signal is input to the signal input terminal 110 of the test circuit 100 via the signal source 300, and power is supplied to the DC power supply terminal 170 of the chip via the DC power supply 400. At this time, the internal test circuit 100 of the chip starts working, directly amplifying and shaping the input high-frequency sine wave signal into a full-swing shaped square wave signal on the chip, and applying it as AC electrical stress to the device under test 200. Throughout the testing process, the square wave amplitude applied to the device under test 200 can be arbitrarily adjusted by changing the setting of the DC power supply 400 according to specific testing requirements. In addition, an oscilloscope can be connected to the signal detection terminal 160 to observe the square wave waveform in real time.

[0047] In this embodiment, the test apparatus 1000 employing the aforementioned test circuit 100 effectively solves the bandwidth bottleneck problem in the prior art when transmitting high-frequency square waves via external cables. Verification based on actual process nodes shows that the test circuit 100 exhibits excellent high-frequency performance under different semiconductor manufacturing processes. For example, under a 40nm node process, the test circuit 100 can achieve high-frequency square wave stress output above 800MHz; under an advanced 28nm node process, the test circuit 100 can achieve high-frequency square wave output above 1GHz.

[0048] Therefore, this application can reduce the dependence on high-frequency pulse generators by using conventional signal sources and DC power supplies, and can achieve high-frequency square wave signals with a near-ideal shape, such as those above 100MHz or even up to 1GHz. Furthermore, the amplitude of the square wave can be arbitrarily adjusted according to the power supply settings, thereby enabling the testing and modeling of high-frequency TDDB and providing data support for the reliability evaluation of devices in high-frequency applications.

[0049] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0050] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A high frequency reliability test circuit, characterized by, include: The signal input terminal is used to receive high-frequency sine wave signals; A DC blocking capacitor, one end of which is coupled to the signal input terminal; The self-biased inverter unit, whose input terminal is coupled to the other end of the DC blocking capacitor, is used to convert the high-frequency sine wave signal into a quasi-square wave signal. A buffer unit, the input of which is coupled to the output of the self-biased inverter unit, is used to shape and amplify the quasi-square wave signal to generate a shaped square wave signal. The signal output terminal is coupled to the output terminal of the buffer unit and is used to output the shaped square wave signal; The signal output terminal is coupled to the device under test (DUT) to apply the shaped square wave signal as AC electrical stress to the DUT.

2. The high frequency reliability test circuit of claim 1, wherein, The self-biased inverter unit includes: a first inverter and a first resistor; The input terminal of the first inverter is coupled to the other end of the DC blocking capacitor, and the output terminal of the first inverter is coupled to the buffer unit. The first resistor is coupled to the input terminal and the output terminal of the first inverter, respectively, to provide a bias voltage.

3. The high frequency reliability test circuit of claim 2, wherein, The capacitance of the DC blocking capacitor is 50pF to 200pF, and the resistance of the first resistor is 100kΩ to 500kΩ.

4. The high frequency reliability test circuit of claim 1, wherein, The buffer unit includes at least two cascaded buffers; The output of the self-biased inverter unit is coupled to the input of the first-stage buffer, the output of the first-stage buffer is coupled to the input of the second-stage buffer, and the output of the second-stage buffer is coupled to the signal output.

5. The high-frequency reliability test circuit as described in claim 4, characterized in that, The buffer includes an inverter.

6. The high-frequency reliability test circuit as described in claim 1, characterized in that, The signal input terminal includes a first pad, which has two ground terminals and one signal terminal, and the signal terminal is used to receive high-frequency sine wave signals.

7. The high-frequency reliability test circuit as described in claim 1, characterized in that, Also includes: The signal detection terminal is used to couple the signal output terminal to an external test device, so as to monitor the waveform of the shaped square wave signal through the external test device.

8. The high-frequency reliability test circuit as described in claim 1, characterized in that, Also includes: The DC power supply terminal is coupled to the self-biased inverter unit and the buffer unit, and the amplitude of the shaped square wave signal is determined according to the voltage of the DC power supply terminal.

9. The high-frequency reliability test circuit as described in claim 1, characterized in that, The device under test is a gate oxide capacitor.

10. A semiconductor reliability testing apparatus, characterized in that, include: A signal source used to generate high-frequency sine wave signals; A DC power supply is used to provide DC voltage. The semiconductor chip under test includes a high-frequency reliability test circuit as described in any one of claims 1 to 9 and a device under test. The signal source is coupled to the signal input terminal of the high-frequency reliability test circuit, the DC power supply is coupled to the DC power supply terminal of the high-frequency reliability test circuit, and the device under test is coupled to the signal output terminal of the high-frequency reliability test circuit.

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