A method for server remote hardware debugging analysis

Abstract

This invention discloses a method for remote hardware debugging and analysis of a server, relating to the field of server hardware management. The method includes: connecting the hardware signal to be debugged and analyzed in the server to a CPLD (Content Processing LD) and mapping it to a hardware status register array; establishing a communication connection between the BMC (Browser Control Center) and the CPLD via a first communication bus and sending a hardware status query configuration command to the CPLD; obtaining the hardware signal level status stored in the corresponding hardware status register from the CPLD via the first communication bus according to the query mode; and presenting the obtained level status through a web interface for remote debugging and analysis. This application solves the problems of existing server hardware signal debugging, such as the inability to remotely implement the process and the difficulty in efficiently acquiring multiple signals in batches and performing long-term continuous analysis. It achieves the effects of remote debugging and monitoring of server hardware signals, efficient batch acquisition of multiple hardware signals, and support for long-term continuous sampling and backtracking analysis.

Description

Technical Field

[0001] This application relates to the field of server hardware management, and in particular to a method for remote hardware debugging and analysis of servers. Background Technology

[0002] Real-time monitoring and troubleshooting of server hardware operating status are crucial for ensuring stable data center operations and reducing downtime, directly impacting the availability and reliability of enterprise-level services. Currently, the industry commonly employs on-site hardware probe measurements, direct data acquisition via onboard logic analyzers, or direct connection to the server motherboard using dedicated debugging cables to obtain changes in the levels of hardware control and status indicators. Maintenance personnel then perform signal analysis and fault location on-site in the data center. These methods require on-site operation by maintenance personnel, rely on dedicated debugging equipment and cables, and cannot achieve remote access or batch monitoring. Furthermore, the signal acquisition process can easily interfere with normal server operations, and it is difficult to perform long-term continuous sampling and retrospective analysis of multiple hardware signals.

[0003] Currently, server hardware signal debugging and status monitoring suffer from technical problems such as the inability to achieve remote operation and the difficulty in efficiently acquiring multiple signals in batches and performing long-term continuous analysis. Summary of the Invention

[0004] This application provides a method for remote hardware debugging and analysis of servers. It employs a method where the server's hardware signals to be debugged are connected to a CPLD (Content Controller Layer), which maps them to a hardware status register array according to their functions. The BMC (Browser Control Center) establishes a connection with the CPLD via a first communication bus, sends configuration commands to set the query mode and target register number, and, based on the configured query mode, obtains the level status data of the corresponding hardware status register from the CPLD. The BMC then visualizes the obtained data through a web interface for remote debugging and analysis of server hardware. This method solves the technical problems of existing server hardware signal debugging and status monitoring, such as the inability to remotely implement the process, the difficulty in efficiently acquiring multiple signals in batches, and the challenge of long-term continuous analysis. It achieves the technical effects of remote debugging and monitoring of server hardware signals, efficient batch acquisition of multiple hardware signals, and support for long-term continuous sampling and retrospective analysis.

[0005] This application provides a method for remote hardware debugging and analysis of a server, comprising: connecting the hardware signals to be debugged and analyzed in the server to a CPLD, wherein the CPLD classifies and maps the connected hardware signals to a preset array of hardware status registers; a baseboard management controller (BMC) integrated on the server motherboard establishes a communication connection with the CPLD through a first communication bus and sends a hardware status query configuration command to the CPLD, wherein the hardware status query configuration command is used to configure a query mode and the number of the hardware status register to be queried; the baseboard management controller (BMC) obtains the hardware signal level status stored in the corresponding hardware status register from the CPLD through the first communication bus according to the query mode in the hardware status query configuration command; and the baseboard management controller (BMC) presents the obtained hardware signal level status through a web interface for remote debugging and analysis.

[0006] In a possible implementation, the following processing is performed: the hardware status query configuration command includes a query mode setting command, a hardware register number setting command, and a continuous query mode setting command; the query mode setting command is used to set the current query mode to real-time mode or continuous mode; the hardware register number setting command is used to set the hardware status register number to be queried; the continuous query mode setting command is used to set the trigger condition and sampling frequency in continuous mode.

[0007] In a possible implementation, the following processing is performed: the query mode includes a real-time mode; wherein, when configured in the real-time mode, the baseboard management controller (BMC) sends a hardware status query configuration command, and the CPLD responds to the hardware status query configuration command by returning the hardware signal level status stored in the hardware status register at the current time.

[0008] In a possible implementation, the following processing is performed: the query mode includes a continuous mode; wherein, when configured in the continuous mode, the CPLD continuously samples the queried hardware status register according to a preset triggering method and sampling frequency, stores the sampled data in an internal buffer, and is acquired in batches by the baseboard management controller (BMC).

[0009] In a possible implementation, after being configured to the continuous mode, the following processing is performed: the CPLD receives and parses the hardware status query configuration command, initializes the sampling parameters according to the configured trigger conditions and sampling frequency; by detecting the level change of the trigger signal, continuous sampling is started when the trigger signal meets the configured trigger conditions; the hardware status register with the specified number is periodically sampled according to the sampling frequency, and the hardware signal level status of each sample is written into the BRAM as sampling data in sequence; when the number of sampling data written into the BRAM reaches a constant threshold, continuous sampling is stopped and the sampling status is updated to sampling complete.

[0010] In a possible implementation, the following processing is performed: the triggering condition includes a triggering mode and a triggering signal source, wherein the triggering mode is at least one of rising edge triggering, falling edge triggering, or double edge triggering, and the triggering signal source is fixed as the hardware signal corresponding to a preset bit in the queried hardware status register.

[0011] In a possible implementation, after continuous sampling is initiated, the following process is performed: a constant threshold matching the capacity of the BRAM is preset in the CPLD logic; before performing polling sampling, the BRAM counter is initialized to 0, where the BRAM is a dedicated buffer in continuous mode, and the counter is incremented by 1 after each set of sampled data is written to the BRAM; when the value of the BRAM counter meets the constant threshold, the CPLD stops sampling and updates the sampling status to sampling complete.

[0012] In a possible implementation, the following process is performed: the substrate management controller (BMC) reads the sampled data in the BRAM in batches, and after reading is completed, sends a reset command to the CPLD, wherein the reset command is used to clear the BRAM counter and restore the state to idle.

[0013] In a possible implementation, the following processing is performed: the hardware signals include at least hardware control signals and hardware status indication signals; the CPLD maps the accessed hardware signals into a preset number of hardware status register arrays according to their functions, with each hardware status register being 8 bits and used to store the real-time level status of 8 hardware signals.

[0014] In a possible implementation, the following processing is performed: the first communication bus is an I2C bus, the baseboard management controller (BMC) and the CPLD interact through I2C custom commands, and the CPLD identifies the command type and configuration parameters by parsing preset bits in the command bytes.

[0015] This application proposes a method for remote hardware debugging and analysis of a server. First, the hardware signals to be debugged and analyzed in the server are connected to a CPLD (Content Processing Logic Controller). The CPLD categorizes and maps the connected hardware signals to a preset array of hardware status registers. Next, a Baseboard Management Controller (BMC) integrated into the server motherboard establishes a communication connection with the CPLD via a first communication bus and sends a hardware status query configuration command to the CPLD. This command configures the query mode and the number of the hardware status register to be queried. Then, the BMC, according to the query mode in the hardware status query configuration command, retrieves the hardware signal level status stored in the corresponding hardware status register from the CPLD via the first communication bus. Finally, the BMC presents the retrieved hardware signal level status through a web interface for remote debugging and analysis. Through this process, the method proposed in this application achieves the technical effects of remote debugging and monitoring of server hardware signals, efficient batch acquisition of multiple hardware signals, and support for long-term continuous sampling and retrospective analysis. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention will be briefly described below. Flowcharts are used in this application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0017] Figure 1 This is a flowchart illustrating a method for remote hardware debugging and analysis of a server, as provided in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram illustrating the principle of a method for remote hardware debugging and analysis of a server, as provided in an embodiment of this application.

[0019] Figure 3 This is a flowchart illustrating the process of a server remote hardware debugging and analysis method provided in this application, in which the CPLD receives a hardware status query command and then feeds back the hardware status to the BMC.

[0020] Figure 4 This is a schematic diagram of the query process for a continuous mode in a method for remote hardware debugging and analysis of a server provided in an embodiment of this application.

[0021] Figure 5 This is a flowchart illustrating the process of continuous sampling of hardware signals by the CPLD after receiving a configuration command in a method for remote hardware debugging and analysis of a server provided in this application embodiment. Detailed Implementation

[0022] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0023] This application provides a method for remote hardware debugging and analysis of a server. The method uses a complex programmable logic device (CPLD) to acquire server hardware signals and, in conjunction with a baseboard management controller (BMC), enables remote real-time querying and continuous sampling analysis. Figure 1 and Figure 2 As shown, the method includes: Step S100: Connect the hardware signals to be debugged and analyzed in the server to the CPLD. The CPLD classifies and maps the connected hardware signals to a preset array of hardware status registers. The hardware signals include at least hardware control signals and hardware status indication signals. The CPLD classifies and maps the connected hardware signals according to their functions to a preset number of hardware status register arrays. Each hardware status register is 8 bits and is used to store the real-time level status of 8 hardware signals.

[0024] Specifically, during the server motherboard hardware design phase, a circuit board routing process is used to connect the CPU's control signals, peripheral interface status indicator signals, power control signals, power normal signals, and other debugging hardware signals to the CPLD's general-purpose input / output pins via copper foil traces on the circuit board. These CPLD general-purpose input / output pins are configured as input ports, preventing any level interference to the connected hardware signals. Multiple hardware status registers are pre-configured within the CPLD, for example, eight registers, each with an 8-bit width, forming a hardware status register array. All connected hardware signals are categorized according to their function: power, clock, control, and status indicator. Each group of eight signals is mapped sequentially to a hardware status register. Each bit in the register corresponds to the real-time high or low level state of one hardware signal. This register array can store the level states of up to 64 hardware signals.

[0025] In step S200, the Baseboard Management Controller (BMC) integrated into the server motherboard establishes a communication connection with the CPLD via the first communication bus and sends a hardware status query configuration command to the CPLD. This hardware status query configuration command is used to configure the query mode and the hardware status register number to be queried. The hardware status query configuration command includes a query mode setting command, a hardware register number setting command, and a continuous query mode setting command. The query mode setting command is used to set the current query mode to real-time mode or continuous mode. The hardware register number setting command is used to set the hardware status register number to be queried. The continuous query mode setting command is used to set the trigger conditions and sampling frequency in continuous mode. The first communication bus is an I2C bus. The Baseboard Management Controller (BMC) and the CPLD interact via I2C custom commands. The CPLD identifies the command type and configuration parameters by parsing preset bits in the command bytes.

[0026] Specifically, the I2C interface of the BMC (Block Controller) and the I2C interface of the CPLD (CPLD) are connected via circuit board wiring to establish a stable serial communication link, and a custom protocol is used for command interaction. The BMC generates an 8-bit binary format hardware status query configuration command according to the preset custom communication protocol and sends it to the CPLD via I2C. The CPLD distinguishes command types and parameters through the combination of high and low bits in the command byte. Three types of commands are defined: In the query mode setting command, bit 0 distinguishes between real-time and continuous modes (bit 0 = 0 for real-time, bit 0 = 1 for continuous mode). Bit 1 is the continuous mode enable bit (0 for disabling continuous mode, 1 for enabling continuous mode). In the hardware register number setting command, bits 0, 1, and 3 specify the array number of the hardware status register to be queried (registers 0 to 7 can be selected). In the continuous query mode setting command, bits 0 and 1 set the trigger mode (01 for rising edge trigger, 10 for falling edge trigger, 11 for double-edge trigger). Bit 2 sets the sampling frequency (0 for 100kHz, 1 for 1MHz). After receiving the 8-bit command, the CPLD reads the level values ​​at the preset positions bit by bit, identifies the command type based on the value combination, extracts the corresponding configuration parameters, and completes the configuration of its own operating mode.

[0027] CPLD sets independent default parameters for each configuration command. When the command value sent by BMC exceeds the preset legal range, CPLD automatically restores the corresponding configuration register to its preset default value to ensure stable system operation.

[0028] In one possible implementation, step S200 further includes step S210, wherein the query mode includes a real-time mode; wherein, when configured in the real-time mode, the baseboard management controller (BMC) sends a hardware status query configuration command, and the CPLD responds to the hardware status query configuration command by returning the hardware signal level status stored in the hardware status register queried at the current time.

[0029] Specifically, the BMC sends a query mode setting command to the CPLD, configuring bit 0 to 0 and bit 1 to 0 to enable real-time query mode. Simultaneously, it sends a hardware register number setting command, specifying the hardware status register number to be queried. Upon receiving the above configuration command, the CPLD locks the corresponding hardware status register, reads the current level status of the eight hardware signals stored in that register in real time, encapsulates the level status data into integrated circuit bus response data, and directly sends it back to the BMC without data buffering or continuous acquisition.

[0030] In one possible implementation, step S200 further includes step S220, wherein the query mode includes a continuous mode; wherein, when configured in the continuous mode, the CPLD continuously samples the queried hardware status register according to a preset triggering method and sampling frequency, stores the sampled data in an internal buffer, and is batch-acquired by the baseboard management controller (BMC).

[0031] Specifically, the BMC sends a query mode setting command, configuring command bit 0 to 1 and bit 1 to 1, thus enabling continuous sampling mode. Simultaneously, it sends a hardware register number setting command to specify the target register and a continuous query mode setting command to configure the trigger method and sampling frequency. After completing all configurations, the BMC sends a start sampling command to the CPLD, triggering the CPLD to enter the sampling preparation state. Based on the configuration parameters, the CPLD waits for the trigger conditions to be met and then periodically samples the target hardware status register at the set sampling frequency. Each sampled level data is sequentially stored in the internal BRAM buffer. Once the buffer is full or sampling is complete, the CPLD waits for the BMC to initiate a batch read request.

[0032] In step S300, the baseboard management controller (BMC) obtains the hardware signal level status stored in the corresponding hardware status register from the CPLD via the first communication bus according to the query mode in the hardware status query configuration command.

[0033] Specifically, such as Figure 3As shown, the BMC sends a hardware status query configuration command to the CPLD via the I2C bus according to the configured real-time mode or continuous mode. In real-time mode, the CPLD writes the value of the hardware status register corresponding to the target number into the hardware query register, encapsulates the 8-bit data of the hardware query register into integrated circuit bus response data, and directly sends it back to the BMC without data buffering or continuous acquisition. In continuous mode, the CPLD reads the sampled data from the BRAM sequentially according to the access address, writes the sampled data into the hardware query register, and sends it to the BMC as response data. After each set of sampled data is sent, the BRAM counter is decremented by 1 and the access address is incremented by 1. When the BRAM counter reaches 0, the CPLD sets the BRAM status to empty and waits for the next sampling or query operation. The BMC completes all data reception and temporary storage.

[0034] like Figures 4-5 As shown, in one possible implementation, after being configured to the continuous mode, step S300 further includes step S310, whereby the CPLD receives and parses the hardware status query configuration command, and initializes the sampling parameters according to the configured trigger conditions and sampling frequency. Specifically, the CPLD fully receives the query mode setting command, hardware register number setting command, and continuous query mode setting command sent by the BMC, and parses the configuration values ​​in the commands bit by bit. The target hardware status register number, trigger mode, sampling frequency, and continuous sampling enable state are extracted as sampling control parameters, the internal sampling counter is cleared, and the BRAM read / write address pointer is reset, completing the parameter initialization operation before sampling.

[0035] Step S320: By detecting the level change of the trigger signal, continuous sampling is initiated when the trigger signal meets the configured trigger conditions. The trigger conditions include a trigger mode and a trigger signal source. The trigger mode is at least one of rising edge triggering, falling edge triggering, or double-edge triggering. The trigger signal source is fixed as the hardware signal corresponding to a preset bit in the queried hardware status register. Specifically, the CPLD continuously detects the hardware signal level corresponding to bit 0 in the target hardware status register; this signal is a fixed trigger signal source. Before sampling begins, the CPLD first saves the value of the hardware status register to the previous value register. During sampling, the value of the hardware status register is read in real time and added to the current value register, comparing the level change of bit 0 of the current value with that of bit 0 of the previous value. According to the configured trigger mode, when a level change from low to high is detected and configured as rising edge triggering, or a level change from high to low is detected and configured as falling edge triggering, or a level transition is detected and configured as double-edge triggering, the BRAM access address is immediately set to 0, the continuous sampling process is initiated, and data acquisition begins.

[0036] Step S330: According to the sampling frequency, the hardware status register with the specified number is periodically sampled, and the hardware signal level status of each sample is written into the BRAM as sampled data. Specifically, the CPLD generates an internal sampling clock corresponding to the configured sampling frequency, clears the sampling timer count value to zero, and increments the sampling timer count value by 1 for each sampling clock cycle. When the sampling timer count value reaches the preset sampling cycle value, 8 bits of level data in the target hardware status register are read once, and this group of data is treated as a single sample data and stored sequentially into the corresponding storage unit of the BRAM according to the writing order. After storing each group of data, the internal sampling counter value is incremented by 1, the BRAM access address is incremented by 1, and the sampling timer count value is cleared, and the next round of counting begins.

[0037] Step S340: When the amount of sampled data written to the BRAM reaches a constant threshold, continuous sampling stops and the sampling status is updated to sampling complete. Specifically, in the CPLD's logic program, a constant threshold matching the BRAM storage capacity is preset. This threshold is determined based on the BRAM capacity corresponding to the CPLD model used. During the sampling process, the sampling counter value is compared with the constant threshold in real time. When the sampling counter value is equal to the constant threshold, the CPLD immediately stops generating the sampling clock, terminates the continuous sampling operation, and updates the value of the internal sampling status register to the sampling complete flag.

[0038] In one possible implementation, after continuous sampling is initiated, step S340 further includes step S341, where a constant threshold matching the BRAM capacity is preset in the CPLD logic. Before executing polling sampling, the BRAM counter is initialized to 0. The BRAM is a dedicated buffer in continuous mode, and the counter increments by 1 after each set of sampled data is written to the BRAM. Specifically, the CPLD internally uses a threshold judgment program written in hardware logic language to calculate the number of storable sampled data sets based on the total number of storage bytes in the device's built-in BRAM, and sets this number as a constant threshold. Before each continuous sampling is initiated, the sampling counter corresponding to the BRAM is reset to 0. After each 8-bit sampled data set is written, the sampling counter automatically increments by 1, recording the number of stored sampled data sets in real time.

[0039] In step S342, when the value of the BRAM counter meets the constant threshold, the CPLD stops sampling and updates the sampling status to "sampling complete". Specifically, the CPLD monitors the value of the sampling counter in real time. When the value reaches the preset constant threshold, it immediately cuts off the sampling trigger path and the sampling clock, and stops all sampling-related operations. At the same time, it modifies the status bit of the internal sampling status register to "sampling complete", modifies the BRAM status bit to "storage full", sets the BRAM access address to 0, and waits for the BMC to read data.

[0040] In one possible implementation, step S300 further includes step S350, whereby the substrate management controller (BMC) reads sampled data from the BRAM in batches, and after reading is completed, sends a reset command to the CPLD, wherein the reset command is used to clear the BRAM counter and restore its state to idle.

[0041] Specifically, the BMC sends hardware sampling status query commands to the CPLD via the I2C bus to poll for the sampling completion status. If the CPLD sampling is not finished, it continues to poll; if sampling is finished, it enters the batch data reading process. After obtaining the sampling completion and storage full status information, the BMC continuously sends hardware status query commands to read all sampled data in the BRAM in batches. During the reading process, for each set of sampled data returned by the CPLD, the BRAM counter is decremented by 1 and the access address is incremented by 1. When the BRAM counter reaches 0, the BRAM status is automatically set to empty. The BMC sends hardware sampling status commands to query the current BRAM status. If the BRAM is not empty, it continues reading; if the BRAM is empty, it is determined that the sampling data acquisition is complete. After the data reading is complete, the BMC sends an 8-bit reset instruction. Upon receiving the reset instruction, the CPLD clears the sampling counter to zero, resets the BRAM read / write pointer, and restores the sampling and storage status to the initial idle state, ready to execute the next sampling operation.

[0042] In step S400, the baseboard management controller (BMC) presents the acquired hardware signal level status through a web interface for remote debugging and analysis.

[0043] Specifically, the BMC converts the received real-time level data or continuous sampling data into text and graphic data that can be recognized by the webpage. The BMC's built-in web server generates a visual interface including drop-down selection boxes, a real-time value display area, and a continuous curve plotting area. Hardware engineers access the server webpage via a remote terminal, select the register number from the drop-down box, and the webpage displays the real-time signal level values ​​of the corresponding register's eight channels. Continuous sampling data is plotted as a continuous curve with time on the horizontal axis and level status on the vertical axis. By viewing the webpage data and curves, hardware engineers can remotely debug and analyze the server hardware.

[0044] This application embodiment employs a method where the server hardware signals to be debugged are connected to a CPLD, which maps them to a hardware status register array according to their functions. The BMC establishes a connection with the CPLD through a first communication bus, sends configuration commands to set the query mode and target register number, and the BMC obtains the level status data of the corresponding hardware status register from the CPLD according to the configured query mode. The BMC then visualizes the obtained data through a web interface for remote debugging and analysis of server hardware. This method solves the technical problems of existing server hardware signal debugging and status monitoring, such as the inability to remotely implement the process and the difficulty in efficiently acquiring multiple signals in batches and performing long-term continuous analysis. It achieves the technical effects of remote debugging and monitoring of server hardware signals, efficient batch acquisition of multiple hardware signals, and support for long-term continuous sampling and backtracking analysis.

[0045] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for remote hardware debugging and analysis of a server, characterized in that, The method includes: The hardware signals to be debugged and analyzed in the server are connected to the CPLD, wherein the CPLD classifies and maps the connected hardware signals to a preset hardware status register array. The Baseboard Management Controller (BMC) integrated on the server motherboard establishes a communication connection with the CPLD through the first communication bus and sends a hardware status query configuration command to the CPLD. The hardware status query configuration command is used to configure the query mode and the hardware status register number to be queried. The baseboard management controller (BMC) obtains the hardware signal level status stored in the corresponding hardware status register from the CPLD via the first communication bus according to the query mode in the hardware status query configuration command. The Baseboard Management Controller (BMC) presents the acquired hardware signal level status through a web interface for remote debugging and analysis.

2. The method for remote hardware debugging and analysis of a server as described in claim 1, characterized in that, include: The hardware status query configuration commands include query mode setting commands, hardware register number setting commands, and continuous query mode setting commands. The query mode setting command is used to set the current query mode to real-time mode or continuous mode. The hardware register number setting command is used to set the hardware status register number to be queried; The continuous query mode setting command is used to set the trigger conditions and sampling frequency in continuous mode.

3. The method for remote hardware debugging and analysis of a server as described in claim 2, characterized in that, The query mode includes a real-time mode; When configured in the real-time mode, the Baseboard Management Controller (BMC) sends a hardware status query configuration command, and the CPLD responds to the hardware status query configuration command by returning the hardware signal level status stored in the hardware status register at the current time.

4. The method for remote hardware debugging and analysis of a server as described in claim 2, characterized in that, The query mode includes a continuous mode; When configured in continuous mode, the CPLD continuously samples the queried hardware status register according to the preset triggering method and sampling frequency, stores the sampled data in the internal buffer, and is then acquired in batches by the baseboard management controller (BMC).

5. The method for remote hardware debugging and analysis of a server as described in claim 4, characterized in that, When configured as the continuous mode, the following are included: The CPLD receives and parses the hardware status query configuration command, and initializes the sampling parameters according to the configured trigger conditions and sampling frequency; By detecting changes in the level of the trigger signal, continuous sampling is initiated when the trigger signal meets the configured trigger conditions. According to the sampling frequency, the hardware status register with the specified number is periodically sampled, and the hardware signal level status of each sample is written into the BRAM as sample data in sequence. When the amount of sampled data written to BRAM reaches a constant threshold, continuous sampling stops and the sampling status is updated to sampling complete.

6. The method for remote hardware debugging and analysis of a server as described in claim 5, characterized in that, The triggering conditions include a triggering method and a triggering signal source. The triggering method is at least one of rising edge triggering, falling edge triggering, or double edge triggering. The triggering signal source is fixed to the hardware signal corresponding to a preset bit in the queried hardware status register.

7. The method for remote hardware debugging and analysis of a server as described in claim 6, characterized in that, After starting continuous sampling, the following is included: In the CPLD logic, a constant threshold matching the BRAM capacity is preset. Before performing polling sampling, the BRAM counter is initialized to 0. The BRAM is a dedicated buffer in continuous mode. The counter is incremented by 1 after each set of sampled data is written to the BRAM. When the value of the BRAM counter meets the constant threshold, the CPLD stops sampling and updates the sampling status to sampling complete.

8. The method for remote hardware debugging and analysis of a server as described in claim 7, characterized in that, The baseboard management controller (BMC) reads the sampled data in the BRAM in batches. After reading, it sends a reset command to the CPLD. The reset command is used to clear the BRAM counter and restore its state to idle.

9. The method for remote hardware debugging and analysis of a server as described in claim 1, characterized in that, The hardware signals include at least hardware control signals and hardware status indication signals; The CPLD maps the incoming hardware signals to a preset number of hardware status register arrays according to their functions. Each hardware status register is 8 bits and is used to store the real-time level status of 8 hardware signals.

10. The method for remote hardware debugging and analysis of a server as described in claim 1, characterized in that, The first communication bus is an I2C bus. The baseboard management controller (BMC) and the CPLD interact through I2C custom commands. The CPLD identifies the command type and configuration parameters by parsing preset bits in the command bytes.

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