A system-in-package method and packaged device

Abstract

This invention relates to the field of integrated circuit packaging technology, and in particular to a system-in-package (SIP) method and packaging device. The SIP method involves first preparing a substrate carrier plate that includes both a base carrier plate and a temporary bonding material layer; then, batch exposure, development, and etching of copper plates, filling circuit gaps with passivation dry film to form a motherboard, and cutting independent thick copper interconnect units adapted to the first type of chip to be packaged; subsequently, the chip and the unit are mounted on the carrier plate, and a second type of chip is soldered using metal bumps, making the unit a customized thick copper redistribution layer; finally, through molding, disassembling the carrier plate, creating passivation layer openings and metal circuit terminals, the SIP is completed. By reconfiguring the process route to achieve pre-integration of thick copper units, the thick copper electroplating process on the front side of the chip is avoided, eliminating wafer warpage problems from the source, significantly simplifying the packaging process, and completely eliminating interface risks caused by adhesive-mediated connections, thus combining high reliability with design flexibility.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit packaging technology, and in particular to a system-level packaging method and packaging device. Background Technology

[0002] As integrated circuit technology rapidly evolves towards high performance, high density, and miniaturization, system-in-package (SIP) has become one of the mainstream technologies for packaging high-end electronic devices due to its core advantages of heterogeneous integration of multiple chips, shortened interconnect paths, and improved system integration. In applications such as automotive power semiconductors, radio frequency communications, and high-performance computing, SIP packages often contain high-power chips, high-frequency chips, or functional chips requiring sophisticated power distribution networks, which place stringent requirements on the current carrying capacity, impedance characteristics, and signal integrity of the interconnect structure.

[0003] The redistribution layer (RDL), as a key interconnect structure in SIP packages connecting chip I / O ports to external solder balls, has its conductor thickness being a core factor determining the interconnect impedance. To meet low-impedance interconnect requirements, the industry typically uses thick copper RDL solutions, mainly categorized into the following three types: 1) Thick copper plating process on the front of the chip Thick copper RDLs are directly fabricated by sequentially performing photolithography and electroplating processes on the front side of the chip or wafer. However, this method has significant drawbacks: on the one hand, the thick copper electroplating process is time-consuming, with extremely long production cycles per batch, which significantly reduces production efficiency, and the high investment and maintenance costs of electroplating equipment further increase the overall packaging cost; on the other hand, the thick copper electroplating process is prone to generating large internal stresses, which can cause irreversible warping of the wafer, seriously affecting the yield of subsequent bonding, molding, and other processes.

[0004] 2) Adhesive-bonded copper foil etching process To circumvent the drawbacks of thick copper plating, some solutions use adhesives to temporarily attach thick copper foil to the chip or wafer surface, and then form a thick copper RDL through photolithography and etching. However, the adhesive layer introduced by this process brings new reliability risks: the thermal conductivity of the adhesive is only on the order of one-thousandth that of copper, which inevitably increases the thermal resistance of the interconnect structure significantly, causing the heat generated during chip operation to be unable to be dissipated quickly, leading to localized overheating; in addition, the thermal expansion coefficients of the adhesive, copper foil, and chip are quite different, which can easily lead to interface delamination under high and low temperature cycling conditions, causing interconnect failure.

[0005] 3) Integral thick copper frame packaging process The chip is directly mounted on a pre-fabricated monolithic thick copper lead frame, which enables low-impedance interconnection. This process has significant limitations: the frame is a uniform monolithic structure, making it impossible to customize for the varying impedance requirements of different chips within the SIP. For scenarios where only localized areas require low-impedance interconnection, this results in a significant waste of thick copper material, substantially increasing packaging costs. Furthermore, the fixed size and structure of the monolithic thick copper frame restricts the layout flexibility of the SIP package, making it difficult to adapt to the complex design requirements of multi-chip heterogeneous integration.

[0006] In summary, existing thick copper RDL fabrication solutions all suffer from technical drawbacks that are difficult to reconcile. They are either complex, costly, and pose reliability risks, or they fail to meet the flexibility and cost-effectiveness requirements of localized, customized low-impedance interconnects in SIP packaging. Therefore, it is imperative for technical personnel to address these issues. Summary of the Invention

[0007] The purpose of this invention is to provide a system-level packaging method that addresses the problems of complex electroplating of thick copper in existing designs, which can easily lead to wafer warping; the risk of thermal resistance and delamination when using adhesive to bond copper foil; and the waste of material and design limitations of the overall thick copper frame.

[0008] This invention relates to a system-level packaging method, comprising the following steps: S1. Prepare a support plate; the support plate includes a base support plate and a temporary bonding material layer covering the surface of the base support plate; S2. Provide a copper plate of preset thickness and perform exposure, development and etching processes on it in sequence to batch produce interconnect circuit patterns that match the pad layout and interconnection requirements of the first type of chip to be packaged. S3. Passivated dry film is used to fill the gaps in the interconnect circuit pattern and form an interconnect unit motherboard structure. Then, it is cut to obtain an independent thick copper interconnect unit that is adapted to the size and pad position of a single first type of chip to be packaged. S4. The first type of chip to be packaged and the independent thick copper interconnect unit obtained in step S3 are both mounted on the surface of the temporary bonding material layer. S5. Metal bumps are made on the surface of the second type of chip, and the metal bumps are soldered to the surface of the thick copper interconnect unit. The thick copper interconnect unit and the second type of chip with metal bumps are used as a whole as a customized thick copper redistribution layer for the first type of chip to be packaged. S6. The first type of chip to be packaged, the thick copper interconnect unit and the second type of chip on the carrier board are encapsulated in a plastic molding compound. The thick copper interconnect unit is completely embedded in the plastic mold or embedded in the passivation layer reserved in the plastic molding stage. S7. Remove the substrate carrier plate to fully expose the pads of the first type of chip to be packaged and the copper surface of the thick copper interconnect unit. S8. An overall passivation layer is formed on the surface of all components after the processing in step S7, and the overall passivation layer has openings for electrical connection at the corresponding positions of the first type of chip pad to be packaged and the corresponding positions of the copper surface of the thick copper interconnect unit. S9. Metal lines are fabricated on the surface of the overall passivation layer of the component to realize signal interconnection between the components, and metal terminals for subsequent soldering are simultaneously formed on the surface of the overall passivation layer of the component.

[0009] As a further improvement to the technical solution disclosed in this invention, in step S2, the thickness of the copper plate is determined according to the current carrying capacity and impedance requirements of the first type of chip to be packaged, and the pattern of the interconnect circuit is pre-customized based on the pad layout and interconnection requirements of the first type of chip to be packaged, and a thick copper electroplating process is not performed on the front side of the first type of chip to be packaged.

[0010] As a further improvement to the technical solution disclosed in this invention, the high-power chip in the first type of chip to be packaged is an integrated circuit chip with a single-chip power consumption ≥1W and a continuous current carrying capacity ≥1A; for the high-power chip, the copper plate thickness is 50-200μm; for the high-frequency chip with an operating frequency ≥1GHz, the copper plate thickness is 20-80μm, and the line width of the interconnect circuit pattern is 10-30μm and the line spacing is 8-25μm; the pad area of ​​the interconnect circuit pattern is a circular or square flared structure, and the size of the flared structure is 5-10μm larger than the pad of the first type of chip to be packaged, and the pad alignment deviation is ≤±3μm.

[0011] As a further improvement to the technical solution disclosed in this invention, the high-power chip includes a power management chip, a power drive chip, an RF power amplifier chip, and an automotive power semiconductor chip, and the thick copper interconnect unit is integrated only in the area where the high-power chip or the high-frequency chip is located.

[0012] As a further improvement to the technical solution disclosed in this invention, in step S6, when the thick copper interconnect unit is completely embedded inside the molding compound, the overall passivation layer thickness of the subsequently fabricated component is 5 to 15 μm; when the thick copper interconnect unit is embedded in the passivation layer reserved in the molding stage, its embedding depth is 1 / 3 to 1 / 2 of its own thickness, and the area exposed on the surface of the passivation layer reserved in the molding stage accounts for no less than 60%; the interconnection between the thick copper interconnect unit and the second type of chip has no adhesive layer.

[0013] As a further improvement to the technical solution disclosed in this invention, in step S3, the passivation dry film is a high-temperature resistant epoxy resin dry film, the curing temperature is 120-150℃, the curing time is 30-60min, and the difference between the thermal expansion coefficient of the cured dry film and the thermal expansion coefficient of the copper plate is ≤5ppm / ℃.

[0014] As a further improvement to the technical solution disclosed in this invention, in step S5, the metal bump is a tin-silver-copper alloy bump with a diameter of 50-100 μm and a height of 30-60 μm, and the welding process is reflow soldering.

[0015] As a further improvement to the technical solution disclosed in this invention, in step S8, the overall passivation layer of the component is a polyimide passivation material, formed by a coating process, with a coating thickness uniformity deviation of ≤±1μm, and the sidewall inclination angle of the opening of the overall passivation layer of the component is 45~60°.

[0016] As a further improvement to the technical solution disclosed in this invention, in step S9, the metal circuit is prepared by a sputtering-electroplating composite process, with a bottom layer of sputtered titanium-tungsten alloy barrier layer having a thickness of 0.5 to 1 μm, and an upper layer of electroplated copper circuit having a thickness of 5 to 15 μm.

[0017] Furthermore, the present invention also discloses a packaging device, which is prepared by the above-mentioned system-in-package method; the packaging device is adapted to wafer-level chip-scale packaging structure, wafer-level fan-out packaging structure and board-level fan-out packaging structure, and is also suitable for system-in-package scenarios that include high-power chips, high-frequency chips or fine power distribution networks.

[0018] In practical applications, the system-level packaging method disclosed in this invention can achieve at least the following beneficial technical effects, specifically: 1) By restructuring the process, a new technical logic has been established: prefabricating thick copper interconnect units and then integrating them into the chip. This involves transferring the forming process of the thick copper interconnect structure to the batch processing stage of an independent copper plate. In related steps, the entire copper plate undergoes uniform exposure, development, etching, and passivation dry film filling operations, enabling the batch fabrication of interconnect units for multiple chips in a single operation. This significantly reduces the overall process steps and production cycle. Furthermore, it completely avoids the thick copper electroplating operation on the front side of the chip, eliminating the internal stress accumulation caused by uneven copper ion deposition during the electroplating stage and preventing wafer warpage. 2) Abandoning adhesive-mediated indirect connection methods, a direct soldering interconnect system of metal bumps and thick copper units is constructed. In the corresponding process, the second type of chip is soldered to the thick copper interconnect unit through metal bumps, forming a metal-metal metallurgical interface. This effectively eliminates the thermal aging and shrinkage problems of organic adhesives under high and low temperature cycling conditions, and eliminates the risk of interface delamination. Furthermore, thanks to the adhesive-free direct interconnect structure, the heat generated by the chip during operation can be quickly conducted to the molding compound or external heat dissipation structure through the thick copper unit, thereby significantly improving the overall heat dissipation efficiency of the package. 3) The implementation of on-demand thick copper allocation means that the interconnect circuit patterns prepared in batches are cut into independent units that are adapted to a single Type I chip to be packaged. Integration is carried out only for chip areas with special impedance requirements such as high power and high frequency, rather than laying thick copper all over the entire packaging substrate. Essentially, the precise placement of thick copper material is achieved. In this way, not only is the material redundancy caused by the overall thick copper framework avoided, but also the modular unit structure adapts to the pad layout of different chips, which significantly improves the design flexibility of multi-chip heterogeneous integration. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the system-level encapsulation method disclosed in this invention.

[0021] Figure 2 This is a schematic diagram of the carrier board structure in the system-level packaging method disclosed in this invention.

[0022] Figure 3 This is a schematic diagram of the interconnect circuit pattern processing of the copper plate in the system-level packaging method disclosed in this invention.

[0023] Figure 4 This is a schematic diagram of the structure of the thick copper interconnect unit motherboard in the system-level packaging method disclosed in this invention.

[0024] Figure 5 This is a schematic diagram of the carrier board mounting of the first type of chip to be packaged and the thick copper interconnect unit in the system-level packaging method disclosed in this invention.

[0025] Figure 6 This is a schematic diagram illustrating the fabrication of the second type of chip metal bumps in the system-in-package method disclosed in this invention.

[0026] Figure 7This is a schematic diagram of the welding of the second type of chip and the thick copper interconnect unit in the system-in-package method disclosed in this invention.

[0027] Figure 8 This is a schematic diagram of the overall plastic encapsulation of the packaged components in the system-level packaging method disclosed in this invention.

[0028] Figure 9 This is a schematic diagram of the component structure after the substrate carrier plate is removed in the system-level packaging method disclosed in this invention.

[0029] Figure 10 This is a schematic diagram illustrating the fabrication of the overall passivation layer and electrical connection openings of the component in the system-in-package method disclosed in this invention.

[0030] Figure 11 This is a schematic diagram of the forming of metal interconnect lines and metal terminals in the system-in-package method disclosed in this invention.

[0031] 10-Carrier board; 101-Temporary bonding material layer; 102-Substrate carrier board; 20-First type of chip to be packaged; 30-Thick copper interconnect unit; 301-Copper plate; 302-Passivation dry film; 40-Second type of chip; 401-Chip body; 402-Metal bump; 50-Molding body; 60-Component overall passivation layer; 70-Metal circuit. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to specific embodiments. Figure 1 The flowchart of the system-level packaging method disclosed in this invention is shown, which mainly includes the following steps: S1. Preparation of the support plate; S2. Batch graphic processing of copper plates; S3, Thick copper interconnect unit forming; S4. Mounting the first type of chip to be packaged onto the carrier board of the thick copper interconnect unit; S5, Fabrication of metal bumps for the second type of chip and welding of thick copper interconnect units; S6. The entire packaged component is encapsulated in plastic; S7. The substrate carrier plate is removed and the copper surface of the first type of chip to be packaged pads and thick copper interconnect units is exposed. S8. Preparation of overall passivation layer for components and opening of electrical connection openings; S9. Fabrication of metal interconnect lines and forming of soldered terminals.

[0033] The carrier board fabrication step (corresponding to step S1 in the process method) is the fundamental step in the entire packaging process. The fabricated carrier board 10 provides a stable carrier for the subsequent mounting and processing of various chips and thick copper interconnect units. It includes a substrate carrier board 102 and a temporary bonding material layer 101 covering the surface of the substrate carrier board 102 (such as...). Figure 2 (As shown in the diagram). The temporary bonding material layer 101 needs to have good adhesion and peelability, so that it can not only firmly support the first type of chip to be packaged and the thick copper interconnect unit to be mounted later, but also achieve damage-free peeling in subsequent processes, creating conditions for the subsequent processing of the packaged components.

[0034] The batch patterning process of copper plates (corresponding to step S2 in the process method) is the core pre-fabrication step for customized thick copper interconnect units. First, the thickness of the copper plate 301 needs to be determined based on the current carrying capacity and impedance requirements of the first type of chip to be packaged 20. Then, based on the pad layout and interconnection requirements of the first type of chip to be packaged 20, the interconnection circuit pattern is pre-designed and customized. Subsequently, exposure, development, and etching processes are sequentially performed on the entire copper plate 301 to batch produce interconnection circuit patterns matching the requirements of the first type of chip to be packaged 20 (e.g., ...). Figure 3 (As shown in the diagram). This process avoids performing thick copper plating on the front side of the first-type chip 20, thus eliminating the accumulation of internal stress caused by uneven copper ion deposition during the plating stage and preventing wafer warping. Furthermore, the standardized batch processing method allows for the simultaneous fabrication of interconnect circuits for multiple first-type chips 20, significantly reducing the overall process steps and production cycle.

[0035] The thickness of the copper plate 301 needs to be set differently for different types of chips in the first category of chips to be packaged 20: high-power chips are integrated circuit chips with a single chip power consumption of ≥1W and a continuous current carrying capacity of ≥1A. High-power chips specifically include power management chips, power drive chips, RF power amplifier chips and automotive power semiconductor chips, and the thickness of the copper plate 301 for this type of high-power chip is 50-200μm.

[0036] For high-frequency chips with operating frequencies ≥1GHz, the thickness of copper plate 301 is 20-80μm, and the corresponding interconnect circuit linewidth needs to be controlled within 10-30μm and the line spacing within 8-25μm. In addition, the pad area of ​​the interconnect circuit needs to be designed as a circular or square flared structure. The size of the flared structure is 5-10μm larger than the pad of the first type of chip to be packaged 20, and the pad alignment deviation needs to be ≤±3μm to ensure the accuracy of subsequent electrical interconnection.

[0037] The thick copper interconnect unit forming stage (corresponding to step S3 in the process method) follows the batch patterning process of copper plates. First, passivated dry film 302 is used to fill the gaps in the interconnect circuit patterns and form the thick copper interconnect unit motherboard structure (e.g., ...). Figure 4As shown in the diagram, the thick copper interconnect unit motherboard structure is then cut to obtain independent thick copper interconnect units 30 that are adapted to the size and pad positions of a single first-type chip 20 to be packaged. The passivation dry film 302 needs to be a high-temperature resistant epoxy resin dry film, and its curing temperature needs to be controlled between 120 and 150°C, and the curing time is 30 to 60 minutes. The difference between the thermal expansion coefficient of the cured dry film and the thermal expansion coefficient of the copper plate 301 is ≤5ppm / °C. This material selection can ensure the thermal matching between the passivation dry film 302 and the copper plate 301, and avoid structural cracking due to thermal expansion differences in subsequent high-temperature processes.

[0038] Furthermore, the modular cutting design in this step enables precise placement of thick copper material. Thick copper interconnect units 30 are integrated only in chip areas with special impedance requirements, such as high-power chips and high-frequency chips in the first type of chip to be packaged 20, rather than laying thick copper across the entire packaging substrate. This not only avoids material redundancy caused by the overall thick copper frame, but also significantly improves the design flexibility of multi-chip heterogeneous integration by adapting the pad layout of different types of first type of chip to be packaged 20 with the modular unit structure.

[0039] In the carrier board mounting step of the first type of chip to be packaged and the thick copper interconnect unit (corresponding to step S4 in the process method), the first type of chip to be packaged 20 and the independent thick copper interconnect unit 30 obtained in step S3 need to be mounted on the surface of the temporary bonding material layer 101 (e.g., Figure 5 (As shown in the figure). During the mounting process, the relative positional accuracy of the two must be ensured to ensure that the pad area of ​​the thick copper interconnect unit 30 corresponds precisely to the pad of the first type of chip to be packaged 20, laying the foundation for subsequent electrical interconnection. At the same time, the adhesiveness of the temporary bonding material layer 101 must meet the load-bearing requirements to avoid displacement of the first type of chip to be packaged 20 or the thick copper interconnect unit 30 after mounting.

[0040] The fabrication of metal bumps and the soldering of thick copper interconnect units for the second type of chip (corresponding to step S5 in the process method) are divided into two stages. The first stage involves fabricating metal bumps 402 on the surface of the second type of chip body 401 of the second type of chip 40 (e.g., Figure 6 As shown in the diagram, the metal bump 402 needs to be made of tin-silver-copper alloy, with a bump diameter controlled between 50 and 100 μm and a height between 30 and 60 μm. The second stage involves soldering the metal bump 402 onto the surface of the thick copper interconnect unit 30 using a reflow soldering process. At this point, the thick copper interconnect unit 30 and the second type of chip 40 with the metal bump 402 together serve as a customized thick copper redistribution layer for the first type of chip to be packaged 20 (as shown in the diagram). Figure 7(As shown in the diagram). This step abandons the adhesive-mediated indirect connection method and constructs a direct welding interconnection system of metal bumps 402 and thick copper interconnect units 30. The metal-metal metallurgical interface can eliminate the thermal aging and shrinkage problems of organic adhesives under high and low temperature cycling conditions, and eliminate the risk of interface delamination. At the same time, the direct interconnection structure without an adhesive layer can eliminate the thermal resistance barrier caused by organic adhesives, allowing the heat generated by the first type of packaged chip 20 and the second type of chip 40 to be quickly conducted through the thick copper interconnect units 30, improving the overall heat dissipation efficiency of the package.

[0041] In the overall plastic encapsulation step (corresponding to step S6 in the process method), molding compound is used to encapsulate the first type of chip to be packaged 20, the thick copper interconnect unit 30, and the second type of chip 40 on the carrier board 10, forming a molded body 50 (e.g., ...). Figure 8 (As shown in the diagram). The thick copper interconnect unit 30 has two embedding methods. If it is completely embedded inside the molding compound 50, the overall passivation layer thickness of the subsequently fabricated component needs to be controlled between 5 and 15 μm. If it is embedded in the passivation layer reserved during the molding stage, its embedding depth is 1 / 3 to 1 / 2 of its own thickness, and the area exposed on the surface of the passivation layer reserved during the molding stage accounts for no less than 60%. Simultaneously, it is necessary to ensure that the interconnection between the thick copper interconnect unit 30 and the second type of chip 40 is free of adhesive layer, thereby maintaining the heat dissipation and connection reliability of the interconnect structure. The molding compound 50 can provide physical protection and environmental isolation for the first type of chip to be packaged 20, the thick copper interconnect unit 30, and the second type of chip 40, ensuring the overall stability of the packaging structure.

[0042] The step of removing the substrate carrier and exposing the pads of the first type of chip to be packaged and the copper surface of the thick copper interconnect unit (corresponding to step S7 in the process method) requires removing the substrate carrier 102 to fully expose the pads of the first type of chip to be packaged 20 and the copper surface of the thick copper interconnect unit 30 (e.g., Figure 9 (As shown in the diagram). The removal process must employ a non-destructive peeling process to avoid impacting or displacing the first type of chip to be packaged 20, the thick copper interconnect unit 30, and the second type of chip 40 on the temporary bonding material layer 101. The exposed pads and the copper surface of the thick copper interconnect unit 30 provide conditions for the subsequent fabrication of electrical connection structures.

[0043] In the process of preparing the overall passivation layer and creating electrical connection openings (corresponding to step S8 in the process method), an overall passivation layer 60 needs to be fabricated on the surface of all components after the treatment in step S7 (e.g., ...). Figure 10(As shown in the diagram). This passivation layer must be made of polyimide-based passivation material and formed using a coating process. The coating thickness uniformity deviation should be ≤ ±1μm. Simultaneously, openings for electrical connections are made at corresponding positions on the pads of the first type of chip to be packaged 20 and at corresponding positions on the copper surface of the thick copper interconnect unit 30. The sidewall tilt angle of the openings must be controlled between 45° and 60°. This tilt angle design ensures smooth connection of subsequent metal lines and improves the stability of the electrical connection. The overall component passivation layer 60 can protect the surfaces of the first type of chip to be packaged 20, the second type of chip 40, and the thick copper interconnect unit 30, preventing oxidation or contamination in subsequent processes.

[0044] In the metal interconnect fabrication and terminal forming stage (corresponding to step S9 in the process method), metal lines 70 need to be fabricated on the surface of the overall passivation layer 60 of the components to achieve signal interconnection between the components. At the same time, metal terminals for subsequent soldering (such as...) are formed simultaneously on the surface of the overall passivation layer 60 of the components. Figure 11 (As shown in the figure). The metal circuit 70 needs to be prepared by a sputtering-electroplating composite process. The bottom layer is sputtered with a titanium-tungsten alloy barrier layer with a thickness of 0.5 to 1 μm, and the top layer is electroplated with copper circuit with a thickness of 5 to 15 μm. The titanium-tungsten alloy barrier layer can prevent the copper circuit from diffusing into the overall passivation layer 60 of the component, ensuring the stability and service life of the metal circuit 70.

[0045] Furthermore, this method is applicable to wafer-level chip-scale packaging, wafer-level fan-out packaging, and board-level fan-out packaging, and can be adapted to system-in-package scenarios that include high-power chips, high-frequency chips, or fine power distribution networks. Its process compatibility and flexibility can meet the low-impedance interconnection requirements of various types of system-in-packages.

[0046] In summary, during the entire low-impedance system-in-package (SIP) molding process, the fabrication of the carrier board 10 lays a stable foundation for the process. The batch patterning of the copper plate 301 and the molding of the thick copper interconnect unit 30 enable the efficient fabrication of customized interconnect structures. The mounting of the first type of chip to be packaged 20 with the thick copper interconnect unit 30 and the welding of the second type of chip 40 with the thick copper interconnect unit 30 construct a highly reliable interconnect system. The encapsulation of the molding compound 50 and the fabrication of the overall passivation layer 60 provide all-round protection. The molding of the metal circuit 70 completes the final electrical interconnection. The organic integration of each process and the collaborative design of the overall process not only achieves efficient and simplified packaging process and ensures low impedance and high reliability of interconnect structure, but also achieves precise allocation of thick copper material, fully meeting the stringent requirements of system-in-package in complex scenarios such as high power and high frequency.

[0047] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system-level encapsulation method, characterized in that, Includes the following steps: S1. Prepare a support plate; the support plate includes a base support plate and a temporary bonding material layer covering the surface of the base support plate; S2. Provide a copper plate of preset thickness and perform exposure, development and etching processes on it in sequence to batch produce interconnect circuit patterns that match the pad layout and interconnection requirements of the first type of chip to be packaged. The thickness of the copper plate is determined according to the current carrying capacity and impedance requirements of the first type of chip to be packaged, and the pattern of the interconnect circuit is pre-customized based on the pad layout and interconnection requirements of the first type of chip to be packaged, and a thick copper electroplating process is not performed on the front side of the first type of chip to be packaged. S3. Passivated dry film is used to fill the gaps in the interconnect circuit pattern and form an interconnect unit motherboard structure. Then, it is cut to obtain an independent thick copper interconnect unit that is adapted to the size and pad position of a single first type of chip to be packaged. S4. The first type of chip to be packaged and the independent thick copper interconnect unit obtained in step S3 are both mounted on the surface of the temporary bonding material layer. S5. Metal bumps are made on the surface of the second type of chip, and the metal bumps are soldered to the surface of the thick copper interconnect unit. The thick copper interconnect unit and the second type of chip with metal bumps are used as a whole as a customized thick copper redistribution layer for the first type of chip to be packaged. S6. The first type of chip to be packaged, the thick copper interconnect unit and the second type of chip on the carrier board are encapsulated in a plastic molding compound. The thick copper interconnect unit is completely embedded in the plastic mold or embedded in the passivation layer reserved in the plastic molding stage. S7. Remove the substrate carrier plate to fully expose the pads of the first type of chip to be packaged and the copper surface of the thick copper interconnect unit. S8. An overall passivation layer is formed on the surface of all components after the processing in step S7, and the overall passivation layer has openings for electrical connection at the corresponding positions of the first type of chip pad to be packaged and the corresponding positions of the copper surface of the thick copper interconnect unit. S9. Metal lines are fabricated on the surface of the overall passivation layer of the component to realize signal interconnection between the components, and metal terminals for subsequent soldering are simultaneously formed on the surface of the overall passivation layer of the component.

2. The system-level packaging method according to claim 1, characterized in that, The high-power chip in the first type of chip to be packaged is an integrated circuit chip with a single-chip power consumption ≥1W and a continuous current carrying capacity ≥1A; for the high-power chip, the copper plate thickness is 50-200μm; for the high-frequency chip with an operating frequency ≥1GHz, the copper plate thickness is 20-80μm, and the line width of the interconnect circuit pattern is 10-30μm and the line spacing is 8-25μm; the pad area of ​​the interconnect circuit pattern is a circular or square flared structure, and the size of the flared structure is 5-10μm larger than the pad of the chip to be packaged in the first type, and the pad alignment deviation is ≤±3μm.

3. The system-level packaging method according to claim 2, characterized in that, The high-power chip includes a power management chip, a power drive chip, an RF power amplifier chip, and an automotive power semiconductor chip, and the thick copper interconnect unit is integrated only in the area where the high-power chip or the high-frequency chip is located.

4. The system-level packaging method according to claim 1, characterized in that, In step S6, when the thick copper interconnect unit is completely embedded inside the molding compound, the overall passivation layer thickness of the subsequently fabricated component is 5-15 μm; when the thick copper interconnect unit is embedded in the passivation layer reserved in the molding stage, its embedding depth is 1 / 3 to 1 / 2 of its own thickness, and the area of ​​its exposed part on the surface of the passivation layer reserved in the molding stage is not less than 60%, and there is no adhesive layer for the interconnection between the thick copper interconnect unit and the second type of chip.

5. The system-level packaging method according to claim 1, characterized in that, In step S3, the passivation dry film is a high-temperature resistant epoxy resin dry film with a curing temperature of 120-150℃ and a curing time of 30-60min, and the difference between the thermal expansion coefficient of the cured dry film and the thermal expansion coefficient of the copper plate is ≤5ppm / ℃.

6. The system-level packaging method according to claim 1, characterized in that, In step S5, the metal bump is a tin-silver-copper alloy bump with a diameter of 50-100 μm and a height of 30-60 μm, and the welding process is reflow soldering.

7. The system-level encapsulation method according to claim 1, characterized in that, In step S8, the overall passivation layer of the component is a polyimide passivation material, which is formed by coating process. The uniformity deviation of the coating thickness is ≤±1μm, and the sidewall inclination angle of the opening of the overall passivation layer of the component is 45~60°.

8. The system-level packaging method according to claim 1, characterized in that, In step S9, the metal circuit is prepared by a sputtering-electroplating composite process, with a bottom layer of sputtered titanium-tungsten alloy barrier layer with a thickness of 0.5-1 μm and an upper layer of electroplated copper circuit with a thickness of 5-15 μm.

9. A packaged device, characterized in that, The system-in-package (SIP) device is manufactured using any one of the system-in-package (SIP) methods described in claims 1-8. The SIP device is compatible with wafer-level chip-scale packaging structures, wafer-level fan-out packaging structures, and board-level fan-out packaging structures, and is also suitable for system-in-package scenarios that include high-power chips, high-frequency chips, or fine power distribution networks.

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