Multi-terminal device with epitaxial oxide on sic substrate

Abstract

A multilayer semiconductor device includes: a substrate comprising silicon carbide (SiC); and an epitaxial transition layer on the substrate, the epitaxial transition layer comprising a first epitaxial oxide material or SiC. One or more epitaxial active regions comprising one or more second epitaxial oxide materials are formed on the epitaxial transition layer, and a metal layer is formed over the one or more epitaxial active regions, the metal layer comprising one or more electrical contacts. The multilayer semiconductor device includes one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET), a vertically conductive MOSFET, a lateral MOSFET, a metal-semiconductor field-effect transistor (MSFET), a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), a metal-insulator-semiconductor (MIS) device, a PN device, a PNP device, an NPN device, or an insulated-gate bipolar transistor (IGBT).

Description

[0001] The epitaxial active region includes one or more second epitaxial oxide materials formed on the epitaxial transition layer; and a metal layer above the one or more epitaxial active regions, wherein the metal layer includes one or more electrical contacts. The multilayer semiconductor device includes one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET), a vertically conductive MOSFET, a lateral MOSFET, a metal-semiconductor field-effect transistor (MSFET), a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), a metal-insulator-semiconductor (MIS) device, a PN device, a PNP device, an NPN device, or an insulated-gate bipolar transistor (IGBT). Attached Figure Description

[0002] Schemes of this disclosure will be discussed with reference to the accompanying drawings.

[0003] Figure 1 This is a symbolic cross-sectional view of a vertical multilayer semiconductor diode device according to an exemplary embodiment.

[0004] Figure 2A This is a simplified energy band diagram of a vertical multilayer semiconductor diode device according to some implementation schemes.

[0005] Figure 2B It is a plot of the trend of the relationship between the supportable critical electric field and the semiconductor bandgap energy.

[0006] Figure 2C It is a graph showing the relationship between specific on-resistance and breakdown voltage for silicon, silicon carbide, and gallium oxide semiconductors.

[0007] Figure 3A and Figure 3B It is based on some implementation schemes such as Figure 1 The symbolic view of the substrate and active region of the vertical multilayer semiconductor device is shown, along with an associated plot of an example of how the doping concentration (i.e., doping density) varies with vertical height.

[0008] Figure 4 This is a symbolic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment.

[0009] Figure 5 It is based on some implementation schemes such as Figure 4 The diagram shows a symbolic view of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device, along with an associated drawing illustrating an example of how doping concentration varies with vertical height.

[0010] Figure 6 It is based on some implementation schemes such as Figure 4The symbolic view of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device is shown, along with an associated drawing of another example of how the doping concentration varies with vertical height.

[0011] Figure 7 It is based on some implementation schemes such as Figure 4 The diagram shows a symbolic view of the substrate, transition layer, and drift layer of a vertically multilayer semiconductor diode device, along with an associated plot of another example of doping concentration varying with vertical height, and an associated plot of an example of composition varying with vertical height.

[0012] Figure 8A This is a symbolic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment.

[0013] Figure 8B This is a symbolic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment.

[0014] Figures 8C to 8F A table is shown according to some embodiments, which depicts combinations of n-type and p-type layers in the case of ohmic contacts with SiC substrates and ohmic or Schottky contacts with epitaxially grown semiconductor layers.

[0015] Figure 9A It is the spatial variation of the conduction band and valence band edge energy maps of a vertically multilayer semiconductor device oriented along the growth direction according to an exemplary embodiment.

[0016] Figure 9B It is the spatial variation of the conduction band edge energy map of a vertically multilayer semiconductor device oriented along the growth direction according to an exemplary embodiment.

[0017] Figure 10 This is a plot comparing the breakdown voltage of β-Ga2O3 with the change in donor doping concentration in the drift region for several film thicknesses, based on some implementation schemes.

[0018] Figure 11A It is a plot of the metal work function energies for a series of metals and the corresponding Schottky barrier energies relative to the (-201) oriented surface of β-Ga2O3, based on some implementation schemes.

[0019] Figure 11B This is a forward bias semi-log-linear current-voltage diagram of a Schottky barrier diode according to some implementation schemes.

[0020] Figure 11C This is a linear-linear forward bias current-voltage diagram of a Schottky barrier diode according to some implementation schemes.

[0021] Figure 12 This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between nickel and the (-201) oriented surface of β-Ga2O3 according to some implementation schemes, as a function of drift donor carrier concentration.

[0022] Figure 13 This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between the nickel-MgO interlayer and the (-201) oriented surface of β-Ga2O3, according to some implementation schemes, as a function of drift donor carrier concentration.

[0023] Figure 14 This is a schematic cross-section of a vertical multilayer semiconductor structure for forming a Schottky barrier diode according to some embodiments, the vertical multilayer semiconductor structure including α-phase Ga2O3 and α-phase (Al2O3) epitaxially formed on a SiC substrate with A-plane, R-plane and M-plane. x Ga 1-x )2O3.

[0024] Figure 15 This is a schematic cross-section of a vertically multilayer semiconductor structure for forming a Schottky barrier diode according to some embodiments, the vertically multilayer semiconductor structure including β-phase Ga2O3 and β-phase (Al2O3) epitaxially formed on a C-plane SiC substrate. x Ga 1-x )2O3.

[0025] Figure 16 This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between nickel and a 5 nm thick MgO interlayer and the (-201) oriented surface of β-Ga2O3, according to some implementation schemes, as a function of drift donor carrier concentration.

[0026] Figure 17 This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between nickel and a 15 nm thick MgO interlayer and the (-201) oriented surface of β-Ga2O3, according to some implementation schemes, as a function of drift donor carrier concentration.

[0027] Figure 18 This is a schematic current-voltage diagram of a vertical multilayer semiconductor Schottky barrier diode according to some implementation schemes, showing the characteristics associated with reverse and forward bias operation.

[0028] Figure 19A This is a plot of the quantum mechanical tunneling probability (coefficient) of electron transport in the conduction band as a function of incident electron energy, calculated based on some implementation schemes for the Schottky barrier of [Ni / β-Ga2O3] multilayer structures.

[0029] Figure 19BThis is a plot of the quantum mechanical tunneling probability (coefficient) of electron transport in the conduction band as a function of incident electron energy, calculated based on some implementation schemes for the Schottky barrier of a [Ni / MgO / β-Ga2O3] multilayer structure.

[0030] Figure 19C It is a drawing of the spatial variation of the conduction band and valence band along the growth direction of a multilayer diode structure including [Ni / ZnGa2O4 intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] according to some implementation schemes.

[0031] Figure 19D This is a drawing of the spatial variation of the conduction band edge and valence band edge along the growth direction of a multilayer diode structure comprising [Ni / ZnGa2O4 intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] according to some embodiments, shown in the vicinity of the depletion region formed by the Schottky barrier.

[0032] Figure 19E and Figure 19F This is a simulated IV diagram of a multilayer semiconductor Schottky barrier diode under forward bias conditions according to some implementation schemes.

[0033] Figure 20 The diagram schematically illustrates the distinct functional regions of a vertically multilayer semiconductor device according to some embodiments, the vertically multilayer semiconductor device including a Schottky metal, an intermediate region, a drift region, a transition region, a substrate, and a back contact (not shown), wherein the intermediate region and the transition region are formed as multiple semiconductor layers.

[0034] Figure 21A and Figure 21B A drawing of the spatial variation of the conduction band edge and valence band edge along the growth direction of a multilayer diode structure comprising [Ni / superlattice intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] according to some embodiments is shown, wherein a finite number of periods of the superlattice intermediate layer comprises, for example, bilayer pairs [ZnGa2O4 / Ga2O3].

[0035] Figure 21C A schematic spatial band diagram of a metal-oxide-metal (MOM) heterostructure according to some embodiments is shown, in which a high electric field band bending effect is depicted for the biased MOM structure.

[0036] Figure 22 This is a plot of the spatial variation of the conduction band and valence band edges along the growth direction with an applied reverse bias in a multilayer diode structure, including an example [Ni / β-Ga2O3 drift layer / 4H-SiC substrate], according to some embodiments, including the barrier reduction effect caused by the surface electric field generated across the Schottky barrier.

[0037] Figure 23 This is a plot of the spatial variation of the conduction band edge along the growth direction of a multilayer diode structure, including an example [Ni / β-Ga2O3 drift layer / 4H-SiC substrate], according to some embodiments, as a function of an applied reverse bias. The plot includes a barrier reduction effect due to the surface electric field generated across the Schottky barrier, where the surface electric field varies from 0 MV / cm to 1 MV / cm, thus showing the variation of the Schottky barrier height and width.

[0038] Figure 24 Plots showing the calculated effective barrier width and potential height of a Schottky heterojunction according to some embodiments as a function of an applied reverse bias and thus the surface electric field are shown.

[0039] Figure 25 The relationship between the quantum mechanical tunneling coefficient calculated according to some embodiments and the incident electron energy passing through the Schottky barrier formed by the [Ni / β-Ga2O3 / 4H-SiC] structure is shown, which varies with the surface electric field.

[0040] Figure 26 The relationship between the quantum mechanical tunneling coefficient calculated according to some embodiments and the incident electron energy crossing the Schottky barrier formed by the [Ni / 5nmMgO / β-Ga2O3 / 4H-SiC] structure is shown, which varies with the surface electric field.

[0041] Figure 27 The calculated component contributions of the thermionic emission current and quantum mechanical tunneling current to the applied surface electric field are plotted according to several embodiments as a function of several substrate temperatures, wherein the device structure includes a vertical multilayer semiconductor structure [Ni / β-Ga2O3 / 4H-SiC].

[0042] Figure 28 The calculated component contributions of the thermionic emission current and quantum mechanical tunneling current to the applied surface electric field are plotted according to several embodiments as a function of several substrate temperatures, wherein the device structure includes a vertical multilayer semiconductor structure [Ni / 5nm MgO / β-Ga2O3 / 4H-SiC].

[0043] Figure 29A Plots of static and optical (high-frequency) dielectric constants calculated for a range of semiconductor and oxide materials according to some embodiments are shown, revealing trends in the relationship between dielectric constant and material bandgap energy.

[0044] Figure 29B It is based on the use of some implementation schemes Figure 29AThe plot shows the relationship between the energy of the conduction band edge barrier reduction caused by the electric field induced by the calculated optical dielectric constant and the band gap energy of the material, with three example electric field intensities plotted for a 5 μm slab.

[0045] Figure 29C Empirical trends of interface state parameters and minimum surface state density as a function of material band gap energy were plotted for some implementation schemes.

[0046] Figure 30 The top figure is a drawing of the spatial variation of the conduction band edge of the superlattice δ-doped drift region of a Ga2O3 host layer along the growth direction, based on some implementation examples of the use of the host layer coupled to a Ni Schottky barrier and deposited on a SiC substrate. The bottom figure depicts the periodic doped layers interspersed in unintentionally doped regions.

[0047] Figure 31 A plot showing the relationship between the effective donor doping concentration and the thickness ratio g of the drift region of a delta-doped superlattice according to some embodiments is presented.

[0048] Figure 32A and Figure 32B This is a plot of forward bias IV curves for two configurations of a vertical multilayer Schottky barrier diode, including a delta-doped SL Ga2O3 drift region, according to some implementation schemes.

[0049] Figure 33A and Figure 33B The spatial variation of the conduction band edge along the growth direction of the double-barrier intermediate region, including [ZnGa2O4 / Ga2O3 / ZnGa2O4], formed between Ni metal and Ga2O3 drift regions according to some embodiments is plotted, and the quantized electronic energy states are shown for zero surface electric field and high surface electric field applied to the structure.

[0050] Figure 34 Electrostatic potentials and electric field lines calculated for an example [metal / Ga2O3 / SiC] vertical structure based on some implementation schemes are plotted, where the topmost Ni contact is surrounded by an insulating dielectric material.

[0051] Figure 35A A top view of an example diode formed on a Ga2O3 / SiC multilayer structure using circular Schottky barrier metal and circular field plate metal contacts according to some embodiments is shown.

[0052] Figure 35B A cross-sectional view of an example diode formed on a Ga2O3 / SiC multilayer structure using circular Schottky barrier metal and circular field plate metal contacts according to some embodiments is shown, wherein the top field plate contact is separated from the surface of the Ga2O3 drift layer by an isolation layer.

[0053] Figure 36 Electrostatic potentials and electric field lines calculated for an example [metal / Ga2O3 / SiC] vertical structure according to some implementation schemes are plotted, in which the topmost Ni contact is surrounded by an insulating dielectric material and an additional field plate positioned on the insulating layer and in electrical contact with a Schottky barrier contact.

[0054] Figure 37A A top view schematically illustrates a plurality of closely arranged circular Schottky barrier metal contacts spaced apart by a fixed radius according to some embodiments.

[0055] Figure 37B It is based on some implementation plans. Figure 37A The cross-sectional view of the structure shows the relationship between the Schottky barrier metal, field plate contacts, isolation layer, drift layer, substrate, and back ohmic contacts.

[0056] Figure 38 A portion of a Schottky metal mesa region formed on an epitaxial drift layer formed on a substrate, according to some embodiments, is depicted.

[0057] Figure 39 A vertically conductive multilayer semiconductor structure according to an exemplary embodiment is depicted.

[0058] Figure 40 It is a two-dimensional thermal model of a vertical multilayer semiconductor diode based on some implementation schemes. This two-dimensional thermal model is used to solve the problem of heat transfer dominated by conduction where convection and radiation occur at the boundary.

[0059] Figure 41 This is a plot of the temperature-dependent thermal conductivity of single-crystal SiC and Ga2O3 materials based on some implementation schemes.

[0060] Figure 42 This is a contour plot of the steady-state thermal distribution of a 2D diode model with a Ga2O3 drift layer and a conductive, low thermal conductivity Ga2O3 substrate. The steady-state current induces ohmic heating in region F8, and the metal contacts are connected to the heat storage body.

[0061] Figure 43 It is a steady-state thermal distribution contour plot of a 2D diode model configured with a Ga2O3 drift layer and a conductive and highly thermally conductive SiC substrate according to some implementation schemes, wherein the steady-state current induces ohmic heating in region F8 and the metal contacts are connected to the thermal storage body.

[0062] Figure 44 This is a plot of transient heat transfer and dissipation rates of a multilayer semiconductor diode for a forward bias current pulse according to some implementation schemes, in which Ga2O3 and SiC substrate configurations are compared.

[0063] Figure 45 It is a two-dimensional thermal model of a vertical multilayer semiconductor diode configured as a mesa drift region according to some implementation schemes. This two-dimensional thermal model is used to solve the problem of heat transfer dominated by conduction where convection and radiation occur at the boundary.

[0064] Figure 46 It is a steady-state thermal distribution contour plot of a 2D diode model configured with a mesa Ga2O3 drift layer and a conductive and low thermal conductivity Ga2O3 substrate according to some implementation schemes, wherein the steady-state current induces ohmic heating in region F8 and metal contacts are connected to the thermal storage body.

[0065] Figure 47 It is a steady-state thermal distribution contour plot of a 2D diode model configured with a mesa Ga2O3 drift layer and a conductive and highly thermally conductive SiC substrate according to some implementation schemes, wherein the steady-state current induces ohmic heating in region F8 and the metal contacts are connected to the thermal storage body.

[0066] Figure 48 The surface orientation dependence of β-Ga2O3 and the absolute energy arrangement of the conduction band and valence band of Si polar and C polar 4H-SiC C-plane surfaces relative to vacuum energy were plotted according to some embodiments.

[0067] Figure 49 It is a plot of the spatial conduction band energy near the β-Ga2O3 / Si polar 4H-SiC heterojunction according to some implementation schemes, wherein the lowest energy quantum confined electron wavefunction is located below the Fermi level.

[0068] Figure 50 A cross-section of the atomic crystal structure of a 4H-SiC polymorph along the

[0001] direction is shown according to some embodiments.

[0069] Figure 51 The atomic crystal structure arrangement of the 4H-SiC polytype observed on a C-face hexagonal surface according to some embodiments is shown.

[0070] Figure 52 This is a cross-sectional view of the monoclinic β-Ga2O3 crystal structure along the [-201] direction according to some implementation schemes.

[0071] Figure 53 The oxygen sublattice arrangement on the (-201)β-Ga2O3 surface is shown according to some embodiments.

[0072] Figure 54 The Si or C hexagonal sublattice of a 4H-SiC(0001) surface is shown according to some embodiments.

[0073] Figure 55 The oxygen hexagonal sublattice of the (-201)β-Ga2O3 surface is shown according to some embodiments.

[0074] Figure 56 The surface orientation and polarity of two sheets, including β-Ga2O3 with (-201) orientation and 4H-SiC with Si polarity or C polarity, are depicted according to some embodiments.

[0075] Figure 57A The atomic arrangement of a bulk 4H-SiC crystal according to some embodiments is shown. The crystal has a Si polar surface with preferentially capped Si atoms and a first oxygen adsorption atomic layer.

[0076] Figure 57B The atomic arrangement of a bulk 4H-SiC crystal according to some embodiments is shown. The crystal has a C polar surface with preferentially capped Si atoms and a first oxygen adsorption atomic layer.

[0077] Figure 57C The atomic arrangement of a bulk 4H-SiC crystal according to some embodiments is shown. The crystal has a Si polar surface with preferentially capped C atoms, a first oxygen adsorption atomic layer, and a second Ga adsorption layer.

[0078] Figure 57D The atomic arrangement of a bulk 4H-SiC crystal according to some embodiments is shown. The crystal has a C polar surface with preferentially capped C atoms, a first oxygen adsorption atomic layer, and a second Ga adsorption layer.

[0079] Figure 57E Possible atomic arrangements at intentionally eccentric 4H-SiC(0001) surfaces according to some embodiments are shown, as well as the subsequent epitaxial Ga-O bond formation as a template for further Ga2O3 film growth.

[0080] Figure 57F A cross-section of a 4H-SiC(0001) crystal offset is depicted according to some embodiments, the crystal offset being used to generate multiple steps and ledges on the SiC surface, thereby creating a film-forming surface tilted relative to the 4H-SiC crystal axis.

[0081] Figure 58These are a series of complete reflected high-energy electron diffraction (RHEED) images according to some embodiments, under azimuth rotation about the rotation axis of epitaxial growth, in which long, sharp RHEED fringes indicate the atomic-level flatness and high crystal quality of the 2µm Si-doped β-Ga2O3 (-201) oriented film deposited on a 0-degree off-cut n+ 4H-SiC (0001) substrate.

[0082] Figure 59 These are a series of RHEED images taken with the azimuth angle rotated about the rotation axis of epitaxial growth. According to some embodiments, the long, sharp RHEED stripes indicate the atomic-level flatness and high crystal quality of the 2µm Si-doped β-Ga2O3 (-201) oriented film deposited on a 4-degree off-center n+ 4H-SiC (0001) substrate, where the RHEED spots represent electron beam transmission through the stepped edges.

[0083] Figure 60A and Figure 60B An in-situ laser reflection method for epitaxially depositing β-Ga2O3 (-201) oriented films on an n+ 4H-SiC(0001) substrate is described according to some embodiments, wherein... Figure 60B The periodic thickness oscillations shown in the experimental data are a result of the constant growth rate of Ga2O3 initially deposited on the bare n+SiC substrate.

[0084] Figure 61A It is a plot of symmetrical bicrystalline rocking curves of X-ray diffraction of a single crystal β-Ga2O3 (-201) oriented film on an n+4H-SiC(0001)_0 degree offcut according to some implementation schemes, wherein the sharp β-Ga2O3 peak indicates pure β phase growth conditions.

[0085] Figure 61B It is a contour plot of the reciprocal lattice spectrum of a β-Ga2O3 (-201) oriented film on an n+4H-SiC(0001)_0 degree off-cut section according to some implementation schemes, in which the reciprocal space spectrum (RSM) of the asymmetric Bragg SiC(107) peak is shown.

[0086] Figure 61C It is a contour plot of the reciprocal space spectrum of a β-Ga2O3 (-201) oriented film on an n+4H-SiC(0001)_0 degree offset according to some embodiments, showing the RSM of the asymmetric Bragg β-Ga2O3 (-403) peak.

[0087] Figure 62 This is a top view of the atomic arrangement of an α-phase Ga2O3 crystal according to some embodiments, showing the (0001) plane and the hexagonal oxygen sublattice.

[0088] Figure 63 This is a top view of the atomic arrangement of a wurtzite phase Ga2O3 crystal according to some embodiments, showing the (0001) plane and hexagonal oxo sublattice.

[0089] Figure 64 This is a schematic diagram of the bulk region and surface region of an oxide epitaxial layer with hydrogen impurities disposed within the structure, according to some implementation schemes.

[0090] Figure 65 This is a drawing of the spatial band structure of a Ga2O3 multilayer structure according to some implementation schemes, which shows the surface depletion and accumulation effects at the surface.

[0091] Figure 66A and Figure 66B It is a plot of forward bias IV curves calculated for Schottky barrier diodes including Ni / β-Ga2O3 / 4H-SiC based on some implementation schemes, in which there are three cases of surface modification of β-Ga2O3 semiconductor and the effect on the turn-on voltage of the diode.

[0092] Figure 67 It is a plot of forward bias IV curves calculated based on some implementation schemes for a series of Schottky barrier diodes including [high work function metal / β-Ga2O3 / 4H-SiC], where there are two cases of surface modification (cleaning and depletion) of β-Ga2O3 semiconductor and the effect on the turn-on voltage of the diode.

[0093] Figure 68 Possible atomic arrangements in the vicinity of a metal-oxide heterojunction according to some embodiments are shown, wherein the surface portion of a single-crystal β-Ga2O3 region with epitaxial coordination of an epitaxial metal region shows an interfacial oxygen capping layer.

[0094] Figure 69A A multilayer epitaxial structure comprising a SiC substrate, an epitaxial semiconductor oxide layer, and an epitaxial metal layer is schematically depicted according to some embodiments.

[0095] Figures 69B to 69E The following are illustrated according to some implementation schemes. Figure 69A RHEED image of the highly symmetric surface diffraction pattern of the structure.

[0096] Figures 69F to 69G The following are examples of implementation schemes. Figure 69A The completed wide-angle and high-resolution X-ray diffraction patterns of the multilayer structure.

[0097] Figure 70AA suitable form for integration with the vertical multilayer semiconductor device disclosed herein, based on some implementation schemes, is illustrated as (Ga2O3). x (ZnO) 1-x and (Al2O3) x (ZnO) 1-x The band gap energy of the binary and ternary components is compared with the changes in the composition.

[0098] Figure 70B A suitable form for integration with the vertical multilayer semiconductor device disclosed herein, based on some implementation schemes, is illustrated as (Ga2O3). x (MgO) 1-x and (Al2O3) x (MgO) 1-x The band gap energy of the binary and ternary components is compared with the changes in the composition.

[0099] Figure 71 The diagram illustrates a suitable form for integration with the vertically multilayer semiconductor device disclosed herein, based on some implementation schemes, as shown in (Zn). x MgO 1-x Ga2O4 and (Zn) x MgO 1-x The band gap energy of the ternary and quaternary components of Al2O4 is compared with the changes in the composition.

[0100] Figure 72 The diagram illustrates suitable integration forms for vertical multilayer semiconductor devices disclosed herein, based on some implementation schemes, as shown in (Al). x GaO 1-x )2ZnO4 and (Al x GaO 1-x The band gap energy of the ternary and quaternary components of 2MgO4 is compared with the changes in the composition.

[0101] Figure 73 and Figure 74 The diagram shows the spatial band structure of a [metal / n+Ga2O3 / 4H-SiC / metal] multilayer structure based on some implementation schemes, illustrating the effect of donor doping concentration in the 4H-SiC region.

[0102] Figure 75 It is a cross-section of a portion of a device, including an epitaxial oxide region, a Schottky metal contact, and a dielectric isolation region, according to some implementation schemes.

[0103] Figure 76 It is a drawing of the spatial band diagram of a heterojunction formed between different oxide or material regions forming an isolation region in an oxide semiconductor according to some implementation schemes.

[0104] Figure 77AThis is a table of calculated dielectric constants for a range of example oxide and fluoride materials compatible with the vertical multilayer device structures disclosed herein, based on some implementation schemes.

[0105] Figure 77B and Figure 77C It is a model based on some implementation schemes of electrostatic interactions between equal and opposite charges located separately in two materials with different dielectric constants. Figure 77B The diagram shows symmetrical equipotential lines between the +Q and -Q charges in a thin sheet of material with equal dielectric constant. Figure 77C The asymmetric equipotential lines between the +Q and -Q charges are shown for thin films of materials with different dielectric constants.

[0106] Figure 77D and Figure 77E It is a model based on some implementation schemes of electrostatic interactions between equal and opposite charges located separately in two materials. Figure 77D The diagram shows a symmetrical distribution of the magnitude of the electric field as a line distributed between charges +Q and -Q in the case of a thin sheet of material with equal dielectric constant. Figure 77E The asymmetric distribution of the electric field intensity as a line distributed between charges +Q and -Q is shown in the case of thin films of materials with different dielectric constants. This disclosure demonstrates the concept of dielectric screening using UWBG materials with different dielectric constants.

[0107] Figure 77F and Figure 77G These are based on some implementation plans. Figure 77D and Figure 77E Parallel E near the heterogeneous interface of the electrostatic model structure in the middle Y and vertical E X Plotting the components of the electric field.

[0108] Figure 78 and Figure 79 This is a two-dimensional electrostatic model of an example multilayer semiconductor diode structure based on some implementation schemes. The semiconductor diode structure includes a lower electrode, a substrate, a drift layer, and a field plate electrode embedded in an isolation region dielectric. The field plate electrode is drawn asymmetrically around the vertical centerline of the structure to simultaneously simulate a structure without a field plate on the upper left and a structure with a field plate on the upper right. Figure 78 This indicates that a thick insulating dielectric layer is used to separate the field plate from the drift region. Figure 79 This indicates that a thin insulating dielectric layer is used to separate the field plate from the drift region.

[0109] Figure 80 and Figure 81 This involves electrostatic simulations of segmented field plate designs with thin dielectric spacing based on some implementation schemes, and the resulting spatial variation of the electric field strength, comparing low-k dielectric isolation layers ( Figure 80 ) and high-k dielectric isolation layer ( Figure 81 There are two scenarios.

[0110] Figure 82 and Figure 83 This involves electrostatic simulations of segmented field plate designs with thick dielectric spacing based on some implementation schemes, and spatial variations of the electric field intensity obtained near the interface between the drift region and the isolation region, with comparisons made to low-k dielectric isolation layers. Figure 82 ) and high-k dielectric isolation layer ( Figure 83 There are two scenarios.

[0111] Figure 84 and Figure 85 This involves electrostatic simulations of a segmented field plate design with thin dielectric spacing based on some implementation schemes, and spatial variations of the electric field intensity obtained near the interface between the drift region and the isolation region, with comparisons made to low-k dielectric isolation layers. Figure 84 ) and high-k dielectric isolation layer ( Figure 85 There are two scenarios.

[0112] Figure 86 and Figure 87 This is a plot of the intensity of the electric field generated within the structure at the heterogeneous interface between the drift layer and the isolation layer, extending laterally along the x-direction. According to some embodiments, the device structure has a thin field plate / isolation layer / drift layer spacing. Figure 86 This is for the case of low-k dielectric isolation layers, and Figure 87 This applies to high-k dielectric isolation layers.

[0113] Figure 88 and Figure 89 This is a plot of the spatial variation of potential energy generated within the structure across three horizontal planes: the heterogeneous interface between the drift layer and the isolation layer, the plane slightly above the heterogeneous interface, and the plane below the heterogeneous interface. According to some embodiments, the device structure has a thin field plate / isolation layer / drift layer spacing. Figure 88 This is for the case of low-k dielectric isolation layers, and Figure 89 This applies to high-k dielectric isolation layers.

[0114] Figure 90 This is a drawing based on simulations of several implementation schemes, which study the effect of the dielectric constant of the isolation layer relative to the dielectric constant of the drift region, applied to the case of thin field plate spacing. The top electrode structure includes the right side (rhs) with the field plate and the left side (lhs) without the field plate. The maximum electric field as a function of the dielectric constant of the isolation layer at the heterojunction between the drift layer and the top electrode (or isolation layer) is calculated for both the rhs and lhs portions of the electrode.

[0115] Figure 91It is based on some implementation plans. Figure 90 The plot generated by the calculation shows the ratio g of the maximum electric field of the field plate relative to the fieldless plate.

[0116] Figure 92 A two-dimensional electrostatic model is shown, according to some embodiments, for simulating the effect of the dielectric constant of the isolation layer in the case of a simple top metal table contact.

[0117] Figure 93 It is a plot of the maximum surface electric field at the heterogeneous interface between the isolation layer (or top metal) and the drift layer surface as a function of the dielectric constant of the isolation layer, according to some implementation schemes, which shows the electric field shielding effect of the high-k dielectric isolation layer.

[0118] Figure 94 These are photographs of a wafer fabricated according to some implementation schemes, including multiple vertical device structures, showing a Ni Schottky barrier metal pattern used for an example design. The back contacts are not processed at this stage, thus revealing the transparent nature of the material.

[0119] Figure 95A Alternative device designs, referred to herein as “T-channel” designs, are shown according to some implementation schemes.

[0120] Figures 95B to 95H It is shown that according to some embodiments, there are similar Figure 95A The spatial electric field modeled (or calculated) within the device of the structure shown.

[0121] Figure 96 Example device configurations according to some implementation schemes are shown, where repetition Figure 95A The device configuration shown is used to form a device array on a common SiC substrate.

[0122] Figure 97A , Figure 97B and Figure 97C It is shown that, according to some embodiments, there are, as about Figure 95A Examples of devices with a described "T-channel" design, and additionally with a transition layer, intermediate layer, or both.

[0123] Figure 98 It is an absolute energy scale comparison of the conduction band edge and valence band edge energies according to some implementation schemes of the following items: N polar and Ga polar GaN surface; Ga polar and O polar Pna21 Ga2O3 surface; monoclinic β-Ga2O3(-201) surface; and SI polar and C polar 4H-SiC surface.

[0124] Figures 99A to 99DPossible combinations of hybrid polar multilayer semiconductor structures including [GaN / Ga2O3 / 4H-SiC] are shown according to some embodiments.

[0125] Figures 100A to 100F Examples of device structures including vertical multilayer semiconductor structures having epitaxial oxide layers and epitaxial nitride layers are shown according to some embodiments.

[0126] Figures 101A to 101C A table is shown according to some embodiments, which depicts combinations of n-type and p-type layers in the case of ohmic contacts with SiC substrates and ohmic or Schottky contacts with epitaxially grown semiconductor layers.

[0127] Figure 102 This is a drawing of twin-crystal X-ray diffraction, showing a symmetrical Ω-2θ scan of an epitaxial multilayer structure according to some embodiments, wherein Ga polar wurtzite GaN is formed on the final surface of a β-Ga2O3(-201) epitaxial layer formed on a SiC or sapphire C-plane substrate.

[0128] Figure 103A and Figure 103B This is a drawing of the spatial band structure of a vertically multilayer semiconductor device according to some embodiments, the vertically multilayer semiconductor device comprising: [Ni / Ga polar GaN / β-Ga2O3(-201) N] 漂移 / n+ 4H-SiC], where the band bending caused by polarization is due to the thickness of the Ga polar GaN top layer, and simulations were performed for three GaN layer thicknesses.

[0129] Figure 103C It is a plot of the spatial valence band energy distribution near the [Ni / Ga-polar GaN / β-Ga2O3] region according to some implementation schemes, which shows the lowest 8 quantum-confined heavy hole wavefunction states due to GaN at the heterojunction interface.

[0130] Figure 103D This is a series of simulated plots of the space conduction band energy near the [Ni / Ga-polar GaN / β-Ga2O3] region according to some implementation schemes, showing the variation of the electron barrier height with the GaN layer thickness.

[0131] Figure 103E It is based on some implementation plans. Figures 55 to 58 The maximum conduction band energy barrier height of the device structure is plotted as a function of GaN layer thickness.

[0132] Figure 104A and Figure 104B This is a schematic diagram of the cross-section of a vertical multilayer semiconductor stack structure. Figure 104AThe topmost portion of the oxide layer, exhibiting surface roughness, is shown. Figure 104B The topmost portion of an oxide layer according to some embodiments is shown, which has been planarized after epitaxial growth to exhibit a smaller surface roughness.

[0133] Figures 105A to 105E This is a generalized example view of an epitaxial oxide semiconductor device that implements a lateral conduction device according to some implementation schemes.

[0134] Figures 106A to 106B This is a generalized example view of an epitaxial oxide semiconductor device that implements a lateral conduction device according to some implementation schemes.

[0135] Figures 107A to 107C This is a generalized example view of an epitaxial oxide semiconductor device that implements a lateral conduction device according to some implementation schemes.

[0136] Figures 108A to 108B This is a generalized view of an example epitaxial oxide semiconductor device for light emission according to some implementation schemes.

[0137] Figures 109A to 109C This is a generalized view of an example three-terminal epitaxial oxide semiconductor device based on some implementation schemes.

[0138] Figures 110A to 110B This is a generalized view of an example lateral epitaxial oxide semiconductor metal-semiconductor-metal (MSM) device based on some implementation schemes.

[0139] Figures 111A to 111B This is a generalized view of an example three-terminal epitaxial oxide mesa semiconductor device based on some implementation schemes.

[0140] Figures 112A to 112B This is a generalized view of an example four-terminal epitaxial oxide mesa semiconductor device based on some implementation schemes.

[0141] Figures 113A to 113C and Figure 114 This is a generalized view of an example epitaxial oxide field-effect transistor (FET) device based on some implementation schemes.

[0142] Figures 115A to 115B This is a generalized view of an example epitaxial oxide field-effect switch configuration of a junction field-effect (JFE) according to some implementation schemes.

[0143] Figure 116 This is a generalized view of an example epitaxial oxide semiconductor planar hybrid insulated gate bipolar transistor (IGBT) / thyristor or MOSFET according to some implementation schemes.

[0144] Figure 117This is a generalized view of an example epitaxial oxide semiconductor metal oxide semiconductor field-effect transistor (MOSFET) device based on some implementation schemes.

[0145] Figure 118 This is a generalized view of an example epitaxial oxide semiconductor hybrid insulated trench gate bipolar transistor (IGBT) / thyristor or MOSFET according to some implementation schemes.

[0146] Figure 119 This is a generalized view of an example epitaxial oxide trench gate metal-oxide field-effect transistor (MOSFET) based on some implementation schemes.

[0147] Figures 120A to 120B This is a generalized view of an example epitaxial oxide semiconductor hybrid V-groove gate IGBT / thyristor or MOSFET based on some implementation schemes.

[0148] Figures 121A to 121B This is a generalized view of an example epitaxial oxide V-groove gate MOSFET based on some implementation schemes.

[0149] In the following description, similar reference numerals in all the figures indicate similar or corresponding parts. Detailed Implementation

[0150] This disclosure describes a semiconductor device including an active region having at least one type of epitaxial oxide material deposited directly on a silicon carbide (SiC) substrate or on a transition layer deposited directly on the SiC substrate. In this context, the “active region” of a semiconductor device is or includes the portion of the device that generates, transports, or modulates charge carriers (electrons and holes) to achieve primary electronic or optoelectronic functions such as conduction, amplification, switching, light absorption, light emission, etc. In many of the topologies disclosed herein, a metal layer (e.g., an epitaxial metal layer) is disposed on the epitaxial oxide layer of the active region. In some embodiments, the materials of the metal layer and the epitaxial oxide layer are selected to form a Schottky junction. In other embodiments, the materials forming the metal layer and the epitaxial oxide layer are used to create ohmic contacts for the semiconductor device disclosed herein.

[0151] Epitaxial oxide materials advantageously include wide band gaps (e.g., about 2.5 eV to about 10 eV, or about 3 eV to about 10 eV, or about 4.5 eV to about 7 eV).

[0152] In some embodiments, the semiconductor device described herein includes layers other than an epitaxial oxide layer (or drift layer) on a SiC substrate. For example, an epitaxial transition layer may be formed between the SiC substrate and the epitaxial oxide layer. In some cases, the transition layer may provide an intermediate level of doping and / or modulate interface strain between the substrate and the epitaxial oxide layer, and thereby affect the electronic and structural properties of the semiconductor diode device, as further described herein. In another example, an intermediate layer may be formed between the epitaxial oxide layer and a metal layer. In embodiments involving a Schottky metal layer, the intermediate layer may advantageously alter the Schottky barrier properties, and thereby affect the electronic properties of the semiconductor diode device, such as the turn-on voltage and / or reverse breakdown voltage, as further described herein. In some example embodiments, one or both of the transition layer and / or intermediate layer are functionally considered part of an active region. In other example embodiments, one or both of the transition layer and / or intermediate layer are not functionally considered part of an active region.

[0153] In some cases, a semiconductor device structure may include both a transition layer and an intermediate layer. The intermediate layer and the transition layer may each be a single layer, or may include multiple material layers, such as in a superlattice layer or a chirped layer.

[0154] Furthermore, in some cases, the semiconductor devices described herein may include an isolation layer surrounding a metal layer. The isolation layer can help mitigate surface currents and modulate the electrostatic vector field of the devices described herein. The isolation layer may include a material having a higher band gap than the material of the epitaxial oxide layer (or drift layer), and may be crystalline (e.g., an epitaxial material) or may be amorphous or polycrystalline. The dielectric constant of the isolation layer material may be lower or higher than the dielectric constant of the epitaxial oxide layer (or drift layer). In some cases, the isolation layer is an oxide. In some cases, the isolation layer is an epitaxial layer formed on an epitaxial oxide layer (or drift layer).

[0155] The materials, structures, and methods described herein can be used in two-terminal, three-terminal, or other multi-terminal semiconductor devices, such as Schottky barrier (SB) diodes, p / n junction diodes, pin diodes, transistors, switches, high-power switches, RF switches, varactor diodes, light-emitting devices, semiconductor devices with quantum wells or superlattices, and semiconductor devices with compositional (or doping density) gradients.

[0156] The semiconductor device described in this paper achieves a high dielectric breakdown voltage (i.e., a high breakdown voltage greater than 50 V, greater than 100 V, or 50 V to 10,000 V) in either the off-state or blocking state. Fundamentally, electrical power P is the product of voltage (V) and current (I). Therefore, for a given operating power, a higher voltage can be utilized while the current is proportionally reduced. Generally, current varies proportionally to the cross-sectional area of ​​the device or conductor; thus, a higher operating voltage allows for a smaller device while reducing ohmic heating losses (I0). 2 R 导通 Reduce on-resistance (R) 导通 This further reduced losses.

[0157] Increasingly stringent requirements for high-power semiconductor devices operating at voltages greater than 1.3 kV have driven simultaneous improvements in size-to-weight-and-power (SWaP) metrics. Compact, high-power-density SWaP power conversion configurations pose challenges to conventional techniques. Semiconductor devices incorporating Ga2O3 have been proposed, but this material exhibits poor thermal conductivity, and the resulting heat typically requires complex thermomechanical devices for dissipation. On the other hand, for the same thickness and doping concentration (or conductivity), currently available all-SiC devices offer lower breakdown voltages compared to comparable devices incorporating Ga2O3. The terms “doping concentration” and “doping density” are used interchangeably herein.

[0158] In this disclosure, the solution to the above problems and the approach to achieving significant improvements include a hybrid approach involving combining a silicon carbide (SiC) substrate with good thermal and electrical conductivity with a layer of epitaxially deposited oxide material (e.g., Ga2O3) for a semiconductor device. For a given vertical or lateral thickness and doping concentration (or electrical conductivity), this results in an improved breakdown voltage compared to a device having a SiC epitaxial layer on a SiC substrate. A further advantage of coupling the active region of an oxide semiconductor to SiC is the potential for increased device configuration flexibility (i.e., heterojunction engineering). The structures and methods described in this paper can also potentially lead to reduced manufacturing costs.

[0159] In some examples of semiconductor diode devices comprising epitaxial oxide layers on silicon carbide (SiC) substrates, the SiC substrates can be made of crystal polymorphs of 4H-SiC, 2H-SiC, 6H-SiC, or 3C-SiC. The SiC substrate orientation can be C-plane SiC (0001), A-plane SiC (11-20), R-plane SiC (10-12), or M-plane SiC (1-100). The thermal conductivity of single-crystal SiC is approximately 300-500 W / (mK), which is significantly higher than other semiconductor substrate materials such as Ga₂O₃ (approximately 20-30 W / (mK)) or Si (approximately 100-150 W / (mK)). The high thermal conductivity of SiC is beneficial for the epitaxial formation of high-power electronic device structures on SiC substrates because it improves heat dissipation through the substrate.

[0160] In some examples of semiconductor diode devices on silicon carbide (SiC) substrates, the epitaxial oxide layers of the active region, transition layer, intermediate layer, and / or isolation layer may include one or more of the following: Ga2O3 (e.g., α-phase or β-phase); (Al x Ga 1-x )2O3 (e.g., α-phase or β-phase), where 0 ≤ x ≤ 1; Mg x Ga 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; Mg x Al 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Zn x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Zn x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Al y O z, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Ni x Ga y O z , where 0≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Ni x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤z ≤ 1; (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y , where 0<x<1 and 0<y<1; or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1, or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4, where , or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ (p, x, y, z) ≤ 1.

[0161] In some embodiments, the oxygen content of the epitaxial oxide materials described herein (e.g., the foregoing epitaxial oxide materials) can vary. For example, different crystal symmetries of the foregoing epitaxial oxide materials can have compositions with an oxygen content that varies (e.g., has a smaller or larger oxygen fraction) compared to the listed compositions. In some cases, due to defects in the material (e.g., oxygen or metal vacancies and / or interstitial atoms), the ratio of metal to oxygen atoms may be less than or greater than the ratio in the compounds described herein.

[0162] The epitaxial oxide materials described herein (e.g., the epitaxial oxide layers of the active region (or drift layer), transition layer, intermediate layer, and / or isolation layer) can be p-type or n-type doped. For example, extrinsic dopants (such as Si, Ge, or Sn) can be used to dope materials such as (Al x Ga 1-xThe epitaxial oxide of 2O3 is n-type doped. In various examples, the dopant can be spatially bounded (e.g., confined to one or more doped layers within a given region). In one example, the dopant can be confined to two or more spatially separated doped layers in a region (e.g., two spatially separated doped layers in a transition layer), or in other examples, the doped layers can span the region or a portion of the region.

[0163] In some embodiments, any epitaxial layer (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may include:

[0164]

[0165] In Material 1, , , ,or These ranges differ from one another, for example, because some embodiments of Material 1 (as described by the above formula) include binary materials, while other embodiments include binary or ternary materials. In other instances herein, the subscripts of the material formulas may include or exclude zero and / or one to distinguish binary, ternary, quaternary, or other materials. The atomic species of Material 1 may be selected from: trivalent A = {Al, Ga, RE, Bi, B', In}; and divalent B = {Ni, Mg, Zn}, where O = oxygen, Al = aluminum, Ga = gallium, RE = at least one rare earth element (e.g., lanthanides), Bi = bismuth, B' = boron, In = indium, Zn = zinc, Mg = magnesium, and Ni = nickel.

[0166] For example, when x = 1 / 2 in the above formula for material 1, the epitaxial layer of the structure or device described herein may include A2B1O4. Some examples of such materials are... , , , , , and .

[0167] In another example, when x = 1 / 3 in the above formula for material 1, the epitaxial layer of the structure or device described herein may include A2B2O5. Some examples of such materials are... , , , , and .

[0168] In another example, when x = 1 / 4 in the above formula for material 1, the epitaxial layer of the structure or device described herein may include A2B3O6. Some examples of such materials are... , , , , and .

[0169] In another example, when x = 1 / 5 in the above formula for material 1, the epitaxial layer of the structure or device described herein may include A2B4O7. Some examples of such materials are... , , , , and .

[0170] In another example, when x = 3 / 4 in the above equation, the epitaxial layer of the structure or device described herein may include A6B1O. 10 Some examples of this type of material are , , , , , and .

[0171] In other examples, x in the above formula for material 1 can be a value , , and Any value within that range. For example, there may also be cases where the concentration of a component is lower, such as when...

[0172] In some embodiments, any epitaxial layer (e.g., epitaxial oxide layer of the active region, transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may include:

[0173]

[0174] In Material 2, , , or ;and , , or The atomic types of material 2 can be selected from: trivalent A and C, which are selected from two of {Al, Ga, RE, Bi, B', In}; and divalent B = {Ni, Mg, Zn}, where O = oxygen.

[0175] For example, when x = 1 / 2 and y = 1 / 10 in the above formula for material 2, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , , , and .

[0176] In some embodiments, any epitaxial layer (e.g., epitaxial oxide layer of the active region, transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may include:

[0177]

[0178] In Material 3, , , or ; , , or ;and , , or The above equation in Material 3 is also subject to constraints, making the sum... The atomic types of material 3 can be selected from: trivalent A, D and C, which are selected from three of {Al, Ga, RE, Bi, B', In}; and divalent B = {Ni, Mg, Zn}, where O = oxygen.

[0179] For example, when x = 1 / 2, y = 18 / 20, and z = 1 / 20 in the above formula for material 3, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , , , and .

[0180] In some embodiments, any epitaxial layer (e.g., epitaxial oxide layer of the active region, transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may include:

[0181]

[0182] In Material 4, , , or ;and , , or The atomic types of material 4 can be selected from: trivalent A = {Al, Ga, RE, Bi, B', In}; and divalent B and C, which are selected from at least two of {Ni, Mg, Zn}, where O = oxygen.

[0183] For example, when x = 1 / 2 and y = 1 / 4 in the above formula for material 4, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , , and .

[0184] In some embodiments, any epitaxial layer (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may include:

[0185]

[0186] In Material 5, , , or ; , , or ;and , , and The atomic types of material 5 can be selected from: trivalent A or D, which are selected from at least two of {Al, Ga, RE, Bi, B', In}; and divalent B and C, which are selected from at least two of {Ni, Mg, Zn}, where O = oxygen.

[0187] For example, when x = 1 / 2, y = 1 / 2, and z = 1 / 2 in the above formula for material 5, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , and .

[0188] In some embodiments, any epitaxial layer (e.g., epitaxial oxide layer of the active region, transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may include:

[0189]

[0190] In Material 6, , , ,or The atomic types of material 6 can be selected from: trivalent A = {Al, Ga, RE, Bi, B', In}; and divalent B = {Ge, Si, Sn}, where O = oxygen, Al = aluminum, Ga = gallium, RE = at least one rare earth element (e.g., lanthanides), Bi = bismuth, B' = boron, Ge = germanium, Si = silicon, and Sn = tin.

[0191] For example, when x = 1 / 2 in the above formula for material 6, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , , , , and .

[0192] For example, when x = 3 / 4 in the above formula for material 6, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , and .

[0193] In some embodiments, any epitaxial layer (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may include:

[0194]

[0195] In Material 7, , , ,or The atomic types of material 7 can be selected from: trivalent A = {Mg, Ni, Zn}; and divalent B = {Ge, Si, Sn}, where O = oxygen, Mg = magnesium, Ni = nickel, Zn = zinc, Ge = germanium, Si = silicon and Sn = tin.

[0196] For example, when x = 1 / 2 in the above formula for material 7, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , , , , and .

[0197] For example, when x = 2 / 3 in the above formula for material 7, the epitaxial layer of the structure or device described herein may include Some examples of this type of material are , , , , and .

[0198] It should be understood that for any epitaxial layer of the structures and devices described herein (e.g., an epitaxial oxide layer of an active region, a transition layer, an intermediate layer, and / or an isolation layer), the compositional fractions (e.g., x, y, and / or z) of any chemical formula of the materials described herein (e.g., materials 1-7 described above) can be different from the exact amounts within the layer. For example, the compositional fractions may vary due to lattice defects (e.g., vacancies, anti-site defects, and / or interstitial species) and random fluctuations within the actual composition. Thus, in some cases, the compositional fractions of the formulas of the materials described herein can be considered as the average composition of the layer.

[0199] It should also be understood that any epitaxial layer of the structures and devices described herein (e.g., an epitaxial oxide layer of an active region, a transition layer, an intermediate layer, and / or an isolation layer) can include stoichiometric compositions of the materials described herein (e.g., materials 1-7 above), such as , or non-stoichiometric compositions, such as , where 0 < p < 2 represents an oxygen-deficient or gallium-rich composition. Another example of a non-stoichiometric composition is , where 0 < q < 1 represents a composition rich in oxygen and / or gallium-deficient. Any oxide composition (e.g., materials 1-7) described herein can be stoichiometric or non-stoichiometric in the current structures and devices.

[0200] In addition, any epitaxial layer of the structures and devices described herein (e.g., an epitaxial oxide layer of an active region, a transition layer, an intermediate layer, and / or an isolation layer) can include a low-alloy composition of any oxide composition (e.g., materials 1-7) described herein. A low-alloy composition is one in which a low concentration of a material is present at a concentration less than 0.1. For example, one of materials 1-7 can include values of x, y, and / or z less than 0.1, or less than 0.05, or less than 0.01. In some cases, a dopant species (e.g., Si, Ge, or Sn) can be incorporated into the materials described herein (e.g., into one of materials 1-7 formed in an epitaxial layer) at a composition less than 0.1, or less than 0.05, or less than 0.01.

[0201] The epitaxial oxide layer may also possess crystal symmetry and orientation to enable epitaxial layer formation on the SiC substrate. In some examples, the epitaxial oxide material is selected to have a lattice mismatch of less than 10%, or less than 8%, or less than 6%, or less than 5%, or less than 2% with the SiC substrate. The thickness of the epitaxial oxide layer may be less than the critical layer thickness of the material (below this critical layer thickness, the epitaxial oxide layer can undergo elastic strain and is substantially coherent with the substrate, while above this critical layer thickness, the epitaxial oxide layer relaxes or partially relaxes). For example, the thickness of the epitaxial oxide layer may be from 1 nm to 100 μm, or 100 nm to 10 μm, or 1 nm to 1 μm, or 5 nm to 500 nm.

[0202] In some examples, the semiconductor devices disclosed herein include short-period superlattices (SPSLs). Epitaxial oxide layers may include SPSLs, and / or other layers of the device (e.g., transition or intermediate layers) may include SPSLs. In some cases, the SPSL comprises alternating sublayers of materials with wider and narrower bandgap materials (barrier and well layers, respectively). The thickness of the barrier or well sublayer in the SPS can be less than 1 monolayer (ML) to 5 ML, less than 1 ML to 10 ML, or less than 1 ML to 20 ML. Barrier and / or well sublayers with a thickness of less than 1 ML or 1 unit cell along the growth direction can be laterally discontinuous (i.e., in a direction parallel to the main surface of the layer).

[0203] In some examples, the semiconductor devices disclosed herein include chirped layers. Epitaxial oxide layers may include chirped layers, and / or other layers of the device (e.g., transition or intermediate layers) may include chirped layers. Chirped layers are similar to SPSLs in that they also contain alternating sublayers of materials with wider and narrower bandgap materials (barrier and well layers, respectively); however, chirped layers have sublayer properties that vary throughout the chirped layer. For example, a chirped layer may contain (Al) with two different compositions (i.e., two different x values). x Ga 1-x Alternating sublayers of 2O3 are used to form a barrier layer and a potential well sublayer, wherein the barrier sublayer and / or the potential well sublayer varies in thickness throughout the chirped layer. In another example, the chirped layer may contain (Al) x Ga 1-x Alternating sublayers of 2O3 are used to form barrier sublayers and potential well sublayers, wherein the barrier sublayers and / or potential well sublayers change composition throughout the chirped layer. In another example, the chirped layer may contain (Al) x Ga 1-x Alternating sublayers of 2O3 are used to form barrier sublayers and well sublayers, wherein the thickness and / or composition of the barrier sublayers and / or well sublayers vary throughout the chirped layer.

[0204] In yet another example, a body-like graded bandgap can be incorporated into the device, the bandgap energy E of which is... g (z) varies along the growth direction z. Along the growth direction, the variation can be linear or nonlinear, monotonic or non-monotonic. For example, it can form (Al). x Ga 1-x The gradient layer of 2O3 makes the alloy composition x a function of the growth direction z, thereby realizing x(z).

[0205] It is possible to form digital alloys using SPSL or similar alloys, and further variations in effective material properties can be imparted along the growth direction.

[0206] The methods for forming the semiconductor devices disclosed herein (including epitaxial oxide layers on silicon carbide (SiC) substrates and metal layers (such as epitaxial metal layers) on the epitaxial oxide layers) are described in commonly assigned U.S. Patent Application No. 18 / 628,178, filed April 5, 2024, which is incorporated herein by reference in its entirety. Such methods may include forming highly crystalline epitaxial oxide layers on SiC substrates using epitaxial layer growth techniques such as molecular beam epitaxy (MBE), gas-source molecular beam epitaxy (GS-MBE), plasma-source MBE (P-MBE), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), vacuum-based laser ablation sources, vapor phase epitaxy (VPE), gas sources, sputtering sources, electron beam evaporation sources, and plasma-based deposition methods. Other epitaxial layer growth techniques are also applicable, ultimately producing a high-crystal-quality oxide film formed on the substrate surface.

[0207] In a general embodiment, an in-situ metal layer can be formed (or deposited) on the epitaxial oxide layer. In another embodiment, the in-situ metal layer can be formed directly on the clean final surface of the epitaxial oxide. Further still, the in-situ metal layer can be formed on the intentionally prepared final epitaxial oxide surface. Even further, a metal layer can be formed on the intentionally prepared final epitaxial oxide surface, wherein the process does not expose the structure or surface to a contaminated environment. Physical vapor deposition techniques (such as MBE, sputtering, pulsed laser deposition, or thermal evaporation of metals) can be used to deposit metal layers (such as elements Ni, Cu, Al, Ti, Pd, Pt, Ir, Er, Gd, Mo, W, Os, and alloys thereof) to form a non-epitaxy metal layer. Alternatively or additionally, epitaxial layer growth techniques (e.g., using MBE, MOCVD, or another epitaxial layer growth technique) can be used to form an epitaxial metal layer on the epitaxial oxide layer to form a substantially crystalline first metal layer in direct contact with the epitaxial oxide layer, thereby forming a metal-oxide heterojunction. Additional metal or conductive layers may be formed on the final surface of the first crystalline metal layer forming the metal-oxide heterojunction. In some cases, multiple epitaxial and / or non-epitaxy metal layers may be deposited. For example, epitaxial and / or non-epitaxy metal layers may be deposited in different regions of the device to perform different functions. Metal layers may also comprise multiple epitaxial and / or non-epitaxy metal layers in the same region of the device, for example, where the first layer is an adhesive layer and subsequent layers are adhered to the adhesive layer. In some cases, the metal layer may comprise a first epitaxial layer to form a low-defect interface with the underlying semiconductor layer, and a non-epitaxy metal layer may be deposited on top of the epitaxial metal layer.

[0208] Metal-induced bandgap states (MIGS) are known in the art to be generated by metal contacts on semiconductor surfaces. Simply put, MIGS are caused by a mismatch in the different crystal structures constituting the metal-oxide semiconductor interface, resulting in unfavorable bonding arrangements at the metal-oxide heterojunction interface. Passivation of the aforementioned interfacial dangling bonds can be used to reduce the impact of MIGS on the Schottky barrier lowering effect.

[0209] In some embodiments, the semiconductor devices disclosed herein include a direct and interconnected arrangement of bonds across a metal-oxide heterojunction, wherein a substantially epitaxial (i.e., crystalline) first metal layer is formed on an anion- or cation-terminated oxide surface.

[0210] In some cases, epitaxial layer growth techniques (e.g., MBE, MOCVD, or another epitaxial layer growth technique) can be used to form an isolation layer between the epitaxial oxide layer and the metal layer (e.g., an epitaxial metal layer). In some cases, a passivation layer can be formed on the device. The passivation layer may include, for example, aluminum oxide (Al₂O₃), magnesium oxide (MgO), zinc magnesium gallium oxide (Zn₂O₃), etc. x Mg1-x Ga2O4, aluminum gallium oxide (Al) x Ga 1-x )2O3, nickel zinc magnesium gallium aluminum oxide (Ni x Zn y Mg 1-x-y (Ga) p Al 1-p )O q Magnesium germanium oxide Mg x Ge y O z Or silicon dioxide (SiO2), where the subscripts x, y, z, p, and q represent atomic fractions, which represent various crystalline, polycrystalline, or amorphous forms.

[0211] In some cases, one or more layers (e.g., epitaxial oxide layers, epitaxial metal layers or metal layers, isolation layers, and / or passivation layers) can be patterned to form a device, such as using photolithography and etching techniques (e.g., using photoresist, plasma etching, and / or metal lift-off processes). In other methods, damascene metal patterning can be utilized, where oxides are used as trenches, and then chemical mechanical polishing is performed as needed.

[0212] Figure 1 A symbolic cross-sectional view of a vertical multilayer semiconductor diode device 100 according to an exemplary embodiment is shown.

[0213] In this example, semiconductor device 100 includes a substrate 110, which comprises silicon carbide (SiC) and has a width and thickness In one example, substrate 110 is formed of a 4H-SiC polymorph of SiC. In another example, substrate 110 is formed of 2H-SiC, 6H-SiC, or 3C-SiC.

[0214] In some cases, substrate 110 is a bulk material, such as single-crystal SiC. In other cases, substrate 110 may include an optional bulk substrate layer 112 and an optional surface layer 114. Substrate 110 including both bulk substrate layer 112 and surface layer 114 is referred to herein as a “composite substrate.” For example, bulk substrate layer 112 may be polycrystalline SiC, while surface layer 114 may be a single-crystal SiC layer. In such structures, surface layer 114 may be a thin layer (e.g., 100 nm to 5 μm, or 100 nm to 1 μm) serving as a template for epitaxial growth, and bulk substrate layer 112 may be a material with high thermal conductivity. For example, surface layer 114 may include one or more single-crystal layers of 4H-SiC polymorphs of SiC, or it may be 2H-SiC, 6H-SiC, or 3C-SiC. In other examples, surface layer 114 may include one or more single-crystal oxide materials (e.g., Ga2O3, Al2O3, or Al...). x Ga 1-x )2O3, where 0 ≤ x ≤ 1). For example, surface layer 114 may include any oxide material described herein, such as any component of materials 1-7.

[0215] For example, such a composite substrate can be formed by removing layer 114 from a single-crystal substrate (e.g., a single-crystal SiC substrate or an oxide substrate) and coupling or bonding it to a bulk substrate layer 112 (e.g., a bulk layer of polycrystalline SiC or other material with high thermal conductivity). In such cases, a layer of the single-crystal substrate (e.g., SiC, Ga2O3, or Al2O3) can be removed and coupled or bonded to the bulk substrate layer 112. In other examples, an epitaxially grown layer (e.g., any composition of materials 1-7 or epitaxially grown SiC) can be removed from the substrate on which it is grown and coupled or bonded to the bulk substrate layer 112. In some cases, the bulk substrate layer 112 can be formed of a material with high thermal conductivity and optionally high electrical conductivity, such as polycrystalline SiC, a metal (e.g., Ni, Al, or Cu), or a ceramic material (e.g., AlN or BN).

[0216] Methods for transferring the single-crystal surface layer 114 from the donor substrate to the bulk substrate layer 112 may include ion implantation (e.g., using H+). + or He +Ions are implanted to form a weakening layer beneath surface layer 114 (e.g., surface layer 114 of the donor substrate, or surface layer 114 as an epitaxial layer on the donor substrate). The surface layer in which the implanted ions are implanted can then be bonded to the bulk substrate layer 112. Subsequently, heat and / or pressure can be applied to form an optional bonding layer 116, as further described below. Force can then be applied between the donor substrate and the bulk substrate layer 112, and the structure will separate at the ion implantation layer (if it is the weakest layer), leaving the surface layer 114 bonded to the bulk substrate layer 112 while removing most of the donor wafer. In some cases, the surface of the transferred surface layer 114 can then be smoothed, the composite substrate annealed, and / or other processes can be performed to prepare the composite substrate for epitaxial growth.

[0217] In other cases, the bulk substrate 112 may be single-crystal SiC, and the surface layer 114 may be a surface region or near-surface region that has been modified, thermally treated, or chemically treated, for example, to reconstruct a surface for epitaxial growth, or to transform it into graphene or an oxide on which an epitaxial oxide layer can be grown. A composite substrate may be advantageous because the bulk substrate 112 can be made of a material with less constraint than the surface layer 114. For use as a template for the epitaxial growth of the oxide layer, the surface layer 114 may be a single-crystal material with a compatible lattice constant and crystal structure, and with sufficiently high material quality (e.g., a low concentration of penetrating dislocations). The bulk substrate 112 of the composite substrate need not be single-crystal and can therefore be made of a conductive and thermally conductive material to which the surface layer 114 can be bonded. In this disclosure, substrates of various embodiments may be utilized. Figure 1 The composite substrate described in the text.

[0218] In some cases, a thin bonding layer 116 is formed between the bulk substrate layer 112 and the surface layer 114. For example, the bonding layer 116 may comprise a metallic or semi-metallic material (e.g., metallic or semi-metallic Si, C, or Si). x C y (Compound). In some cases, the bonding layer 116 may be thermally and electrically conductive. For example, a metallic or half-metallic bonding layer may be formed as a result of surface activation and thermal bonding between the surface layer 114 (e.g., single-crystal SiC) and the bulk substrate layer 112 (e.g., polycrystalline SiC).

[0219] In some cases, the bulk substrate 112 can be thinned after device fabrication (e.g., by mechanical processes, etching processes, or chemical mechanical polishing) to further reduce the effective resistance and / or thermal resistance of the bulk substrate 112. This can be advantageous because the cost of layer 112 can be significantly lower than the cost of the single-crystal high-quality surface layer 114.

[0220] The vertical direction of the multilayer semiconductor device 100 is defined as approximately perpendicular to the top surface 111 of the substrate 110, as indicated by the arrow, where the dimension " "Increases in the vertically upward direction. An epitaxial active region 120 (e.g., a drift layer) is formed above the SiC substrate 110 and, in this example, on the top surface 111 of the substrate 110. This epitaxial active region includes a layer thickness..." The semiconductor oxide material itself has a top surface 121. A metal layer 130 is formed above the epitaxial active region 120 and, in this case, on the top surface 121 of the epitaxial active region 120. In some embodiments, the material properties of the active region 120 and the metal layer 130 are selected to form a Schottky barrier at the interface region 140 between the metal layer 130 and the epitaxial active region 120. In other embodiments, the material properties of the metal layer 130 are selected to form an ohmic contact of the semiconductor device 100. The metal layer 130 may be an epitaxial metal layer or a non-epitaxy metal layer having an active region underneath it. In some cases, the metal layer 130 is an epitaxial metal layer that forms a low-defect interface with the epitaxial oxide layer of the active region 120 (compared to the interface formed between the epitaxial oxide layer 120 and a non-epitaxy metal layer) to form a Schottky barrier junction. The second metal layer 132 forms an ohmic (or approximately ohmic) electrical contact with the substrate 110 at the back surface opposite to the top surface 121.

[0221] exist Figure 1 The thickness of the layers is not shown to scale in any figure, whether in a symbolic cross-sectional view of the multilayer semiconductor device illustrated herein. For example, substrate thickness t 衬底 Comparable active region thickness 120 t D Much thicker. In some cases, the substrate thickness t 衬底 The thickness can be 1 mm to 3 mm, or 100 micrometers to 1 mm, or 10 micrometers to 500 micrometers. The active region has a thickness of 120 t. D It can be 10 nm to 100 micrometers, or 1 micrometer to 100 micrometers.

[0222] like Figure 1 As depicted, device 100 may include an ohmic anode contact region 151 (“A”) and an ohmic cathode contact region 152 (“C”), which may be formed on or in the metal layer 130 and the metal layer 132, respectively. In an example, the ohmic anode contact region 151 includes the metal layer 130. In an example, the ohmic cathode contact region 152 includes the metal layer 132.

[0223] In the example, the SiC substrate 110 may be n-type or p-type doped, thereby imparting a conductivity type dominated by charge carriers of electrons or holes, respectively. When the substrate 110 is a composite substrate, the bulk substrate layer 112 and / or the surface layer 114 may be n-type or p-type doped, thereby imparting a conductivity type determined by charge carriers of electrons or holes, respectively.

[0224] In some cases, the epitaxial active region 120 comprises a semiconductor oxide material. The epitaxial active region 120 may comprise any oxide material described herein, such as any of the components in materials 1-7.

[0225] In various examples, the epitaxial active region 120 is Ga2O3 or (Al2O3). x Ga 1-x Semiconductor oxide materials in the form of 2O3, where 0 ≤ x ≤ 1.

[0226] In another form, the epitaxial active region 120 is a semiconductor oxide material in the form of a ternary oxide, including but not limited to Mg. x Ga 2(1-x) O 3-2x (where 0 ≤ x ≤ 1) or Mg x Al 2(1-x) O 3-2x (where 0 ≤ x ≤ 1).

[0227] In another form, the epitaxial active region 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z Semiconductor oxide materials in the form of 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1.

[0228] In another form, the epitaxial active region 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z Semiconductor oxide materials in the form of 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z < 1.

[0229] In another form, the epitaxial active region 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y) 2(1-z) O 3-2z Semiconductor oxide materials in the form of 0 < x < 1, 0 ≤ y ≤ 1 and 0 ≤ z < 1.

[0230] In some examples, the epitaxial active region 120 may include one or more of the following: Ga2O3 (e.g., α-phase or β-phase); (Al x Ga 1-x )2O3 (e.g., α-phase or β-phase), where 0 ≤ x ≤ 1; Mg x Ga 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; Mg x Al 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Zn x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Zn x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Ni x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Ni x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y, where 0 < x < 1 and 0 < y < 1; or (Mg x Ni 1-x )) z (Al y Ga 1-y )) 2(1-z) O 3-2z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4, where ; or (Zn p Mg x Ni 1-x-p )(Al z (Al y Ga 1-y )) 2(1-z) O 3-2z , where 0 ≤ (p, x, y, z) ≤ 1.

[0231] In other examples, all or part of the epitaxial active region 120 is n-type or p-type doped. In some cases, one or more impurity substances can be added to the epitaxial active region 120 to externally dope the layer. In some cases, the epitaxial active region 120 can be a polar material doped by polarization doping.

[0232] In another example, the epitaxial active region 120 is formed of β-Ga2O3 -201), and the substrate 110 is formed of C-plane SiC(0001). In the case where the substrate 110 is a composite substrate, the surface layer 114 can include C-plane SiC (0001), and the bulk substrate layer 112 can include polycrystalline SiC.

[0233] In yet another example, the epitaxial active region 120 is formed of β-Ga2O3 -201), and the substrate 110 is formed of C-plane SiC(0001), where an oxide is formed on the silicon-polarity (Si-polarity) SiC surface.

[0234] The epitaxial active region 120 of another example is formed of β-Ga2O3 -201), and the substrate 110 is formed of C-plane SiC (0001), where an oxide is formed on the carbon-polarity (C-polarity) SiC surface.

[0235] In the example, the epitaxial active region 120 is formed wholly or partially of α-phase α-Ga₂O₃ with crystal symmetry group R₃m, and the substrate 110 is formed of 4H-SiC. The epitaxial oxide α-Ga₂O₃ is mainly formed as an A-plane oriented epitaxial film on the A-plane oriented 4H-SiC (11-20), R-plane 4H-SiC (10-12), or M-plane 4H-SiC (10-10) surfaces. That is, there may be A-plane α-Ga₂O₃ oriented epitaxial films on the A-plane, R-plane, and M-plane 4H-SiC surfaces. The SiC surface can be selected from silicon polar or carbon polar orientations. The polarity of the surface directly affects the heterojunction formed with the epitaxial oxide, which can be used as a form of polarization control at the interface and can also promote polarization doping. The epitaxial oxide of the epitaxial active region 120 can be nonpolar, semi-polar, or polar, depending on the oxide crystal symmetry group and the film orientation relative to the substrate surface.

[0236] In the example, the epitaxial active region 120 is composed of β-(Al) x Ga 1-x )2O3 is formed, in which In another example, the epitaxial active region 120 is composed of β-(Al) x Ga 1-x )2O3 (of which The substrate 110 is formed of C-plane SiC (0001). The SiC substrate described herein can be silicon polar or carbon polar. In the case of a composite substrate, the surface layer 114 can be silicon polar or carbon polar single-crystal SiC, while the bulk substrate layer 112 can be another material. This is a potential advantage of composite substrates because the surface layer 114 can be a material that can be used as a template for the epitaxial growth of the oxide layer, while the bulk substrate layer 112 can be made of a material with less constraint.

[0237] Furthermore, SiC substrates can be fabricated with intentional miscuts on their surfaces, thereby exposing multiple atomic steps and plateaus. For example, a miscut C-plane 4H-SiC (0001) oriented surface can be fabricated to form a miscut angle between 0 and 6 degrees pointing towards the A-plane (11-20). A 4-degree miscut is a standard substrate type used in the prior art for growing epitaxial SiC films on n-doped 4H-SiC substrates. In some examples of this disclosure, insights are provided regarding how a 4-degree miscut of 4H-SiC can contribute to improving the crystal quality of epitaxial oxides.

[0238] In some cases, the SiC substrate is not diced, meaning that the surface orientation plane of the substrate is approximately parallel to the crystal planes of the SiC substrate. For example, an undicated substrate may have an angle between 0 and 1 degree between the surface orientation plane of the substrate and the crystal planes of the SiC substrate. For example, an undicated substrate may have a C-plane 4H-SiC(0001) orientation surface with a dicing angle of 0 to 1 degree pointing towards the A-plane (11-20).

[0239] In the example, the epitaxial active region 120 is composed of α-(Al x Ga 1-x )2O3 (of which The substrate 110 is formed from either A-plane SiC (1-100), R-plane SiC (2100), or M-plane SiC (1-100). The surface orientation of the SiC substrate with these orientations can also be offset by approximately 0 to 6 degrees to improve the crystal properties of the epitaxial oxide. In other cases, the SiC substrate may not be offset (i.e., the offset angle is 0 to 1 degree).

[0240] In some examples, the composition of the epitaxial active region 120 varies in the vertical direction. Similarly, the doping concentration may also vary in the vertical direction. In various examples, the active region 120 may have the following combinations: (i) constant doping concentration and constant composition in the vertical direction; (ii) gradient doping concentration and constant composition in the vertical direction; (iii) constant doping concentration and gradient composition in the vertical direction; or (iv) gradient doping concentration and gradient composition in the vertical direction.

[0241] In some embodiments, the epitaxial active region 120 may be formed as a superlattice comprising a variety of different or dissimilar oxide materials. In some embodiments, the active region 120 may be formed as a chirped layer comprising a variety of oxide materials, wherein the chirped layer is similar to a superlattice having layers of varying thickness within the active region 120. The superlattice or chirped layer may contain wider and narrower bandgap materials, thereby forming a potential barrier layer and a potential well layer, respectively. In some cases, the superlattice or chirped layer of the active region 120 may have the following combinations in the vertical direction: (i) constant doping concentration and constant composition; (ii) graded doping concentration and constant composition; (iii) constant doping concentration and graded composition; or (iv) graded doping concentration and graded composition. In the case of graded doping and / or composition, the variation in doping and / or composition can be achieved by changing the barrier layer and / or potential well layer in the active region 120. For example, the thickness of the barrier layer and / or well layer can be varied to form a gradient component in the active region 120. In another example, the doping concentration of the barrier layer and / or well layer can be varied to form a gradient doping distribution in the active region 120. In some cases, the doping concentration, thickness, and / or composition can be varied within one or more barrier layers and / or well layers of the superlattice or chirped layer of the active region 120 to form a gradient doping concentration and / or gradient component.

[0242] In some examples, one or more layers of non-semiconductor oxide or non-SiC materials may be formed between the substrate 110 and the active region 120, while still maintaining the configuration in which the epitaxial active region 120 is formed above the substrate 110. For example, a single-crystal metal layer, a half-metal layer, or an insulating layer may be formed between the substrate 110 and the active region 120. Such a layer may be used to improve contact resistance or to provide a tunnel barrier within a low-resistance (or ohmic) contact between the substrate 110 and the active region 120.

[0243] Figure 2A A simplified electronic band diagram 200 of a vertical multilayer semiconductor device is shown, in which " "The direction of increase is as follows" Figure 1 The diagram corresponds to a vertical upward movement. In this example, band structure 200 depicts the Schottky barrier junction (SBJ) region 210, the active region 220, the n-doped substrate 225, and the ohmic junction region 230 corresponding to the ohmic contact (OC) region of the semiconductor device 100, wherein the active region (e.g., a drift layer) is an n-doped semiconductor oxide material. Schottky metal (SM) and ohmic metal (OM) are chosen to achieve high potential barriers, respectively. and low energy barrier SM and OM may be different metals or the same metal. Valence band energy is shown. and conduction band energy With vertical distance The change also indicates the band gap energy. .

[0244] As can be seen from the inspection, at equilibrium, the Fermi level at the interface between the epitaxial metal layer 130 and the epitaxial active region 120... Cross-interface matching and forming a Schottky barrier Meanwhile, the depletion region extends downwards in the epitaxial drift layer by a distance. .

[0245] Figure 2B It shows a bandgap with electronic energy. Critical electric fields supported by various semiconductors The relationship between them is derived empirically. The avalanche breakdown process, caused by impact ionization induced by high-energy carriers, determines the maximum sustainable electric field that the bulk semiconductor can support (i.e., the critical or breakdown voltage across a semiconductor of finite thickness is defined as...). The maximum electric field at breakdown (also known as the critical electric field E) is known. 临界 It will change with the semiconductor bandgap E g It widens and increases in size. Figure 2B Data and fitting relationships for the selection of unintentionally doped (NID) semiconductors across a range from small bandgap (“NBG”, e.g., InAs, InP, GaAs, InGaP), wide bandgap (“WBG”, e.g., GaN, ZnO, SiC), to ultra-wide bandgap (“UWBG”, e.g., diamond, Ga2O3, AlN, ZnGaO). Dashed line 250 shows the fitting of data, resulting in the power law shown in the figure. Solid line 255 shows the preferred fitting of WBG and UWBG data, resulting in the power law shown in the figure. This dependence (solid line 255) provides the main impetus for the adoption of wide bandgap (WBG) and ultra-wide bandgap (UWBG) semiconductors in high-power electronics.

[0246] Figure 2C The important relationships describing the quality factors of a given semiconductor are plotted. Specific on-resistance per unit thickness of material is also shown. This determines the efficiency or loss of a diode when it is in the conducting state. (Draw) and The relationship illustrates the fundamental trends of a given semiconductor technology. This plot shows that both WBG 4H-SiC and UWBG β-Ga2O3 offer significant advantages over bulk Si, with on-resistance reduced by 3 to 4 orders of magnitude for a given maximum operating voltage. In particular, the devices disclosed herein leverage the benefits of UWBG Ga2O3 to further extend the improvements achievable in high-power device design relative to WBG SiC. Shaded bands represent variations in possible material properties such as crystallinity, defects, carrier mobility, etc. Figure 2C It can serve as a guide for designing high-power diode operation and demonstrates the trade-off between low loss and high-voltage operation.

[0247] Figure 3A It shows things like Figure 1 Symbolic view 300 of the substrate 110 and active region (e.g., such as a drift layer) 120 of the multilayer semiconductor diode device shown, and doping concentration. (A and D refer to donor and acceptor sites, respectively) with vertical height Example of variation, associated with plot 301. For example, highly doped n-type (e.g., n... + The doped substrate 110 will have a large N D Concentration (e.g., 10) 18 cm -3 Up to 10 20 cm -3 , or 10 19 cm -3 Up to 10 20 cm -3 ), and highly doped p-type (e.g., p + The doped substrate 110 will have a large N A Concentration (e.g., 10) 18 cm -3 Up to 10 20 cm -3 , or 10 19 cm -3 Up to 10 20 cm -3 In this example, there is a discrete variation in the drift layer doping concentration 320 and the substrate doping concentration 310, which occurs at the interface 111 between the substrate layer 110 and the active region 120. In this example, the active region 120 has a smaller doping concentration than the substrate 110. For example, the N-type active region 120 has a smaller doping concentration than the substrate 110. D The concentration can be 10 15 cm -3 Up to 10 18 cm -3 And the N-doped p-type active region 120 A The concentration can be 10 15 cm -3 Up to 10 18 cm -3 In some implementations, both the substrate 110 and the active region 120 are n-type doped or both are p-type doped.

[0248] Figure 3B It shows things like Figure 1Symbolic view 302 of the substrate 110 and active region 120 of the multilayer semiconductor diode device shown, and doping concentration. (A and D refer to donor and acceptor sites, respectively) with vertical height Example of variation, associated with plot 303. In this example, the p-type SiC substrate 110 has N... A Concentration 312 (e.g., about 10) 17 cm -3 To about 10 20 cm -3 or about 10 19 cm -3 To about 10 20 cm -3 Furthermore, the n-type drift layer doping concentration of 320 has N D Concentration (e.g., about 10) 15 cm -3 To about 10 20 cm -3 or about 10 17 cm -3 To about 10 20 cm -3 or about 10 15 cm -3 To about 10 18 cm -3 In such embodiments, a p / n junction is formed between the SiC substrate 110 and the active region 120. For example, the active region 120 may include epitaxial Ga2O3. In such examples, Figure 1 The metal contact 130 can be a metal that forms an ohmic contact with the active region 120. When the SiC substrate 110 is p-type doped, the metal 130 can be a metal selected from Ti, Al, Ni, Au, Pt, Mo, and / or Ta, as well as alloys and layered stacked structures thereof. The thickness of the active region 120 can be from about 100 nm to 100 μm, or from about 500 nm to about 5 μm, or from about 1 μm to about 15 μm, or from about 3 μm to about 5 μm. The SiC substrate 110 can be Si-polarized or C-polarized, and in some cases can optionally have a tangentially oriented surface to improve the quality of the oxide material. In some examples, the tangential angle can range from 0.5 degrees to 10 degrees, or 1 degree to 5 degrees, or 1 degree to 4 degrees. The substrate tangential can be selected to provide stepped and plateau-like surfaces to assist oxide epitaxy.

[0249] Figure 4 A symbolic cross-sectional view of a multilayer semiconductor device 400 (e.g., a portion of a diode or multi-terminal device) according to an exemplary embodiment is shown. The device 400 in this example is similar to... Figure 1Device 100 is included, but device 400 also includes a transition layer 160 disposed between substrate 110 and active region 120. In various examples, the intermediate transition layer 160 may be formed of SiC or semiconductor oxide material or a combination of both. The thickness of transition layer 160 is... .

[0250] In some cases, transition layer 160 comprises a semiconductor oxide material. Transition layer 160 may comprise any oxide material described herein, such as any of the components in materials 1-7. Transition layer 160 may comprise a single semiconductor oxide component, or more than one sublayer with different semiconductor oxide components (e.g., the sublayers may form a bilayer, multilayer structure, superlattice, or chirped layer), any of which may be selected from materials 1-7. In some cases, transition layer 160 comprises a gradient component (e.g., a linear, stepped, or chirped component gradient) comprising one or more of materials 1-7. In some cases, transition layer 160 comprises one or more of materials 1-7, which are doped with a single doping concentration or with a doping concentration that varies throughout the depth of transition layer 160.

[0251] In some examples, the transition layer 160 may include one or more of the following: Ga2O3 (e.g., α-phase or β-phase); (Al x Ga 1-x )2O3 (e.g., α-phase or β-phase), where 0 ≤ x ≤ 1; Mg x Ga 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; Mg x Al 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Zn x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Zn x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Ga y O z, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Ni x Ga y O z , where 0≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Ni x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0≤z ≤ 1; (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y , where 0<x<1 and 0<y<1; or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4, where ; or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ (p, x, y, z) ≤ 1.

[0252] Figure 5 shows a symbolic view 500 of a substrate 110, a transition layer 160, and an active region 120 of a multi-layer semiconductor diode device (e.g., such as Figure 4 shown), and an associated plot of the doping concentration varying with the vertical height variation example.

[0253] In this example, the transition layer doping concentration 560 may have a doping concentration between the substrate doping concentration 510 and the drift layer doping concentration 520, wherein the doping concentration between the substrate 110 and the transition layer 160, and between the transition layer 160 and the active region 120, has discrete variations. In this example, the substrate 110 may be n + Doped (i.e., doping concentration of 10) 19 Up to 10 20 cm -3 The transition layer 160 can be n - Doped (i.e., doping concentration of approximately 10) 18 cm -3 , or 10 17 cm -3 Up to 10 18 cm -3 And the active region 120 can be n - - Doped (i.e., doping concentration of 10) 15 cm -3 Up to 10 17 m -3 This provides n that moves vertically upward from the substrate 110 to the active region 120. + doped region to n -- Transition between doped regions. Similarly, p-type devices can be formed, wherein the substrate 110 is p-type. + Doped, transition layer 160 is p - Doped, and the active region 120 is p - - Doped, wherein the layer has an acceptor-rather than donor doping concentration as described above. In other cases, the substrate 110 may be n... + or p + The doped active region 120 can be correspondingly n - or p - The transition layer 160 is doped (to form a Schottky barrier junction), and the doping concentration of the transition layer 160 can be between the doping concentrations of the substrate 110 and the active region 120. For example, the transition layer 160 can be formed of SiC, while the active region 120 can be formed of a semiconductor oxide material. In another example, the transition layer 160 (TL) can be formed of a semiconductor oxide material, while the active region 120 can be formed of the same semiconductor oxide material as TL or a different oxide material. In this example, the transition layer 160 can be formed of a material selected to provide a structural matching region between the substrate 110 and the active region 120. For example, the transition layer 160 can be formed between the SiC substrate 110 and the active region 120, and this transition layer includes Mg. x Zn y Ni z (Al p Ga 1-p )Oq The semiconductor oxide material in the form of Ga2O3 or compositionally graded Al, wherein the active region 120 comprises Ga2O3 or Al. x Ga 1-x O3. Another example of a semiconductor oxide material is silicon oxy-carbide (Si). x C y O z The active region 120 may be in the form of a transition layer 160 and may be formed between the SiC substrate 110 and the active region 120, wherein the active region 120 comprises Ga2O3 or compositionally graded Al. x Ga 1- x O3. Another example of a semiconductor oxide material is silicon oxy-nitride (Si). x N y O z The active region 120 may be in the form of a transition layer 160 and may be formed between the SiC substrate 110 and the active region 120, wherein the active region 120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. Another example of transition layer 160 is one that includes silicon-germanium carbide (Si). x Ge y C z The transition layer 160 is a material of a form that allows the transition layer 160 to be used to manage the interfacial strain formed between the SiC substrate 110 and the active region 120, wherein the active region 120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3.

[0254] In some cases of structures 400 and 500, the transition layer 160 and the active region 120 comprise n-type Ga2O3 (e.g., Ga2O3 deposited by single-crystal epitaxial deposition), and the doping concentration 560 of the transition layer is at least an order of magnitude higher than the doping concentration 520 of the drift layer. The doping concentration within the transition layer 160 can be constant (e.g., ...). Figure 5 As shown), or it can vary spatially in the growth direction (e.g. Figure 6 and Figure 7 As shown, and discussed further below). The doping concentration of the transition layer 160 may be less than or equal to the doping concentration of the SiC substrate 110. The thickness of the Ga2O3 transition layer 160 may be from about 10 nm to about 1 μm. The thickness of the Ga2O3 drift layer may be from about 1 μm to 100 μm, or from about 2 μm to about 15 μm, or from about 3 μm to about 10 μm. The SiC substrate 110 may be Si-polarized or C-polarized, and in some cases may optionally have a tangentially oriented surface.

[0255] The surface of a SiC substrate or layer can be intentionally capped with one or more materials. For example, intentional surface capping of a SiC surface may include capping materials that are substantially silicon (Si), carbon (C), oxygen (O), or nitrogen (N). Capping with a single material (e.g., uniform capping) can be advantageously used to guide nucleation of epitaxial deposition of semiconductor oxide (or metal oxide) films, such that the interfacial bonds are aligned with a low lattice mismatch (or with a reduced mismatch, or with an acceptable amount of mismatch) compared to surfaces not capped with a single material. For example, a SiC surface can be prepared in a vacuum such that a Si capped surface is configured. The Si capped surface can then be preferentially reacted with an active oxygen material to form a -C-Si-O- bond sequence. Conversely, a C capped surface can be configured such that the reaction with active oxygen produces a Si-CO- sequence immediately adjacent to the interface. The oxygen can then readily bond with Ga (or another cation atom) to subsequently form a Ga2O3 single-crystal epitaxial layer.

[0256] Other possible interface layers can also be advantageously used. For example, silicon carbide (SiO2) can be used. x C y O z The interface surface constituting the transition layer can also be formed between the SiC substrate 110 and the active region 120, wherein the active region 120 includes Ga2O3 or Al with a compositional gradient. x Ga 1-x O3.

[0257] Alternatively, silicon carbonitride (Si) x C y N z The interface surface, which may be included in the transition layer, may also be formed between the SiC substrate 110 and the active region 120, wherein the active region 120 includes Ga2O3 or compositionally graded Al. x Ga 1-x O3.

[0258] Including germanium nitride (Ge) x N y The interface surface, which may be included in the transition layer 160, may also be formed between the SiC substrate 110 and the active region 120, wherein the active region 120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3.

[0259] Another example of a transition layer oxide is in the form of magnesium oxide (MgO), which may be included in the transition layer 160 and may be formed between the SiC substrate 110 and the active region 120, wherein the active region 120 comprises Ga2O3 or compositionally graded Al. x Ga 1-xO3. For 4H-SiC(0001) surfaces, the transition layer with MgO(111) orientation can have a thickness of only a few unit cells.

[0260] Another example of a transition layer oxide is in the form of zinc gallium oxide (e.g., spinel crystal symmetry ZnGa2O4, for example having the Fd3m space group), which may be included in the transition layer 160 and may be formed between the SiC substrate 110 and the active region 120, wherein the active region 120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. For 4H-SiC(0001) surfaces, the transition layer with ZnGa2O4(111) orientation can have a thickness of one or only a few unit cells or more.

[0261] In other examples, one or more layers of non-semiconductor oxide or non-SiC materials may be formed between substrate 110 and transition layer 160 and / or between transition layer 160 and active region 120. For example, a single-crystal metal layer, a half-metal layer, or an insulating layer may be formed between substrate 110 and transition layer 160. Such layers may be used to improve contact resistance or provide a tunnel barrier to form a low-resistance (or ohmic) contact between substrate 110 and transition layer 160.

[0262] Figure 6 Multilayer semiconductor devices (e.g., such as) are shown. Figure 4 A symbolic view 600 of the substrate 110, transition layer 160, and active region 120 (shown), and the doping concentration. With vertical height Another example of change is the associated plot 601. Figure 6 An example is shown in which the transition layer 160 has a varying doping density (i.e., doping concentration). The transition layer 160 may have a variable doping density that varies in a direction perpendicular to the top surface of the substrate. In some cases, the variable doping density of the transition layer 160 includes a doping density between the doping density of the substrate and the doping density of the drift layer (e.g., the average doping density of the layer).

[0263] In this example, the transition layer doping concentration 660 has a monotonic gradient in the z-direction, which begins at a doping concentration lower than (i.e., less than) the doping concentration of the substrate 110 and ends at a doping concentration approximately equal to the doping concentration of the active region 120. In some cases, the transition layer doping concentration 660 has a monotonically varying doping concentration, which begins at approximately equal to the substrate doping concentration or between the substrate doping concentration 610 and the drift layer doping concentration 620, and ends at approximately equal to the active region doping concentration or between the substrate doping concentration 610 and the drift layer doping concentration 620. In this example, the transition layer doping concentration 660 may match the substrate doping concentration 610 at the interface between the substrate 110 and the transition layer 160, and then continuously vary to match the drift layer doping concentration 620 at the interface between the transition layer 160 and the active region 120. In this example, the variation of the transition layer doping concentration 660 may vary with vertical height. Changes that are essentially linear (e.g., such as) Figure 6 (As shown). In another example, the transition layer concentration 660 can vary with vertical height. The change is continuous (i.e., without significant abrupt changes, and varies monotonically or non-linearly, for example). In another example, the transition layer concentration 660 can vary with vertical height. It changes in a step-by-step manner. Figure 6 The transition layer 160 in the middle may have as described above (e.g., relative to...). Figure 4 The transition layer 160 described in the transition layer 160) has any of the following properties.

[0264] In the example, the initial transition layer doping concentration 660 at the interface between the substrate 110 and the transition layer 160 may differ from the substrate doping concentration 610 (e.g., such as...). Figure 6 (As shown). Similarly, and in another example, the final transition layer doping concentration 660 (moving upward in the z direction) at the interface between the transition layer 160 and the active region 120 may differ from the drift layer doping concentration 620.

[0265] Return to reference Figure 1Discrete variations in composition, such as those occurring with the SiC substrate 110 and the oxide-based active region 120 (e.g., Ga2O3), can lead to defects at the interface surface 111. These defects can affect carrier transport across the heterojunction between the substrate 110 and the active region 120 (e.g., conduction band and valence band discontinuities providing potential confinement or barriers and / or electroactive defects and / or crystal defects). In some cases, through-dislocations can also form in the active region 120 due to differences in material properties (e.g., lattice constant, crystal symmetry, and / or orientation) between the substrate 110 and the active region 120, resulting in defects at the interface 121 between the drift layer and the overlying layer (e.g., metal layer 130). Defects at interface 121 can affect carrier transport across the heterojunction between the active region 120 and the overlying layer (e.g., metal layer 130), which can, for example, affect the properties of a Schottky barrier diode.

[0266] Figure 7 It shows things like Figure 4 Symbolic view 700 of the substrate 110, transition layer 160 and active region 120 of the multilayer semiconductor diode device shown. Figure 7 The doping concentration is also shown. With vertical height Another example of the variation is shown in plot 701, which relates to the variation and the bandgap energy. With vertical height The associated drawing 702 shows an example of a change (such as a change that would occur due to a change in composition). In this example, the SiC substrate will have a first bandgap energy of approximately 3.2 eV 770. As can be seen in this example, the transition layer 160 has a bandgap energy of 780. With increasing vertical height, the bandgap energy increases substantially linearly from the value of 770 near the substrate 110 to the bandgap energy of 790 near the active region 120. The value of . In other examples, the composition of the transition layer 160 can be varied to induce a bandgap energy of 790. The bandgap energy increases stepwise from the substrate 110 to the active region 120.

[0267] The transition layer doping concentration of 760 in this example is similar to... Figure 6 The transition layer in the medium has a doping concentration of 660 and can have all the same properties as described above. Figure 7 An example is shown where the transition layer doping concentration 760 begins at a doping concentration approximately equal to the doping concentration of the substrate 110 (substrate doping concentration 710) and ends at a doping concentration approximately equal to the doping concentration of the active region 120 (active region doping concentration 720).

[0268] In some cases of structures 400, 600, and 700, the transition layer 160 and the active region 120 comprise n-type Ga2O3 (e.g., Ga2O3 deposited via single-crystal epitaxial deposition), and the doping concentration 660 or 760 of the transition layer 160 is at least an order of magnitude higher than the doping concentration 620 or 720 of the active region. The doping concentration 660 or 760 within the transition layer 160 can be constant (e.g., ...). Figure 5 (as shown) or can vary spatially in the growth direction (e.g.) Figure 6 and Figure 7 (As shown). When the doping concentration varies spatially within the transition layer 160, at least one of the values ​​of doping concentration 660 or 760 within the transition layer 160 is at least an order of magnitude higher than the active region doping concentration 620 or 720. For example, the transition layer 160 may include a doping concentration 660 or 760 equal to or similar to the active region doping concentration 620 or 720 at the interface between the transition layer 160 and the active region 120. In such cases, the gradient of doping concentration 660 or 760 may increase between the active region 120 and the SiC substrate 110 to at least an order of magnitude greater than the doping concentration 720 of the active region 120. In other examples, the doping concentration of the transition layer 160 may be higher than that of the active region 120, and discrete variations in doping density may exist between the transition layer 160 and the active region 120. In such cases, the transition layer 160 may also have spatially varying doping concentrations, such that some or all of the doping concentrations within the transition layer 160 are at least an order of magnitude greater than the doping concentration of the active region 120. The doping concentration of the transition layer 160 may be less than or equal to the doping concentration of the SiC substrate 110. The thickness of the Ga2O3 transition layer 160 may be from about 10 nm to about 1 μm. The thickness of the Ga2O3 active region 120 may be from about 1 μm to 100 μm, or from about 2 μm to about 15 μm, or from about 3 μm to about 10 μm. The SiC substrate 110 may be Si-polarized or C-polarized, and in some cases may optionally have a tangentially oriented surface.

[0269] Figure 8A This is a symbolic cross-sectional view of a multilayer semiconductor device 800 according to an exemplary embodiment, the multilayer semiconductor device including a substrate 110, an active region 120, an intermediate layer 170, and a metal layer 130. In this example, device 800 is similar to... Figure 1 The device 100 includes an intermediate layer 170 formed of semiconductor oxide disposed between the active region 120 and the metal layer 130. The intermediate layer 170 has a layer thickness of [missing information]. In this example, the intermediate layer 170 is formed directly on the top surface 121 of the active region 120, and the metal layer 130 is formed on the top surface 171 of the intermediate layer 170.

[0270] In some cases, the intermediate layer 170 may include a high carrier concentration to form an ohmic contact between the active region 120 and the metal layer 130. For example, the intermediate layer 170 may include a high n-type doping concentration (e.g., N₂) when the active region 120 is n-type. D For about 10 19 cm -3 Or 10 20 cm -3 ), or when the active region 120 is p-type, it includes a high p-type doping concentration (e.g., N). A For about 10 19 cm -3 Or 10 20 cm -3 In such cases, the doping concentration of the active region can be relatively low (e.g., about 10). 15 cm -3 To about 10 18 cm -3 or below 10 15 cm -3 The intermediate layer 170 may have a doping concentration at least an order of magnitude higher than that of the active region 120 to form an ohmic contact with the metal layer 130. Such an ohmic contact can be useful, for example, when a p / n junction exists between other layers of the structure. For example, the p / n junction can be formed using a p-type SiC substrate 110 and an n-type active region 120 (e.g., including epitaxial Ga2O3), or between an n-type drift layer and a p-type epitaxial layer within the active region, as further described herein. The thickness of the active region 120 may be from about 1 micrometer to 100 micrometers, or from about 3 micrometers to about 15 micrometers, or from about 3 micrometers to about 5 micrometers. The SiC substrate 110 may be Si-polarized or C-polarized, and in some cases may optionally have a tangentially oriented surface.

[0271] Figure 8B A symbolic cross-sectional view of a vertical multilayer semiconductor diode device 802 according to an exemplary embodiment is shown. In this example, device 802 is similar to device 800, but similar in... Figure 4 The device 400 also includes a transition layer 160 disposed between the substrate 110 and the active region 120.

[0272] A further advantage of the epitaxial oxide-SiC hybrid structure described herein is its applicability to additional doping methods for forming doped regions (e.g., planar doped regions, selectively doped regions, or doped regions penetrating the depth or thickness of the layer) within the host oxide region. For example, p-type or n-type doping of SiC can be effectively achieved using in-situ epitaxial layer growth or post-epitaxial layer growth ion implantation followed by high-temperature recrystallization annealing. Diffusion doping in SiC is not an efficient method for post-growth doping and / or selectively doping because the high bond energy of SiC hinders the favorable activation of impurity material doping. In contrast, post-growth diffusion doping can be used to dope oxides (e.g., Ga₂O₃) and can be highly efficient. As an example, spin-coated glass dopants can be selectively applied to the Ga₂O₃ surface as a capping layer or for selected regions, and diffusion-driven processes can be employed to transport impurity material into the oxide material. The nature of oxides is that once driven into the oxide, the dopant material can be activated with a relatively low thermal budget, for example, using rapid thermal annealing techniques. For example, diffusion-driven dopants can use dopants (such as Mg, H, Fe, Zn) to change the conductivity type of Ga2O3 from the low n-type doping used in drift layers to a semi-insulating conductivity type. In another example, Si or Ge can be used to increase the n-type doping of Ga2O3, in some cases by at least an order of magnitude. In yet another example, spin-coated glass can be used to provide a surface reservoir of dopant impurities that can be driven into the relevant oxide region. The spin-coated dopant can be patterned to provide selective regional doping. Diffusion time and temperature can be used to control the lateral and vertical extent of the doped region. Spin-coated glass materials can include SiO2, GeO2, Fe2O3, B2O3, MgO, P2O5, or hydrogen-containing materials. Therefore, not only can ion implantation or in-situ epitaxial layer doping be used, but post-growth diffusion-driven processes can also be used to do n-type or p-type doping of epitaxial oxide layers.

[0273] In the example, the intermediate layer 170 is formed of different semiconductor oxides, the band gap of which... The band gap is wider than that of the semiconductor oxide material forming the active region 120. In this example, the oxide material used for the intermediate layer 170 is selected to improve diode performance characteristics, such as turn-on voltage and / or reverse breakdown voltage. In some cases, the intermediate layer 170 may alter the Schottky barrier. This alters the diode's performance characteristics, such as the turn-on voltage and / or reverse breakdown voltage. In some cases, the intermediate layer 170 may be composed of a correspondingly varied bandgap. The gradient semiconductor oxide composition is formed. In another example, the intermediate layer has a multilayer, superlattice, or chirped layer configuration comprising two or more different semiconductor oxide materials, for example, said semiconductor oxide materials are selected to improve reverse breakdown voltage performance (e.g., by changing the Schottky barrier). )。In some cases, it can be advantageous for the bandgap of the intermediate layer 170 to be greater than the bandgap of the active region 120. For example, the active region 120 may include Ga2O3, and the intermediate layer 170 may include (Al x Ga 1-x )2O3, where 0 < x ≤ 1, or where 0 ≤ x ≤ 0.3.

[0274] In another example, the intermediate layer 170 is formed of a different semiconductor oxide, the bandgap of which is narrower or smaller than the bandgap of the semiconductor oxide material forming the active region 120. In an example, the intermediate layer 170 is selected to improve diode performance characteristics such as turn-on voltage and / or reverse breakdown voltage. For example, a material with a narrower bandgap can advantageously exhibit charge carriers of the opposite conduction type, thereby forming an improved depletion region between the active region 120 and the intermediate layer 170. For example, nickel oxide (NiO), copper oxide (Cu2O), lithium oxide (Li2O), or composite oxides (such as spinel crystal structures NiGa2O4, ZnGa2O4, MgGa2O4) can provide p-type characteristics, which can be advantageously used in a heterojunction formed with an n-type (Al x Ga 1-x )2O3 UWBG active region 120. In addition, ternary oxides or spinel oxides in the form of, for example, NiGa2O4, Cu2GaO4, and LiGaO2 can also be utilized in the intermediate layer 170. As a further example, an intermediate layer including a multi-layer p-type NiO / NiGaO formed on Ga2O3 can also be adopted. For example, NiGaO can be formed directly or by intermixing via high-temperature annealing between NiO and Ga2O3. In some cases, the intermediate layer 170 has a smaller bandgap than the active region 120, and due to band alignment, there is a conduction band offset at the interface between the intermediate layer 170 and the active region 120. In this case, even though the intermediate layer 170 has a smaller bandgap than the active region 120, the intermediate layer 170 can form an electron tunneling barrier between the active region 120 and the Schottky metal layer 130.

[0275] Figure 8A and Figure 8B The structure in can include an n-type or p-type 4H-SiC substrate 110, an n-type or p-type epitaxial oxide drift layer 120 (e.g., n-type Ga2O3 or p-type NiO), an optional n-type or p-type intermediate layer 170 (e.g., n-type Ga2O3 or p-type NiO), and a metal contact layer 130 that can form an ohmic contact or a Schottky barrier with the intermediate layer 170. Additionally, as Figure 8BAs shown, an optional n-type or p-type transition layer 160 (e.g., SiC or Ga2O3) may be included. The polar 4H-SiC substrate may be n-type or p-type doped using intrinsic and / or intriguing dopants, and / or may have n-type or p-type induced charges due to its polarity. The epitaxial oxide drift layer 120 and the intermediate layer 170 may also be polar in some cases (e.g., using Pna21 Ga2O3), and in such cases, may be doped using intrinsic and / or intriguing dopants and / or may have n-type or p-type induced charges due to their polarity. In other cases, the epitaxial oxide drift layer 120 and the intermediate layer 170 may be non-polar and may be n-type or p-type doped using intrinsic and / or intriguing dopants.

[0276] Figures 8C to 8F A table is shown according to some embodiments, which depicts combinations of n-type and p-type layers in the case of an ohmic contact (“metal S”) with an epitaxially grown semiconductor layer and an ohmic or Schottky contact (“metal E”). Figure 1 , Figure 4 , Figure 8A and Figure 8B The structure shown may have Figures 8C to 8F The corresponding doping type of the layer is shown in the table below. In some cases, SiC (e.g., 4H-SiC) substrate 110 ( Figures 8C to 8F The n-type or p-type doping of the "substrate" (in this context) can be 1e15cm. -3 up to 1e21cm -3 、or 1e17cm -3 Up to 1e20cm -3 or less than 1e15cm -3 or greater than 1e21cm -3 Epitaxial oxide drift layer 120 ( Figures 8C to 8F The “oxide” in the text) (e.g., n-type Ga2O3 or p-type NiO), intermediate layer 170 ( Figures 8C to 8F The “IL” in the text) (e.g., n-type Ga2O3 or p-type NiO) and transition layer 160 ( Figures 8C to 8F The n-type or p-type doping of "TL" in the figure can each be 1e15cm. -3 up to 1e21cm -3 、or 1e16cm -3 Up to 1e20cm -3 、or 1e15cm -3 up to 1e18cm -3 or less than 1e15cm -3 or greater than 1e20cm -3The doping density of the "i" (intrinsic or unintentional doping), "n--", or "p--" layers can be approximately 1e15cm. -3 or less than approximately 1e15cm -3 The doping density of the "n-" or "p-" layer can be approximately 1e15cm. -3 Approximately 1e16cm -3 The doping density of the "n" or "p" layer can be approximately 1e16 cm⁻¹. -3 Approximately 1e18cm -3 The doping density of the “n+” or “p+” layer can be greater than approximately 1e18 cm⁻¹. -3 or larger than approximately 1e19cm -3 or greater than approximately 1e20cm -3 It should be understood that these ranges can overlap by up to an order of magnitude. Generally, when the same impurity doping is applied to the dopant, increasing the band gap energy of the host material may result in a significantly reduced activation doping density. Therefore, in the structure and device, the substrate 110, the epitaxial oxide drift layer 120 (e.g., n-type Ga2O3 or p-type NiO), the intermediate layer 170 (e.g., n-type Ga2O3 or p-type NiO), and the transition layer 160 may each be an n-type (e.g., n-, n, n+, etc.) layer, a p-type (p-, p, p+, etc.) layer, or an i-type (e.g., intrinsic or unintentionally doped, which may also be n-- or p--) layer.

[0277] Ohmic contacts on SiC substrates ( Figures 8C to 8F The “metal S” in the text is optional and can be omitted in some cases. For example, the layers of the structure can be patterned and selectively etched so that two or more contacts are fabricated on two or more epitaxial layers of the structure, rather than on the back side of the substrate.

[0278] For example, Figure 8E This includes cases where the [polar 4H-SiC 110 / epitaxial oxide 120 / intermediate layer 170 / metal 130] structure is an nnn-Schottky metal structure or a ppp-Schottky metal structure. In such cases, the Schottky metal contact 130 ( Figures 8C to 8F The “metal E” in the diagram will form a Schottky barrier with the n-type or p-type epitaxial oxide drift layer 120 and the intermediate layer 170. The resulting structure can be used to form diodes, transistors, or other devices. For example, metal-oxide-semiconductor field-effect transistors (MOSFETs) can be formed by ion implantation to create doped regions below the source and drain contacts, and the oxide layers of these structures can be used as channel regions, which are separated from the gate contacts by gate oxide. The epitaxial intermediate layer 170 can form the gate oxide, or in other cases, a non-epitaxy (e.g., sputtered) gate oxide can be deposited. Alternatively, similar structures can be used...Figure 8D The structure shown is formed as [polar 4H-SiC 110 / transition layer 160 / epitaxial oxide 120 / metal 130], which includes annn-Schottky metal structure or ppp-Schottky metal structure.

[0279] In another example, Figure 8E This includes cases where the [polar 4H-SiC 110 / epitaxial oxide 120 / intermediate layer 170 / metal 130] structure is an nnp-ohmic contact structure, an nnp-Schottky metal structure, a ppn-ohmic contact structure, or a ppn-Schottky metal structure. In such cases, a p / n junction is formed between the epitaxial oxide layer and the intermediate layer. Alternatively, in the case of including a Schottky metal, a Schottky barrier is formed with the n-type or p-type intermediate layer. This Schottky barrier can be used to increase or decrease the built-in potential within the device, and / or to form a potential well for a 2D electron gas or a 2D hole gas, as further described below. The resulting structure can be used to form diodes, transistors, or other devices. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed by using ion implantation to form doped regions below the source and drain contacts. In another example of a transistor, the intermediate layer can be patterned and selectively etched to form doped regions below the source and drain contacts, and a gate oxide can be formed between the epitaxial oxide drift layer 120 and the gate contact. In other cases, such structures can be used to form LEDs, where epitaxial oxide and / or polar group III nitride layers emit light. Additionally, similar structures can be used... Figure 8D The structure shown is formed as [polar 4H-SiC 110 / transition layer 160 / epitaxial oxide 120 / metal 130], which includes nnp-ohmic contact structure, nnp-Schottky metal structure, ppn-ohmic contact structure or ppn-Schottky metal structure.

[0280] In another example, Figure 8E and Figure 8FThe structure [polar 4H-SiC 110 / epitaxial oxide 120 / intermediate layer 170 / metal 130] can be a pnn-ohmic contact structure, a pnn-Schottky metal structure, an npp-ohmic contact structure, or an npp-Schottky metal structure. In this case, a p / n junction is formed between the polar 4H-SiC substrate and the epitaxial oxide layer. Additionally, an optional n-type or p-type transition layer 160 (e.g., SiC or Ga2O3) can be included between the polar 4H-SiC substrate and the epitaxial oxide layer, which can move the p / n junction interface to the interface between the polar 4H-SiC substrate and the transition layer, or to the interface between the transition layer and the epitaxial oxide layer. Furthermore, in the case of including a Schottky metal, a Schottky barrier can be formed with the n-type or p-type intermediate layer. The Schottky barrier can be used as a second built-in potential within the device, and if the potentials are in opposite directions (e.g., forming back-to-back potentials), the structure can be used as a transistor or switch in some cases (e.g., in a metal-insulator-semiconductor (MIS) transistor structure). The resulting structure can be used to form diodes, transistors, or other devices. For example, ion implantation can be used to form doped regions beneath the source and drain contacts to form a metal-oxide-semiconductor field-effect transistor (MOSFET). In other cases, such structures can be used to form LEDs, where epitaxial oxide and / or polar group III nitride layers emit light. Additionally, similar structures can be used... Figure 8D The structure shown is formed as [polar 4H-SiC 110 / transition layer 160 / epitaxial oxide 120 / metal 130], which includes pnn-ohmic contact structure, pnn-Schottky metal structure, npp-ohmic contact structure or npp-Schottky metal structure.

[0281] In another example, Figure 8E and Figure 8FThe structure [polar 4H-SiC 110 / epitaxial oxide 120 / intermediate layer 170 / metal 130] can be a pnp-ohmic contact structure, a pnp-Schottky metal structure, an npn-ohmic contact structure, or an npn-Schottky metal structure. In this case, a p / n junction is formed between the polar 4H-SiC substrate and the epitaxial oxide layer, and a p / n junction is also formed between the epitaxial oxide layer and the intermediate layer (in opposite directions). Additionally, an optional n-type or p-type transition layer 160 (e.g., SiC or Ga2O3) can be included between the polar 4H-SiC substrate and the epitaxial oxide layer, which can move the p / n junction interface to the interface between the polar 4H-SiC substrate and the transition layer, or to the interface between the transition layer and the epitaxial oxide layer. Furthermore, in the case of including a Schottky metal, a Schottky barrier will be formed with the n-type or p-type intermediate layer. This Schottky barrier can be used to increase or decrease the built-in potential within a device, and / or to form a potential well for a 2D electron gas or a 2D hole gas, as further described below. The resulting structure can be used to form diodes, transistors, or other devices. For example, a bipolar junction transistor (BJT) can be formed by patterning and selectively etching the structure to form individual contacts for the p-type and n-type layers of an npn or pnp structure. In such devices, metal contacts adjacent to the oxide layer or intermediate layer can form the source or drain contacts of the BJT, and additional source or drain contacts can be formed. In other cases, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed by patterning and selectively etching the intermediate layer and ion implantation to form a doped region beneath the source and drain contacts. In other cases, such a structure can be used to form an LED in which an epitaxial oxide and / or polar group III nitride layer emits light. Additionally, similar structures can be used... Figure 8D The structure shown is formed as [polar 4H-SiC 110 / transition layer 160 / epitaxial oxide 120 / metal 130], which includes a pnp-ohmic contact structure, a pnp-Schottky metal structure, an npn-ohmic contact structure, or an npn-Schottky metal structure.

[0282] A further possible benefit of the intermediate layer 170 is the favorable reaction between the Schottky metal 130 and the selective region 141, which can form an alloy. The selective alloying region 141 can be formed via rapid thermal annealing or a diffusion process.

[0283] (For example, respectively in Figure 1 , Figure 4 , Figure 8A and Figure 8BAny of the active region 120, transition layer 160, and / or intermediate layer 170 in devices 100, 400, 800, or 802 may comprise a single epitaxial oxide layer, or may comprise multiple layers of epitaxial oxide material (e.g., bilayer, trilayer, superlattice, and / or chirped layers). The bilayer, trilayer, and other multilayer structures of layers 120, 160, and / or 170 may comprise different compositions and / or different doping densities. In different examples, the total number of layers within any of the active region 120, transition layer 160, and / or intermediate layer 170 may be 1 to 100, 1 to 20, or 1 to 10.

[0284] (For example, respectively in Figure 1 , Figure 4 , Figure 8A and Figure 8B Any of the active region 120, transition layer 160, and / or intermediate layer 170 of the devices 100, 400, 800, or 802 may include superlattices and / or chirped layers, which comprise epitaxial oxide semiconductor materials. Superlattices (such as short-period superlattices) comprise alternating layers (i.e., barrier and well layers) forming unit cells, and the unit cells are repeated to form the superlattice. Chirped layers are similar to superlattices because they also comprise alternating layers; however, the layer thickness and / or composition of the layer monotonically vary along the thickness (or growth direction) of the chirped layer. The thickness of each of the barrier layer, well layer, and / or unit cell within the superlattice or chirped layer can be less than 1 monolayer (ML) to 100 ML, or less than 1 ML to 20 ML, or less than 1 ML to 10 ML, or less than 1 ML to 5 ML, or 1 ML to 20 ML, or 1 ML to 10 ML, or 1 ML to 5 ML. Layers less than 1 ML in thickness may be discontinuous in the lateral direction (i.e., in the direction parallel to the surface on which the substrate layer is grown).

[0285] Superlattices can be used to form digital alloys, whereby the barrier and well layers of the superlattice possess material properties that give the superlattice an overall material property (i.e., composite material properties) that differ from both the material properties of the barrier and well layers. Superlattices can also be used to alter the effects of electrons and / or holes within a device, for example, by creating a barrier to the electron and / or hole flow across the superlattice.

[0286] Chirped layers can also be used to form digital alloys and influence electrons and / or holes within devices as described herein. Furthermore, chirped layers introduce varying material parameters within the chirped layer, such as varying average lattice constant, varying average band gap, and / or varying average doping density. For example, chirped layers can be used to form electron blocking layers (EBLs). Chirped layers can also be used to alter the lattice constant within a structure, such as forming a drift layer on a SiC substrate, where the drift layer has a different lattice constant than SiC. Based on the desired R... 导通 and V击穿 The design flow to achieve the target performance of UWBG power devices is described in detail in commonly assigned U.S. Patent Application No. 18 / 628,178, filed April 5, 2024, which is incorporated herein by reference in its entirety.

[0287] Figure 9A yes Figure 4 The illustrated detailed simulated band structure diagram 2000 of the conduction and valence band edges of the multilayer semiconductor device shows the following regions (moving from left to right): Schottky barrier metal 2010 (Ni in this example), which forms a rectified junction with drift layer 2012 and transition layer 2014 (β-Ga2O3(-201) in this example); and substrate 2016 (Si polar 4H-SiC(0001) in this example). The band structure diagram is constructed based on detailed knowledge of the band structure and absolute electron affinity of each material, thus enabling the determination of accurate heterojunction offsets. The substrate is n-type doped 4H-SiC, making... The transition layer is n-type β-Ga2O3 And the drift zone is The barrier height is shown to be... The ideal case for nickel Schottky metals is considered, with the Fermi energy chosen as the zero-energy reference. The example semiconductor device is a fundamental unipolar device where the majority of charge carriers are electrons. Under the first-order approximation, holes in the valence band are negligible. Furthermore, the detailed band structure of β-Ga₂O₃ reveals a significantly heavier hole mass compared to 4H-SiC. The hole mobility in the valence band is also limited due to the flat valence band energy dispersion in the crystal's momentum space.

[0288] refer to Figure 9B Band plot 2001 reveals that the effective n-type doping of the drift layer has a significant impact on the depletion width of the Schottky potential penetrating into the drift region. Band plot 2001 is a close-up view of the band values ​​(y-axis) from 0 eV to 1.4 eV in band plot 2000. (Width of depletion potential is shown.) This will affect the reverse bias leakage behavior, and This determines the thermionic emission process under forward bias. As expected, the size or extent of the depletion region decreases with increasing doping concentration. Not shown in band structure diagram 2001 is the ohmic contact layer located beneath the substrate (e.g., Figure 4 The ohmic cathode contact region 152 in the diagram. Band diagram 2001 also illustrates an ideal Schottky barrier generated by a metal-semiconductor junction. The Schottky barrier energy reduction effect caused by mirror forces, etc., is not shown – although important, it does not diminish the main conclusions discussed above.

[0289] exist Figures 9A to 9B In this example, the SiC substrate has a highly n-type doping concentration (i.e., n+), for example, about 10. 19 To about 10 20 cm -3 Therefore, it is highly conductive. If the epitaxial layer is deposited on a Si polar surface, the back side of the substrate is essentially C polar. Ohmic contacts on the C polar surface of the SiC substrate can be formed using Ti, Ti / Al, or nickel. Nickel-silicide can be formed by high-temperature annealing, in which a portion of the deposited Ni and Si in the SiC surface region reacts to form Ni. x Si 1-x In some cases, high-temperature processing can also carbonize the SiC surface, which is detrimental to the production of ohmic contacts. In this example, a thin Si substrate (approximately 1-3 nm) can be deposited on the SiC surface, followed by Ni deposition. This prevents Si loss from the SiC surface and enhances Ni deposition. x Si 1-x Formation. In other words, the n+SiC / Si / Ni stacked structure can be formed by post-deposition heat treatment to form n+SiC / Ni. x Si 1-x / Ni. Alternatively, Ni and / or Si can be deposited in situ at high temperatures. To create a Schottky barrier... Raising the potential barrier beyond what a simple metal-semiconductor junction can achieve, it is also possible to insert intermediate layers (e.g., Figure 8A or Figure 8B The intermediate layer 170 in the middle, as discussed further in this paper.

[0290] Figure 10 This is drawing 3000, which shows the selection of thickness. Breakdown voltage of β-Ga2O3 The breakdown voltage varies with the n-type doping concentration. For a given wafer thickness, the breakdown voltage decreases with increasing doping density, where inflection points 3005, 3010, 3015, 3020, and 3025 indicate... The best choice. For example, choose The optimal configuration is It can achieve .

[0291] Generally, the on-resistance of a multilayer semiconductor device under forward bias will be mainly determined by... The decision, and the breakdown voltage Will be The thickness of the drift region under reverse bias is determined by the drift region.

[0292] Figure 11AThis is a plot 4000 of the experimental work functions of various high work function metals (shown on the x-axis) that are favorable for forming Schottky barrier junctions with ultra-wide bandgap semiconductor oxide materials, as determined in this disclosure. A series of metal work function energies are plotted on the left y-axis, with Cu having the lowest value and osmium having the highest. Vacuum energy is also plotted. Defined as zero, the work function energy WF of a metal is understood to have a value WF < 0. Relative to... Given the electron affinity of the conduction band edge of a semiconductor It can be used to compare the absolute energy alignment of metals and semiconductors. Figure 11A Ideal Schottky barrier heights for various metals on clean surfaces with a metal / β-Ga2O3 (-201) orientation Data points are plotted as hollow circles on the right y-axis. Selenium (Se) and osmium (Os) provide the highest... In fact, all the metals listed in the figure can be used to form Schottky barrier diodes, especially Ni, Pt, and Pd, which are relatively stable.

[0293] A unique feature described in this disclosure is the β-Ga2O3 (-201) oriented surface. As discussed later, the surface can be advantageously modified to engineer the surface depletion charge to produce improved Schottky barrier diodes. By depleting a small depth of the n-doped β-Ga2O3 (-201) surface, relative... The significant increase is shown in the diamond-shaped data points. Through careful examination... Figure 11A It can be seen that Cu-metal / depleted β-Ga2O3(-201) can achieve similar results to Ir-metal / clean β-Ga2O3(-201). Clean surfaces and depleted surfaces will be discussed later in this disclosure. Figure 11A Any metal can be used to form an oxide layer between the Schottky metal contact layer and the drift layer, as further described herein. For example, the Schottky metal may include platinum, the drift layer may include Ga2O3 (or various epitaxial oxides as described herein), and an intermediate layer comprising PtO2 may be formed between the Schottky metal contact layer and the drift layer. The metal oxide used for the intermediate layer (e.g., PtO2, or containing...) Figure 11A Metal oxides of any metal can be deposited as oxides (e.g., using MBE, ALD, MOCVD or another epitaxial or non-epitaxy growth method) or as metal deposits that are subsequently oxidized to form metal oxides.

[0294] Figure 11B and Figure 11C Drawing such as Figure 9A and Figure 9BThe diagram illustrates the forward bias current-voltage (IV) behavior of a diode formed using Schottky barrier metal (SBM) = Ni, which is deposited on substrates with various doping concentrations. The structure is deposited on a depletion surface with a 2 mm thick β-Ga₂O₃ (-201) n-type drift layer on a Si polar 4H-SiC n-type substrate. (Reference) Figure 11B At room temperature T=25°C, the semi-logarithmic IV plot shows the subthreshold current as a function of forward bias V. F And increase, until approximately V F It turns on at 1V. Electron transduction Thermionic emission (TE) transport determines the forward conduction current density. Relative to the applied positive bias V F The relationship is as follows:

[0295]

[0296] Richardson's constant can be explicitly calculated as... , is the effective mass of the electron, n is the ideality constant, and q is the electron charge. This is the Boltzmann constant. Therefore, a strong temperature dependence is desirable for TE-dominated conduction. Figures 11B to 11C The example involving Ni / clean β-Ga2O3 has an effective mass of drift layer electrons of [missing information]. And led to In practice, the ideal factor n can be extracted from the fabricated diode, and this ideal factor can be fitted to the diode using Equation 1 above. Figure 11B The subthreshold slope is 4005. The range is... Ideal factors are possible, such as in some examples, for example, And depends on .

[0297] Figure 11C Showing the target Figure 11B The example shows a linear IV plot, where the on-resistance changes with n-type doping. The differential resistance decreases with increasing voltage, such as after the turn-on voltage is 4010. As shown.

[0298] Figure 12This is a simulated band structure diagram 5000 of the conduction band edge of a multilayer semiconductor device with a configuration of 5050. This configuration includes: a substrate layer having SiC (0001) (i.e., SiC with a (0001) orientation); a TL layer having n+ β-Ga2O3 (-201); a drift layer formed of β-Ga2O3 (-201) (i.e., β-phase Ga2O3 with a (-201) orientation); and a metal layer formed of Ni (111) (i.e., Ni with a (111) orientation). In this example, the Schottky barrier value is approximately 1.15 eV, and the drift layer is doped with... The range varies, as shown by the five curves plotted in band structure diagram 5000. As shown, the depletion layer width is affected by... Strong control, thereby targeting (Curve 5010) generates a thin quantum mechanical barrier, where carrier transport will be a combination of TE and quantum mechanical tunneling. That is, the total current density across the barrier... It will have two components, one of which is the thermionic current related to temperature and peak energy barrier. And one of them is a quantum mechanical tunneling component. , making .for The lower the value, the narrower the depletion barrier. Conversely, quantum tunneling through the potential barrier becomes particularly important for designing high-voltage reverse-biased operations.

[0299] Figure 13 This is a simulated energy band diagram 6000 of the conduction band edge of a vertically multilayer semiconductor device with a configuration of 6050, which is similar to... Figure 12 The depicted configuration, with the exception of including an additional intermediate layer (IL) 100 Å thick, formed of single-crystal MgO (111) (i.e., MgO with (111) orientation). Simulations show that incorporating the intermediate layer in this example increases the Schottky barrier to a value of approximately 3.1 eV. Of particular interest is the lower electron affinity exhibited by MgO compared to Ga2O3 and SiC. As expected, when the drift layer is doped with... When varying between these values, the depletion layer width is strongly controlled, however... Figure 12 Unlike other devices, IL presents a fixed quantum mechanical tunneling barrier for electron transport. Figure 13 The increased potential barrier of a device can be further used to adjust the turn-on voltage (or threshold voltage) of a semiconductor device. For example, selecting an IL oxide with a large bandgap and low electron affinity will result in a large SB potential, and thus can be used to design the turn-on voltage of a diode. This is particularly advantageous for producing high-voltage semiconductor devices that are less susceptible to low-voltage noise. A large barrier also helps reduce reverse leakage current under high reverse bias and high electric fields.

[0300] Intermediate layer 170 may include an epitaxial semiconductor oxide material formed on the epitaxial drift layer. In some cases, intermediate layer 170 includes an epitaxial oxide material, and the structure further includes an epitaxial metal layer formed on the epitaxial intermediate layer 170 (e.g., Figure 8B The intermediate layer 170 may comprise any oxide material described herein, such as any of the components of materials 1-7. The intermediate layer 170 may comprise a single semiconductor oxide component, or more than one sublayer with different semiconductor oxide components (e.g., the sublayers may form bilayers, multilayer structures, superlattices, or chirped layers), any of which may be selected from materials 1-7. In some cases, the intermediate layer 170 includes a gradient component (e.g., a linear, stepped, or chirped component gradient) comprising one or more of materials 1-7. In some cases, the intermediate layer 170 comprises one or more of materials 1-7, which are doped at a single doping concentration or at a doping concentration that varies with depth within the intermediate layer 170.

[0301] In some examples, the intermediate layer (e.g., Figure 8A or Figure 8B The intermediate layer 170 may be formed of or include a material selected from one or more of the following materials:

[0302] • Epitaxial single crystal, polycrystalline or amorphous Al2O3

[0303] • Epitaxial single crystal, polycrystalline or amorphous NiO

[0304] • Epitaxial β-(Al x Ga 1-x )2O3, of which (See Figure 8)

[0305] • Extensional α-(Al x Ga 1-x )2O3, of which (see Figure 7 )

[0306] • Epitaxial (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z Where 0 ≤ x, y, z ≤ 1

[0307] • Extensional Zn x Ga y O z, where 0 ≤ x, y, z ≤ 1

[0308] • Epitaxial Zn x Al y O z , where 0 ≤ x, y, z ≤ 1

[0309] • Epitaxial Mg x Ga y O z , where 0 ≤ x, y, z ≤ 1

[0310] • Epitaxial Mg<​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Other crystal orientations of SiC (e.g., particularly 4H-SiC) can also be advantageously used for the epitaxial growth of other oxide compositions and polymorphs in the devices, structures, and methods described herein. For example, A-, R-, and M-plane 4H-SiC substrates can be prepared from bulk-grown single-crystal materials by preferentially dicing along specific crystal planes followed by chemical mechanical polishing (CMP) to form epitaxially ready surfaces. Furthermore, some examples may include the epitaxial deposition of an α-phase Ga2O3 film on the aforementioned adjacent-cut SiC substrate surface. The ability to form α-Ga2O3 provides at least two improvements applicable to this disclosure. First, at room temperature, α-Ga2O3 exhibits a larger fundamental bandgap energy than β-Ga2O3 (…). This can advantageously increase the possible critical electric field and thus improve the performance of semiconductor devices. Secondly, α-Ga₂O₃ grown on the A, R, and M planes can achieve a full alloy range when alloyed with Al, making it suitable for all alloy ranges. , All are possible, including Compared to conventional devices, this wide bandgap design range used to generate heterojunctions significantly improves the performance of possible diodes (and other devices such as p / n junction diodes, transistors, switches, varactor diodes, or light-emitting devices).

[0317] Figure 14 and Figure 15 This is an example of other vertical multilayer semiconductor device configurations including intermediate layers according to this disclosure. Figure 14 An example of structure 7000 is shown, which has a SiC substrate oriented on the A-plane, R-plane, or M-plane, an α-Ga₂O₃ drift layer, and an α-(Al₂O₃)-coated substrate. x Ga 1-x The intermediate layer is α-(Al₂O₃) (where 0 ≤ x ≤ 1) and the metal layer forms the Schottky barrier. For the intermediate layer, it has an α-(Al₂O₃) alloy content x(z) that is related to the growth direction. x Ga 1-x Gradient alloying of O2O3 is also possible. Figure 15 An example of structure 8000 is shown, which has a SiC substrate oriented on the C-plane, a β-Ga2O3 drift layer, and a β-(Al2O3)2O3 drift layer. x Ga 1-x The structure consists of an intermediate layer of β-Ga₂O₃ (where 0 ≤ x ≤ 0.3) and a metal layer forming a Schottky barrier. In practice, the highest Al content achievable to preserve the single-crystal β phase is x ~ 0.3, or in some cases x = 0.4, which represents the possibility of achieving x = 0, i.e., β-Ga₂O₃ / β-(Al₂O₃)₂O₃. x Ga 1-x )2O3 achieves the maximum band gap of the heterojunction.

[0318] Figure 16 and Figure 17 These are simulated energy band diagrams for two example multilayer semiconductor device configurations with intermediate layer (IL) thicknesses of approximately 50 Å and 150 Å, respectively. Both devices consist of a 4H-SiC substrate, a Ga₂O₃ drift layer, an MgO intermediate layer, and a Ni metal layer. The drift layer is doped with... The thickness varies within a range, as shown by the five curves plotted in band diagrams 9000 and 10000. In some examples, the thickness of the intermediate layer can be configured to control the quantum mechanical tunneling current, for example, to control the quantum mechanical tunneling current under reverse bias near the reverse breakdown voltage. In some examples, the thickness of the intermediate layer can be configured to mitigate the reduction in Schottky barrier height due to metal-induced bandgap states at the metal-intermediate interface. Figure 16 and Figure 17 In these examples, IL was selected as UWBG MgO, thus showing the effect on MgO thickness ( Figure 16 50 Å and Figure 17 Two examples of conduction band bending (150 Å) under various drift region doping conditions are shown. Figure 16 This represents a thin quantum mechanical tunneling barrier, while Figure 17 The thicker potential barrier reduces or suppresses quantum mechanical tunneling. This design is advantageous for controlling reverse leakage under high voltage and electric field conditions.

[0319] Figure 18 A simplified example of a representative current-voltage characteristic curve 11000 of a vertical multilayer semiconductor device according to this disclosure is shown. Under reverse bias, at the breakdown voltage (V 击穿 The previous leakage current region itself will include three regions:

[0320] • Thermionic emission region (“Thermionic Emission Region”) appears in low to medium electric fields, where current will be generated by charge carriers with sufficient energy to overcome the potential barrier;

[0321] • The combined quantum tunneling and hot electron emission region (“combined tunneling and hot electron region”) appears under moderate electric fields, where current is generated by a combination of charge carriers with sufficient energy to overcome the potential barrier (i.e., hot electron emission) and charge carriers tunneling through the potential barrier; and

[0322] • The quantum tunneling region (“QM tunneling region”) appears under a high electric field, where the current will be generated by charge carriers tunneling through the barrier.

[0323] In conventional devices, the actual reverse bias breakdown voltage (V) 击穿The strength of the current leakage is determined not only by the breakdown strength of the drift region, but also by the device structure, the specific material properties used, and the possible alternative current leakage paths that may occur when subjected to extreme electric fields.

[0324] For example, a simple metal-semiconductor Schottky barrier exhibits only a finite quantum mechanical barrier height and an asymmetric potential width. In some cases, due to the barrier reduction effect (BLE), tunneling current may cause devices with Schottky barrier junctions at extremely high electric fields to exhibit a lower reverse breakdown voltage than expected.

[0325] The electric field value at breakdown voltage, and Figure 18 The values ​​of low, medium, and high electric fields can vary depending on the materials and device structure used. For example, a low electric field can be less than 100 V / cm or less than 1000 V / cm, a medium electric field can be between 100 V / cm and 1000 V / cm or between 1000 V / cm and 10,000 V / cm, and a high electric field can be greater than 1000 V / cm or greater than 10,000 V / cm.

[0326] Reverse bias current includes hot electrons and quantum mechanical tunneling The superposition of current components results in:

[0327]

[0328] Where T(E) is the quantum mechanical (QM) transmission probability, which varies with the relationship between the incident electron energy and the potential barrier, and E f It is the Fermi energy reference for the conduction band energy. Integration limit. It covers the range of electron injection structures for incident quasi-ballistics.

[0329] Figure 19A and Figure 19B These are the QM tunneling current transmission coefficient / probability T(E) as the injected electron energy relative to the Fermi level (E). F The plots 12000 and 12100 vary with the relationship between (=0). Illustrations 12001 and 12101 show the corresponding energy barriers at the conduction band edges in these examples, and the electrons in each of the tunneling barriers. The curves are calculated using a finite element method for a piecewise approximation of the space potential, combined with a complex transmission matrix for each sub-region, taking into account both the real and imaginary parts of the reflected and transmitted wave functions. Figure 19A With N 漂移 =5e16cm -3 In the case of Figure 9BThe T(E) for the specific band structure shown corresponds to 12010, thus demonstrating significant SB penetration below the maximum barrier value (indicated by arrow 12015), while approaching one above the barrier value. It should be noted that T(E) < 1 holds even for incident energies above the maximum potential value. The triangular potential exhibits an asymmetric barrier, which suppresses QM interference between the reflected and transmitted electron wavefunctions. Arrow 12015 corresponds to the height of the Schottky barrier in this example.

[0330] Introducing a wider bandgap IL between the Schottky metal and the Ga2O3 active region can effectively increase the potential barrier of the rectifier contact. Figure 19B In this study, IL is selected from MgO (Eg = 7.8 eV), and its electron affinity is X. A (MgO) = -1.0 eV, thus providing a maximum barrier of 3.0 eV. It has been found that drift layer doping has a small effect on the T(E) characteristics, while the MgO thickness has a significant impact. Figure 19B The observed oscillatory behavior has a significant impact. The 'slow-opening' T(E) curve 12110 is for a thin MgO layer L... IL The case of (MgO)=5nm, while the steep 'on' and narrow resonance T(E) curves 12120 are for thicker L. IL The case where (MgO) = 10 nm. Referring again to equation (2), T(E) can be used to calculate the reverse leakage current relative to the surface electric field. It has been found that the reverse leakage current is significantly reduced when UWBG IL is introduced, and is therefore advantageous for use in high-voltage diodes, for example, by increasing the forward-reverse (on / off) ratio.

[0331] Figure 19C and Figure 19D The image shows a further example of an IL including a ZnGa2O4(111) oriented layer, which is inserted into a device with: Ni metal / IL = ZnGa2O4 NID 10nm / Ge: β-Ga2O3 5e16cm -3 / TL=Ge:β-Ga2O31e17cm -3 / 1e19cm -3 4H-SiC Si polar substrate. Figure 19C The band structure along the growth direction z is shown in diagram 12200, and... Figure 19D Figure 12300 shows a close-up of the conduction band near the Schottky barrier (at z=0 nm). The IL effectively increases the Schottky barrier, which directly affects the performance of semiconductor devices, such as… Figure 19E and Figure 19F As shown. Figure 19EThe semi-log positive bias IV curves in Figure 12400 show that, in the case of a clean and depleted β-Ga2O3 (-201) surface, the subthreshold slope of the metal-intermediate-substrate (MIS) structure (IL=Zn2Ga2O4) shifts to higher voltages when compared to a Ni / β-Ga2O3 diode (MS curve). Figure 19F Drawing 12500 shows Figure 19E The three cases of linear IV forward bias are compared. Introducing IL also has the effect of increasing the impedance of the device when it is in conduction mode.

[0332] Incorporating an intermediate layer in various implementation schemes offers numerous advantages, including:

[0333] • If the band gap of the intermediate layer is larger than the band gap of the drift region, the turn-on voltage will be increased to a higher value;

[0334] • Reduce the prevalence of defects and / or metal-induced bandgap states (MIGS) between the metal and drift layer, thereby reducing the height of the Schottky barrier relative to its theoretical expectation. Although MIGS may exist between the intermediate layer and the metal layer, its impact on the barrier height is reduced because this interface is separated from the semiconductor / metal Schottky junction interface;

[0335] • Increased reverse breakdown voltage due to both thermionic emission and quantum tunneling; and

[0336] • A wider bandgap intermediate layer spatially separates the metal-induced bandgap states (MIGS) from the active semiconductor oxide material on the surface of the drift region, which helps maintain the Schottky barrier and reduce reverse leakage current.

[0337] The devices and methods disclosed herein utilize a unique insight that suggests that by configuring an intermediate layer to further limit tunneling current, high-field performance under reverse bias can be improved, thereby further increasing the reverse breakdown voltage of the device.

[0338] In any of the examples described in this disclosure, the intermediate layer may include repeating characteristics. Repeating characteristics may be repeating variations in composition (e.g., as in a superlattice structure), or repeating variations in doping concentration (e.g., in the concentration of intriguing dopant material, or defects or vacancies within the crystalline layer).

[0339] Figure 20This is a symbolic cross-sectional view of a multilayer semiconductor device 14000, where the repeating characteristics of the intermediate layer (IL) 1450 or transition layer (TL) 1460 are configured by forming the IL and / or TL as a superlattice or multilayer epitaxial stack. The substrate 1400 is SiC, such as a 4H polytype. The substrate may have a specific adjacent tangent orientation, i.e., a C-plane, A-plane, R-plane, or M-plane as known in the literature. The adjacent tangent may be positively oriented or intentionally offset towards a specific crystal plane. For example, the offset angle of the C-plane may range from 0 to 6 degrees. The transition layer 1460 may be a semiconductor oxide or a non-oxide, or a combination thereof. For example, the transition layer 1460 may include silicon germanium carbide (Si... x Ge y C 1-x-y This allows for in-plane lattice constant and strain tuning of the drift region composition. Other optional TL and IL compositions may include polar or non-polar semiconductors. For example, nitrogen-polar or metallic polar aluminum nitride (AlN) may be formed.

[0340] exist Figure 20 In one example, the superlattice within at least a portion of the IL (or TL) is formed by two repeating sublayers 14010 and 14020 (or sublayers 14030 and 14040 for the TL), the repeating sublayers varying in thickness as they pass through the intermediate layer. In another example, the superlattice may form a digital alloy. In yet another example, the superlattice may be formed by three or more repeating sublayers having constant or varying thicknesses. In various examples, the superlattice may be periodic or aperiodic.

[0341] The use of A-face, R-face, and M-face 4H-SiC enables the realization of α-phase α-(Al) with R3c space group. x Ga 1-x Epitaxial and selective growth of 2O3. Furthermore, throughout the entire alloy range... Inside, α-(Al x Ga 1-x Epitaxial growth of α-(Al₂O₃) is possible. Therefore, TL or IL can include superlattices with the following terms: α-(Al₂O₃) x Ga 1-x )2O3 / α-(Al y Ga 1-y )2O3 and , making This allows the bandgap to be tuned from 4.7 eV (x=0) to 8.6 eV (x=1), while imposing a conduction band discontinuity of approximately 4 eV in electronic confinement and transport designs. (Al) x Ga 1-x )2O3 / α-(Al y Ga 1-yThe lattice constant mismatch between O2 and O3 produces biaxial strain at the heterogeneous interface, which can be controlled by selecting an appropriate layer thickness.

[0342] Figure 21A This is a simplified energy band diagram of a multilayer semiconductor device, shown in Figure 15000. This multilayer semiconductor device has the same characteristics as... Figure 20 The structure is similar to that in structure 14000 and includes an intermediate layer formed by a finite-period superlattice comprising ZnGa₂O₄(111) and β-Ga₂O₃(-201) sublayers. Other numbers of layers and / or other material combinations for the superlattice are also possible. The complete conduction and valence band diagram 15000 shows the stepped barrier caused by the superlattice structure with the intermediate layer and the Ga₂O₃ drift layer. ). Figure 21B It shows that it has an effective and N 漂移 =5e16cm -3 A close-up energy band diagram of the metal / SL IL / drift layer is shown in Figure 15020. In one example, the superlattice structure is configured such that the effective barrier is increased, resulting in a decrease in the quantum mechanical tunneling transmission coefficient and a tuning of the thermionic emission initiation point to a higher turn-on voltage. The increased effective barrier energy also improves the high-temperature performance of the device. As previously discussed, using such a structure to increase the effective barrier energy also reduces the leakage current associated with quantum tunneling across the barrier under reverse bias.

[0343] In fact, although Schottky barriers and UWBG interlayers can be realized in the devices, structures, and methods described in this paper, a phenomenological barrier reduction effect (BLE) exists under the influence of high electric fields. Notably, the BLE is related to both the bandgap energy and dielectric constant of the specific material used. Figure 21C A schematic diagram showing a thickness Energy map 15030 of a semiconductor thin film (oxide 15032), the energy map including band gap (The distance between the dashed lines) The semiconductor wafer is further sandwiched between two metals, 15031 and 15033, thereby forming a zero-bias (V=0) barrier at the heterojunction. Metal-oxide-metal (MOM) structures generate an electric field when a bias is applied. The electric field changes the band diagram as shown in the figure, where the rectangular barrier (V=0) becomes a distorted parallelogram 15035 (e.g., with a certain band curvature) (V<0).

[0344] Electrons injected into the oxide layer from the left metal electrode induce equal but opposite positive mirror charges in the metal. If an electron is injected into the oxide at a distance z > 0, a Coulomb mirror force is generated between charges separated by a distance 2z. for:

[0345]

[0346] This generates electrostatic potential. It is given by the following:

[0347]

[0348] Clearly, the biased MOM oxide barrier space potential consists of the following terms: (i) a rectangular barrier; (ii) a linear electric field; and (iii) a mirror potential, such that:

[0349]

[0350] Figure 22 This shows the results for Ni / 1e16cm, including the ideal. -3 Ga2O3 / n+Ga2O3 / n + The image force band bending of the Schottky barrier in an example of a 4H-SiC device. Figure 23 A close-up of the band bend near the potential peak is shown. For UWBG oxides, sensitivity analysis shows that BLE is comparable to that of available... It is relatively small compared to others.

[0351] BLE causes the peak barrier to be lowered. Reduce by one amount This quantity can be quantitatively expressed in terms of high-frequency (optical) dielectric constant and applied field.

[0352] condition It produces a maximum value and is located far from the heterogeneous interface. place, making

[0353]

[0354] Figure 22 The example shown illustrates the incorporation of BLE into a metal Schottky barrier device. This example case pertains to Schottky barrier metals (SBMs), which include N... 漂移 =1e16cm -3 β-Ga2O3(-201) has a 1250 nm drift region with In nitrogen-doped n+ 1e18cm -3 n+ β-Ga2O3(-201) 1e17cm was deposited on a 4H-SiC substrate. -3The transition layer. Band diagrams were plotted for zero bias (0V) and reverse bias (4V and 8V) to show the variation in depletion width. Figure 23 The results show the surface electric field for a series of applied reverse biases. Figure 22 A close-up view of the conduction band near the Schottky barrier peak. Band degradation and band bending are shown.

[0355] Figure 24 The energy of the effective barrier height reduction was plotted. (Curve 15110 and the right y-axis) and effective barrier width The extracted values ​​(curve 15120 and the left y-axis) vary with the surface electric field. Change. For Due to the depletion field, the built-in electric field is approximately 52 kV / cm.

[0356] Referring again to Equation 2, the tunneling current also depends on temperature and the transmission coefficient of electrons through the barrier, which varies with the surface electric field (see reference). Figure 23 ).

[0357] Figure 25 and Figure 26 The quantum mechanical transmission coefficients were calculated for the following two device configurations: (i) Figure 25 NiSBM / 5e16cm -3 Ga2O3 / n+ 4H-SiC; and (ii) Figure 26 Ni SBM / 5nm MgO IL / 5e16cm -3 Ga2O3 / n+4H-SiC, Figure 26 The device is incorporated into a 5nm UWBG MgO intermediate layer. Transmittance coefficient... Depends on the energy of the incident electron Relative to Fermi energy (E 费米 The magnitude of the potential (taken as zero) depends on the surface electric field. For ranges from 0 to... Figure 23 The maximum potential energy shown By integrating the tunneling current, we can obtain... Figure 27 and Figure 28 The curve in the middle.

[0358] Figure 27 and Figure 28 Draw for Figure 25 and Figure 26 The thermal electron current in each of the two device structures ( ) and tunneling current ( ) for total current ( The contribution of ) to the calculation is shown. Three example operating temperatures, namely Ts =300K, 400K and 500K indicate the operating temperatures discussed above for the thermal performance of oxide / SiC hybrid devices.

[0359] Careful inspection Figure 27 The curves depicted in detail show that at low surface electric fields... Below this threshold, the reverse leakage current of a Schottky barrier diode is primarily determined by the hot electron current component. Above this critical surface electric field... At this point, the temperature-dependent tunneling current dominates and actually outweighs the contribution of thermionic emission. This indicates that the design of the heterojunction Schottky barrier is crucial for modulating and limiting the reverse leakage current in high surface electric field states.

[0360] Figure 28 A similar plot of the calculated reverse leakage current is shown in the case of a diode structure with an intentionally incorporated UWBG 5nm MgO interlayer between the Schottky metal and the Ga2O3 drift region. (See attached image.) Figure 28 The curves show a decrease in the critical surface electric field, with thermionic emission and tunneling components dominating. However, with Figure 27 Compared to the case where IL is absent, the absolute reverse leakage current of both the hot electron and tunneling components is significantly reduced. Therefore, this disclosure shows that the UWBG interlayer can help improve the reverse leakage performance of Schottky barrier diodes as disclosed herein.

[0361] The static dielectric constants (low frequency) of non-oxide and oxide materials were obtained from theoretical calculations and experimental data. and (high frequency) optical dielectric constant Relative to band gap This trend. Density functional theory is used to simulate the band structure and dielectric dispersion of various crystal structures. Figure 29A The figure shows a series of oxide materials, and it indicates that the dielectric constant generally increases with band gap energy. The static dielectric constant decreases (decreases) as the value increases. As shown in the figure, the static dielectric constant... and optical dielectric constant They exhibit similar trends, but with different bends.

[0362] Figure 29B Three cases of applying an electric field across a thin sheet are shown. Compared to The expected variation is observed in the 5mm thick sheet, which contains a selected oxide semiconductor. For large band gaps, a significant barrier reduction was observed, partly due to the weakening of dynamic shielding as the band gap increases. Furthermore, since the time associated with electron transport across the barrier is very short, a high-frequency (optical) dielectric constant should be used to simulate the shielding associated with barrier reduction. An intermediate layer can be used to accommodate high surface electric fields, as described when applied to high-voltage rectifiers.

[0363] Figure 29C Further trends in the advantageous incorporation of intermediate layer oxide materials into semiconductor structures are disclosed. The interface quality given surface states... The quality factor of the interface state parameters can also be estimated by its relationship with the trend of the dielectric constant. For clarity, a definition is provided.

[0364]

[0365] in ,and This represents an ideal surface with a surface state density of 0, and This represents the infinite surface state density. It can also be used to empirically fit the induced bandgap state estimate, thus obtaining the minimum surface state density. Furthermore, it is also related to the dielectric constant through the following terms:

[0366]

[0367] in This allows a typical dipole to span at least one unit cell of the material, which is the case for MgO. .

[0368] Refer again Figure 19C and Figure 21A Both methods employ a heterostructure design that incorporates an intermediate layer (e.g., MgO or other materials) between the metal and Ga2O3 to reduce the surface state density while maintaining the high barrier and low reverse leakage current required for forward bias rectification.

[0369] In another example, the repetitive characteristics of the intermediate or drift layer are configured by introducing repetitive spatial modulation of the doping concentration that varies with the growth direction (“z”). For example, the intermediate or drift layer may have a single material composition, and the conduction band potential can be modified using repetitive spatial modulation of the doping concentration. In one example, the spatial extent of the doped region is very small and has a very high doping concentration. In another example, the doped region extends one or more units of the host composition, but is less than about 10 nm. In yet another example, the doped region includes an extremely high doping concentration, approximately [missing information]. 10 18 -10 20 cm-3 In another example, the doped region is referred to as a delta-doped region, where the thickness of the doped region is approximately 10-20 nm or less. In some cases, the thickness of the doped region is approximately one or more monolayers of the host material composition. For very thin doped region thicknesses, a thickness similar to that of a bulk material can be defined. Related equivalent two-dimensional doping density , making

[0370]

[0371] In other words, Equivalent to surface density .

[0372] In one example, the repetitive spatial modulation of doping concentration can have a homogeneous epitaxial superlattice type structure similar to the superlattice described above, except that in this example, the sublayers will have a constant composition but different doping concentrations, rather than the sublayers having different compositions.

[0373] In another example, the repetitive characteristics of the intermediate layer include both repetitive spatial modulation of the doping concentration and repetitive variations in the composition of the intermediate layer.

[0374] Figure 30 The figure shows an example of a homoepitaxial delta-doped superlattice (δ-SL) forming the drift region of a Schottky barrier (SB) diode 16000. Nickel metal is used to form the SB (“SB metal”) with the delta-doped SL drift region (“δ-doped SL”), which is formed by using a light dopant of Sn, Ge, or Si in the bulk β-Ga₂O₃ composition (i.e., using Ga₂O₃ throughout the drift region). Figure 16100 shows the areal density doping of two different periods of a periodic [δ-doped Ga₂O₃ / NID Ga₂O₃] superlattice (δ-SL). The superlattice extends 2 mm, thus forming a drift layer of the monolithic structure (Ni / δ-doped SL drift / n+TL / n+4H-SiC). The high work function Ni metal is in direct contact with the first NID Ga2O3 layer of the δ-SL, thereby maximizing the SB potential. As an example, two δ-SL periods are selected, and conduction band diagrams are plotted as a function of the growth direction. Figure 16100 shows the representation including... The first δ-SL 16110 of the 19 cycles and including The curves for the second δ-SL 16120 over four periods. The SL doping ratio is defined as:

[0375]

[0376] So that the first and second δ-SL respectively have 20 and 80.

[0377] The band structure again exhibits as a Schottky barrier diode, where the effective bulk doping densities of the first and second δ-SLs are respectively... and .

[0378] Compared to continuous co-doping growth of Ga2O3, the advantage of using periodic delta-doping in the drift region of the active region to achieve an effective n-type doping level for a similar structure lies in the potential for higher epitaxial material quality. Generally, n-type impurities are doped at 1e17 cm⁻¹. -3 Higher levels of doping within the range of 5 μm or above can lead to a relatively lower crystal quality during co-doped epitaxial growth. Furthermore, reactive oxygen species may interact with Si, Ge, or Sn dopant sources in the growth reaction chamber, forming potentially undesirable byproducts. Periodicity and short doping bursts during epitaxial growth allow the dopant to be confined to small layers, followed by NID material growth, which often corrects any crystal distortions caused by the incorporation of impurity atoms into the Ga₂O₃ lattice. This periodic doping method further improves the crystal quality of the effectively doped drift region for applications in thick drift regions of 5 μm and above.

[0379] Figure 31 This demonstrates how to achieve the objective using δ-SL. Possible design space. Example configuration uses a single delta-doped layer of one length. It is located at three different 2D surface doping densities, namely ( = 2.2e11cm -2 (1e17cm -3 ), 1.0e12cm -2 (1e18 cm -3 ) and 2.9e12 cm -2 (5e18 cm -3 Furthermore, it can interpolate the surface doping density between curves.

[0380] Figure 32A and Figure 32B Presented Figure 30 The forward bias IV curves of a Schottky barrier diode are shown, with two examples of this diode incorporating the δ-SL drift region, which has... and 2.5e16cm -3 ,in Figure 32A Use a semi-log scale, and Figure 32B Use a linear scaling factor. The subthreshold slope is comparable, while for As expected, the differential resistance is higher.

[0381] In another example, the intermediate layer is formed as including at least one quantum well (QW) sublayer sandwiched between wider bandgap layers, the QW being formed by electronic confinement due to the potential wells thus created. Within the narrow bandgap QW layer, the QW has at least one quantized discrete energy level. In one example, the quantum well sublayer is configured such that resonant tunneling current occurs only for a specific bias configuration; that is, the quantum well sublayer is configured to have bias-dependent tunneling current. In one example, this can be used for voltage-dependent switches or bistable switches that generate pulsed currents. Such a device can be a resonant tunneling diode with two terminals exhibiting a nonlinear IV response. The nonlinear IV response can have the property of negative differential resistance, which can be advantageously used in switching or oscillator configurations of circuits.

[0382] In another example, the two-terminal switch can be used as part of a power converter to control the pulse width and duration of the current.

[0383] The following describes an example of a vertically conducting resonant tunneling diode. A double-barrier intermediate layer incorporated into a single QW uses β-(Al) 0.2 Ga 0.8 )2O3 / β-Ga2O3 / β-(Al 0.2 Ga 0.8 The β-Ga₂O₃ heterostructure is formed, which is further deposited on an n-type β-Ga₂O₃ drift layer, which is further deposited on a SiC conductive substrate. 0.2 Ga 0.8 The thickness of the 2O3 barrier is thin enough to enable electron tunneling, for example, L₂O₃. 势垒 =1-10nm or equal to (Al) 0.2 Ga 0.8 The unit multiple (e.g., 1, 2, 3, 5, or 1 to 10 times) of the β-Ga₂O₃ crystal cell along the growth direction. The thickness of the β-Ga₂O₃ layer, including the QW, can be selectively n-type doped or NID, and the thickness is approximately one monolayer to approximately ten monolayers, where one monolayer is defined as half the unit cell size along the epitaxial growth direction. Because β-Ga₂O₃ ( ) and 4H-SiC ( Both have relatively large effective electron masses (and are essentially isotropic in terms of crystal momentum), thus quantum confinement occurs even within shallow potential wells in physically thin QW layers. As an example, Figure 33A and Figure 33B The two electric field strengths applied to the structure along z (i.e. The case illustrates a bi-heterogeneous structure including a thin QW: α-(Al)x Ga 1-x )2O3 / QW α-Ga2O3 / α-(Al x Ga 1-x α-Ga₂O₃ / drifted α-Ga₂O₃. The QW thickness was chosen to be 1 nm so that only two quantum confinement states were realized within the potential well, with a barrier component x=1 to provide the highest barrier. Wider QW thicknesses support an increased number of quantum confinement states. Lowest energy quantum confinement electron spatial wavefunction distribution. The energy levels are plotted relative to the quantized energy levels within the QW. Above-barrier states are also plotted to represent the propagation states. To achieve significant barrier penetration of the electron wavefunction, the barrier thickness can be approximately 1 nm or less. Such resonant tunneling structures require precise epitaxial growth to accurately control the layer thickness and achieve resonance.

[0384] The advantage of the devices and structures described herein lies in the fact that SiC has a thermal conductivity approximately two orders of magnitude higher than Ga2O3, which advantageously allows heat generated in the oxide drift layer to be rapidly conducted away from the device through the SiC substrate. The self-heating effect of conventional all-Ga2O3 power devices utilizing thick β-Ga2O3 substrates constitutes one of the most challenging problems for practical applications in high power density technologies. Compared to all-SiC devices using thick SiC substrates, the Ga2O3 substrates in conventional devices exhibit low thermal conductivity, thus requiring other forms of thermal management, such as substrate thinning and integration with diamond heat sinks. This disclosure describes devices, structures, and methods that utilize UWBG oxide materials and integrate them with SiC substrates with extremely high thermal conductivity and low resistance to simultaneously improve the electrical performance of the device. In other words, it achieves a simultaneous solution to both the electrical and thermal performance of the device. In terms of overall device performance, this represents a significant improvement over thermally insulating and electrically conductive β-Ga2O3 substrates.

[0385] A further advantage of using hybrid integrated semiconductor oxide-SiC materials to form Schottky barrier diodes in this disclosure is the improved electrostatic field distribution within the device.

[0386] Figure 34 A drawing 900 shows a simulated electric field line 915 (and associated potential line 910) of a vertically multilayer semiconductor device configured similar to... Figure 1 The illustrated device 100 includes an isolation layer 180 surrounding the metal layer 130, which serves to mitigate surface currents and modulate the electrostatic vector field. Figure 34 The electric field lines 915 and equipotential lines 910 shown indicate the expected results for the potential difference between the conductive substrate 110 and the metal layer 130 in the range of about 100 V to about 10,000 V.

[0387] In this example, a Ni metal patterned contact (metal layer 130) is positioned on a β-Ga₂O₃ active region 120, which is disposed on a conductive 4H-SiC substrate 110. An isolation layer 180 is selected from a low dielectric constant composition, such as Al₂O₃. The device is surrounded by a vacuum or air. The contact (metal layer 130) is forced to a positive potential (+V), while the conductive substrate 110 is forced to a negative potential (-V).

[0388] As can be seen from the inspection, electric field lines 915 point from the surface boundary of the rectangular contact to the conductive substrate surface 110, thus forming equipotential lines between the metal layer 130 and the substrate 110. Drawing 900 shows a high concentration of electric field in the region of the isolation layer 180 and the active region 120 near the corners of the metal layer 130. As will be understood, in some cases, the electric field... The intensity may become so concentrated that it exceeds the breakdown electric field of the host material (e.g., as shown in the image). Figure 2B (As shown). In practice, sharp corners at conductor features concentrate the electric field, and if possible, they can be rounded. Fabrication methods used for metal patterning (such as lift-off or damascene) typically cannot produce perfectly circular features in a vertical cross-section. However, the in-plane (top surface) patterning of contacts can be manipulated via lithographic expression to form circular pads or rounded corners, which can also help reduce the electric field density.

[0389] It should be noted that the isolation layer 180 is made of a material with a band gap significantly larger than that of the oxide active drift layer. Otherwise, the isolation layer 180 would not be able to effectively isolate the material. Low electrical conductivity also determines the selection of a suitable material for the isolation layer 180. Compatibility with the UWBG active drift region 120 is another factor in the material selection for the isolation layer 180. In some cases, the isolation layer 180 also possesses a low dielectric constant, allowing for a reduction in the electric field strength within the main isolation layer 180. (See again...) Figure 29A The example selection of materials in the text shows the trend of dielectric constant and bandgap energy, and there is a range of suitable materials that are compatible with Ga2O3 active drift layers and can be used as isolation layer 180 materials.

[0390] In some examples, the isolation layer 180 may comprise one or more materials with lower dielectric constants and higher band gaps compared to the drift layer semiconductor. If the drift layer comprises Ga2O3, then isolation layer compositions of MgO and Al2O3 are possible. While SiO2 possesses even better isolation layer properties, practical deposition methods (e.g., PECVD) produce hydrogenated H:SiO2 films with amorphous properties and characteristics significantly different from single-crystal quartz (α-SiO2). Atomic layer deposition of Al2O3 constitutes one of the most advantageous methods for producing high-quality amorphous and conformal coatings while still exhibiting a larger effective band gap and lower dielectric constant relative to Ga2O3. Amorphous materials (Al2O3) deposited by ALD may also be used. x Ga 1-x )2O3 (for x>0), or other materials as described herein.

[0391] Referring again to the metal contact components on the tabletop, Figure 34 The electric field surrounding contact 130 is shown to be relatively unbounded. An improved high-voltage contact arrangement can be implemented to modulate the lateral range of the electric field while keeping the contact area between 130 and the drift region constant.

[0392] Figure 35A and Figure 35B Top view and symbolic cross-sectional view of a vertical multilayer semiconductor device 1000 according to an exemplary embodiment are shown, which incorporates a lateral electric field plate arrangement to change the vector electric field of the device.

[0393] In this example, device 1000 includes as previously described (e.g., in...). Figure 1 The substrate 1010 of device 100 (in the device 100) Figure 35B The system comprises an epitaxial active region 1020 (e.g., a drift layer) and a metal layer 1030. In this example, an isolation layer 1080 is formed on top of the epitaxial active region 1020 and surrounds the metal layer 1030. Formed on the top surfaces of the metal layer 1030 and the isolation layer 1080 is a field plate arrangement, in the form of a field plate layer 1090, which is formed of metal and has a central aperture 1091, the size and shape of which are designed to expose the metal layer 1030. In this example, both the metal layer 1030 and the field plate layer 1090 have a circular configuration, and the isolation layer 1080 has a ring or annular configuration surrounding (or enclosing) the metal layer 1030. The field plate layer has an outer diameter d. FP And above the isolation layer 1080, there is a w FP The cantilever section.

[0394] In this example, metal layer 1030, isolation layer 1080, and field plate layer 1090 each have complementary circular or annular configurations, which helps to minimize edges that might otherwise form stronger electric fields. In other examples, the Schottky barrier metal of metal layer 1080 may have an n-gonal (e.g., rectangular, rounded elongated stripe, hexagonal, etc.) configuration, and other layers may have complementary configurations as needed. Figure 35B The diameter of the Schottky barrier metal layer 1030 is shown in the figure. Diameter and ring width of the 1090-layer plate and And the thicknesses of the active region 1020 and the isolation layer 1070 are respectively and .

[0395] In the example, the active region 1020 will have a dielectric constant. and band gap energy Furthermore, the isolation layer 1080 will have a dielectric constant. and band gap energy In the example, the materials of the active region 1020 and the isolation layer 1080 are selected such that... and .

[0396] We will now discuss the design principles applicable to the design of the isolation layers and field plates described in this paper. Consider a parallel metal plate capacitor separated by planes of thickness t, where the dielectric is positioned between metal plates of a finite lateral extent of area A. Capacitance C p Defined as: To minimize the overhang of the field plate w FP Effective parasitic capacitance C p You can choose low k (i.e., low k) Materials and / or increased isolation layer thickness t 隔离 Furthermore, low-k dielectric materials can be compared with Ga2O3 using the following relationship:

[0397]

[0398] If using Thickness, then (C p / A) =89fF / mm 2 In order to achieve a relative reduction in the capacitance density of the overhang to the target value. This device can be used with a thickness of Al2O3.

[0399] In the example, the field plate layer 1090 and the SB metal contact 1030 can be formed of the same metal, such as the following high work function metals or alloys: Cu, Te, Be, Rh, Co, C, Ni, Au, Ir, Pd, Pt, Se, Os, and combinations thereof (see reference). Figure 11A In another example, metal layer 1030 may be formed of a high work function metal, including but not limited to Cu, Te, Be, Rh, Co, C, Ni, Au, Ir, Pd, Pt, Se, Os, and combinations thereof, while the field plate layer 1090 metal may be selected from a non-high work function metal, such as Al, Ti, Mo, W, etc. High melting point metals may be advantageous, for example, for high-temperature operation (e.g., above 300°C).

[0400] The ohmic contacts of the substrate can also include high work function metals to achieve synergistic processing of the front and back sides of the device structure. For example, Ni can be used as the SB metal on the drift layer surface, while Ni can serve as the ohmic contact of a highly doped SiC substrate. Furthermore, silicides can be used to form low-resistance ohmic contacts on the substrate. Silicon can be precipitated from the SiC substrate to form silicides through thermal annealing of the contact metal. For example, Ni can form Ni... x Si 1-x And similarly, Ti can form Ti x Si 1-x Furthermore, multiple metal layers can form ohmic contacts on the substrate, such as SiC / Ti. x Si 1-x / Ti / Al.

[0401] Some examples of field plate metal layer 1090 / isolation layer 1080 / Schottky barrier metal 1030 / wide bandgap oxide drift layer 1020 / substrate 1010 / ohmic contact layer structure are:

[0402] Al / Al2O3 / Al / Ni / Ga2O3 / 4H-SiC / Ni / Al

[0403] Cu / Al2O3 / Al / Ni / Ga2O3 / 4H-SiC / Ni / Cu

[0404] Cu / Al2O3 / Al / Ni / NiO / Ga2O3 / 4H-SiC / Ni / Cu

[0405] Cu / Al2O3 / Al / Ni / Ni x Cu y O / Ga2O3 / 4H-SiC / Ni / Cu

[0406] Al / Al2O3 / Al / Ni / Pd / Ga2O3 / 4H-SiC / Ni / Cu.

[0407] In one embodiment, the isolation layer 1080 is formed of a bandgap material that is wider than that of the drift layer 1020. In one example, the isolation layer 1080 is formed of Al2O3. In another example, the isolation layer 1080 is formed of SiO2.

[0408] In other examples, the isolation layer may be a wide-bandgap oxide having p-type conductivity. For example, the oxide used for the isolation layer may include nickel oxide, nickel-copper oxide, copper oxide, tellurium oxide, or osmium oxide. The isolation layer may also include a portion of a metal oxide formed from SB metal.

[0409] In other examples, the intermediate layer may also have p-type characteristics, and may or may not have a larger band gap than the drift layer.

[0410] Figure 36 A drawing 1100 shows a simulated electric field distribution 1110 of a multilayer semiconductor device, which is configured similarly to... Figure 35A and Figure 35B The illustrated device 1000 incorporates features previously described (e.g., regarding...). Figure 35A and Figure 35B (The arrangement of the field boards.)

[0411] As can be seen from the inspection, this includes the outer diameter (e.g., Figure 35B d in FP ) and the overhang above the isolation layer 1080 (e.g., Figure 35B w in FP The field plate layer 1090 acts to reduce the concentration of electric field lines near the vertical boundary or corner of the metal layer 1030 in contact with the surface of the active region. Compared with the case without the field plate layer 1090, the equipotential lines 1110 between the interface of the contact metal 1030 and the active region 1020 are significantly flatter. The concentration of electric field lines 1115 is also significantly reduced near the contact area (metal layer 1030) in direct contact with the active region 1020. The low-k isolation layer 1080 also acts to laterally extend the equipotential lines, thereby reducing the maximum electric field intensity below the field plate layer 1090. In addition, the conductive channel formed between the metal layer 1030 in contact with the active region and the laterally disposed conductive substrate 1010 exhibits a basically uniform electric field. Without being limited by theory, the electric field concentration is reduced in the region adjacent to the metal layer 1030 (especially in the corner region near the interface between the active region 1020 and the metal layer 1030, such as...). Figure 1 The electric field density in the interface region 140 shown can improve device performance, for example by reducing the peak electric field within the device to well below the critical breakdown field of the bulk drift material.

[0412] For a fixed vertical device configuration, the efficiency can be improved by proportionally adjusting the contact area 140 to a larger area, or by reusing multiple parallel diodes. Figure 1 The current-carrying capacity of the semiconductor device structure shown is illustrated. By distributing the vertical current among multiple parallel-interconnected diodes, a trade-off can be achieved between the consumed epitaxial area, the maximum vertical current capacity, and the thermal effect.

[0413] Figure 37A and Figure 37B Horizontal and vertical cross-sectional views of a composite semiconductor device 1200 having multiple unit cells 1250 are shown respectively. This composite semiconductor device is similar to Figure 35A and Figure 35B The illustrated vertical multilayer semiconductor device 1000. Figure 37A The top view cross section is cut through section AA, thus representing a plane parallel to the substrate surface that intersects the circular metal layer 1030 and the isolation layer 1080. Figure 37B The vertical cross-sectional view in the figure relates to the features of an optional continuous top contact metal 1220 interconnected with multiple Schottky barrier (SB) metal contacts 1030, wherein the top contact metal 1220 serves as a top field plate 1090. Active regions 1020 (e.g., drift regions) are disposed on the substrate 1010 and the ohmic contact 1240. The metal layer 1030 includes a plurality of circular metal regions. An isolation layer 1080 extends across the composite semiconductor device 1200 and surrounds each of the circular metal regions of the metal layer 1030. Active regions, such as drift layers (e.g., Figure 35B The active region 1020 shown may be located between the metal layer 1030 and the substrate (e.g., Figure 35B Between the substrate 1010 in the middle, and extending across the composite diode device 1200. Field plate layer 1220 (e.g., Figure 35B The 1090 (in the model) can be formed above the metal layer 1030 and can also extend across the composite semiconductor device 1200. Each unit cell 1250 has a circumference 1092, which can be correlated with the outer diameter of the field plate and the overhang size required for each unit cell to reduce electric field concentration at each point in the circular region of the metal layer 1030. Therefore, in this example, the dimensions of the field plate layers 1090 / 1220 are a limiting factor regarding the number of unit cells that can be arranged within a given surface area.

[0414] In various examples, the width of each unit cell can vary between 1 micrometer and 100 micrometers, or from 100 micrometers up to 1 cm. In these examples, each unit cell will share a common substrate (1010) and drift layer 1020. In these examples, high-resistivity edge capping regions can be formed between each unit cell. In these examples, the capping regions are formed as physical trenches or channels extending down into the active region 120 and forming the boundary between each of the unit cells 1250. In another example, the capping regions can be formed by ion implantation, wherein resistive trenches or channels are formed in the oxide material of the active region 1020.

[0415] In various implementation schemes, in forming an epitaxial active region (e.g., Figure 1 The active region 120 or Figure 35A and Figure 35B Following the active region 1020 and in any additional epitaxial layers formed above the active region, a metal layer is deposited using a metal deposition process (such as sputtering, thermal evaporation, electron beam deposition, or by electrodeposition). Figure 1 Metal layer 130 or Figure 35A and Figure 35B (Metal layer 1030 in the text). That is, the metal deposition process is non-in-situ compared to the epitaxial oxide deposition. As will be understood, this requires a process change from the epitaxial oxide layer deposition process to the metal deposition process. The topmost surface of the final deposited epitaxial oxide can be protected by limiting exposure to a contaminated environment prior to metal deposition. This can be achieved by configuring a separate deposition chamber with a vacuum wafer transfer mechanism. In other methods, metal deposition can be performed in the same processing chamber as oxide deposition once the detrimental material has been removed from the chamber. In some cases, metal can be epitaxially deposited in an epitaxial oxide deposition chamber, as further described herein.

[0416] According to some implementation plans Figure 38An intermediate product 1370 is illustrated for a process flow used to form the vertical multilayer semiconductor device disclosed herein. In the illustrated example, according to some embodiments, the intermediate product 1370 includes an epitaxial active region of oxide material forming a Schottky barrier junction and a metal layer 1330. Specifically, the intermediate product includes a substrate 110, an active region 120, an epitaxial metal layer 1330 (e.g., formed using MBE, ALD, or MOCVD) or a non-epitaxy metal layer (e.g., formed using sputtering, pulsed laser deposition, or thermal evaporation of metal), and an optional patterned contact layer 1351. The lattice constant and / or crystal structure mismatch between the final surface reconstruction of a particular metal and oxide surface plays a significant role in the metal-oxide interface quality. In one example, the thickness of the (epitaxy) metal layer 1330 is between 1 angstrom and 100 angstroms. The epitaxial metal or the first deposited metal layer may be relatively thin, and another metal layer may subsequently be deposited to increase the total layer thickness. The second metal deposition step may include a metal with a different composition than the first metal, or the same metal. In some cases, a non-epitaxy metal layer may be used to form a Schottky barrier junction with the epitaxially deposited active region 120. In some cases, a transition layer (e.g., such as...) may be deposited between the substrate 110 and the drift layer 120. Figure 4 (As shown in structure 400 and described above). In some cases, an intermediate layer may be deposited between the drift layer 120 and the (epitaxy) metal layer 1330 (e.g., as shown in structure 400 and described above). Figure 8A (As shown in structure 800 and described above).

[0417] According to some implementation plans Figure 38 An example of a multilayer semiconductor device 1407 is shown, which includes an epitaxial drift layer of oxide material and a metal layer forming a Schottky barrier junction. Semiconductor device 1407 includes a bottom contact layer 1452, a SiC substrate 1410, an epitaxial active region 1420, opposing in-device field capping regions 1471, opposing inter-device isolation regions 1475, a top passivation layer 1476, an isolation layer 1480, a field plate layer 1490, and a guard ring 1495. In some cases, the SiC substrate 1410 includes a body substrate layer and a surface layer (e.g., Figure 1 The substrate 110 is a composite substrate consisting of a bulk substrate layer 112 and a surface layer 114, wherein the surface layer comprises single-crystal SiC.

[0418] Metal layer 1430 can be an epitaxial metal layer or a non-epitaxy metal layer. In the example, isolation layer 1480 is formed of a suitable oxide material, such as Al2O3, NiGa2O4, AlCu2O4, GaCu2O4, MgO, ZnGa2O4, or SiO2. In the example, isolation layer 1480 is formed to have a layer thickness of 100 nm to 300 nm.

[0419] In some cases, metal layer 1430 is thinner than field plate layer 1490. In various examples, the top metal layer (e.g., 1430, 1490, and / or 1495) may be formed of Ti / Al, Al, Ni, Mo, Pd, or combinations thereof. In some cases, the device does not include an intermediate layer (e.g., as...). Figure 1 Structure 100 in the middle, or Figure 4 (as shown in structure 400), and a protective ring 1495 may be deposited on the epitaxial oxide layer. In this example, the top passivation layer 1476 is formed of a suitable oxide material (such as Al2O3 or SiO2).

[0420] Used to form a reference Figure 38 and Figure 39 Example process flows for the vertically multilayer semiconductor devices shown and described herein are described in detail in commonly assigned U.S. Patent Application No. 18 / 628,178, filed April 5, 2024, which is incorporated herein by reference in its entirety. The processes described herein can be used to fabricate any device structure described herein (e.g., Figure 1 Structure 100 in Figure 3A and Figure 3B Structure 300 in Figure 4 Structure 400 in Figure 6 Structure 600 in Figure 6, structure 800 in Figure 8, Figure 35A and Figure 35B Structure 1000 and Figure 37A (Structure 1200 in the middle).

[0421] Figure 40 This is an example of a symbolic cross-sectional view of a vertical multilayer semiconductor device configuration Y100 adopted to simulate thermally induced heating effects. In the thermal model of this example, it is assumed that the semiconductor device configuration Y100 is continuous in the left-right direction (i.e., semi-infinite) without lateral boundary conditions.

[0422] from Figure 40 The bottom of the semiconductor device Y100 is generally moved upward (in the positive z-direction), and the semiconductor device configuration Y100 includes a horizontally extending back drain metal ohmic contact layer F1 (cathode), the lower surface of which (i.e., S1) is maintained at a temperature The next layer comprises a substrate Y110 (F5). Thermal modeling is performed in various examples illustrated below to compare different substrate materials, such as highly doped (n-type or p-type) SiC or Ga2O3. Under the first-order approximation, the doping level and type do not significantly alter the thermal conductivity of the host material.

[0423] Formed above the substrate Y110 is an epitaxial active region Y120 (F6+F7+F8) comprising a semiconductor oxide material. In this example, the epitaxial active region is modeled as three regions: a central region F8 and opposing boundary regions F6 and F7. This division of the active region Y120 into three regions allows for the separate characterization of the temperature performance characteristics of the central region F8 (see below for example). Figure 44 Due to the large forward conduction channel, the central region F8 is where most of the ohmic heating occurs. Regions F7 and F6 represent semiconductor regions that experience less or no vertical current flow.

[0424] Located above the central region F8 of the epitaxial active region Y120 is the Schottky barrier metal layer Y130 (in region F3), which forms a Schottky barrier junction between the metal layer Y130 and the central region F8 of the epitaxial active region Y120.

[0425] Located above the boundary regions F6 and F7 of the epitaxial active regions are the corresponding isolation layer Y180 boundary regions F2 and F4, which are formed of a bandgap material with a wider band than the semiconductor oxide material forming the epitaxial active region Y120. Generally, isolation layer regions F2 and F4 may include components with lower thermal conductivity than the active regions Y120 (F7, F8, and F6). Extending above the Schottky barrier metal layer Y130 and partially above the isolation layer Y180 regions F2 and F4 is the field plate layer Y190 (in region F9), which is formed of a low, medium, or high work function metal. A centrally located metal interconnect F10 extends upward from the field plate layer Y190 to an overlying horizontally extending top contact bus metal layer F11 (anode). In one example, the field plate layer Y190, the metal interconnect F10, and the top contact metal layer F11 may be formed of Al. In another example, the conductivity type can be changed to the opposite conductivity type, in which case the top bus metal layer F11 will be used as the cathode. As will be understood, the thermal conductivity performance will be equivalent.

[0426] In this example, the exposed bottom surface of the top contact busbar metal layer F11, the exposed side surface of the interconnect F10, the exposed side and top surfaces of the field plate layer Y190, and the exposed top surfaces of the boundary regions F2 and F4 of the isolation layer Y180 are all assumed to be at ambient air temperature. (like Figure 40(As depicted). In this way, these exposed surfaces are modeled to allow heat generated by device configuration Y100 to be transferred by convection to the “air”. This will be considered a worst-case scenario, because in other examples the “air” region would be a thermally insulating dielectric material (e.g., a polymer planarization layer), while minimally transferring heat from device configuration Y100 (e.g., interconnects F10 are implemented as wire bonds in the form of bonding pads connected to contact bus metal layers F11). Additionally, it is assumed that the lower surface S1 of the metal contact region F1 remains at a temperature... And assuming that the upper surface of the metal contact bus region F11 remains at a temperature .

[0427] Figure 41 A plot Y200 showing the thermal conductivity as a function of temperature for various semiconductor materials is shown. This plot can be used for temperature modeling of a vertical multilayer semiconductor device configuration Y100, as described below. The plot shows the thermal conductivity profiles of semiconductor materials, including the thermal conductivity profile Y210 for the potential substrate material 4H-SiC and the thermal conductivity profile Y220 for n+-doped (Sn) Ga2O3; and the thermal conductivity profile Y230 for unintentionally doped Ga2O3, which in one example may be used to form the epitaxial drift layer Y120 of the device configuration Y100, such as... Figure 40 As shown.

[0428] As can be seen from the examination, the thermal conductivity of all the depicted materials decreases with increasing temperature. At an operating temperature of 200°C, the thermal conductivity of SiC is at least five times greater than that of the depicted Ga2O3-based materials. This represents one of the main advantages of the hybridization method disclosed herein.

[0429] In the example, thermal modeling includes simulating the initial application of approximately 1 volt to the top contact layer F11 while the drain contact layer F1 remains at ground potential. The voltage in the central region. In this example, the applied simulated voltage corresponds to the initial current of 65 amps conducted between the top contact layer F11 and the drain contact layer F1 of the model configuration Y100. Furthermore, the temperature of the surface S1 of the configuration model Y100... The temperature is set to 25°C, and the temperature of surface S2 is... The temperature was set to 75°C. The model was then allowed to evolve to an equilibrium state, where the semiconductor device was configured to conduct steady-state forward current via Y100.

[0430] The model is calculated using the finite element method, which constructs a piecewise representation of the spatial distribution of material properties within a high-density tensor mesh. Heat transfer across the entire 2D model structure is solved using parabolic partial differential equations.

[0431]

[0432] Where Q represents heat transfer and T represents temperature. It is specific heat. It is thermal conductivity, and It refers to the material density. Each parameter represents the density of each element. A function of time and spatial location.

[0433] The simulation workflow includes the following steps or blocks: (i) creating a 2D physical model for steady-state or transient simulation; (ii) applying a spatial mesh algorithm to discretize the model; and (iii) processing matrix elements. (iv) Assign a value; (v) Specify the internal heat source Q within the geometry; (v) Specifies the ambient temperature, convective heat transfer coefficient, and radiative heat flux; (vi) Specifies the emissivity ε and Steffen-Boltzmann constant σ for each material in the structure. Once the model is fully specified, the simulation heat flux algorithm is initialized with the initial temperature or an initial guess.

[0434] Now for reference Figure 42 The temperature contour shaded plot Y300 shows the steady-state temperature distribution obtained after thermal modeling of a semiconductor device configuration Y100, which in this example includes a highly doped Ga2O3 substrate Y110 (e.g., Figure 41 The material Y220) and the Ga2O3 epitaxial active region Y120 (e.g., Figure 41 The material Y230). The Schottky barrier metal layer Y130 was chosen to be a high work function metal, such as Ni, and the Ga2O3-based epitaxial active region Y120 is n. - Doped. In other examples, the Schottky barrier metal layer Y130 can be selected from other high work function metals, such as Pt, Pd, Cu, or Os. In alternative configurations, the Ga2O3 epitaxial oxide layer is p - The doped Schottky barrier metal layer Y130 can be selected from low work function metals, such as Al or Ti. The thermal conductivity of most of the chosen metals does not significantly alter the conclusions of this paper. The internal heat source within structure Y300 is generated by the resistive heating effect caused by the vertical current (e.g., a constant current) flowing within region F8 of drift region Y120.

[0435] As from Figure 42As can be seen, the highest temperature region Y310 is within the central region F8 of the drift layer Y120, reaching approximately 400°C, with the temperature gradient extending laterally into the contacts and field plate Y190. The top contacts and isolation layer are coupled to open surfaces to allow for air convection. Even so, the top contact Y190 rises to approximately 300°C, meaning that refractory metals may be required for stability (or reliability or durability). Generally, metal junction temperatures exceeding 250°C are problematic for high-power and high-reliability applications. For this example model, it can be concluded that the materials comprising the Schottky barrier metal layer Y130, the isolation layer Y180, and the field plate layer Y190 will need to operate at temperatures in the 250°C to 300°C range, which is expected to adversely affect reliability.

[0436] The operation of the forward-biased diode is modeled as follows: the central epitaxial active region Y130, region F8, conducts current like a current "filament," in which the heating power will follow... Relationship, among which It is the current flowing through that region and It is the effective resistance of the region, determined by the doping concentration.

[0437] Refer again Figure 42 The steady-state temperature of the interface between the Ga2O3 drift region and the substrate junction is also shown to be approximately 350°C, with a gradient extending toward the back contact, which is maintained at 25°C. The low thermal conductivity of the Ga2O3 substrate leads to this self-heating effect in the active region.

[0438] and Figure 42 The structure is opposite, Figure 43 The substrate is now replaced with a high thermal conductivity substrate. A temperature contour shading plot Y400 is shown, illustrating the effect on... Figure 42 The temperature distribution obtained after thermal modeling of semiconductor devices configured with Y100, with the exception of those using SiC substrates (e.g., see...). Figure 41 The material Y210) replaced Figure 42 The structure adopted in the paper is based on a Ga2O3 substrate.

[0439] and Figure 42 The modeling results shown are the opposite. Figure 43 The results show that the highest temperature in the central region F8, and the highest temperature in Y410, are in the range of 200°C to approximately 220°C, which is significantly lower than... Figure 42 The highest temperature at which the structure with a Ga2O3 substrate was modeled. It should be noted that... Figure 42 and Figure 43Both utilize the same heat source. Furthermore, the materials comprising the Schottky barrier metal layer Y130, the isolation layer Y180, and the field plate layer Y190 operate at approximately 175°C, which is more advantageous for conventional heat dissipation methods. The SiC substrate, with its high thermal conductivity, provides efficient heat dissipation in the active region and offers lateral thermal management throughout the structure. The lower temperature achieved through the improved thermal management described in this paper also relaxes the constraints on the types of metals that can be used and advantageously impacts device reliability.

[0440] Many material parameters are temperature-dependent. Generally, thermal conductivity, heat capacity, and band gap energy decrease with increasing temperature. Thermally activated carrier generation also increases the number of free carriers and reduces resistance in semiconductors. Conversely, in metals, resistance typically increases with increasing temperature. Therefore, when heat dissipation is limited, Figure 42 The self-heating effect disclosed in the paper could lead to thermal "runaway" and premature device failure.

[0441] The transient thermal response of the model reveals further advantages and disadvantages of coupling oxide drift regions to high and low thermal conductivity substrates.

[0442] refer to Figure 44 The transient response of device models Y300 and Y400 to two current pulse cycles generated in the current filament region F8 is shown. Figure 42 (i.e., having a Ga2O3 substrate) and Figure 43 (That is, with a SiC substrate) The two device configurations shown provide the integrated thermal intensity of region F8 of the drift layer Y120. The plot Y500 shows the time (in microseconds) variation of the two device configurations, assuming the pulse current input to region F8 has a 5 Conduction period and 5 Off-time (with 50% duty cycle). Upon examination, although both devices have the same Ga2O3 drift layer and top contact structure, the maximum thermal intensity Y510 of the SiC-based device is approximately three times lower than the maximum thermal intensity Y520 of the Ga2O3-based device. Furthermore, the thermal intensity of the SiC-based device is able to [perform better] in the next 5 [days / months / years]. The device recovers to zero Y530 before the second pulse begins, which contrasts with the recovery Y540 of devices based on Ga2O3 substrates.

[0443] As will be understood, the increased time required for Ga2O3-based semiconductor devices to dissipate heat compared to SiC-based devices will increase the minimum dwell time required for any switching application. Alternatively, if this minimum dwell time (or off-time duration) is insufficient, Ga2O3-based devices may suffer from thermal "runaway".

[0444] Figure 45 A symbolic cross-sectional view of a vertical multilayer semiconductor device configuration Y600, adopted to simulate the thermal performance of a mesa-structured semiconductor device, is shown. In this example, the epitaxial drift layer Y620 (F6+F7+F8) of the device model configuration Y600 has been formed as a mesa structure with sloping walls extending upwards from the substrate Y610 (F5), and the region outside the mesa is assumed to be at ambient air temperature. (like Figure 45 (As shown).

[0445] Again, from Figure 45 The bottom of the device moves generally upwards, and the device model configuration Y600 includes a horizontally extending back drain metal ohmic contact layer F1 (cathode), the lower surface of which (i.e., S1) is maintained at a temperature The next layer comprises a substrate Y610 (F5). Formed above the substrate F5 is an epitaxial active region Y620 (e.g., a drift layer), which comprises a semiconductor oxide material and is again modeled as three regions, including a central region F8 and opposing boundary regions F6 and F7 to allow characterization of the central region F8. Above the central region F8 of the epitaxial active region Y620 is a Schottky barrier metal layer Y630 (F3), which forms a Schottky barrier junction between the metal layer Y630 (F3) and the central region F8 of the epitaxial drift layer Y620. In this example, the metal layer Y630 also forms a top contact layer, and it is assumed that its upper surface is maintained at a temperature... (For example, the upper surface is coupled to a temperature T) S2 (Radiator).

[0446] In this example, thermal modeling includes simulating approximately 1 ohm of thermal energy initially applied to the Schottky barrier metal layer Y630 while the drain contact layer F1 remains at ground potential. The voltage in the central region. In this example, the applied simulated voltage corresponds to the initial current of 65 amps conducted between the Schottky barrier metal layer Y630 and the drain contact layer F1 of the model configuration Y600. Furthermore, the temperature of the surface S1 of the configuration model Y600... The temperature is set to 25°C, and the temperature of surface S2 is... The temperature was set to 75°C. The model was then allowed to evolve to an equilibrium state, where the device configuration Y600 conducts a steady-state forward current.

[0447] Now for reference Figure 46 The steady-state temperature contour shaded plot Y700 shows the resulting temperature distribution after thermal modeling of configuration Y600, which in this example includes a highly doped Ga2O3 substrate (see, for example, [link to relevant documentation]). Figure 41The material Y220) and Ga2O3 epitaxial drift layer (e.g., see Figure 41 The material is Y230). The Schottky barrier metal layer Y630 was chosen to be a high work function metal, such as Ni, and the Ga2O3 epitaxial oxide layer is n - Doped. In other examples, the Schottky barrier metal layer Y630 can be selected from other high work function metals, such as Pt, Pd, or Os. In alternative configurations, the Ga2O3 epitaxial oxide layer is p - The doped, and Schottky barrier metal layer Y630 can be selected from low work function metals, such as Al.

[0448] As from Figure 46 The modeling results shown (and their relationship with) Figure 42 As can be seen from the modeling results (similar to those in the modeling), the highest temperature of the central region F8, Y710, is approximately 350°C, which again far exceeds the expected operating temperature of the semiconductor device, 200°C to 220°C. Furthermore, the extended region of the epitaxial active region Y620 will need to operate at temperatures in the range of 250°C to 300°C, which is expected to impact reliability.

[0449] Now for reference Figure 47 The image shows the steady-state temperature contour shaded plot Y800, which illustrates the effect of... Figure 46 The temperature distribution obtained after thermal modeling of the semiconductor device configuration Y600 in the modeling process, except now using a SiC substrate (see, for example, [reference]). Figure 41 The material Y210) was used instead of the Ga2O3 substrate. Through... Figure 46 In comparison, the highest temperature in the central region F8 and the highest temperature in Y810 are in the range of 200℃ to 220℃, which is significantly lower than... Figure 46 The highest temperature shown is for the Ga2O3 substrate-based device. Additionally, the overall operating temperature of the epitaxial drift layer Y620 is approximately 150°C, which is well within the typical operating temperature range for these types of semiconductor devices.

[0450] The thermal model described in this paper illustrates the advantageous hybrid integration of oxide active regions on high thermal conductivity SiC substrates to significantly improve steady-state and transient device performance, which can be applied to high-power switches.

[0451] Further details regarding the structure and fabrication methods of hybrid metal-oxide-semiconductor and SiC substrate devices will now be discussed.

[0452] Figure 48 The following are examples of β-Ga2O3 and 4H-SiC. The crystal surface orientation electron affinity of the surfaces (i.e., Si polar surfaces and C polar surfaces) on an absolute energy scale relative to vacuum, labeled with the Miller index (hkl) for adjacent tangent surfaces. The drawing is Z1-1000. The band gap for each material is represented by a shaded box, where the top horizontal line represents the conductor edge and the bottom boundary of each box represents the valence edge. Figure 48 The band gap and ( Density functional theory (DFT) is used to calculate for a specific material crystal sheet.

[0453] Specifically, the Si polar 4H-SiC(0001) surface is favorable for the epitaxial deposition of β-Ga2O3(-201) oriented films. Assuming unintentionally doped materials, the electron affinity of β-Ga2O3(-201) is shown to be Z1-1010, and that of 4H-SiC(0001) is Z1-1020.

[0454] The interface between the epitaxially grown β-Ga2O3 (-201) layer and the 4H-SiC (0001) layer produces, as... Figure 49 The band arrangement is shown. Figure 9B The image shows the conduction band edge Z2-2020 along the device growth direction at the heterojunction. The active region is n-type (5e16cm). -3 Furthermore, the n-type 4H-SiC region is 1e19cm. -3 This leads to the conduction band discontinuity shown in the figure, where a triangular potential well is induced on the Ga2O3 side. Figure 9B The device configuration further demonstrates that the first quantized energy level in the potential well is below the Fermi energy, thereby inducing a two-dimensional electron gas (2DEG) at the heterojunction. The lowest energy quantized electron wavefunction, as an example of a 2DEG located at the heterojunction, is shown as Z2-2010. The presence of the 2DEG is advantageously used in this disclosure to form an electrical contact between the two regions and to effectively pin the conduction band locally.

[0455] The devices, structures, and methods described herein may include crystallographic matching of two different crystal space groups (SG), including Ga2O3 (SG=C2m) and 4H-SiC (SG=P63mc).

[0456] Figure 50 and Figure 51 The detailed atomic arrangement of Si and C atoms constituting the single-crystal 4H-SiC polytype is shown. They are oriented along the C direction Z3-3020 and on the C plane, respectively. Figure 50 A single crystal cell Z3-3010, comprising a wurtzite-like hexagonal atomic arrangement, is shown. Polar orientation refers to the oriented Si-C bonds along the

[0001] or [000-1] axis, as evident from the Si and C planes shown. Figure 51The diagram shows a C-plane (i.e., (0001) or (000-1)) oriented surface with in-plane Si-Si and CC lattice spacing. The stacking sequence along the Si polarity direction is (ABCB-ABCB-…), with an equal number of cubic and hexagonal bonds.

[0457] Single-crystal Ga₂O₃ compositions can be epitaxially bonded to various SiC surfaces, but Ga₂O₃ can form various polymorphs exhibiting different symmetry groups selected from monoclinic (C₂m), trigonal (R₃c or R₃m), orthorhombic (Pna₂₁), cubic (Fm₃m), and even hexagonal (P₆₃mc). Ideally, a single homogeneous polymorph is desirable for epitaxial layers to achieve the highest electronic performance for current applications. Mixed polymorph epitaxial layer compositions are possible, but may result in materials and devices of lower quality. The stability of a given polymorph epitaxially formed on a SiC surface is determined by several factors: (i) the in-plane lattice mismatch between different crystal symmetry space groups of the epitaxial layer and the substrate for a given crystal orientation plane and epitaxial layer; (ii) the surface energy of the SiC surface; (iii) the bonding between the first bonding atom species on the SiC surface and the first complementary atom species of Ga2O3 (i.e., Ga or O); (v) the relative ratio of the incident fluxes of Ga and active O atoms at a given surface deposition temperature for chemisorption and physisorption, and other factors.

[0458] The devices, structures, and methods described herein may include Ga2O3 in the form of a β-phase monoclinic crystal, which can be stabilized to a wide growth window by selective deposition on the C-plane surface of 4H-SiC. Furthermore, as Figure 52 As shown, the β-Ga₂O₃ film is epitaxially formed in a layer-by-layer growth mode, oriented along the [-201] crystal direction Z4-4020. In monoclinic Ga₂O₃, 50% of the Ga-O bonds are tetrahedral coordinated, and the remaining 50% are octahedral coordinated. The coordination of the O-terminated SiC surface and its effect on the stacking sequence of the Ga₂O₃ epitaxial structure will be discussed later. The stacking sequence of Ga and O atoms along the epitaxial growth direction Z4-4020 is of interest. The atomic planes consist of: buckled Ga-Ga layers, followed by a pre-planar two-dimensional O lattice, a pre-planar two-dimensional Ga lattice, and again a pre-planar two-dimensional O lattice – this sequence repeats along the growth direction. Self-assembly of the crystalline structure occurs during the co-deposition of the Ga and O species. An optional final surface on the (-201) plane is shown as the oxygen-terminated surface Z4-4030. This can be achieved after epitaxial deposition by exposing the surface to active O material (or only active O material). Figure 53 The surface reconstruction of the O-sealed end face is shown, thus revealing the hexagonal arrangement of O atoms Z4-4010.

[0459] Figure 54 A further simplified lattice model is shown, which is used for... Figure 54 The interatomic distance in the middle has a planar hexagonal shape. The positive axis C-plane orientation of 4H-SiC is used to evaluate the lattice mismatch of the first Si-terminated or C-terminated surface.

[0460] Figure 55 The oxygen hexagonal lattice of an oxygen-capped (-201) oriented β-Ga₂O₃ surface is shown. The O lattice is a hexagonal lattice with... The deformed hexagon. This allows us to estimate the range of in-plane lattice constant mismatch (LM) as follows:

[0461]

[0462] In fact, for epitaxial layers with low defect density, LM < 5% is desirable, which suggests that the O lattice should be able to elastically adapt to in-plane compressive strain.

[0463] Figure 56 The diagram schematically depicts potential epitaxial orientations for producing oxide-SiC articles. A C-faceted 4H-SiC substrate Z9-9030 can be oriented to expose either the Si or C face for epitaxial deposition. The intrinsic polarity of 4H-SiC Z9-9040 affects surface electron affinity (e.g., ...). Figure 48 (As shown), and thus aligned with the heterojunction bands of the epitaxial oxide. If 4H-SiC is oriented with the surface normal Z9-9010, this defines the epitaxial growth direction Z9-9010. It is also possible that the epitaxial layer can be grown / assembled at a certain tilt, such that the surface normal may not completely coincide with the crystal plane of the epitaxial layer. For example, the semiconductor oxide Z9-9020 could be β-Ga2O3. The first surface Z9-9050 of the epitaxial layer can be predetermined by the growth sequence that initiates the epitaxial process. Furthermore, the final epitaxial layer surface Z9-9060 can also be predetermined according to the growth process.

[0464] Figure 57A , Figure 57B , Figure 57C and Figure 57D Further analysis of the 4H-SiC C-plane oriented surface structure is shown in the figure.

[0465] Figure 57AA cross-sectional view of the atomic arrangement of the prepared C-plane 4H-SiC crystal is shown. This crystal is Si polarity Z10-10010 and exhibits a final surface with a top plane of Si atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing up to approximately 1000 °C. Alternatively, exposure of a low flux of Si atoms impacting the surface can also ensure the final Si surface states once the native silicon carbide desorbs. Exposure of the Si-terminated surface with an oxygen-active material can then self-confined the surface to have an O-terminated surface. The stacking order from surface down is: -O-Si-C-Si-C-.

[0466] Figure 57B A cross-sectional view of the atomic arrangement of the prepared C-plane 4H-SiC crystal is shown. This crystal is C-polarity Z10-10020 and exhibits a final surface with a topmost plane of Si atoms preferentially bonded to oxygen (O) atoms. This can be achieved through ultra-high vacuum annealing up to approximately 1000 °C. Alternatively, exposure of a low flux of Si atoms impacting the surface can also ensure the final Si surface states once the native silicon carbide desorbs. Exposure of the Si-terminated surface with an oxygen-active material can then self-confined the surface to have an O-terminated surface. The stacking order from surface down is: -O-Si-C-Si-C-.

[0467] Figure 57A and Figure 57B The comparison reveals the oxygen bonding between the topmost O-Si atoms, which exhibits dissimilar bonding symmetry, determining the preferred next Ga arrangement (see reference). Figure 52 (Ga and O in the arrangement) adsorption atomic layer.

[0468] Oxygen can be bonded to Si or C with the following bond strengths:

[0469] , ,

[0470] ,and

[0471] Figure 57C and Figure 57D Alternative first oxygen bond arrangements on the top surface of carbon, configured on Si polar or C polar 4H-SiC surfaces, are shown respectively.

[0472] Figure 57CA cross-sectional view of the atomic arrangement of the prepared C-faceted 4H-SiC crystal is shown. This crystal is Si polar Z10-10030 and exhibits a final surface with a topmost plane of C atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing at over approximately 1000 °C. Alternatively, exposure to a low flux of C atoms impacting the surface can also ensure the final C surface state once the native silicon carbide desorbs. Exposure to the C-terminated surface with an oxygen-active material then self-confined the surface to have an O-terminated surface. The stacking order from surface down is: -OC-Si-C-. Further crystal growth is shown, where an additional Ga adsorbed layer is shown with a tetragonal bonded arrangement forming the sequence -Ga-OC-Si-C-.

[0473] Figure 57D A cross-sectional view of the atomic arrangement of the prepared C-faceted 4H-SiC crystal is shown. This crystal is C polarity Z10-10040 and exhibits a final surface with a topmost plane of C atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing at over approximately 1000 °C. Alternatively, exposure to a low flux of C atoms impacting the surface can also ensure the final C surface state once the native silicon dioxide desorbs. Exposure to the C-terminated surface with an oxygen-active material then self-confined the surface to have an O-terminated surface. The stacking order from surface down is: -OC-Si-C-. Further crystal growth is shown, where an additional Ga adsorbed layer is shown with a tetragonal or octahedral bonded arrangement forming the sequence -Ga-OC-Si-C-.

[0474] Under the methods and structures disclosed in this paper, SiC surface preparation is an important step in realizing high-quality single-crystal β-Ga2O3(-201) oriented epitaxial layers.

[0475] Figure 57E and Figure 57F The effect of intentionally offsetting the C-plane 4H-SiC surface from the positive axis surface (i.e., offset at an angle > 0 with respect to the positive axis surface) on the growth of Ga2O3 epitaxial layers is depicted.

[0476] Figure 57E A cross-sectional view of a Si polar 4H-SiC crystal along the

[0001] direction Z10-10010 is shown, where the off-cut surface Z10-10070 is tilted at an angle θ relative to the positive axis c-plane surface Z10-10050. Z10-10065 is the off-cut direction perpendicular to the substrate surface, and the direction Z10-10060 is the c-axis of SiC. Figure 57EThe angle θ (or off-cut angle) is not drawn to scale. In some cases, θ is 2 to 6 degrees, or about 4 degrees. Below the plane of the off-cut surface Z10-10070 is a SiC crystal, and above it is epitaxial Ga2O3 growth. The epitaxial layer may be grown along the Z10-10060 direction with stacking faults, or at an angle that is substantially inclined to the orientation of the epitaxial layer crystal plane Z10-10055. Figure 57F The epitaxial layer crystal plane grown on the 4H-SiC crystal Z10-10080 with the inclined plane Z10-10055 is schematically depicted.

[0477] Figure 57A , Figure 57B , Figure 57C and Figure 57D The exemplary fabrication process of the structural template surface disclosed herein is described in detail in commonly assigned U.S. Patent Application No. 18 / 628,178, filed April 5, 2024, which is incorporated herein by reference in its entirety.

[0478] Additionally, an example process flow for fabricating a thick oxide film epitaxially deposited on a SiC substrate is described in detail in commonly assigned U.S. Patent Application No. 18 / 628,178, filed April 5, 2024, which is incorporated herein by reference in its entirety.

[0479] Figure 58 Experimental data from epitaxial β-Ga₂O₃(-201) films directly deposited on the surface of a prepared positive-axis n-type 4H-SiC(0001) oriented substrate are presented. Atomic beam epitaxy was performed in an ultra-high vacuum deposition chamber using pure Ga metal and an activated oxygen source from a high-power quartz lamp-coupled RF plasma source. In some examples, growth-grade O₂, N₂, and N₂O were co-fed into one or more RF plasma sources. Epitaxial systems and methods are described, for example, in U.S. Patent Nos. 10,964,537, 11,282,704, 11,342,484, and 11,670,508, which are incorporated herein by reference.

[0480] against Figure 58The example 4H-SiC substrate is directly heated using a high-temperature or mid-infrared emissivity SiC heater. The wafer is rotated and positioned relative to the source during growth, allowing for the deposition of a highly uniform film on a 4” diameter wafer. Depending on the resistivity of the SiC substrate, the substrate growth temperature is between 500°C and 1000°C. Due to the direct emissivity matching between the heater and the substrate, n-type 4H-SiC (0001) substrates are grown at approximately 500°C to 700°C without a back coating. Due to the direct emissivity matching between the heater and the substrate, semi-insulating 4H-SiC substrates are grown at approximately 700°C to 950°C without a back coating. In some examples of epitaxial growth, it has been found that the highest quality single-crystal films are achieved by higher substrate deposition temperatures.

[0481] Reflected high-energy electron diffraction (RHEED) is an essential in-situ diagnostic method for directly and in real-time assessing the quality and crystal structure of epitaxial films. Figure 58 The RHEED pattern of an approximately 2 μm thick β-Ga₂O₃(-201) epitaxial layer grown on an n-type 4H-SiC(0001)Si polar positive axis substrate is shown, varying with substrate rotation about the surface normal at high symmetry points. Excellent single-crystal quality is demonstrated by the long, sharp RHEED diffraction fringes indicating an atomically flat film. The RHEED fringes were monitored and maintained throughout film growth. As expected, the (-201) oriented film exhibits a 60-degree periodicity and is completely free of any polycrystalline arcs or pyramidal surface features, such as spots.

[0482] Figure 59 RHEED images of a thick β-Ga₂O₃ (-201) epitaxial layer grown on an n-type 4H-SiC(0001) Si polar substrate with an intentionally 4-degree offset relative to the positive axis surface toward the A-plane are shown. Sharp and strong stripes are also shown, and the stripes are bent due to the offset of the substrate. Spots are superimposed on the stripes, indicating that the incident RHEED electron beam partially penetrates through the plateau step. It is determined in this disclosure that growth on the offset SiC surface can provide a superior Ga₂O₃ film quality relative to the possible rotating domains reconstructed in (-201).

[0483] Figure 60A and Figure 60B This provides further evidence of the high crystal and optical quality of the epitaxial layer Ga2O3 grown on the SiC substrate, which is achieved at wavelengths of [missing information]. In-situ oblique incidence laser reflection method at 405nm ( Figure 60A The device setup is shown in the diagram. The high initial reflectivity of the exposed SiC surface (…). Figure 60B The drawing in the image shows a decrease after Ga2O3 film deposition, while the percentage of... This will result in optical thickness oscillation, in which Growth rates (GR) between 0.1 and 4 Å / s are possible. Higher growth rates are also possible with proportionally adjusted element source and chamber characteristics.

[0484] Figure 61A Wide-angle bicrystalline diffraction of a Ga2O3 epitaxial layer on a SiC substrate is shown. Symmetrical scanning revealed sharp and strong β-Ga₂O₃ n(-2 0 1) (n=1, 2, 3, 4 and 5) Bragg peaks without any indication of parasitic polymorphs.

[0485] Figure 61B and Figure 61C Asymmetric X-ray diffraction (XRD) reciprocal lattice patterns of two Bragg peaks centered at 4H-SiC(107) and βGa2O3(-403) are disclosed for a heteroepitaxial structure formed by a 2 μm thick βGa2O3(-201) / / 4H-SiC(0001) 0-degree offcut. RSM patterns show that the oxide film is single-crystal with high quality and conforms to different crystal symmetry space groups.

[0486] In another example, Ga2O3 epitaxial layers may also exhibit other pure-phase polymorphs when deposited on alternative SiC surface orientations. For example, Figure 62 A crystal structure similar to sapphire and capable of forming on AR- or M-plane SiC (2H-, 4H- or 6H-) of α-phase Ga2O3 (SG=R3c) was described. Figure 63 Possible wurtzite crystal polymorphs of Ga₂O₃ with SG = P63mc are also shown, which may form on some SiC substrate orientations. Other polymorphs are also possible, such as SG = Pna₂₁ or cubic crystals (defect SG = Fm₃m). Of particular interest are the Pna₂₁ and P63ms space groups, due to their intrinsic properties as polar crystals. It has been determined in this disclosure that forming Ga₂O₃ films (e.g., with Pna₂₁ and P63ms space groups) on Si-polar or C-polar SiC allows for the potential construction of novel electronic devices utilizing spontaneous polarization and piezoelectric polarization-induced carrier doping.

[0487] Figure 64The novel aspects of this disclosure are schematically illustrated, relating to the predetermined electronic properties of the final surface of an oxide epitaxial film. It has been found that β-Ga₂O₃ (-201) surfaces possess electron affinity sensitive to deposition conditions, post-deposition conditions, thermal annealing, annealing in oxygen, and exposure to other environments. It has been further found that hydrogen can play a significant role in controlling the final state of the surface electron affinity. The bulk region of the β-Ga₂O₃ film or substrate is depicted as Z17-17010, which may have been previously doped with hydrogen (or hydrogen-containing) impurities Z17-17020 distributed throughout the bulk or within a thickness Z17-17030. For example, bulk-grown Ga₂O₃ substrates exhibit high levels of hydrogen impurities. These hydrogen impurities can be released from the surface region Z17-17040 through heat treatment or chemical treatment Z17-17050, in which hydrogen (or hydrogen-containing) particles Z17-17045 diffuse or migrate to the surface Z17-17055 and are removed from the structure Z17-17060. Therefore, the topmost surface portion with a thickness Z17-17035 may differ from the bulk region Z17-17030.

[0488] Conversely, the surface region Z17-17040 can be chemically or thermally treated using process Z17-17050, which introduces hydrogen material into the surface region Z17-17040 up to a certain depth of Z17-17035. In one example, the high-temperature epitaxial growth of the oxide layer terminates, and the growth temperature gradually decreases to ambient temperature over time (t) while still being subjected to a high oxygen partial pressure. Oxygen annealing during the gradual decrease in substrate temperature after epitaxial growth may selectively deplete impurities in the surface region Z17-17040 or induce an effect of depleting charge carriers in the surface. Such techniques can be useful, for example, if the epitaxial layer is co-doped with Si, Ge, or Sn during epitaxy, the final doping level of the surface region Z17-17040 may be significantly lower than that of the bulk region Z17-17010. Without modification, this depleted surface will directly affect the formation of the Schottky barrier, as discussed in this paper.

[0489] Figure 65 The effect on the surface of a β-Ga2O3 (-201) oriented epitaxial layer deposited as an n-type drift layer on top of a highly doped n+ layer or substrate is shown. The band gap Eg is shown as the distance between the conduction band edges. Price with edge In this example, Si-doped Ga2O3 with impurity donor doping is used for the epitaxial layer (“epitaxy”). 漂移 =5e16cm -3 .

[0490] Intentionally exposing the epitaxially grown surface to hydrogen gas and atomic hydrogen can result in a neutral surface. However, at elevated substrate temperatures, hydrogen exposure can create a surface electron accumulation layer that penetrates into the epitaxial layer to a certain depth Z. 积累 (“Z 深度,积累 Conversely, when exposed to high-temperature oxygen, the epitaxial layer surface develops a depleted surface after growth. The surface bands may bend in this scenario. Figure 65 It is shown as a 'depleted surface' or 'charge accumulation surface'.

[0491] Figure 65 , Figure 66A and Figure 66B A similar design using Ni metal contacts is shown. Figure 9A The effect of surface modification on the β-Ga2O3 (-201) active region (e.g., the drift layer) of the device shown is illustrated. The neutral drift layer surface will result in an SB potential of... The depleted surface will have a high potential barrier at the heterogeneous interface. The accumulation of surface charge will lead to .exist Figure 66A (semilogarithm) and Figure 66B The (linear) plot shows the results of the positive bias IV.

[0492] The plot shows that the surface states of the post-grown active region directly affect the diode's turn-on voltage and subthreshold slope.

[0493] Figure 67 The comparison shown is similar to Figure 9A The device structures shown (but with different contact metals) have 'clean' and 'depleted' surfaces with a series of high work function metal β-Ga2O3 (-201) drift layers. The clean surfaces are treated with hydrogen at high temperature, while the depleted surfaces are annealed in oxygen.

[0494] Figure 67 The large variations in the possible positive IV curves for various high work function metals when deposited on two types of surfaces (depleted or clean surfaces) are shown. This helps to explain the variations in experimental results for various devices and processing methods.

[0495] An example process flow for manipulating the surface charge state of the final surface of an epitaxial oxide layer is described in detail in commonly assigned U.S. Patent Application No. 18 / 628,178, filed April 5, 2024, which is incorporated herein by reference in its entirety.

[0496] Figure 69 illustrates the deposition of an epitaxial Ni metal contact layer (SB) directly onto the semiconductor β-Ga2O3 (-201) surface (“Semi”). A monolayer of oxygen (OI) can be used on the O-capping surface to form bonding bonds with the nickel (M) metal contact (SB). In some cases, a thick, intentionally deposited NiO layer can be formed, followed by a Ni metal cap layer. Figure 68 Structures similar to those shown are also possible. In some cases, any metallic material used for the Schottky metal described herein can form an oxide at the interface between the drift layer and the Schottky metal layer. For example, Figure 11A Any metallic material can form an oxide comprising the metallic substance and oxygen (e.g., PtO2) at the interface between the active region (e.g., including Ga2O3 or other epitaxial oxide materials) and the metal (Schottky contact) layer. In some cases, the oxide of the metal forming the Schottky barrier can form an intermediate layer, as described herein. In some cases, the oxide of the metal forming the Schottky barrier can be compared to... Figure 68 The example shown is thicker. For instance, the thickness of this oxide can be within the range of the intermediate layers described herein.

[0497] The devices, structures, and methods described herein may include in-situ single-crystal Ni(111) oriented films deposited directly on β-Ga2O3(-201) surfaces at low temperatures and high vacuum <1e-8torr.

[0498] There are many other possible configurations to achieve intermediate (IL) or drift layers that include UWBG oxide components.

[0499] Figures 69A to 69G An experimental example of an epitaxial structure is shown, comprising an epitaxial β-Ga2O3(-201) layer and an epitaxial Ni(111) layer formed on a SiC(0001) substrate. The Ni(111) layer in this example has a thickness of 20 nm. The epitaxial structure in this example was formed using the technique described herein, employing MBE.

[0500] Figure 69A A multilayer epitaxial structure 70100 is schematically depicted, which includes a SiC substrate 70105, an epitaxial semiconductor oxide layer 70110, an epitaxial metal layer 70115, an optional additional contact layer 70120 for the metal layer 70115, and an optional contact layer 70125 for the substrate 70105.

[0501] Figure 69B The in-plane azimuth angle of the highly symmetric surface of structure 70205 is shown. The RHEED image of the diffraction pattern is 70200. The structure includes a single-crystal epitaxial β-Ga2O3(-201) orientation layer at the top surface, which is formed on a 4-degree off-cut n-type Si polar 4H polymorph SiC(0001) substrate. Figure 69B The elongated and slender RHEED stripes demonstrate the high quality of the single-crystal oxide film.

[0502] Figure 69C The same highly symmetric surface in-plane azimuth angle of structure 70215 is shown. The RHEED image of the diffraction pattern 70210 shows a structure that includes a single-crystal epitaxial Ni(111) oriented layer at the top surface, which is directly deposited on the single-crystal epitaxial β-Ga2O3(-201) oriented surface of structure 70205. Figure 69C The elongated and slender RHEED stripes demonstrate the high quality of the single-crystal metal film.

[0503] Figure 69D It shows Figure 69B The in-plane azimuth angle of the highly symmetric surface of the same structure 70205 ( The RHEED image 70300 of the diffraction pattern shows a single-crystal epitaxial β-Ga₂O₃(-201) oriented surface directly deposited on a 4-degree off-center n-type Si polar 4H polymorph SiC(0001) substrate. The elongated and slender RHEED fringes shown further demonstrate the high quality of the single-crystal oxide film.

[0504] Figure 69E The same in-plane azimuth angle of the highly symmetric surface of structure 70215 is shown. The RHEED diffraction pattern for structure 70310 shows a single-crystal epitaxial Ni(111) oriented surface deposited directly on the single-crystal epitaxial β-Ga2O3(-201) oriented surface of structure 70205. The elongated and slender RHEED fringes shown further demonstrate the high quality of the single-crystal metal film.

[0505] Figure 69C and Figure 69E The RHEED results shown confirm that each The periodicity of the surface azimuth RHEED diffraction pattern will appear, indicating that the Ni(111) orientation film includes face-centered cubic crystals.

[0506] Figure 69F and Figure 69GWide-angle X-ray diffraction pattern 70400 and high-resolution X-ray diffraction pattern 70500 of the completed multilayer structure 70215 are shown, respectively. This completed multilayer structure includes epitaxial Ni(111) formed on an epitaxial β-Ga₂O₃(-201) layer, which in turn is formed on a Si polar 4H polymorph SiC(0001) substrate. Inset 70505 shows the atomic structure of the Ni(111) oriented surface. Figure 69G The high-resolution X-ray diffraction pattern 70500 in the image includes thickness fringes for the Ni(111) peak, which shows the high-quality interface and low degree of surface roughness of structure 70215.

[0507] Figures 69B to 69G These RHEED and X-ray diffraction results clearly show the Bragg diffraction patterns of pure-phase (or single-phase) semiconductor oxides and Ni-metals, thus indicating the coherent epitaxial relationship between the deposited layers.

[0508] Figure 70A , Figure 70B , Figure 72 and Figure 73 A range of suitable UWBG semiconductor oxide compositions are disclosed, which are possible and beneficial for improving the performance of semiconductor devices such as high-power devices and diodes.

[0509] Generally speaking, any material described herein (e.g., any component of the following materials 1-7: (Mg) x Zn 1-x (Al) y Ga 1-y )2O4, of which , or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z Where 0 ≤ (x, y, z) ≤ 1, or (Ni) z Mg x Zn 1-x-z (Al) y Ga 1-y )2O4, of which , or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z, where 0 ≤ (p, x, y, z) ≤ 1) can be used as drift layers, intermediate layers and other layers of the devices, structures and methods described in this paper.

[0510] For example, Figure 70A Possible bandgap ranges for the compositions in the form of zinc gallium oxide and zinc aluminum oxide are disclosed. Spinel structures ZnGa2O4 and ZnAl2O4 exhibit SG=Fd3m and are deposited as (111) oriented films on β-Ga2O3 (-201) or C-face 4H-SiC.

[0511] In another example, Figure 70B Possible bandgap ranges for the compositions in the form of magnesium gallium oxide and magnesium aluminum oxide are disclosed. Spinel structures MgGa2O4 and MgAl2O4 exhibit SG=Fd3m and are deposited as (111) oriented films on β-Ga2O3 (-201) or C-face 4H-SiC.

[0512] In other examples, Figure 72 and Figure 73 The quaternary composition of oxide materials for the active region, intermediate layer, and other layers, which can be used in the devices, structures, and methods described herein, is shown.

[0513] Figure 72 The possible bandgap variations of magnesium zinc gallium oxide and magnesium zinc aluminum oxide are shown.

[0514] Figure 73 The possible bandgap variations of magnesium aluminum gallium oxide and zinc aluminum gallium oxide are shown.

[0515] In some cases, the drift layer, intermediate layer, and other layers of the devices, structures, and methods described herein may include spinel-form (SG=Fd3m) (Mg) x Zn 1-x ) (Al y Ga 1-y )2O4, of which The resulting composite oxide can be realized as an intrinsic p-type or n-type conductor (without impurity doping), thus reducing the need for impurity doping. In another form, spinel can be deposited as a (111) oriented film on β-Ga2O3 (-201) or C-face 4H-SiC.

[0516] In the example, the composite oxide (e.g., having a spinel form (SG=Fd3m)) is formed from (Ni) z Mg x Zn 1-x-z (Al) y Ga 1-y )2O4 (of which ) or (Mgx Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (where 0 ≤ (x, y, z) ≤ 1) can be used as intrinsic, p-type, or n-type conductivity types in the structures and devices described herein (without impurity doping), thereby reducing the need for impurity doping. In another form, spinel can be deposited as a (111) oriented film on β-Ga2O3 (-201) or C-faceted 4H-SiC in the structures and devices described herein.

[0517] Other SG forms of the following items may also be used in the materials, structures, and devices described herein: Ga2O3 (e.g., α-phase or β-phase); (Al x Ga 1-x )2O3 (e.g., α-phase or β-phase), where 0 ≤ x ≤ 1; Mg x Ga 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; Mg x Al 2(1-x) O 3-2x , where 0 ≤ x ≤ 1; (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z Zn, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Zn x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Mg x Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Ni x Ga y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; Nix Al y O z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1; (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y , where 0 < x < 1 and 0 < y < 1; or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z , where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 1, or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4, where , or (Zn<000​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​The device performance in the diode structure.

[0521] Therefore, controlling the epitaxial process used to fabricate structures to simultaneously control the doping density of SiC (substrate or layer) can be advantageous. For example, highly conductive 4H-SiC substrates can be fabricated for epitaxial oxide growth. When the SiC substrate is heated in a vacuum to the desired growth temperature, the surface charge density of the SiC substrate can be altered, and potential impurity dopants can be desorbed. This can significantly reduce the donor density on the 4H-SiC surface, and thus produce a significantly wider depletion region extending into the SiC material. The result can be higher on-resistance of the diode and increased electrical losses.

[0522] In some cases, SiC substrates are heated to the desired growth temperature in an environment that avoids altering the surface charge density. For example, SiC substrates can be heated in an inert environment or under a Si beam to prevent Si desorption.

[0523] Those skilled in the art may not fully understand that heterojunctions formed at the interface between two different oxide materials can also exhibit complex interactions. As discussed above, metal-oxide-semiconductor (MOS) junctions can form Schottky barrier contacts or ohmic contacts. The different bandgap energies, compositions, electron affinities, and other dielectric constants of the two oxides directly affect the properties of the vicinity of the heterojunction.

[0524] Figure 75 A simplified cross-sectional physical structure of an active region oxide semiconductor is shown, wherein a portion of the active region oxide surface is deposited with metal along the A-A' direction parallel to the growth direction z. Similarly, the isolation layer discussed above, serving as a dielectric insulator between the field plate and the oxide active region (see reference...) Figures 79 to 86 It also forms along the B-B' direction, along a portion of the oxide drift surface, as shown in the figure. The thickness t indicates the thickness of the isolation layer (isolation). 隔离 and the thickness t of the active region 漂移 Assuming the isolation layer also includes an oxide material component, which possesses a wider bandgap energy than the oxide component in the active region, then... Then the equivalent energy band diagram along the B-B' direction is Figure 76 As shown in the image.

[0525] Figure 76 This is a drawing of the space band diagram of a heterojunction formed between the active region of an oxide semiconductor and different oxide or material regions forming the isolation region. (Space conduction band diagram) The left side corresponds to the active region and the right side corresponds to the isolation layer, where the balance Fermi energy is... The position is between two possible first-electron quantized states in the inverted potential well located at the heterogeneous interface.

[0526] if Above the first quantized electronic state, there may be a two-dimensional electron gas at the heterojunction interface, with a surface charge N of the two-dimensional electron gas. s 界面 The charge is greater than 0, thus forming a negatively charged sheet at the interface. Depending on the surface roughness at the interface, this charged sheet may be continuous or discontinuous, but it represents a surface leakage path that is detrimental to the operation of vertically conductive devices. This can be used in lateral transport devices.

[0527] Conversely, if If the electron is located below the first quantized electronic state, the heterointerface will not accumulate surface charge. And thus it can serve as a suitable barrier.

[0528] A further specific aspect of the interaction between abrupt interfaces of different oxide material compositions is that the dielectric constant can vary significantly, resulting in large dielectric constant discontinuities at the heterogeneous interface. Dielectric confinement (deconfinement) effects may increase (decrease) the Coulomb interaction between charge carriers located at or near discontinuities.

[0529] For example, if the active region includes Ga2O3 and the isolation layer includes a low-k dielectric constant material, then Alternatively, in another example, if the drift layer comprises Ga2O3 and the isolation layer comprises a high-k dielectric material, then .

[0530] Figure 77A The calculated static and optical dielectric constants of some example UWBG oxide materials suitable for inclusion in this disclosure are shown in a list. For some materials, crystal orientation-dependent properties exist.

[0531] This paper addresses the concepts of dielectric confinement and shielding by specifically referencing the boundary between two thin sheets of oxide materials with different dielectric constants.

[0532] Figure 77B and Figure 77C Electrostatic equipotential lines were plotted between two equal and opposite charge regions, which are separated by a distance of 0.5 units in the x-direction and embedded in thin films of materials with different dielectric constants. Figure 77B Provided a thin sheet on the left side ( ) and the thin slice on the right ( The case where the dielectric constants of the two are equal is shown. Symmetrical equipotential lines are illustrated. However, for... Figure 77CThe middle shows In the case of ratios, the equipotential lines are highly asymmetrical across the entire heterodielectric interface, where the potential is shielded within a thin sheet with a higher dielectric constant.

[0533] from Figure 77B and Figure 77C Calculated separately Figure 77D and Figure 77E The electric field intensity is shown in the contour plot. The electric field shielding effect in the high dielectric region is illustrated. Quantitative values ​​of the electric field vector near the heterodielectric interface were calculated, and... Figure 77F and Figure 77G The quantitative value is shown in the figure.

[0534] Figure 77F The electric field E is shown. X (E Y The spatial variation of the x and y components of ). If both halves of the structure have equal dielectric constants (satisfying... The diagram illustrates the E along the interface for three cases: x=0 at the interface and the very close regions on both sides (x= + / -0.005 units). X and E Y Symmetry of the components. As expected, the symmetry of the curves reflects equal and opposite charges.

[0535] Figure 77G It shows The simulation illustrates a scenario where the electric field within the high-dielectric region is essentially shielded, as shown in the figure. This phenomenon can be utilized in this disclosure to design for the maximum electric field generated in the device structure due to effects induced by fabrication geometry. For example, sharp edges typically formed around metal contacts through photolithography, stripping, or etching can generate unfavorable edge fields. Therefore, it is desirable to manage these edge fields at sharp metal features, as they can generate electric fields exceeding the breakdown strength of oxide electric fields.

[0536] Figure 78 and Figure 79 Two-dimensional electrostatic models of two types of vertical multilayer semiconductor devices are shown.

[0537] Two similar structures are shown, differing only in the thickness between the field plate (FP) overhang and the final surface of the active region (F4). The SiC substrate F3 is conductive, while the isolation region F2 is endowed with a bandgap energy exceeding that of the active region, but its dielectric constant can be chosen to be different from that of the active region. Region F1 is treated as air, and the drift region F4 is Ga2O3 with a low charge density. Figure 78 In the model, the gap between the FP and the active region is 0.4 units in the vertical direction, while for Figure 79The model uses a gap of 0.05 units in the vertical direction. Furthermore, the Schottky metal contacts are drawn as segmented field plates, with no field plate overhang on the left side. This allows for comparison of designs with and without field plates using the same simulation. For small-gap configurations, the FP contributes more to the overall device capacitance, which is crucial for high-speed switching applications.

[0538] Figure 80 and Figure 81 The calculated spatial electric field strength is shown as contour lines for a thin FP with a bias of +1000V and a back contact with a bias of -1000V. Figure 80 have and Figure 81 have The dielectric constant of all regions was considered in the case of [the previous case].

[0539] Figure 82 and Figure 83 Close-up images of the 'thick' FP contour lines for low k and high k conditions are shown respectively.

[0540] Figure 84 and Figure 85 Thin FP close-ups of the electrostatic field contour lines are shown for low k and high k conditions, respectively.

[0541] The quantitative values ​​of the potential energy at the contact points between the horizontal interface of the active region and the metal contact layer and the isolation layer were calculated. Figure 86 and Figure 87 The figures show the cases of thin FPs with low-k and high-k insulating materials. The potential is maximum at the metal interface and slightly lower near the contact, but slightly below the interface. The lateral range of the FPs shows that the potential is maintained for the high-k insulating material, while the potential drops rapidly for the low-k insulating material.

[0542] Figure 88 and Figure 89 The spatial intensity of the electric field near the interface was plotted for both low-k and high-k thin FP insulating materials. A large peak in the electric field at the metal contact corner is evident, and the effect of the transverse FP is also significant. The results show that a high-k insulating layer can effectively reduce the peak electric field at the critical point of the metal contact.

[0543] Further analysis of the segmented FP structure allows for direct comparison of the maximum electric field generated at the interface between the drift layer and the metal contact.

[0544] Figure 91 and Figure 92This is a plot of the spatial variation of the electric field intensity generated within the structure across three horizontal planes: the heterogeneous interface between the drift layer and the isolation layer, slightly above the interface, and below the interface. The device structure has a thin field plate / isolation layer / drift layer spacing.

[0545] Figure 90 The maximum electric field within the structure at the interface between the active region and the metal contact is plotted as a function of the dielectric constant used in the isolation material, with and without the field plate. It has been shown that FP reduces the maximum electric field for all cases where the dielectric constant of the isolation layer is lower or higher than that of the active region material. Beyond [a certain value]... At this point, diminishing returns exist for FPs, where, in alternative examples, simple metal mesa contacts and conformal high-k dielectrics offer superior performance. A high-k isolation layer can also be deposited, followed by etching to define the area for the Schottky metal contacts.

[0546] Figure 91 The ratio g of the maximum electric field with and without FP was further investigated by defining the following term:

[0547]

[0548] When the ratio of the dielectric constant of the isolation layer to the drift layer is approximately When within the range of 2.0, Figure 91 The maximum benefit of FP is confirmed at the minimum value of the ratio γ. For this range, a reduction of approximately 45% in the maximum electric field is possible. For high-k insulating materials (i.e.... >3.0), when dielectric confinement and shielding dominate, the effectiveness of FP is reduced, and simple metal mesa contact is efficient.

[0549] In various implementation schemes, when optimizing semiconductor design according to this disclosure, the results of the above exploration of isolation layer materials and the role of FP can be taken into account.

[0550] Figure 92 A two-dimensional electrostatic model of a simple metal mesa Schottky contact embedded in insulating materials with different dielectric constants is depicted.

[0551] Figure 93 The calculations for the maximum surface electric field intensity at the interface between the drift layer and the metal / isolation layer are plotted. By utilizing an isolation layer material selected from high dielectric constants, a reduction in the peak surface electric field by orders of magnitude can be achieved. High dielectric materials with band gaps larger than the drift region and dielectric constants far exceeding those of Ga₂O₃ are found in rare earth metal oxides, titanium oxide, etc. Rare earth metal oxides are of interest; they can be alloyed with aluminum to increase the effective band gap while maintaining a high dielectric constant.

[0552] It is worth noting that nickel oxide exhibits a large dielectric constant due to its low band gap energy.

[0553] Figure 94 A photograph shows a partially completed Schottky barrier diode formed on a Ga2O3 epitaxial layer deposited on a 4H-SiC substrate. The Schottky barrier metal is Ni, and a second metal, Al, is used to thicken the contacts. The back ohmic contacts are untreated, thus revealing the transparency of the substrate.

[0554] In some implementations, the structures and devices described herein include a “T-channel” design that can further improve the operating characteristics of the semiconductor devices described herein.

[0555] As discussed above, the dielectric constant of the material incorporated into the structure of a semiconductor device determines the electrostatic behavior of the device under high (or strong) electric fields. Furthermore, as described herein, the insulating layer surrounding the metal contacts can be used to design the surface electric field at the interface between the oxide active region and the metal. For example, a high-dielectric-constant insulating layer material can be used to minimize the surface electric field at the critical point of the metal contacts.

[0556] Figure 95AAn alternative device design, referred to herein as a “T-channel” design, is shown. A back contact 96132 (F4) and an oxide semiconductor drift layer 96125 (F6) fabricated onto a SiC substrate 96110 (F2) are shown. In the “T-channel” design, the oxide semiconductor channel region 96120 (F3) is formed together with the Schottky metal layer 96130 (F5) as a mesa structure (e.g., by selective region etching). In some cases, the oxide semiconductor drift layer 96125 has a higher doping density than the oxide semiconductor channel region 96120. A higher doping density of the oxide semiconductor drift layer 96125 can be beneficial, for example, in reducing the on-resistance of the device. The doping density of the oxide semiconductor channel region 96120 can be tuned to produce a Schottky junction with tunable characteristics (e.g., with a desired depletion width). Therefore, the doping density of the oxide semiconductor channel region 96120 can be higher or lower than the doping density of the drift layer 96125, depending on the desired Schottky junction properties. Sidewall layers 96180 (F7 and F8) are formed around the mesa structure. Sidewall layers 96180 (F7 and F8) may surround the mesa structure. Sidewall layers 96180 (F7 and F8) may physically contact one or more walls 96122 and 96124 of the mesa structure. Walls 96122 and 96124 of the mesa structure include the interface between the oxide semiconductor channel region 96120 and the Schottky metal layer 96130. Field plate layer 96190 (F9) may be on the top surface of the Schottky metal layer 96130 and extend laterally (i.e., in the x-direction) beyond the Schottky metal layer 96130 (and laterally extend beyond the mesa structure), such that this field plate layer is also on the top surface of the sidewall layer 96180 (e.g., ...). Figure 2A (As shown). The Schottky metal layer 96130 may include any suitable metal described herein, for example, Figure 11A Any material (i.e., Cu, Te, Be, Rh, Co, C, N, Ni, Au, Ir, Pd, Pt, Se, or Os), or Figure 11A An alloy of metals in the substrate. Additionally, in some cases, substrate 96110 is a composite substrate comprising a surface layer and a bulk substrate layer (e.g., Figure 1 The substrate 110 in the substrate 110 has a bulk substrate layer 112 and a surface layer 114, wherein the surface layer comprises single-crystal SiC.

[0557] For example, Figure 95AThe mesa structure, including the oxide semiconductor channel region 96120 and the Schottky metal layer 96130, may have a circular cross-section, and the sidewall layer 96180 may surround (or wrap around) the mesa structure in an annular shape. In such an example, walls 96122 and 96124 (or sidewalls) would be the same walls surrounding a cylindrical mesa structure. In another example, the mesa structure may be rectangular, and the sidewall layer 96180 may be in a shape similar to the rectangular ring surrounding the mesa structure. In such an example, the sidewall layer 96180 may be in physical contact with walls 96122 and 96124, as well as two other walls (not shown) of the rectangular prism-shaped mesa structure. In some cases, the dielectric constant (k) of the sidewall layer 96180 may be greater than or equal to the dielectric constant of the oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120. For example, the dielectric constant (k) of the sidewall layer 96180 may be greater than 10, or greater than 100, or about 10 to about 1200. For example, the drift layer may include Ga2O3, and the sidewall layer 96180 may include TiO2 (dielectric constant about 100), barium titanate BaTiO3, and associated polymorphs (dielectric constant about 1200) or diamond (dielectric constant about 16.5).

[0558] In another example, walls 96122 and 96124 (or sidewalls) may be tapered inward or outward from the top of drift layer 96125. In another example, the cone may be curved to adopt a generally convex or concave profile. In another example, the slope or tangent of the cone toward the interface defined by oxide semiconductor channel region 96120 and drift layer 96125 changes smoothly. In yet another example, the slope or tangent of the cone toward the interface defined by oxide semiconductor channel region 96120 and contact layer Schottky metal layer 96130 changes smoothly.

[0559] In other examples, the shape of the oxide semiconductor channel region 96120 can be configured to be perpendicular to Figure 95A The view shown extends longitudinally in the "z direction" so that the cross-sectional area of ​​the channel can be adapted to a predetermined current density.

[0560] Figure 95AIn this context, region 96010 (F1) represents air, which has the dielectric constant of air. The dielectric constant of sidewall layer 96180 may be greater than, equal to, or less than the dielectric constant of the oxide drift region and the channel region. For example, oxide semiconductor regions 96125 and 96120 may be Ga2O3, and the dielectric constant of the sidewall dielectric may be less than, equal to, or greater than the dielectric constant of Ga2O3. In some embodiments, the band gap energy of the dielectric material of sidewall layer 96180 exceeds the band gap energy of the drift element and the channel oxide material, making it behave as an insulator. In other cases, the band gap energy of the dielectric material of sidewall layer 96180 is equal to or less than the band gap energy of the drift element and the channel material, and the dielectric material of sidewall layer 96180 is semi-insulating or insulating.

[0561] In some cases, the oxide semiconductor channel region 96120 has a different doping density and / or material composition compared to the oxide semiconductor drift layer 96125. For example, the doping density of the oxide semiconductor channel region 96120 may be lower than that of the oxide semiconductor drift layer 96125. In another example, the composition of the oxide semiconductor channel region 96120 may differ from that of the oxide semiconductor drift layer 96125, such that the band gap of the oxide semiconductor channel region 96120 is lower than, equal to, or higher than that of the oxide semiconductor drift layer 96125.

[0562] The oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120 may be formed of the same semiconductor oxide material or different oxide materials. In some cases, the oxide semiconductor drift layer 96125 is formed of an oxide semiconductor material having the same composition and crystal symmetry as the oxide semiconductor material forming the oxide semiconductor channel region 96120. In other cases, the oxide semiconductor drift layer 96125 is formed of an oxide semiconductor material having a different composition and / or crystal symmetry than the oxide semiconductor material forming the oxide semiconductor channel region 96120. In an example, the oxide semiconductor drift layer 96125 may be formed of a material selected to provide a structural matching region between the substrate 96110 and the oxide semiconductor channel region 96120. The oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120 may also be formed of materials having the same or different band gaps. For example, the band gap of the oxide semiconductor drift layer 96125 may be greater than or less than the band gap of the oxide semiconductor channel region 96120. In some cases, the oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120 have a conduction band shift that does not significantly impede the movement of electrons from the oxide semiconductor drift layer 96125 to the oxide semiconductor channel region 96120, or vice versa. In some cases, the oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120 have a valence band shift that does not significantly impede the movement of holes from the oxide semiconductor drift layer 96125 to the oxide semiconductor channel region 96120, or vice versa. Generally, the band gap of any region (including the channel region) of the structure or device described in this disclosure can be modified by appropriately changing the composition of the material. For example, for materials such as (Al... x Ga 1-x The band gap of ternary materials containing Al₂O₃ can be altered by changing the mole fraction x from Al₂O₃ to Ga₂O₃. In practice, there can be limitations on the possible compositional range when maintaining high-quality (i.e., low-defect) materials. x Ga 1-x In the example of Ga₂O₃, x < 0.35 is a limitation, and when x > 0.35, it may be difficult to obtain high-quality single-phase (Al₂O₃) on a Ga₂O₃ bulk layer. x Ga 1-x )2O3.

[0563] For example, including Mg x Zn y Ni z (Al p Ga 1-p )O qAn oxide semiconductor drift layer 96125 of a semiconductor oxide material (or another oxide semiconductor material described herein) may be formed between a SiC substrate 96110 and an oxide semiconductor channel region 96120, wherein in some examples, the oxide semiconductor channel region 96120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. Another example of a semiconductor oxide material is silicon carbide (Si). x C y O z The form may include an oxide semiconductor drift layer 96125 and may be formed between a SiC substrate 96110 and an oxide semiconductor channel region 96120, wherein in some examples, the oxide semiconductor channel region 96120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. Another example of a semiconductor oxide material is silicon oxynitride (Si). x N y O z The form may include an oxide semiconductor drift layer 96125 and may be formed between a SiC substrate 96110 and an oxide semiconductor channel region 96120, wherein in some examples, the oxide semiconductor channel region 96120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. Another example of an oxide semiconductor drift layer 96125 is one that includes silicon germanium carbide (Si). x Ge y C z The oxide semiconductor drift layer 96125 is a material of a form that allows the oxide semiconductor drift layer 96125 to be used to control the interfacial strain formed between the SiC substrate 96110 and the oxide semiconductor channel region 96120, wherein in some examples, the oxide semiconductor channel region 96120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3.

[0564] In some cases, the doping concentration of the oxide semiconductor channel region 96120 can be between the doping concentration of the substrate 96110 and the doping concentration of the oxide semiconductor channel region 96120, wherein there are discrete variations in the doping concentration between the substrate 96110 and the oxide semiconductor drift layer 96125, and between the oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120. In the example, the substrate 96110 can be n + Doped (i.e., doping concentration of 10) 19 Up to 10 20 cm -3The oxide semiconductor drift layer 96125 can be n - Doped (i.e., doping concentration of approximately 10) 18 cm -3 , or 10 17 cm -3 Up to 10 18 cm -3 Furthermore, the oxide semiconductor channel region 96120 can be n - - Doped (i.e., doping concentration of 10) 15 cm -3 Up to 10 17 cm -3 This configuration provides n that moves vertically upward from the substrate 96110 to the oxide semiconductor channel region 96120. + doped region to n -- Transition between doped regions. Similarly, p-type devices can be formed, where the substrate 96110 is p-type. + The doped oxide semiconductor drift layer 96125 is p - Doped, and the oxide semiconductor channel region 96120 is p - - Doped, wherein the layer has an acceptor rather than donor doping concentration as described above.

[0565] In some cases, the doping density of the oxide semiconductor drift layer 96125 has a monotonically varying gradient in the z-direction. For example, the doping density of the oxide semiconductor drift layer 96125 may begin (closer to the substrate 96110) at a doping concentration close to or lower than (i.e., less than) the doping concentration of the substrate 96110, and end (farther from the substrate 96110) at a doping concentration approximately equal to the doping concentration of the oxide semiconductor channel region 96120. In some cases, the oxide semiconductor drift layer 96125 has a monotonically varying doping concentration that begins at approximately equal to the doping concentration of the substrate 96110 or between the doping concentration of the substrate 96110 and the doping concentration of the oxide semiconductor channel region 96120, and ends at approximately equal to the doping concentration of the oxide semiconductor channel region 96120 or between the doping concentration of the substrate 96110 and the doping concentration of the oxide semiconductor channel region 96120. In the example, the doping concentration of the oxide semiconductor drift layer 96125 can be matched to the doping concentration of the substrate 96110 at the interface between the oxide semiconductor drift layer 96125 and the underlying layer (e.g., substrate 96110), and then continuously varied to match the doping concentration of the oxide semiconductor channel region 96120 at the interface between the oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120. In the example, the variation of the doping concentration of the oxide semiconductor drift layer 96125 can vary with vertical height. The doping concentration of the 96125 oxide semiconductor drift layer varies linearly with vertical height. In some cases, the doping concentration can vary with vertical height. The doping concentration varies continuously with vertical height (i.e., without significant abrupt changes, and varies monotonically or nonlinearly, for example). In some cases, the doping concentration of the oxide semiconductor drift layer 96125 can vary with vertical height. It changes in a step-by-step manner.

[0566] In other examples, the doping density of the oxide semiconductor channel region 96120 may be higher than or equal to the doping density of the oxide semiconductor drift layer 96125, and the composition of the oxide semiconductor channel region 96120 may differ from the composition of the oxide semiconductor drift layer 96125, such that the band gap of the oxide semiconductor channel region 96120 is lower than, equal to, or higher than the band gap of the oxide semiconductor drift layer 96125. In some embodiments, there is no significant (or a very small) barrier for electron flow between the back contact 96132 and the oxide semiconductor channel region 96120. In other words, in some cases, electrons can flow freely from the back contact 96132 to the oxide semiconductor channel region 96120. Therefore, in some cases, the band gap of the drift region 96125 is equal to or less than the band gap of the oxide semiconductor channel region 96120. In other cases, the band gap of the drift region 96125 is larger than that of the oxide semiconductor channel region 96120, and since band alignment is achieved due to the absence (or minimal) conduction band shift between the materials, there is no significant (or minimal) barrier for the electron flow from the drift region 96125 to the oxide semiconductor channel region 96120.

[0567] Figures 95B to 95H It shows a similar Figure 95A The spatial electric field within the device of the structure shown is modeled (or calculated), where the sidewall material 96180 has a different dielectric constant relative to the oxide semiconductor of the drift layer and the channel layer. Specifically, Figures 95B to 95H This shows the effect for a dielectric constant of The sidewall layer is made of 96180 material, and a potential of -1000V is applied to the lower electrode and a potential of +1000V is applied to the upper field plate. Therefore, the modeled device covers a range of sidewall layer 96180 materials, ranging from low-k dielectrics to high-k dielectrics.

[0568] Figure 95B It shows Figure 95A The calculated (i.e., modeled) electric field strength along the vertical centerline located at x=0 in the structure shown. Figure 95B The channel region 96126 (from y=0.2 to y=0.6) along the vertical centerline (x=0) is also shown. This is related to the dielectric constant of the sidewall layer 96180. The electric field exhibits some unique properties as the Ga2O3 channel transitions from low k to high k. For (For example, with a dielectric constant approximately equal to that of Al2O3), the electric field is maximum at the interface between the Schottky metal and the channel. For In this case, the electric field is still maximum at the interface between the Schottky metal and the channel. For In the case of [condition], the electric field has a minimum value inside the channel, while for [condition]... In the case of Schottky metal, the opposite is true, and the electric field is minimal at the interface between the Schottky metal and the channel.

[0569] Figures 95C to 95F Showing the target Figure 95B The contour maps of the electric field for each case are drawn in the image. Figure 95C It shows In this situation, Figure 95D It shows In this situation, Figure 95E It shows The situation, and Figure 95F It shows The situation.

[0570] Figure 95G and Figure 95H Draw respectively for Figure 95A The dielectric constant value in the figure, at the heterodielectric interface (i.e., at Figure 95A The electric field strength and x-component of the electric field at y=0.2 are shown. Extracting the electric field components at the heterodielectric interface further illustrates the influence of the sidewall dielectric constant on device behavior.

[0571] therefore, Figures 95C to 95H The electric field results shown demonstrate that choosing the value of the sidewall dielectric constant can be used to control the maximum electric field at the heterodielectric interface and mitigate the occurrence of some of the high peak electric fields observed in some other devices described herein (e.g., without a "T-channel" design). Furthermore, using an oxide channel region with a "T-channel" design to move the Schottky barrier contact away from (or away from) the surface of the channel region can significantly reduce the peak electric field at the surface of the channel region (i.e., at the heterodielectric interface) in epitaxial oxide / Schottky devices.

[0572] in addition, Figure 95A The “T-channel” device designs shown and described herein can also be combined with any other device layer configurations and geometries described herein. For example, devices with transition layers (such as…) Figures 4 to 7 Those shown can also be obtained by... Figure 95AA transition layer is added between the SiC substrate 96110 and the oxide semiconductor drift layer 96125 to incorporate a "T-channel" design. In another example, an intermediate layer can be added between the oxide semiconductor channel region 96120 and the Schottky metal layer 96130, as described herein, for example... Figures 13 to 17 And as described in the associated description. In another example, a protective ring, such as..., can be added around the platform structure. Figure 39 D to Figure 39 As shown in G. As those skilled in the art will appreciate, many of the features of the devices described herein can be combined with a "T-channel" design, including but not limited to... Figure 20 , Figures 28 to 30 , Figure 40 , Figure 45 , Figure 48 , Figure 77A and Figures 79 to 80 The features shown.

[0573] Figure 96 An example device configuration is shown, in which repeating Figure 95A The illustrated device configuration (i.e., multiple devices placed side-by-side) forms a device array on a common SiC substrate 96110. In some cases, the top contacts (Schottky metal layer 96130 and optional field plate layer 96190) can be interconnected using electrical interconnects schematically shown by interconnect 97110. Interconnect 97110 can be a metal layer, metal trace, or wire bond wire that couples the field plate layers 96190 to each other. For example, interconnect 97110 can be a blanket metal layer covering the entire surface of the field plate layer 96190. In other cases, interconnect 97110 can be a patterned metal layer that electrically couples the field plate layer 96190. In some cases, the SiC substrate 96110 and the back contacts 96132 are shared by multiple devices in the device array. In some cases, the oxide semiconductor drift layer 96125 is shared by multiple devices in a device array, and the devices are separated by separate mesa structures comprising the oxide semiconductor channel region 96120 and the Schottky metal layer 96130, such as... Figure 96 As shown.

[0574] Figure 96Two devices are shown on a common SiC substrate 96110, but in other cases, 2 to 1000 devices can be formed on the common SiC substrate 96110 (e.g., in any other arrangement such as a rectangular array, a hexagonal array, or multiple mesa structures). Such a configuration including an array of devices can be advantageous. For example, current carrying capacity can be increased by multiplexing multiple parallel devices on the common SiC substrate 96110. By distributing vertical current among multiple parallel interconnected devices, a trade-off (or optimization) can be achieved between consumed epitaxial area, maximum vertical current capacity, and / or thermal effects. In some cases, the distance 97120 (e.g., minimum distance) between devices, shown as the distance from one wall (or sidewall) of a mesa to the wall (or sidewall) of an adjacent mesa, is adjusted (or optimized) to balance consumed epitaxial area, maximum vertical current capacity, and / or thermal effects. In some cases, the width 97130 of the mesa (or oxide semiconductor channel region 96120) in the x-direction, and the width 97130 of the mesa (or oxide semiconductor channel region 96120) in the z-direction (in... Figure 96 The width (outside the page plane) is adjusted (or optimized) to balance the consumed epitaxial area, maximum vertical current capacity, and / or thermal effects. In some cases, the minimum distance between devices 97120, the width of the mesa (or oxide semiconductor channel region 96120) in the x-direction 97130, and / or the width of the mesa (or oxide semiconductor channel region 96120) in the z-direction (in the... Figure 96 The width (outside the page plane) is adjusted (or optimized) to balance the consumed extraterrestrial area, maximum vertical current capacity, and / or thermal effects.

[0575] Figure 97A , Figure 97B and Figure 97C It shows that it has the following characteristics: Figure 95A Examples of devices with a described “T-channel” design, and additionally with a transition layer 96133, an intermediate layer 96131, or both. These structures can be advantageous because they combine the advantages of a “T-channel” device design with the advantages of a device design having the transition layer and / or intermediate layer described herein. For example, the transition layer 96133 can affect the electronic and structural properties of a semiconductor diode device, while the intermediate layer 96131 can alter the Schottky barrier properties and affect the electronic properties of the semiconductor diode device, such as the turn-on voltage and / or reverse breakdown voltage. The intermediate layer 96131 and the transition layer 96133 can each be a single layer, or can include multiple material layers, such as in a superlattice layer or a chirped layer.

[0576] Figure 97A It shows that it has the following characteristics: Figure 95AThe described "T-channel" design, and an example of a device further comprising a transition layer 96133 between a substrate layer 96110 and an oxide semiconductor drift layer 96125. The transition layer 96133 is similar to... Figures 4 to 7 and Figure 8B The transition layer 160 in the middle, and may have as relative to Figures 4 to 7 and Figure 8B The same properties are described in transition layer 160. Transition layer 96133 may have any of the properties of transition layers described herein. For example, transition layer 96133 may provide an intermediate level of doping and / or modulated interface strain between substrate 96110 and oxide semiconductor drift layer 96125, and thereby affect the electronic and structural properties of semiconductor diode devices, as further described herein.

[0577] The transition layer 96133 may be formed of a semiconductor oxide material, and the oxide semiconductor drift layer 96125 and the oxide semiconductor channel region 96120 may be formed of the same semiconductor oxide material as the transition layer 96133 or a different oxide material. In an example, the transition layer 96133 may be formed of a material selected to provide a structural matching region between the substrate 96110 and the oxide semiconductor drift layer 96125. For example, Mg... x Zn y Ni z (Al p Ga 1-p )O q A transition layer 96133 of a semiconductor oxide material (or another oxide semiconductor material described herein) may be formed between the SiC substrate 96110 and the oxide semiconductor drift layer 96125, wherein in some examples, the oxide semiconductor drift layer 96125 and / or the oxide semiconductor channel region 96120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. Another example of a semiconductor oxide material is silicon carbide (Si). x C y O z The form may include the transition layer 96133 and may be formed between the SiC substrate 96110 and the oxide semiconductor drift layer 96125, wherein in some examples, the oxide semiconductor drift layer 96125 and / or the oxide semiconductor channel region 96120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. Another example of a semiconductor oxide material is silicon oxynitride (Si). x N y O zThe form may include the transition layer 96133 and may be formed between the SiC substrate 96110 and the oxide semiconductor drift layer 96125, wherein in some examples, the oxide semiconductor drift layer 96125 and / or the oxide semiconductor channel region 96120 comprises Ga2O3 or compositionally graded Al. x Ga 1-x O3. Another example of the transition layer 96133 is one that includes silicon-germaniu...

Claims

1. A multilayer semiconductor device, the multilayer semiconductor device comprising: A substrate, said substrate comprising silicon carbide (SiC); An epitaxial transition layer, the epitaxial transition layer comprising a first epitaxial oxide material or SiC, wherein the epitaxial transition layer is on the substrate; One or more epitaxial active regions, the one or more epitaxial active regions comprising one or more second epitaxial oxide materials formed on the epitaxial transition layer; A metal layer above the one or more epitaxial active regions, wherein the metal layer includes one or more electrical contacts; and The multilayer semiconductor device includes one of the following: metal-oxide-semiconductor field-effect transistor, vertically conductive metal-oxide-semiconductor field-effect transistor, lateral field-effect transistor, metal-semiconductor field-effect transistor, bipolar junction transistor, junction field-effect transistor, metal-insulator-semiconductor device, PN device, PNP device, NPN device, or insulated-gate bipolar transistor.

2. The multilayer semiconductor device as claimed in claim 1, wherein: The vertical direction is perpendicular to the top surface of the substrate; The one or more epitaxial active regions include epitaxial drift regions formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions also include an epitaxial channel region formed on the top surface of the epitaxial drift region; A gate region is formed in the sidewall of the epitaxial channel region, and the gate region has an inner gate region boundary parallel to the sidewall; and The one or more epitaxial active regions further include a channel control region in the epitaxial channel region, the channel control region having a width defined by the boundary of the inner gate region.

3. The multilayer semiconductor device as described in claim 2, wherein: The one or more epitaxial active regions further include epitaxial source regions formed on the top surface of the epitaxial channel region; The metal layer includes a source contact formed on the top surface of the epitaxial source region; The substrate includes a drain region having a first conductivity type; The epitaxial drift region has the first conductivity type; The channel control region has the first conductivity type; The epitaxial source region has the first conductivity type; and The gate region has a second conductivity type.

4. The multilayer semiconductor device as claimed in claim 2, wherein: The sidewall of the extended channel region forms an angle with the vertical direction, making the extended channel region conical.

5. The multilayer semiconductor device as described in claim 2, wherein: The multilayer semiconductor device includes a junction field-effect transistor.

6. The multilayer semiconductor device as claimed in claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate is configured as a collector region; The epitaxial transition layer is configured as a buffer; The one or more epitaxial active regions include a first epitaxial implantation region formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions further include an epitaxial drift region formed on the top surface of the first epitaxial injection region; The one or more epitaxial active regions further include a second epitaxial injection region formed on the top surface of the epitaxial drift region; The one or more epitaxial active regions further include a body region formed within the second epitaxial injection region; The one or more epitaxial active regions further include emitter regions formed within the body region; A gate electrode is formed over one or more epitaxial active regions and is electrically isolated from the one or more epitaxial active regions by a gate oxide. The metal layer includes an emitter contact formed above the gate electrode, the emitter contact being electrically isolated from the gate electrode and electrically contacting the emitter region; and Collector contacts are formed on the bottom surface of the substrate.

7. The multilayer semiconductor device as claimed in claim 6, wherein: The collector region has a first conductivity type; The buffer has the first conductivity type; The first epitaxial implantation region has the opposite second conductivity type; The epitaxial drift region has the first conductivity type; The second epitaxial implantation region has the second conductivity type; The body region has the second conductivity type; and The emitter region has the first conductivity type.

8. The multilayer semiconductor device as claimed in claim 6, wherein: The multilayer semiconductor device includes an insulated gate bipolar transistor.

9. The multilayer semiconductor device as claimed in claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate is configured as a collector region; The epitaxial transition layer is configured as a buffer; The one or more epitaxial active regions include epitaxial injection regions formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions further include an epitaxial drift region formed on the top surface of the epitaxial injection region; The one or more epitaxial active regions also include an epitaxial channel region formed on the top surface of the epitaxial drift region; The one or more epitaxial active regions also include body regions formed within the epitaxial channel regions; The one or more epitaxial active regions further include emitter regions formed within the body region; A gate electrode is formed over one or more epitaxial active regions and is electrically isolated from the one or more epitaxial active regions by a gate oxide. The metal layer includes an emitter contact formed above the gate electrode, the emitter contact being electrically isolated from the gate electrode and electrically contacting the emitter region; and Collector contacts are formed on the bottom surface of the substrate.

10. The multilayer semiconductor device of claim 9, wherein: The collector region has a first conductivity type; The buffer has the first conductivity type; The epitaxial implantation region has the opposite second conductivity type; The epitaxial drift region has the first conductivity type; The epitaxial channel region has the first conductivity type; The body region has the second conductivity type; and The emitter region has the first conductivity type.

11. The multilayer semiconductor device of claim 10, wherein: The multilayer semiconductor device includes an insulated gate bipolar transistor.

12. The multilayer semiconductor device of claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate and the epitaxial transition layer are configured as a drain region; The one or more epitaxial active regions include epitaxial drift regions formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions also include a volume region formed within the epitaxial drift region; The one or more epitaxial active regions further include source regions formed within the body region; Drain contacts are formed on the bottom surface of the substrate; A gate electrode is formed over one or more epitaxial active regions and is electrically isolated from the one or more epitaxial active regions by a gate oxide. and The metal layer includes a source contact formed above the gate electrode, the source contact being electrically isolated from the gate electrode and electrically contacting the source region.

13. The multilayer semiconductor device of claim 12, wherein: The drain region has a first conductivity type; The epitaxial drift region has the first conductivity type; The body region has a second conductivity type; and The source region has the first conductivity type.

14. The multilayer semiconductor device of claim 12, wherein: The multilayer semiconductor device is a metal-oxide-semiconductor field-effect transistor.

15. The multilayer semiconductor device of claim 12, wherein: The multilayer semiconductor device is a vertically conductive metal-oxide-semiconductor field-effect transistor.

16. The multilayer semiconductor device of claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate is configured as a collector region; The epitaxial transition layer is configured as a buffer; The one or more epitaxial active regions include a first epitaxial implantation region formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions further include an epitaxial migration region formed on the top surface of the first epitaxial injection region; The one or more epitaxial active regions further include a second epitaxial injection region formed on the top surface of the epitaxial drift region; The one or more epitaxial active regions further include a body region formed on the top surface of the second epitaxial injection region; The one or more epitaxial active regions further include emitter regions formed within the body region; The isolation region extends vertically from the top surface of the body region and into the one or more epitaxial active regions; The gate electrode is formed within the isolation region; The metal layer includes an emitter contact formed above the gate electrode, the emitter contact being electrically isolated from the gate electrode by a gate oxide and electrically contacting the emitter region; and Collector contacts are formed on the bottom surface of the substrate.

17. The multilayer semiconductor device of claim 16, wherein: The collector region has a first conductivity type; The buffer has the first conductivity type; The first epitaxial implantation region has the opposite second conductivity type; The epitaxial drift region has the first conductivity type; The second epitaxial implantation region has the second conductivity type; The body region has the second conductivity type; and The emitter region has the first conductivity type.

18. The multilayer semiconductor device of claim 16, wherein: The multilayer semiconductor device includes an insulated gate bipolar transistor.

19. The multilayer semiconductor device of claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate is configured as a collector region; The epitaxial transition layer is configured as a buffer; The one or more epitaxial active regions include epitaxial injection regions formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions further include an epitaxial drift region formed on the top surface of the epitaxial injection region; The one or more epitaxial active regions also include an epitaxial channel region formed on the top surface of the epitaxial drift region; The one or more epitaxial active regions further include a body region formed on the top surface of the epitaxial channel region; The one or more epitaxial active regions further include emitter regions formed within the body region; The isolation region extends vertically from the top surface of the body region and into the one or more epitaxial active regions; The gate electrode is formed within the isolation region; The metal layer includes an emitter contact formed above the gate electrode, the emitter contact being electrically isolated from the gate electrode and electrically contacting the emitter region; and Collector contacts are formed on the bottom surface of the substrate.

20. The multilayer semiconductor device of claim 19, wherein: The collector region has a first conductivity type; The buffer has the first conductivity type; The epitaxial implantation region has the opposite second conductivity type; The epitaxial drift region has the first conductivity type; The epitaxial channel region has the first conductivity type; The body region has the second conductivity type; and The emitter region has the first conductivity type.

21. The multilayer semiconductor device of claim 19, wherein: The multilayer semiconductor device includes an insulated gate bipolar transistor.

22. The multilayer semiconductor device of claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate and the epitaxial transition layer are configured as a drain region; The one or more epitaxial active regions include epitaxial drift regions formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions further include an epitaxial body region formed on the top surface of the epitaxial drift region; The one or more epitaxial active regions further include source regions formed within the epitaxial body regions; The isolation region extends vertically from the top surface of the epitaxial body region and into the one or more epitaxial active regions; The gate electrode is formed within the isolation region; The metal layer includes a source contact formed above the gate electrode, the source contact being electrically isolated from the gate electrode by a gate oxide and electrically contacting the source region; and Drain contacts are formed on the bottom surface of the substrate.

23. The multilayer semiconductor device of claim 22, wherein: The drain region has a first conductivity type; The epitaxial drift region has the first conductivity type; The epitaxial region has a second conductivity type; and The source region has the first conductivity type.

24. The multilayer semiconductor device of claim 22, wherein: The multilayer semiconductor device is a metal-oxide-semiconductor field-effect transistor.

25. The multilayer semiconductor device of claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate is configured as an electrically isolated region; The one or more epitaxial active regions include epitaxial body regions formed on the top surface of the epitaxial transition layer; The epitaxial region includes a source region formed near the top surface of the epitaxial region; The epitaxial region further includes a drain region, which is formed near the top surface of the epitaxial region and is disposed laterally relative to the source region; A gate electrode is formed above the top surface of the epitaxial body region and electrically isolated from the epitaxial body region, and the gate electrode is laterally disposed between the source region and the drain region; The metal layer includes source contacts formed on the top surface of the source region; and The metal layer also includes a drain contact formed on the top surface of the drain region.

26. The multilayer semiconductor device of claim 25, wherein: The epitaxial region has a first conductivity type; The source region has a second conductivity type; and The drain region has the second conductivity type.

27. The multilayer semiconductor device of claim 25, wherein: The epitaxial region, the source region, and the drain region have the same conductivity type but different doping concentrations.

28. The multilayer semiconductor device of claim 26, further comprising: A drift region is formed near the top surface of the epitaxial region, the drift region being laterally separated from the source region by a portion of the epitaxial region and in contact with the drain region; in: The drain region has the second conductivity type.

29. The multilayer semiconductor device of claim 25, wherein: The multilayer semiconductor device is a lateral field-effect transistor.

30. The multilayer semiconductor device of claim 1, wherein: The vertical direction of the multilayer semiconductor cell is perpendicular to the top surface of the substrate; The substrate is configured as an electrically isolated region; The one or more epitaxial active regions include epitaxial drift regions formed on the top surface of the epitaxial transition layer; The one or more epitaxial active regions include a first channel region and a second channel region, the first channel region and the second channel region being formed on the top surface of the epitaxial drift region and disposed laterally to each other; An isolation region is formed on the top surface of the epitaxial drift region and is laterally formed between the first channel region and the second channel region; The first metal region of the metal layer is formed above the first channel region; and The second metal region of the metal layer is formed above the second channel region.

31. The multilayer semiconductor device of claim 30, wherein: The first metal region includes Schottky metal; The second metal region includes ohmic metal; and The first metal region and the first channel region form a Schottky barrier junction.

32. The multilayer semiconductor device of claim 30, wherein: The first metal region includes Schottky metal; The second metal region includes Schottky metal; The first metal region and the first channel region form a first Schottky barrier junction; and The second metal region and the second channel region form a second Schottky barrier junction.

33. The multilayer semiconductor device of claim 30, further comprising: A first ohmic contact is formed on the first metal region and the isolation region, the first ohmic contact extending laterally from the first metal region above the isolation region.

34. The multilayer semiconductor device of claim 30, wherein: The isolation region has a dielectric constant greater than or equal to that of the epitaxial drift region.

35. The multilayer semiconductor device of claim 30, wherein: The multilayer semiconductor device includes one of PNP, NPN, or MIS devices.

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