System and method for predicting power consumption of integrated circuits and method for designing integrated circuits
By using simulators and power prediction circuits to generate vector data in the early stages of integrated circuit design, the challenge of predicting power consumption in integrated circuits is solved, enabling accurate prediction and resource optimization, and reducing design costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2025-10-28
- Publication Date
- 2026-07-07
AI Technical Summary
In the process of integrated circuit design, existing technologies have difficulty accurately predicting power consumption in the early stages, leading to problems such as layout modifications and circuit corrections, which increase design time and resource consumption.
By generating vector data using a simulator and utilizing a power prediction circuit, the power consumption of an integrated circuit is predicted within a preset time using the input vector before the data synthesis gate level in the RTL design. This includes the system design of the processor, memory, simulator, and power prediction circuit.
It enables accurate power consumption prediction in the early stages of integrated circuit design, reducing design time and resource consumption, and lowering additional design costs.
Smart Images
Figure CN122347102A_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority to Korean Patent Application No. 10-2025-0048026, filed April 14, 2025, and U.S. Patent Application No. 63 / 742670, filed January 7, 2025, which are incorporated herein by reference in their entirety. Technical Field
[0003] Embodiments of this disclosure generally relate to semiconductor integrated circuits, and more specifically, to a system and method for predicting the power consumption of an integrated circuit, and a method for designing an integrated circuit using the system and method. Background Technology
[0004] As the manufacturing process for integrated circuits becomes smaller and the size of circuits integrated into a single chip increases, the power consumption of integrated circuits also increases.
[0005] During the verification phase of the layout design process—the final stage of integrated circuit design—excessive voltage drop may be detected in the integrated circuit. In such cases, layout modifications, circuit corrections, redesigns, etc., may be necessary, and the time and resources consumed in the design process may become obstacles to gaining product competitiveness.
[0006] Therefore, it is necessary to predict power consumption in the early stages of integrated circuit design and to respond to the predicted power consumption. Summary of the Invention
[0007] A system according to an embodiment of the present disclosure may include: a simulator configured to generate vector data by verifying the functionality of a target circuit implemented using Register-Transfer Level (RTL) design data; and a power prediction circuit configured to predict power consumption by processing multiple requests within a preset prediction time using the vector data as an input vector to the target circuit implemented using the RTL design data before the RTL design data is synthesized into a gate level.
[0008] A method for predicting power consumption according to an embodiment of the present disclosure may be an operational method of a system for predicting the power consumption of an integrated circuit, and may include: generating vector data by verifying the functionality of a target circuit implemented using register transfer level (RTL) design data; and predicting power consumption by controlling the target circuit implemented using the RTL design data to process multiple requests within a preset prediction time using the vector data as an input vector before synthesizing the RTL design data into a gate level.
[0009] A method for designing an integrated circuit according to an embodiment of the present disclosure may be an operational method of a system for designing an integrated circuit, and may include: receiving register transfer level (RTL) design data corresponding to the result of a behavioral level design of a target circuit; generating vector data by the system through verifying the functionality of the target circuit, the target circuit being implemented using the RTL design data; when the verification of the functionality is successful, controlling the target circuit implemented using the RTL design data to process multiple requests within a preset prediction time to predict power consumption by using the vector data as an input vector; and synthesizing the RTL design data with predicted power consumption into a gate level by the system.
[0010] The embodiments of this disclosure can accurately predict the power consumption of an integrated circuit at an early stage of integrated circuit design. Furthermore, it can minimize the time and resources required for integrated circuit design and reduce additional design costs. Attached Figure Description
[0011] Figure 1 This is a configuration diagram of a system for predicting the power consumption of an integrated circuit according to embodiments of the present disclosure.
[0012] Figure 2 This is a configuration diagram of integrated circuits according to embodiments of the present disclosure.
[0013] Figure 3 This is a configuration diagram of a power prediction circuit according to an embodiment of the present disclosure.
[0014] Figure 4 This is a diagram illustrating the concept of monitoring information for each time window and power prediction using the monitoring information, according to embodiments of the present disclosure.
[0015] Figure 5 This is a flowchart describing a method for predicting the power consumption of an integrated circuit according to embodiments of the present disclosure.
[0016] Figure 6 This is a diagram illustrating a method for designing an integrated circuit according to embodiments of the present disclosure. Detailed Implementation
[0017] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
[0018] Figure 1 This is a system configuration diagram of a predictive integrated circuit for power consumption according to an embodiment of the present disclosure, the integrated circuit being the target circuit for circuit design.
[0019] Reference Figure 1The system 10 may include a processor 110, a memory 120, a simulator 130, a power prediction circuit 140, a storage medium 150, an input device 160, an output device 170, and an external interface 180.
[0020] The components included in system 10 can be connected to each other, for example, via a bus, to enable mutual communication.
[0021] Processor 110 may include at least one core capable of running a particular instruction set. Processor 110 may execute instructions stored in memory 120 and may perform at least some of the power-predicted functions according to embodiments of the present disclosure by running programs stored in memory 120.
[0022] Memory 120 may be the working memory of system 10. Memory 120 may store programs to be run on system 10, register transfer stage (RTL) design data of the target circuit, reference input data required for simulating RTL design data, and vector data obtained as a result of simulation.
[0023] The program, RTL design data, reference input data, and vector data can be stored in the storage medium 150, and at least a portion of the program, RTL design data, reference input data, and vector data stored in the storage medium 150 can be loaded into the memory 120.
[0024] The memory 120 may include volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM), and may include non-volatile memory such as flash memory.
[0025] In an embodiment, processor 110 can execute at least a portion of a design target circuit or power consumption prediction by running at least one instruction included in a program stored in storage medium 150 and memory 120.
[0026] RTL design data and reference input data can be provided to simulator 130, and simulator 130 can generate vector data by simulating the operation of a target circuit defined by the RTL design data based on the reference input data. This vector data indicates the time-dependent values of the input signals, internal signals, and output signals of the RTL design data for the target circuit. In embodiments, the vector data can be at least one of a Value Change Dump (VCD) format or a Fast Signal Database (FSDB).
[0027] The power prediction circuit 140 can use vector data generated by the simulator 130 as an input vector to predict the power consumption of the target circuit.
[0028] The power prediction circuit 140 can receive RTL design data and input vectors of the target circuit, and then, within a preset operating time, run the target circuit represented in logic levels corresponding to the RTL design data according to the input vectors. The power prediction circuit 140 can divide the operating time of the RTL design data into a preset number of time windows based on the input vectors, and then predict the power consumption for each time window. The power prediction circuit 140 can predict the maximum power range based on the predicted power consumption for each time window.
[0029] Storage medium 150 can be configured to retain stored data even during power interruptions to the supply of power to system 10. In embodiments, storage medium 150 may include non-volatile memories such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM). Storage medium 150 may be detachably connected to system 10.
[0030] Storage medium 150 can store data to be processed by processor 110 and / or data already processed by processor 110. Storage medium 150 can store programs, RTL design data, reference input signals and vector data, and can also store data generated during the operation of system 10.
[0031] Input device 160 may include a keyboard, pointing device, etc., and output device 170 may include a display device, printer, speaker, etc. Through input device 160, the operator of system 10 can trigger processor 110 to run programs, input data required for the operation of system 10, or input conditions or data required for designing target circuits or predicting power consumption.
[0032] Through output device 170, system 10 can output signals generated during the design or power consumption prediction of the target circuit.
[0033] External interface 180 can provide access to networks outside of system 10. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or other types of links.
[0034] Figure 2 This is a configuration diagram of an integrated circuit as a target circuit in a circuit design according to embodiments of the present disclosure.
[0035] Integrated circuit 20 may include controller 210 and memory resources 220.
[0036] The controller 210 can respond to instructions from an external device (not shown), perform operations based on data sent from the external device or read from memory resource 220, and can store data accompanying the operations in memory resource 220. Memory resource 220 may include multiple memory devices 221, 223, and 225.
[0037] The controller 210 may include an external interface 211, a processor 213, and a memory controller 215.
[0038] The controller 210 can be connected to an external device via the external interface 211 and can then receive requests from the external device. The controller 210 can process requests from the external device under the control of the processor 213 and can control memory resources 220 in response to such request processing.
[0039] External interface 211 can relay communication between external devices and integrated circuit 20 based on the established interface protocol. In an embodiment, external interface 211 can support multiple sub-protocols defined in the Compute Express Link (CXL) protocol, and can send and receive messages and / or data between external devices and integrated circuit 20 through these multiple sub-protocols. Sub-protocols of the CXL protocol may include, for example, a non-conformance protocol (or I / O protocol: IO) (CXL.io), a conformance protocol (or cache protocol; CACHE) (CXL.cache), and a memory access protocol (or memory protocol: MEM) (CXL.mem).
[0040] Processor 213 may include an accelerator that provides functionality useful to external devices. For example, processor 213 may include at least one of the following: a programmable component such as a Graphic Processing Unit (GPU) or a Neural Processing Unit (NPU); a component providing fixed functionality such as an Intellectual Property (IP) core; and a reconfigurable component such as a Field Programmable Gate Array (FPGA).
[0041] The memory controller 215 can communicate with the memory resource 220 based on a protocol independent of or dependent on the external interface 211. The memory controller 215 can access the memory resource 220 under the control of the processor 213 to read or write data. The memory controller 215 can provide access to the memory resource 220, and can also provide access to the memory resource 220 by external devices through the external interface 211. In some embodiments, the memory resource 220 may correspond to a memory attached to a device having a CXL specification.
[0042] In this embodiment, integrated circuit 20 may be a CXL memory device, but is not limited thereto.
[0043] System 10 can predict power consumption and maximum power range by operating RTL design data within a preset operating time according to an input vector generated by simulating the RTL design data of integrated circuit 20, which is a CXL memory device.
[0044] Figure 3 This is a configuration diagram of a power prediction circuit 140 according to an embodiment of the present disclosure.
[0045] Reference Figure 3 The power prediction circuit 140 may include an RTL design data processing circuit 141, a first parameter calculation circuit 143, a second parameter calculation circuit 145, and a maximum power range prediction circuit 147.
[0046] RTL design data execution circuit 141 can provide an external device request to integrated circuit 20 represented by RTL design data, and can process the RTL design data, that is, can cause integrated circuit 20 to run for a preset time—for example, predict the time—based on the input vector. The input vector may include signal information required by integrated circuit 20 to process the external device request. Here, the external device may be virtual for integrated circuit 20, and therefore the external device request may be predetermined.
[0047] The first parameter calculation circuit 143 can divide the prediction time into a preset number of time windows, and then calculate the average number of outstanding requests for each time window, i.e., the average outstanding count.
[0048] The uncompleted count (OSC) can be the number of requests provided from an external device to the integrated circuit 20 for which the integrated circuit 20 has not yet sent a response signal to the external device. In other words, the uncompleted count (OSC) can be the number of requests for which the integrated circuit 20 has not yet completed processing.
[0049] In this embodiment, the average number of unfinished tasks can be calculated based on the following [Equation 1]. .
[0050] [Equation 1]
[0051]
[0052] In [Equation 1], " st "It can be the start time of each time window," et "It can be the end time of the time window, and" "It can be a time window" t The incomplete count.
[0053] The second parameter calculation circuit 145 can calculate the average throughput for each time window.
[0054] In this embodiment, the average throughput can be calculated based on the following [Equation 2]. .
[0055] [Equation 2]
[0056]
[0057] In [Equation 2], " st "It can be the start time of each time window," et "It can be the end time of the time window, and" "It can be within a time window" t The number of requests with a specific length.
[0058] The maximum power range prediction circuit 147 can predict the average unfinished count for each time window within the prediction time. and average throughput The average number of incomplete counts and average throughput The maximum power range corresponding to the corresponding maximum value.
[0059] Compared with the average number of uncompleted counts The time window corresponding to the maximum value can be different from that of the average throughput. The time window corresponding to the maximum value. In this case, it can be compared with the average unfinished count. The time window corresponding to the maximum value and the average throughput The time window corresponding to the maximum value is considered as the maximum power range for both.
[0060] Figure 4This is a diagram illustrating the concept of monitoring information for each time window and power prediction using the monitoring information, according to embodiments of the present disclosure.
[0061] Reference Figure 4 During the power prediction interval T to T+n, the power prediction circuit 140 can control the integrated circuit 20 implemented using RTL design data to run the request of an external device according to the input vector.
[0062] The power prediction circuit 140 can divide the power prediction interval T to T+n into multiple time windows T to T+a, T+a to T+b, ..., T+(n-2) (not shown) to T+(n-1) and T+(n-1) to T+n.
[0063] The power prediction circuit 140 can calculate the average unfinished count for each of the time windows TW1 (T to T+a), TW2 (T+a to T+b), ..., TWn (T+(n-1) to T+n). and average throughput .
[0064] The power prediction circuit 140 can predict the average number of unfinished counts. Maximum or average throughput The maximum value or a combination of both of these time windows TWx is predicted as the interval with the maximum power consumption, i.e., the maximum power interval.
[0065] Figure 5 This is a flowchart illustrating a method for predicting the power consumption of integrated circuit 20 according to embodiments of the present disclosure.
[0066] Figure 5 A method can be used to show the power consumption within a unit time window of the prediction interval.
[0067] The power consumption prediction system 10 can predict power consumption when it makes a request to the integrated circuit 20 implemented using the RTL design data within a preset prediction time, based on the input vector obtained from the simulation results as RTL design data.
[0068] Reference Figure 5 System 10 can provide a request to integrated circuit 20 in operation S100, and can increment the request count and incomplete count OSC in operation S101.
[0069] System 10 can calculate the average uncompleted count (OSC) and average throughput in the current time window during operation S103.
[0070] System 10 can determine in operation S105 whether the request count exceeds the threshold TH. When the request count does not exceed the threshold TH (in the case of "No" in operation S105), system 10 can provide a request to integrated circuit 20 in operation S100.
[0071] When the request count exceeds the threshold TH (if "Yes" is true in operation S105), system 10 can determine whether the average uncompleted count OSC of the current time window is greater than the maximum value of the average uncompleted count OSC calculated in at least one previous time window. Optionally, in operation S107, system 10 can determine whether the maximum value of the average uncompleted count OSC of at least one previous time window is equal to the average uncompleted count OSC of the current time window, and can determine whether the average throughput of the current time window is greater than the maximum value of the average throughput of at least one previous time window.
[0072] When the average uncompleted count (OSC) of the current time window is greater than the maximum value of the average uncompleted count (OSC) calculated in at least one previous time window, or when the maximum value of the average uncompleted count (OSC) calculated in at least one previous time window is equal to the average uncompleted count (OSC) of the current time window and the average throughput of the current time window is greater than the maximum value of the average throughput calculated in at least one previous time window (if "Yes" is true in operation S107), the system 10 may update the maximum value using the average uncompleted count (OSC) or average throughput of the current time window in operation S109, and may store the updated maximum value as predicted data in operation S111.
[0073] When the average uncompleted count OSC in the current time window is less than the maximum value of the average uncompleted count OSC calculated in at least one previous time window, or when the maximum value of the average uncompleted count OSC calculated in at least one previous time window is equal to the average uncompleted count OSC in the current time window and the average throughput in the current time window is less than the maximum value of the average throughput calculated in at least one previous time window (in the case of "No" in operation S107), system 10 can reset the request count and uncompleted count OSC in operation S113 and can predict the power consumption in the next time window.
[0074] The predicted maximum power range can be stored in the controller of the physically designed integrated circuit 20, and can then be used for Quality of Service (QoS) policies, such as throttling of the integrated circuit 20.
[0075] Figure 6 This is a diagram illustrating a method for designing an integrated circuit 20 according to an embodiment of the present disclosure.
[0076] Reference Figure 6 For example, a behavioral-level design can be performed in operation S201, which is configured to design the functionality of the integrated circuit 20 as desired by system 10. The behavioral-level design can be a process that allows the target circuit to operate according to a predetermined algorithm.
[0077] When the functional design is complete, in operation S203, RTL design can be executed through system 10. That is, integrated circuit 20 can be designed at the logic level using RTL. Through RTL design, integrated circuit 20 can be represented by RTL design data. RTL design can be the process of accurately executing the data transfer between the designed registers and integrated circuit 20 represented by RTL design data.
[0078] In an embodiment, RTL design can be a programming process using a Hardware Description Language (HDL). Examples of HDLs include Verilog and VHSIC Hardware Description Language (VHDL).
[0079] Following the RTL design, in operation S205, system 10 can perform functional verification on the RTL design data. Functional verification can be a process of generating vector data by simulating the operation of integrated circuit 20 defined by the RTL design data based on reference input data. This vector data indicates the time-dependent values of the input signals, internal signals, and output signals of integrated circuit 20.
[0080] If the RTL design data operation fails (in the case of "No" in operation S207), the RTL design can be re-executed through system 10 in operation S203.
[0081] When the RTL design data is successfully processed (in the case of "Yes" in operation S207), system 10 can use the vector data generated as a result of functional verification as an input vector to predict the power consumption of the target circuit in operation S209.
[0082] As referenced above Figures 3 to 5 The process of predicting power consumption, as described, may include the following steps: dividing the power consumption prediction interval into multiple time windows; calculating the average uncompleted count and average throughput for each time window; and predicting the time window corresponding to the maximum value of the average uncompleted count and / or the maximum value of the average throughput as the maximum power interval.
[0083] In operation S211, system 10 can synthesize RTL design data by converting RTL design data into a gate-level netlist based on design conditions and libraries. Design conditions may include conditions related to area, speed, power, etc. Libraries may include information such as standard cells, memory, and functional circuits (IPs).
[0084] In operation S213, system 10 can physically design integrated circuit 20 based on the synthesis results.
[0085] When the RTL design data, which is the result of operation S203, is successfully run, the maximum power range can be predicted, and thus it can be determined in advance whether the power conditions required for the synthesis process in operation S211 are met.
[0086] Therefore, when power conditions are not met, the integrated circuit can be modified immediately at the RTL level, thereby reducing the time and resources consumed in integrated circuit design.
[0087] As described above, those skilled in the art to which this disclosure pertains will understand that embodiments of this disclosure may be implemented in other specific forms without departing from the spirit or essential characteristics of this disclosure. Therefore, it should be understood that the above embodiments are illustrative and not restrictive in all respects. It should be understood that embodiments of this disclosure are defined by the appended claims rather than specific embodiments, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are included within the scope of this disclosure. Furthermore, these embodiments may be combined to form other embodiments.
Claims
1. A system comprising: The simulator generates vector data by verifying the functionality of the target circuit, which is implemented using register transfer level design data, i.e., RTL design data. as well as A power prediction circuit, before the RTL design data is synthesized into a gate level, predicts power consumption by having the target circuit implemented using the RTL design data use the vector data as an input vector to process multiple requests within a preset prediction time.
2. The system according to claim 1, wherein, The power prediction circuit divides the prediction time into a preset number of time windows, and predicts power consumption for each time window.
3. The system according to claim 1, wherein, The power prediction circuit divides the prediction time into a preset number of time windows, and calculates the average unfinished count and average throughput for each of the time windows.
4. The system according to claim 1, wherein, The power prediction circuit: The predicted time is divided into a preset number of time windows, and for each time window, the average unfinished count and average throughput are calculated. The time window corresponding to the maximum value of the average incomplete count, or the time window corresponding to the maximum value of the average throughput, or a combination of both, is predicted as the maximum power consumption range.
5. The system according to claim 1, wherein, The target circuit includes a computational fast link memory device, namely a CXL memory device.
6. A method of operating a system for predicting the power consumption of a target circuit, the method comprising: Vector data is generated by verifying the functionality of the target circuit, which is implemented using register transfer level design data, i.e., RTL design data. as well as Before synthesizing the RTL design data into a gate level, power consumption is predicted by controlling the target circuit implemented using the RTL design data to process multiple requests within a preset prediction time using the vector data as an input vector.
7. The operating method according to claim 6, wherein, The predicted power consumption includes: The predicted time is divided into a preset number of time windows, and the predicted power consumption is calculated for each time window.
8. The operating method according to claim 6, wherein, The predicted power consumption includes: The predicted time is divided into a preset number of time windows, and the average unfinished count and average throughput are calculated for each of the time windows.
9. The operating method according to claim 6, wherein, The predicted power consumption includes: The predicted time is divided into a preset number of time windows, and for each time window, the average unfinished count and average throughput are calculated; and The time window corresponding to the maximum value of the average incomplete count, or the time window corresponding to the maximum value of the average throughput, or a combination of both, is predicted as the maximum power consumption range.
10. A method for operating a system for designing a target circuit, the method comprising: The system receives register transfer level design data, i.e., RTL design data, corresponding to the behavioral level design results of the target circuit. The system generates vector data by verifying the functionality of the target circuit, which is implemented using the RTL design data. When the function is successfully verified, the system controls the target circuit implemented using the RTL design data to use the vector data as the input vector and process multiple requests within a preset prediction time to predict power consumption. as well as The system synthesizes the RTL design data, which predicts power consumption, into a gate level.
11. The operating method according to claim 10, wherein, The predicted power consumption includes: The predicted time is divided into a preset number of time windows, and the predicted power consumption is calculated for each time window.
12. The operating method according to claim 10, wherein, The predicted power consumption includes: The predicted time is divided into a preset number of time windows, and the average unfinished count and average throughput are calculated for each of the time windows.
13. The operating method according to claim 10, wherein, The predicted power consumption includes: The predicted time is divided into a preset number of time windows, and for each time window, the average unfinished count and average throughput are calculated; and The time window corresponding to the maximum value of the average incomplete count, or the time window corresponding to the maximum value of the average throughput, or a combination of both, is predicted as the maximum power consumption range.