Clock signal receiver circuit with active inductance, common mode voltage source and negative capacitance

Abstract

In one implementation, an apparatus (such as a clock signal receiver circuit) is disclosed. The apparatus includes: a common mode voltage generator configured to generate a common mode voltage at an output; an input circuit including: a first field effect transistor (FET); a second FET; a first capacitor coupled between a first differential clock input and a first gate of the first FET; a second capacitor coupled between a second differential clock input and a second gate of the second FET; a first resistive device coupled between the output of the common mode voltage generator and the first gate of the first FET; and a second resistive device coupled between the output of the common mode voltage generator and the second gate of the second FET; and an active inductive circuit coupled in series with the first FET and the second FET between an upper voltage rail and a lower voltage rail, respectively.

Description

Cross-reference to related applications

[0001] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 537,708, filed December 12, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] All aspects of this disclosure relate in general to serializer-deserializer (SerDes) communication links, and more specifically to a clock signal receiver comprising an active inductor circuit, an input circuit (including a common voltage source), one or more negative capacitors, and a current-mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) converter. Background Technology

[0003] A serializer / deserializer (SerDes) communication link is used to transmit one or more data signals and an associated clock signal from a transmitting device to a receiving device. The receiving device in a clock-forwarding SerDes architecture typically includes a clock signal receiver configured to process the clock signal for data detection of the associated one or more data signals. Summary of the Invention

[0004] The following is a simplified overview of one or more specific implementations to provide a basic understanding of such implementations. This overview is not an exhaustive summary of all envisioned implementations, nor is it intended to identify key or essential elements of all implementations, nor to depict the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0005] One aspect of this disclosure relates to an apparatus. The apparatus includes: a common-mode voltage generator configured to generate a common-mode voltage at an output; and an input circuit including: a first field-effect transistor (FET) (e.g., Figure 4 M41); second FET (e.g., Figure 4 M42); First capacitor (e.g., Figure 4 (C41), the first capacitor is coupled between the first differential clock input and the first gate of the first FET; the second capacitor (e.g., Figure 4 (C42), the second capacitor is coupled between the second differential clock input and the second gate of the second FET; the first resistor device (e.g., Figure 4(R41), the first resistive device is coupled between the output of the common-mode voltage generator and the first gate of the first FET; and the second resistive device (e.g., R41) Figure 4 (R42), the second resistor device is coupled between the output of the common-mode voltage generator and the second gate of the second FET; and the active inductor circuit (e.g., Figure 4 (M54 and M55), the active inductor circuit is coupled in series with the first FET and the second FET between the upper voltage rail and the lower voltage rail, respectively.

[0006] Another aspect of this disclosure relates to a method. The method includes: AC coupling a first differential clock signal to the gates of a differential pair of field-effect transistors (FETs); providing common-mode voltages to the gates of the differential pair of the FETs; and amplifying the first differential clock signal, including operating an active inductor circuit using the differential pair of the FETs to generate a second differential clock signal.

[0007] Another aspect of this disclosure relates to an apparatus. The apparatus includes: means for AC coupling a first differential clock signal to the gates of a differential pair of field-effect transistors (FETs); means for providing common-mode voltages to the gates of the differential pair of the FETs; and means for amplifying the first differential clock signal, including operating an active inductor circuit using the differential pair of the FETs to generate a second differential clock signal.

[0008] Another aspect of this disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a wireless transceiver including a radio frequency (RF) front end coupled to the at least one antenna, wherein the wireless transceiver includes a first data / clock signal transceiver; a serializer / deserializer (SerDes) communication link coupled to the first data / clock signal transceiver; and at least one integrated circuit (IC) including one or more signal processing cores coupled to a second data / clock signal transceiver, wherein the second data / clock signal transceiver is coupled to the SerDes communication link.

[0009] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the description of the embodiments is intended to include all such aspects and their equivalents. Attached Figure Description

[0010] Figure 1 A block diagram illustrating an example clock forwarder serializer-deserializer (SerDes) communication link according to one aspect of this disclosure is shown.

[0011] Figure 2 A schematic diagram of an example clock signal receiver circuit according to another aspect of this disclosure is shown.

[0012] Figure 3 A block diagram of another example clock signal receiver circuit according to another aspect of this disclosure is shown.

[0013] Figure 4 A block diagram of another example clock signal receiver circuit according to another aspect of this disclosure is shown.

[0014] Figure 5 A schematic diagram of another example clock signal receiver circuit according to another aspect of this disclosure is shown.

[0015] Figure 6 A flowchart illustrating an example method for processing clock signals according to another aspect of this disclosure is provided.

[0016] Figure 7 A block diagram illustrating an example wireless communication device according to another aspect of this disclosure is shown. Detailed Implementation

[0017] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0018] Figure 1A block diagram illustrating an example clock-forward serializer-deserializer (SerDes) communication link 100 according to one aspect of this disclosure is shown. The SerDes communication link 100 includes a first set of one or more data channels (shown as slices) for transmitting data from a clock signal transmitter side (left) to a clock receiver side (right). Each data channel in the first set of one or more data channels includes a data signal transmitter 110, a channel 170, and a data signal receiver 120. Similarly, the SerDes communication link 100 includes a second set of one or more data channels (shown as slices) for transmitting data from the clock receiver side to the clock transmitter side. Each data channel in the second set of one or more data channels includes a data signal transmitter 130, a channel 190, and a data signal receiver 140. Furthermore, the SerDes communication link 100 includes a clock data channel that includes a clock signal transmitter 150, a channel 180, and a clock signal receiver circuit 160. The clock signal may be a periodic square wave signal used to clock pulses for transmitting and receiving data.

[0019] The data signal transmitter 110 further includes a parallel-to-serial (P2S) converter 112, a feedforward equalizer (FFE) 114, a transmit driver 116, and a first terminating resistor R. T1 (It can be variable), differential output pads 118+ / 118-, and clock buffer 113. In one example, differential output pads 118+ / 118- may include electrostatic discharge (ESD) protection circuitry (not shown). The P2S converter 112 is configured to operate based on a phase-locked loop (PLL) based clock signal CLK received via clock buffer 113. PLL To receive and serialize parallel data signals D TXP1 (For example, generated at a downstream component (e.g., a modem) to generate a serial data signal D) TXS1 The FFE 114 is configured to equalize the serial data signal D. TXS1 To generate equalized data signal D TXSE1 This is to compensate for signal loss caused during propagation via channel 170. The transmit driver 116 is configured to amplify and / or level-shift equalize the data signal D. TXSE1 Differential transmit signal D is generated across differential output pads 118+ / 118-. TX1 First terminating resistor R T1 The characteristic impedance Zo of channel 170 can be set to reduce unwanted signal reflections at data signal transmitter 110. Differential transmission signal D TX1 It is transmitted to the data signal receiver 120 via channel 170.

[0020] The data signal receiver 120 includes differential input pads 121+ / 121- and a second terminating resistor R. T2 (It can be variable), amplifier / equalizer 122 (e.g., a variable gain amplifier followed by a continuous-time linear equalizer (CTLE) or a CTLE with gain), slicer 124, serial-to-parallel (S2P) converter 126, clock and data recovery (CDR) circuitry 128, and clock buffer 129. When transmitting data signal D TX1 When propagating through channel 170, the transmitted data signal serves as the received data signal D. RX1 Data signal reaches receiver 120. Second terminating resistor R T2 The characteristic impedance Zo of channel 170 can be set to reduce unwanted signal reflections at data signal receiver 120. Amplifier / equalizer 122 amplifies and equalizes the received data signal D. RX1 (For example, to compensate for signal loss across channel 170), to generate amplified / equalized data signal D. RXSE1 Slicer 124 will amplify / equalize the data signal D. RXSE1 Converted into serial data signal D RXS1 The S2P converter 126 converts the serial data signal D... RXS1 Converted into parallel data signal D RXP1 This parallel data signal can be provided to the transmitter front end for wireless transmission. The CDR128 is based on the parallel data signal D. RXP1 and the output received clock signal CLK received via clock buffer 129 RXO To generate clock signal CLK RXS1 (For example, its clock pulse edge is essentially located at the same position as the serial data signal D) RXS1 (The middle of the associated eye diagram).

[0021] Similarly, the data signal transmitter 130 includes a parallel-to-serial (P2S) converter 132, a feedforward equalizer (FFE) 134, a transmit driver 136, and a third terminating resistor R. T3 (It can be variable), differential output pads 138+ / 138-, and clock buffer 133. The P2S converter 132 is configured to receive and serialize the parallel data signal D based on the clock signal received via clock buffer 133. TXP2 (For example, generated at an upstream component (e.g., the receiver front end)) to generate the serial data signal D TXS2 The FFE 134 is configured to equalize the serial data signal D. TXS2 To generate equalized data signal D TXSE2 This is to compensate for signal loss during propagation via channel 190. The transmit driver 136 is configured to amplify and / or level-shift equalize the data signal D.TXSE2 Differential transmit signal D is generated by spanning differential output pads 138+ / 138-. TX2 Third terminating resistor R T3 The characteristic impedance Zo of channel 190 can be set to reduce unwanted signal reflections at data signal transmitter 130. Differential transmission signal D TX2 It is transmitted to the data signal receiver 140 via channel 190.

[0022] The data signal receiver 140 includes differential input pads 141+ / 141- and a fourth terminating resistor R. T4 (It can be variable), amplifier / equalizer 142 (e.g., a variable gain amplifier followed by a CTLE or a CTLE with gain), slicer 144, serial-to-parallel (S2P) converter 146, clock and data recovery (CDR) circuitry 148, and clock buffer 149. When transmitting data signal D TX2 When propagating through channel 190, the transmitted data signal serves as the received data signal D. RX2 Data signal reaches receiver 140. Fourth terminating resistor R T4 The characteristic impedance Zo of channel 190 can be set to reduce unwanted signal reflections at data signal receiver 140. Amplifier / equalizer 142 amplifies and equalizes the received data signal D. RX2 (For example, to compensate for signal loss across channel 190), to generate amplified / equalized data signal D. RXSE2 Slicer 144 amplifies / equalizes the data signal D. RXSE2 Converted into serial data signal D RXS2 The S2P converter 146 converts the serial data signal D... RXS2 Converted into parallel data signal D RXP2 This parallel data signal can be provided to the modem for further processing. CDR 148 is based on the parallel data signal D. RXP2 and the PLL-based clock signal CLK received via clock buffer 149 PLL To generate clock signal CLK RXS2 (For example, its clock pulse edge is essentially located at the same position as the serial data signal D) RXS2 (The middle of the associated eye diagram).

[0023] Clock signal transmitter 150 includes phase-locked loop (PLL) 152, clock buffer 153, duty cycle controller (DCC) 154, transmit driver 156, and fifth terminating resistor R. T5 And differential output pads 158+ / 158-. PLL 152 is configured to generate a PLL-based clock signal CLK. PLLAs discussed earlier, the PLL-based clock signal CLK PLL Clock buffer 113 is provided to PS2 converter 112 via data signal transmitter 110, and clock buffer 149 is provided to CDR 148 via data signal receiver 140. Clock buffer 153 is configured to output a PLL-based clock signal CLK from PLL 152. PLL The DCC 154 is configured to control the PLL-based clock signal CLK. PLL The duty cycle is used to generate the duty cycle controlled clock signal CLK. DC The transmit driver 156 is configured to amplify and / or level-shift the duty cycle control of the clock signal CLK. DC A differential transmit clock signal CLK is generated by spanning differential output pads 158+ / 158-. TX Fifth terminating resistor R T5 The characteristic impedance Zo of channel 180 can be set to reduce unwanted signal reflections at clock signal transmitter 150. Differential transmission clock signal CLK TX It is transmitted to the clock signal receiver 160 via channel 180.

[0024] The clock signal receiver 160 includes differential input pads 161+ / 161- and a sixth terminating resistor R. T6 (It can be variable), clock signal receiver circuit 162, differential-to-single-ended (Δ2SE) converter 164, duty cycle controller (DCC) 166, and clock buffer 168. When transmitting clock signal CLK... TX When propagating through channel 180, the transmit clock signal serves as the receive data signal CLK. RX The clock signal reaches receiver 160. Sixth terminating resistor R T6 The characteristic impedance Zo of channel 180 can be set to reduce unwanted signal reflections at clock signal receiver 160. As discussed further in more detail herein, clock signal receiver circuit 162 receives the clock signal CLK. RX Amplification, equalization, and conversion to rail-to-rail swing are performed to generate a differential amplified / equalized / rail-to-rail clock signal C. RXE The Δ2SE converter 164 is configured to convert the clock signal CLK... RXE Converted to single-ended clock signal CLK RXSE Clock buffer 168 is configured to buffer the single-ended clock signal CLK. RXSE To generate the output receive clock signal CLK RXOAs previously discussed, the output receive clock signal is provided to CDR 128 via clock buffer 129 of data signal receiver 120 and to P2S 132 via clock buffer 133 of data signal transmitter 130.

[0025] Figure 2 A schematic diagram illustrating an example clock signal receiver circuit 200 according to another aspect of this disclosure is shown. The clock signal receiver circuit 200 may be an example implementation of the clock signal receiver circuit 162 of the SerDes communication link 100.

[0026] The clock signal receiver circuit 200 includes a current source in the form of a field-effect transistor (FET) (e.g., a p-channel FET) M21, which includes a source coupled to an upper voltage rail Vdd and a drain coupled to the respective sources of FETs M22 and M23 (e.g., also p-channel FETs). FET M21 may have a variable or programmable size to set the current range of the current source. FET M21 includes a gate configured to receive a bias voltage vbp for setting the current generated by the current source FET M21 (within the programmed current range). FETs M22 and M23 operate as an input differential pair, which includes gates configured to receive differential clock signals inp / inn (e.g., CLK), respectively. RX ).

[0027] The clock signal receiver circuit 200 also includes an inductor-capacitor (LC) energy storage circuit, which includes a capacitor C21 (which may be variable) coupled across the drains of FETs M22 and M23, respectively. The LC energy storage circuit may also include inductor pairs L21 and L22 coupled between the drains of FETs M22 and M23 and the drains of FETs M24 and M27 (e.g., n-channel FETs), respectively. Additionally, to reduce the Q of the LC energy storage circuit, the clock signal receiver circuit 200 also includes resistor pairs R21 and R22 coupled between inductors L21 and L22 and the drains of FETs M25 and M26 (e.g., n-channel FETs), respectively. FETs M24 and M27, as well as FETs M25 and M26, include gates configured to receive high-speed (hs) and medium-speed (ms) control signals, respectively. The sources of FETs M24 through M27 are coupled to a lower voltage rail (e.g., ground). The clock signal receiver circuit 200 includes differential outputs outp / outn, which are coupled to nodes between the drains of FETs M22 and M23 and inductors L21 and L22, respectively.

[0028] The clock signal receiver circuit 200 also includes a negative resistor circuit comprising a current source in the form of a FET M28 (e.g., a p-channel FET), which is coupled between the upper voltage rail Vdd and the respective sources of FETs M29 and M30 (e.g., also p-channel FETs). The FET M28 may have a variable or programmable size to set the current range of the current source. The FET M28 includes a gate configured to receive a bias voltage vbp for setting the current generated by the current source FET M28 (within the programmed current range). FETs M29 and M30 include gates coupled to the drains of FETs M30 and M29, and the differential output terminals outp / outn, respectively. Although the lines connecting the gates (M29 / M30) to the drains (M30 / M29) are shown as a cross for illustration purposes, these lines are not actually connected.

[0029] In operation, for high-speed (hs) or high-frequency clock signal operation (e.g., speeds or frequencies higher than medium-speed (ms), the hs control signal is asserted, and the ms control signal is deasserted. This turns on FETs M24 and M27, and turns off FETs M25 and M26. Therefore, the clock signal receiver circuit 200 is configured to include a substantially un-Q-diminished LC circuit tuned to the frequency of the clock signals inp / inn to provide an output amplified clock signal outp / outn. For medium-speed (ms) or high-frequency clock signal operation, the hs control signal is deasserted, and the ms control signal is asserted. This turns off FETs M24 and M27, and turns on FETs M25 and M26. This causes resistors R21 and R22 to Q-diminished the LC energy storage circuit to save power when a lower-frequency clock signal inp / inn is received. Therefore, the clock signal receiver circuit 200 is configured to include a Q-dropped LC circuit tuned to the frequency of the clock signals inp / inn to provide an output amplified clock signal outp / outn. Negative resistor circuits (e.g., M28 to M30) cancel the parasitic resistance associated with the LC energy storage circuit to support the target resonance of the LC energy storage circuit.

[0030] Several disadvantages may exist associated with the clock signal receiver circuit 200. For example, the common-mode voltage associated with the received clock signal inp / inn may drift, and if this drift is too high, it may cause operational problems such as reducing the gate-to-source voltage of FETs M22 and M23, which may adversely reduce or essentially stop the current flowing through such devices. Furthermore, the clock signal receiver circuit 200 may consume significant power via inductors L21 / L22, resistors R21 / R22, and FETs M24 through M27. Additionally, such inductors L21 / L22 and resistors R21 / R22 may consume significant circuit or integrated circuit (IC) area, which may be undesirable. Finally, the clock signal receiver circuit 200 may introduce clock signal delay (e.g., due to LC injection lock-in delay), which may affect the output clock signal CLK applied to slicer 124. RXS1 Jitter (e.g., high N cycle jitter) (e.g., clock signal CLK) RXS1 The clock pulse edge may be received by the data signal D. RXSE1 (The eye diagram shows jitter near the middle).

[0031] Figure 3A block diagram illustrating another example of a clock signal receiver circuit 300 according to another aspect of this disclosure is shown. The clock signal receiver circuit 300 may be an example implementation of the clock signal receiver circuit 160 of the SerDes communication link 100. As discussed further in more detail herein, the clock signal receiver circuit 300 addresses the shortcomings discussed with respect to the clock signal receiver circuit 200.

[0032] For example, the input differential clock signal is AC-coupled to the input differential pair 315, and an internally generated common-mode voltage vcm is applied to the input differential pair 315. This effectively eliminates any common-mode voltage drift from the input clock signal. Additionally, to save power and circuit area, inductors L21 / L22, resistors R21 / R22, and Q-down mode FETs M24 to M27 are eliminated. Furthermore, the clock signal receiver circuit 300 includes an active inductor circuit 330 to better control the frequency poles or peaks to achieve the desired frequency response of the clock signal receiver circuit 300. In a more detailed implementation, the clock signal receiver circuit 300 includes input and output negative capacitors to mitigate or cancel parasitic capacitance and to provide a fast phase step response to improve clock jitter (e.g., N-cycle clock jitter).

[0033] Specifically, the clock signal receiver circuit 300 includes an input circuit 310, a common-mode voltage generator 320, an active inductor circuit 330, and a current-mode logic to complementary metal-oxide-semiconductor (CML to CMOS) converter 340. The input circuit 310 further includes an input differential FET pair 315, an AC coupling capacitor pair C31 and C32, and a resistor pair R31 and R32 (e.g., typically resistive devices). The AC coupling capacitors C31 and C32 are coupled between the differential clock signal input terminals inp / inn and the differential input terminals in+ / in- (e.g., the gate) of the input differential FET pair 315. Similarly, the resistors R31 and R32 are coupled between the output terminal (Vcm) of the common-mode voltage generator 320 and the differential input terminals in+ / in- of the input differential FET pair 315.

[0034] An active inductor circuit 330 is differentially series coupled to an input differential FET pair 315 (e.g., via its differential outputs ou+ / ou-) between an upper voltage rail Vdd and a lower voltage rail (e.g., ground). The active inductor circuit 330 is configured to receive a control signal (CS) for controlling the frequency response of a clock signal receiver circuit 300. A CML-to-CMOS converter 340 includes differential inputs + / - coupled to the differential outputs ou+ / ou- of the input differential FET pair 315. The CML-to-CMOS converter 340 includes differential clock signal outputs outp / outn.

[0035] Input differential clock signal CLK IN The differential input terminals inp / inn are routed to the differential input terminals in+ / in- of the input differential FET pair 315 via AC coupling capacitors C31 and C32, respectively. Therefore, AC coupling capacitors C31 and C32 essentially block the input differential clock signal CLK. IN The associated common-mode voltage. Therefore, the clock signal receiver circuit 300 is essentially unaffected by the input clock signal CLK. IN The common-mode drift effect. In addition, the common-mode voltage generator 320 is configured to generate a substantially stable common-mode voltage vcm, which is applied to the differential input terminals in+ / in- of the input differential FET pair 315 via resistors R31 and R32, respectively.

[0036] The active inductor circuit 330 is configured to receive a control signal CS for controlling the frequency response (e.g., poles or peaks) of the clock signal receiver circuit 300. Therefore, the input differential FET pair 315, combined with the active inductor circuit 330, is configured to generate an intermediate differential clock signal CLK at the differential output terminals ou+ / ou- of the input differential FET pair 315. INT This intermediate differential clock signal compensates for losses incurred during channel propagation. The CML-to-CMOS converter 340 is configured to receive and process the intermediate differential clock signal CLK. INT To generate a rail-to-rail differential clock signal CLK at the differential output terminals outp / outn. OUT .

[0037] Figure 4 A block diagram illustrating another example of a clock signal receiver circuit 400 according to another aspect of this disclosure is shown. The clock signal receiver circuit 400 may be an example implementation of the clock signal receiver circuit 160 of the SerDes communication link 100. The clock signal receiver circuit 400 may be a more detailed implementation of an example of the previously discussed clock signal receiver circuit 300. The clock signal receiver circuit 400 includes an input circuit 410, a first negative capacitor circuit 420, a common-mode voltage generator 430, an active inductor circuit 440, a second negative capacitor circuit 450, and a CML-to-CMOS converter 460.

[0038] The first negative capacitor circuit 420 includes a first FET M44 (e.g., a p-channel FET, which may have a programmable size) and a second FET M46 (e.g., a p-channel FET), which are coupled in series (via their respective source and drain) between the upper voltage rail Vdd and the first (e.g., positive) differential input inp of the clock signal receiver circuit 400. The first negative capacitor circuit 420 also includes a third FET M45 (e.g., a p-channel FET, which may have a programmable size) and a fourth FET M47 (e.g., a p-channel FET), which are coupled in series (via their respective source and drain) between the upper voltage rail Vdd and the second (e.g., negative) differential input inn of the clock signal receiver circuit 400. FETs M44 and M45 include gates coupled together, which are configured to receive a bias voltage pbias for setting the current through FETs M44 and M45. Additionally, the first negative capacitor circuit 420 includes a capacitor C43 coupled across the drains of FETs M44 and M45 (and across the sources of FETs M46 and M47). FETs M46 and M47 include gates coupled to the differential input terminals inn / inp, respectively.

[0039] The common-mode voltage generator 430 includes a reference current source Iref (e.g., a bandgap current source) coupled in series with the drain and source of a first FET M48 (e.g., n-channel) between an upper voltage rail Vdd and a lower voltage rail (e.g., ground). FET M48 includes a gate coupled to its drain. The common-mode voltage generator 430 also includes a second FET M50 (e.g., p-channel) coupled in series with a third FET M49 (e.g., n-channel) (via their respective source / drain and drain / source) between the upper and lower voltage rails. FET M49 includes a gate coupled to the gate of FET M48, both gates being configured to receive a bias voltage nbias. FET M50 includes a gate coupled to its drain. Additionally, the common-mode voltage generator 430 includes a fourth FET (e.g., a p-channel FET) series coupled between the upper voltage rail Vdd and the lower voltage rail, a first diode-connected FET M52, and a second diode-connected FET M53. FET M51 includes a gate coupled to the gate of FET M50, both gates being configured to receive a bias voltage pbias. Three pins Iref-M48, M50-M49, and M51-M53 form a current mirror to mirror a reference current to the third pin, where a common-mode voltage vcm is generated at the drains of FETs M51 and M52.

[0040] Input circuitry 410 includes differential FET pairs M41 and M42 (e.g., n-channel FETs) coupled in series with FET M43 (e.g., an n-channel FET, which may have a programmable size) between the differential outputs ou+ / out- and the lower voltage rail. FET M43 includes a gate configured to receive a bias voltage nbias. Additionally, input circuitry 410 includes AC coupling capacitors C41 and C42 coupled between the differential inputs inp / inn of clock signal receiver circuitry 400 and the gates of FETs M41 and M42, respectively. Furthermore, input circuitry 410 includes resistors R41 and R42 (e.g., typically resistive devices) coupled in series between the drains of FETs M41 and M42 (e.g., the outputs of a common-mode voltage generator 430 that generates a common-mode voltage vcm) and the gates of FETs M41 and M42, respectively.

[0041] The active inductor circuit 440 includes a first FET M54 (e.g., a p-channel FET) coupled between the upper voltage rail Vdd and the positive differential output terminal ou+ of the input circuit 410. The active inductor circuit 440 includes a first capacitor C44 (e.g., the first capacitor may have a programmable capacitance) coupled in series with a first resistor R43 (e.g., a typical resistive device that may have a programmable resistor) between the upper voltage rail Vdd and the positive differential output terminal ou+ of the input circuit 410. The active inductor circuit 440 includes a second capacitor C45 (e.g., the second capacitor may have a programmable capacitance) coupled in series with a second resistor R44 (e.g., it may typically have a programmable resistor) between the upper voltage rail Vdd and the negative differential output terminal ou- of the input circuit 410.

[0042] The second negative capacitor circuit 440 includes a first FET M56 (e.g., a p-channel FET, which may have a programmable size) and a second FET M58 (e.g., a p-channel FET), the first FET M56 and the second FET M58 (via their respective source and drain) being series coupled between the upper voltage rail Vdd and the positive differential output terminal ou+ of the input circuit 410. The second negative capacitor circuit 450 also includes a third FET M57 (e.g., a p-channel FET, which may have a programmable size) and a fourth FET M59 (e.g., a p-channel FET), the third FET M57 and the fourth FET M59 (via their respective source and drain) being series coupled between the upper voltage rail Vdd and the negative differential output terminal ou- of the input circuit 410. FETs M56 and M57 include gates coupled together and configured to receive a bias voltage pbias for setting the current through FETs M56 and M57. Additionally, the second negative capacitor circuit 450 includes a capacitor C46 coupled across the drains of FETs M56 and M57 (and across the sources of FETs M58 and M59). FETs M58 and M59 include gates that are coupled to the differential outputs ou- and ou+ of the input circuit 410, respectively.

[0043] The CML-to-CMOS converter 460 includes a first AC coupling capacitor C47 and a second AC coupling capacitor C48, a first feedback inverter and a second feedback inverter (e.g., FET M60 and FET M61 and feedback resistor R45; and FET M62 and FET M63 and feedback resistor R46), a latch (which includes cross-coupled inverters INV1 and INV2), and a first output inverter INV3 and a second output inverter INV4. The first feedback inverter includes an FET M60 (e.g., a p-channel FET) coupled in series with an FET M61 (e.g., an n-channel FET) (via their respective source / drain and drain / source) between the upper voltage rail Vdd and the lower voltage rail. The first AC coupling capacitor C47 is coupled between the positive differential output terminal ou+ of the input circuit 410 and the gates of FET M60 and FET M61. A feedback resistor R45 (e.g., typically a resistive device) is coupled between the drain and gate of FETs M60 and M61. A second feedback inverter includes FET M62 (e.g., a p-channel FET) coupled in series with FET M63 (e.g., an n-channel FET) (via their respective source / drain and drain / source) between the upper voltage rail Vdd and the lower voltage rail. A second AC coupling capacitor C48 is coupled between the negative differential output terminal ou- of input circuit 410 and the gates of FETs M62 and M63. A feedback resistor R46 (e.g., typically a resistive device) is coupled between the drain and gate of FETs M62 and M63.

[0044] Cross-coupled inverters INV1 and INV2 are coupled between the outputs of the first feedback inverter and the second feedback inverter (the drains of FET M60 / FET M61 and FET M62 / FET M63). The first output inverter INV3 and the second output inverter INV4 include inputs coupled to the outputs of the first feedback inverter and the second feedback inverter, as well as the differential outputs outp / outn of the clock signal receiver circuit 400.

[0045] During operation, the differential clock signal CLK is input. IN The differential input terminals inp / inn are provided to the clock signal receiver circuit 400. The differential clock signal is CLK. IN The capacitors are ac-coupled to the gates of the input differential FET pair M41 and M42 via ac-coupling capacitors C41 and C42, respectively. The ac-coupling capacitors C41 and C42 essentially block the input differential clock signal CLK. INThe associated common-mode voltage ensures that the operation of the clock signal receiver circuit 400 is unaffected by such common-mode voltage drift. The common-mode voltage vcm (which can be substantially stable due to the bandgap current reference Iref) is applied to the gates of the input differential FET pair M41 and M42 via resistors R41 and R42, respectively. Therefore, this effectively eliminates the operational problem of common-mode voltage drift. The first negative capacitor circuit 420 cancels or mitigates the parasitic capacitance associated with the input circuit 410 to improve the bandwidth of the clock signal receiver circuit 400.

[0046] The active inductor circuit 440 presents the active inductor output impedance of the input circuit 410 to generate relatively high frequency poles or peaks in the frequency response of the clock signal receiver circuit 460. The programmable capacitors C44 and C45, and the programmable resistors R43 and R44, can be configured to place high-frequency poles based on the input differential clock signal CLK. IN The intermediate differential clock signal CLK is generated by using the differential output terminals ou+ / ou- of the input circuit 410. INT And compensate for the input differential clock signal CLK IN This causes channel loss. The second negative capacitor circuit 450 cancels or reduces the parasitic capacitance associated with the input of the CML to CMOS converter 460 to improve the bandwidth of the clock signal receiver circuit 400.

[0047] The CMOS to CMOS converter 460, across the clock signal receiver circuit 400, generates a rail-to-rail (e.g., essentially Vdd to ground) differential clock signal CLK at its differential output terminals outp / outn. OUT The first feedback inverter M60-M61-R45 and the second feedback inverter M62-M63-R46 receive the intermediate differential clock signal CLK via AC coupling capacitors C47 and C48, respectively. INT The first feedback inverter M60-M61-R45 and the second feedback inverter M62-M63-R46 convert the intermediate differential clock signal CLK... INT Converted to a basic rail-to-rail differential clock signal CLK RR The latches (cross-coupled inverters INV1 and INV2) latch the rail-to-rail differential clock signal CLK. RR The output inverters INV3 and INV4 (e.g., used as buffers) will output the rail-to-rail differential clock signal CLK. RR Invert to generate the output differential clock signal CLK OUT .

[0048] In one example Figure 4 The CMOS clock signal receiver circuit 400 is replaceable. Figure 2A clock signal receiver circuit 200 based on LC injection locking. Although Figure 2 and Figure 4 The two clock signal receiver circuits can achieve the same functionality, but the clock signal receiver has higher power / area efficiency, less injection latch-up delay, and is more robust to the input VCM level.

[0049] Figure 5 A schematic diagram illustrating another example of a clock signal receiver circuit 500 according to another aspect of this disclosure is shown. The clock signal receiver circuit 500 may be an example implementation of the clock signal receiver circuit 162 of the SerDes communication link 100. The clock signal receiver circuit 500 includes a common-mode voltage generator 520 configured to generate a common-mode voltage vcm at its output.

[0050] The clock signal receiver circuit 500 further includes an input circuit 510, which includes: a differential pair 515 (i.e., a first field-effect transistor (FET) F1 and a second FET F2); a first capacitor C51 coupled between a first differential clock input terminal inp and a first gate g1 of the first FET F1; a second capacitor C52 coupled between a second differential clock input terminal inn and a second gate g2 of the second FET F2; a first resistor device R51 coupled between the output of a common-mode voltage generator 520 and the first gate g1 of the first FET F1; and a second resistor device R52 coupled between the output of the common-mode voltage generator 520 and the second gate g2 of the second FET F2. The clock signal receiver circuit 500 also includes an active inductor circuit 530, which is differentially coupled in series with the first FET F1 and the second FET F2 between an upper voltage rail Vdd and a lower voltage rail (e.g., ground).

[0051] Figure 6 A flowchart illustrating an example method 600 for processing a clock signal according to another aspect of this disclosure is shown. Method 600 includes coupling a first differential clock signal AC to the gate of a differential pair of a field-effect transistor (FET) (block 610). Examples of components for coupling the first differential clock signal AC to the gate of the differential pair of the field-effect transistor (FET) include any one of AC coupling capacitors C31-C32, C41-C42, and C51-C52.

[0052] Method 600 further includes providing a common-mode voltage to the gates of the differential pair of the FETs (block 620). Examples of components for providing a common-mode voltage to the gates of the differential pair of the FETs include any of common-mode voltage generators 320, 430, and 520, and any of resistive devices R31-R32, R41-R42, and R51-R52. Additionally, method 600 includes amplifying a first differential clock signal, including operating an active inductor circuit using the differential pair of the FETs to generate a second differential clock signal (block 630). Examples of components for amplifying the first differential clock signal (including operating an active inductor circuit using the differential pair of the FETs to generate the second differential clock signal) include input differential FET pairs 315 and 515, FET M41 and FET M42, and any of active inductor circuits 330, 440, and 530.

[0053] Figure 7 A block diagram illustrating an example wireless communication device 700 according to another aspect of this disclosure is shown. The wireless communication device 700 may be a smartphone, desktop computer, laptop computer, tablet device, Internet of Things (IoT), wearable wireless device (e.g., wireless watch), and other types of wireless devices.

[0054] Specifically, the wireless communication device 700 includes an integrated circuit (IC) that can be implemented as a system-on-a-chip (SOC) 710. The SOC 710 includes one or more signal processing cores 720, each including a data / clock signal transceiver 730. The one or more signal processing cores 720 are configured to generate a transmit baseband (BB) signal and process a receive baseband (BB) signal. The data / clock signal transceiver 730 is configured to transmit the baseband (BB) signal along with a transmit clock signal CLK. TX Send to the wireless transceiver (WTR) 740 and receive the receive baseband (BB) signal along with the receive clock signal CLK from the wireless transceiver (WTR) 740. RX Both are communicated via the serializer / deserializer (SerDes) communication link 780. Regarding the reception of the receive clock signal CLK... RX The data / clock transceiver 730 may include a clock signal receiver, such as one of the clock signal receivers 300, 400 and 500 described herein.

[0055] The wireless communication device 700 may also include a wireless transceiver (WTR) 740 and at least one antenna 770 (e.g., an antenna array). The transceiver 740 is configured to convert a transmit baseband (BB) signal into a transmit radio frequency (RF) signal and a receive RF signal into a receive BB signal. In this regard, the wireless transceiver (WTR) 740 includes a data / clock signal transceiver 750 configured to receive the transmit baseband (BB) signal along with the transmit clock signal CLK. TX It will receive the baseband (BB) signal and the clock signal CLK. RX The data / clock signal transceiver 730 sent to IC 710 is both transmitted via the SerDes communication link 780. Regarding the receiving and transmitting clock signal CLK... TX The data / clock transceiver 750 may include a clock signal receiver, such as one of the clock signal receiver circuits 300, 400 and 500 described herein.

[0056] The transceiver 740 also includes a radio frequency (RF) front end 760 configured to convert a transmit baseband (BB) signal into a transmit RF signal and a receive RF signal into a receive baseband (BB) signal. The transceiver 740 is coupled to at least one antenna 770 to provide a transmit RF signal for electromagnetic radiation into a wireless medium for wireless transmission, and to receive a receive RF signal electromagnetically picked up from the wireless medium by the at least one antenna 770.

[0057] The following provides an overview of the various aspects of this disclosure:

[0058] Aspect 1: An apparatus comprising: a common-mode voltage generator configured to generate a common-mode voltage at an output; an input circuit comprising: a first field-effect transistor (FET); a second FET; a first capacitor coupled between a first differential clock input and a first gate of the first FET; a second capacitor coupled between a second differential clock input and a second gate of the second FET; a first resistive device coupled between the output of the common-mode voltage generator and the first gate of the first FET; a second resistive device coupled between the output of the common-mode voltage generator and the second gate of the second FET; and an active inductor circuit coupled in series with the input circuit (e.g., the first FET and the second FET) between an upper voltage rail and a lower voltage rail.

[0059] Aspect 2: The apparatus according to aspect 1, wherein the input circuit further includes a third FET coupled between the first FET and the second FET and the lower voltage rail, wherein the third FET includes a third gate configured to receive a bias voltage.

[0060] Aspect 3: The apparatus according to aspect 1 or 2, wherein the size of the third FET is programmable.

[0061] Aspect 4: The apparatus according to any one of Aspects 1 to 3, wherein the active inductor circuit comprises: a third FET coupled between the upper voltage rail and the first FET of the input circuit; a fourth FET coupled between the upper voltage rail and the second FET of the input circuit; a first capacitor coupled in series with a third resistive device between the upper voltage rail and a first node between the first FET and the third FET, wherein a second node between the first capacitor and the third resistive device is coupled to a third gate of the third FET; and a second capacitor coupled in series with a fourth resistive device between the upper voltage rail and a third node between the second FET and the fourth FET, wherein a fourth node between the second capacitor and the fourth resistive device is coupled to a fourth gate of the fourth FET.

[0062] Aspect 5: The apparatus according to aspect 4, wherein the first capacitor and the second capacitor are each configured with a programmable capacitor.

[0063] Aspect 6: The apparatus according to aspect 4 or 5, wherein the third resistor device and the fourth resistor device are each configured with a programmable resistor.

[0064] Aspect 7: The apparatus according to any one of Aspects 1 to 6, wherein the common-mode voltage generator comprises: a current source configured to generate a first current; one or more current mirrors configured to generate a second current based on the first current; and one or more diode-connected FETs configured to generate the common-mode voltage based on the second current.

[0065] Aspect 8: The apparatus according to any one of Aspects 1 to 7, the apparatus further comprising a current-mode logic to complementary metal-oxide-semiconductor (CML to CMOS) converter, the current-mode logic to complementary metal-oxide-semiconductor (CML to CMOS) converter including a first differential input coupled to a first node between the active inductor circuit and the first FET of the input circuit, and a second differential input coupled to a second node between the active inductor circuit and the second FET of the input circuit.

[0066] Aspect 9: The apparatus according to aspect 8, wherein the CML to CMOS converter comprises: a first feedback inverter; a third capacitor coupled between the first node and a first input terminal of the first feedback inverter; a second feedback inverter; and a fourth capacitor coupled between the second node and a second input terminal of the feedback inverter.

[0067] Aspect 10: The apparatus according to Aspect 9, wherein the CML to CMOS converter further comprises: a latch coupled across a first output and a second output of the first feedback inverter and the second feedback inverter, respectively; a first inverter coupled between the first output of the first feedback inverter and a first differential clock output; and a second inverter coupled between the second output of the second feedback inverter and a second differential clock output.

[0068] Aspect 11: The apparatus according to any one of Aspects 1 to 10, the apparatus further comprising a negative capacitor circuit coupled to the first differential clock input and the second differential clock input.

[0069] Aspect 12: The apparatus according to any one of Aspects 1 to 11, the apparatus further comprising a negative capacitor circuit coupled to a first node and a second node between the active inductor circuit and the first FET and the second FET, respectively.

[0070] Aspect 13: A method comprising: AC coupling a first differential clock signal to the gates of a differential pair of field-effect transistors (FETs); providing common-mode voltages to the gates of the differential pair of the FETs; and amplifying the first differential clock signal, including operating an active inductor circuit using the differential pair of the FETs to generate a second differential clock signal.

[0071] Aspect 14: According to the method of aspect 13, wherein coupling the first differential clock signal ac to the gate of the differential pair of the FET includes passing the first differential clock signal through the capacitor pair respectively.

[0072] Aspect 15: The method according to aspect 13 or 14, wherein providing a common-mode voltage to the gate of the differential pair of the FET comprises passing the first differential clock signal through the resistor pair, respectively.

[0073] Aspect 16: The method according to any one of aspects 13 to 15, the method further comprising generating the common-mode voltage.

[0074] Aspect 17: The method according to any one of aspects 13 to 16, the method further comprising applying a negative capacitor to a differential input receiving the first differential clock signal.

[0075] Aspect 18: The method according to any one of Aspects 13 to 17, the method further comprising: generating a second differential clock signal at a differential output of the differential pair of the FET; and applying a negative capacitor to the differential output of the differential pair of the FET.

[0076] Aspect 19: The method according to any one of aspects 13 to 18, the method further comprising generating a third differential clock signal having a substantially rail-to-rail voltage swing based on the second differential clock signal.

[0077] Aspect 20: The method according to any one of aspects 13 to 19, the method further comprising operating the active inductor circuit to achieve a specific frequency response associated with the generation of the second differential clock signal.

[0078] Aspect 21: An apparatus comprising: means for AC coupling a first differential clock signal to the gates of a differential pair of field-effect transistors (FETs); means for providing common-mode voltages to the gates of the differential pair of the FETs; and means for amplifying the first differential clock signal, including operating an active inductor circuit using the differential pair of the FETs to generate a second differential clock signal.

[0079] Aspect 22: A wireless communication device comprising: at least one antenna; a wireless transceiver including a radio frequency (RF) front end coupled to the at least one antenna, wherein the wireless transceiver includes a first data / clock signal transceiver; a serializer / deserializer (SerDes) communication link coupled to the first data / clock signal transceiver; and at least one integrated circuit (IC) including one or more signal processing cores coupled to a second data / clock signal transceiver, wherein the second data / clock signal transceiver is coupled to the SerDes communication link.

[0080] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: A common-mode voltage generator, configured to generate a common-mode voltage at its output; Input circuit, the input circuit comprising: First field-effect transistor (FET); Second FET; A first capacitor is coupled between a first differential clock input and a first gate of the first FET. The second capacitor is coupled between the second differential clock input and the second gate of the second FET; A first resistive device is coupled between the output of the common-mode voltage generator and the first gate of the first FET; and A second resistive device is coupled between the output of the common-mode voltage generator and the second gate of the second FET; and An active inductor circuit is connected in series with the input circuit between the upper voltage rail and the lower voltage rail.

2. The apparatus of claim 1, wherein the input circuitry further comprises a third FET coupled between the first FET and the second FET and the lower voltage rail, wherein the third FET includes a third gate configured to receive a bias voltage.

3. The apparatus of claim 2, wherein the size of the third FET is programmable.

4. The apparatus of claim 1, wherein the active inductor circuit comprises: A third FET is coupled between the upper voltage rail and the first FET of the input circuit; A fourth FET, which is coupled between the upper voltage rail and the second FET of the input circuit; A first capacitor is coupled in series with a third resistive device between the upper voltage rail and a first node between the first FET and the third FET, wherein a second node between the first capacitor and the third resistive device is coupled to the third gate of the third FET; and A second capacitor is coupled in series with a fourth resistive device between the upper voltage rail and a third node between the second FET and the fourth FET, wherein the fourth node between the second capacitor and the fourth resistive device is coupled to the fourth gate of the fourth FET.

5. The apparatus of claim 4, wherein the first capacitor and the second capacitor are each configured with a programmable capacitor.

6. The apparatus of claim 4, wherein the third resistor device and the fourth resistor device are each configured with a programmable resistor.

7. The apparatus of claim 1, wherein the common-mode voltage generator comprises: A current source, configured to generate a first current; One or more current mirrors, the one or more current mirrors being configured to generate a second current based on the first current; and One or more diode-connected FETs are configured to generate the common-mode voltage based on the second current.

8. The apparatus of claim 1, further comprising a current-mode logic to complementary metal-oxide-semiconductor (CML to CMOS) converter, the current-mode logic to complementary metal-oxide-semiconductor (CML to CMOS) converter including a first differential input coupled to a first node between the active inductor circuit and the first FET of the input circuit, and a second differential input coupled to a second node between the active inductor circuit and the second FET of the input circuit.

9. The apparatus of claim 8, wherein the CML to CMOS converter comprises: First feedback inverter; A third capacitor is coupled between the first node and the first input terminal of the first feedback inverter; Second feedback inverter; and A fourth capacitor is coupled between the second node and the second input terminal of the feedback inverter.

10. The apparatus of claim 9, wherein the CML to CMOS converter further comprises: A latch, wherein the latch is coupled across the first output terminal and the second output terminal of the first feedback inverter and the second feedback inverter, respectively; The first inverter is coupled between the first output terminal of the first feedback inverter and the first differential clock output terminal; and The second inverter is coupled between the second output terminal of the second feedback inverter and the second differential clock output terminal.

11. The apparatus of claim 1, further comprising a negative capacitor circuit coupled to the first differential clock input and the second differential clock input.

12. The apparatus of claim 1, further comprising a negative capacitor circuit, the negative capacitor circuit being coupled to a first node and a second node between the active inductor circuit and the first FET and the second FET, respectively.

13. A method, the method comprising: The first differential clock signal is AC coupled to the gate of the differential pair of field-effect transistors (FETs); A common-mode voltage is provided to the gate of the differential pair of the FET, respectively; as well as Amplifying the first differential clock signal includes operating an active inductor circuit using the differential pair of the FET to generate a second differential clock signal.

14. The method of claim 13, wherein coupling the first differential clock signal ac to the gate of the differential pair of the FET comprises passing the first differential clock signal through the capacitor pair, respectively.

15. The method of claim 13, wherein providing a common-mode voltage to the gate of the differential pair of the FET comprises passing the first differential clock signal through the resistor pair, respectively.

16. The method of claim 13, further comprising generating the common-mode voltage.

17. The method of claim 13, further comprising applying a negative capacitor to the differential input terminal receiving the first differential clock signal.

18. The method according to claim 13, further comprising: The second differential clock signal is generated at the differential output terminal of the differential pair of the FET respectively; as well as Negative capacitances are applied to the differential output terminals of the differential pair of the FETs, respectively.

19. The method of claim 18, further comprising generating a third differential clock signal having a substantially rail-to-rail voltage swing based on the second differential clock signal.

20. The method of claim 13, further comprising operating the active inductor circuit to achieve a specific frequency response associated with generating the second differential clock signal.

21. An apparatus comprising: A component for AC coupling a first differential clock signal to the gate of a differential pair of field-effect transistors (FETs); Components for providing common-mode voltages to the gates of the differential pair of the FETs, respectively; and The components for amplifying the first differential clock signal include an active inductor circuit that utilizes the differential pair of the FET to generate a second differential clock signal.

22. The apparatus of claim 21, wherein the means for coupling the first differential clock signal ac to the gate of the differential pair of the FET includes means for passing the first differential clock signal through the capacitor pair, respectively.

23. The apparatus of claim 21, wherein the component for providing a common-mode voltage to the gate of the differential pair of the FET includes components for passing the first differential clock signal through the resistor pair, respectively.

24. A wireless communication device, the wireless communication device comprising: At least one antenna; A wireless transceiver, the wireless transceiver including a radio frequency (RF) front end coupled to the at least one antenna, wherein the wireless transceiver includes a first data / clock signal transceiver; A serializer / deserializer (SerDes) communication link, coupled to the first data / clock transceiver; and At least one integrated circuit (IC) includes one or more signal processing cores coupled to a second data / clock transceiver, wherein the second data / clock transceiver is coupled to the SerDes communication link.

25. The wireless communication device of claim 24, wherein the first data / clock signal transceiver comprises: A common-mode voltage generator, configured to generate a common-mode voltage at its output; Input circuit, the input circuit comprising: First field-effect transistor (FET); Second FET; A first capacitor is coupled between a first differential clock input and a first gate of the first FET. The second capacitor is coupled between the second differential clock input and the second gate of the second FET; A first resistive device is coupled between the output of the common-mode voltage generator and the first gate of the first FET; and A second resistive device is coupled between the output of the common-mode voltage generator and the second gate of the second FET; and An active inductor circuit is connected in series with the input circuit between the upper voltage rail and the lower voltage rail.

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