Capacitance measurement circuit and capacitance measurement method

Abstract

The application discloses a capacitor measurement circuit and a capacitor measurement method, and belongs to the field of semiconductors. The capacitor measurement circuit can accurately measure the junction capacitance of a semiconductor detector (a device to be measured) in real time and on line while applying thousands of volts of direct-current working voltage to the semiconductor detector by coupling an alternating-current test signal in a high-voltage bias loop and directly responding to charge changes by using a detection module, so that the measurement result truly reflects the capacitance characteristics of the device under the actual high-voltage working state. The entire circuit adopts a topology combining alternating-current injection and charge detection, effectively isolates the influence of high-voltage direct current on the precision detection circuit, guarantees high measurement precision and a signal-to-noise ratio, has good electrical safety, and is also compatible with the capacitor measurement demand under conventional low-voltage or zero-bias conditions, thereby improving the universality and application flexibility of the circuit.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to capacitance measurement circuits and capacitance measurement methods. Background Technology

[0002] In the research and performance evaluation of semiconductor detectors (such as high-purity germanium detectors and silicon detectors), junction capacitance is a key parameter reflecting the internal electric field distribution, depletion layer thickness, and charge collection efficiency of the device. However, such detectors require a high voltage bias of several kilovolts to achieve full depletion during actual operation. Commercial precision LCR (inductance, capacitance, and resistance) meters or impedance analyzers typically have low safety test voltages (generally below 100V), making online measurement impossible under the high voltage conditions of actual detector operation. Therefore, existing technologies can only perform offline measurements at zero or low bias, resulting in capacitance values ​​that deviate from the device's true operating point and fail to accurately reflect the actual characteristics of junction capacitance under high voltage. This leads to a lack of crucial on-the-go data support for process diagnostics, performance evaluation, and quality control. While some customized high-voltage measurement solutions exist, they are often complex, costly, or lack versatility, making it difficult to simultaneously meet the dual requirements of kV-level high voltage application and high-precision capacitance measurement, and also unable to flexibly accommodate a wide range of measurement needs from zero to high bias. Summary of the Invention

[0003] To address the problem that existing commercial LCR oscilloscopes and other instruments cannot perform online capacitance measurements under the high-voltage conditions of actual semiconductor detector operation due to insufficient test voltage, resulting in measured values ​​deviating from the true operating point and a lack of effective data support for process diagnosis and performance evaluation, this paper provides a capacitance measurement circuit and method designed to achieve synchronous and accurate measurement under a high-voltage bias of several kilovolts.

[0004] This application provides a capacitance measurement circuit, including:

[0005] The bias module has its output connected to one end of the device under test (DUT) and is used to apply a DC operating voltage to the DUT and to couple an AC signal through a second capacitor C2.

[0006] The signal injection terminal is connected between the output terminal of the bias module and one end of the device under test, and is used to input a test AC signal.

[0007] The detection module has its input end connected to the other end of the device under test (DUT) and is used to detect the charge change of the DUT and output a voltage signal in response to the test AC signal.

[0008] Optionally, the bias module includes:

[0009] A first resistor R1, one end of which is connected to a first power supply;

[0010] The second resistor R2 has one end connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to one end of the second capacitor C2 to serve as the output terminal of the bias module. The other end of the second capacitor C2 is used to connect to the AC signal.

[0011] The first capacitor C1 has one end grounded and the other end connected to the other end of the first resistor R1.

[0012] Optionally, it also includes:

[0013] A voltage divider module is connected between the signal injection terminal and the bias module. The input terminal of the voltage divider module is connected to the signal injection terminal to receive the test AC signal and to attenuate the test AC signal.

[0014] Optionally, the voltage divider module includes:

[0015] The third resistor R3, one end of which serves as the input terminal of the voltage divider module;

[0016] The fourth resistor R4 has one end connected to the other end of the third resistor R3, which together serve as the output terminal of the third resistor R3 and is connected to the bias module; the other end of the fourth resistor R4 is grounded.

[0017] Optionally, the detection module includes:

[0018] The fifth resistor R5, one end of which is connected to the second power supply;

[0019] An operational amplifier, wherein the non-inverting input terminal of the operational amplifier is connected to the other end of the fifth resistor R5, and the inverting input terminal of the operational amplifier is connected to a bias voltage;

[0020] A field-effect transistor, wherein the drain of the field-effect transistor is connected to the other end of the fifth resistor R5, and the source of the field-effect transistor is grounded;

[0021] The sixth resistor R6, one end of which is connected to the gate of the field-effect transistor;

[0022] The third capacitor C3, one end of which is connected to one end of the sixth resistor R6 and the gate of the field-effect transistor, together serving as the input terminal of the detection module, and the other end of the third capacitor C3, which is connected to the other end of the sixth resistor R6 and the output terminal of the operational amplifier, together serving as the output terminal of the detection module.

[0023] Optionally, the device under test includes a capacitor under test and a reference element;

[0024] The capacitance measurement circuit also includes:

[0025] A switching unit is used to selectively switch the input terminal of the detection module to the other end of the capacitor under test or the measurement terminal of the reference element;

[0026] When connected to the reference element, it is used to perform circuit verification or calibration; when connected to the capacitor under test, it is used to perform capacitance measurement.

[0027] This application also provides a capacitance measurement method, applied to the above-mentioned capacitance measurement circuit, comprising:

[0028] A DC operating voltage is applied to one end of the device under test through a bias module, and an AC signal is introduced into the device under test through capacitive coupling.

[0029] A test AC signal is injected into the signal injection terminal connected between the output terminal of the bias module and one end of the device under test.

[0030] The detection module detects the charge change of the device under test in response to the test AC signal and converts it into an output signal.

[0031] The electrical parameters of the device under test are determined based on the output signal.

[0032] Optionally, after injecting the test AC signal, the following may also be included:

[0033] The test AC signal is attenuated by a voltage divider module connected between the signal injection terminal and the bias module.

[0034] Optionally, the device under test includes a capacitor under test and a reference element; the capacitance measurement method further includes:

[0035] By using a switching unit, the input terminal of the detection module can be selectively connected to the other end of the capacitor under test or the reference element;

[0036] When connected to the reference element, the measurement circuit is verified or calibrated.

[0037] When connected to the capacitor under test, a capacitance measurement of the capacitor under test is performed.

[0038] This application also provides an electrostatic capacitance measuring device, which includes the capacitance measuring circuit described above.

[0039] The beneficial effects of the above technical solution are as follows:

[0040] In this technical solution, the capacitance measurement circuit couples an AC test signal into a high-voltage bias circuit and directly responds to charge changes using a detection module. This allows for real-time, online, and accurate measurement of the junction capacitance of the semiconductor detector (device under test) while applying a DC operating voltage of several kilovolts. The measurement results accurately reflect the capacitance characteristics of the device under actual high-voltage operating conditions. The entire circuit adopts a topology combining AC injection and charge detection, effectively isolating the influence of high-voltage DC on the precision detection circuit. While ensuring high measurement accuracy and signal-to-noise ratio, it also possesses good electrical safety. Furthermore, this structure is compatible with capacitance measurement requirements under conventional low-voltage or zero-bias conditions, enhancing the circuit's versatility and application flexibility. Attached Figure Description

[0041] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0042] Figure 1 This is a circuit diagram of one embodiment of the capacitance measurement circuit described in this application;

[0043] Figure 2 This is a flowchart of one embodiment of the capacitance measurement method described in this application. Detailed Implementation

[0044] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0046] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0047] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0048] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0049] like Figure 1 As shown, this application provides a capacitance measurement circuit, including: a bias module 1, a signal injection terminal, and a detection module 2.

[0050] Bias module 1, the output terminal of which is connected to one end of the device under test C4, is used to apply a DC operating voltage HV to the device under test C4 and is coupled to an AC signal through a second capacitor C2;

[0051] The signal injection terminal is connected between the output terminal of the bias module 1 and one end of the device under test C4, and is used to input the test AC signal Vin.

[0052] The detection module 2 has its input terminal connected to the other end of the device under test (DUT) C4, and is used to detect the charge change of the DUT C4 and output a voltage signal in response to the test AC signal.

[0053] In this embodiment, the capacitance measurement circuit couples an AC test signal into the high-voltage bias circuit and directly responds to charge changes using the detection module 2. This allows for real-time, online, and accurate measurement of the junction capacitance of the semiconductor detector while applying a DC operating voltage of several kilovolts. The measurement results accurately reflect the capacitance characteristics of the device under actual high-voltage operating conditions. The entire circuit adopts a topology that combines AC injection and charge detection, effectively isolating the influence of high-voltage DC on the precision detection circuit. While ensuring high measurement accuracy and signal-to-noise ratio, it also has good electrical safety. Furthermore, this structure is compatible with capacitance measurement requirements under conventional low-voltage or zero-bias conditions, improving the circuit's versatility and application flexibility.

[0054] In an optional embodiment, the bias module 1 may include:

[0055] A first resistor R1, one end of which is connected to a first power supply;

[0056] The second resistor R2 has one end connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to one end of the second capacitor C2, which together serve as the output terminal of the bias module 1. The other end of the second capacitor C2 is used to connect to an AC signal.

[0057] The first capacitor C1 has one end grounded and the other end connected to the other end of the first resistor R1.

[0058] It should be noted that the DC operating voltage can be several kilovolts (e.g., 5kV).

[0059] In this embodiment, the bias module 1 forms a two-stage low-pass filter network through a first resistor R1 and a first capacitor C1, and a second resistor R2 and a second capacitor C2, providing a stable DC operating voltage to the device under test (DUT) C4 from the first power supply. The first capacitor C1 is connected between the voltage divider node and ground, forming a low-pass filter loop, which can effectively suppress power supply noise and high-frequency interference, ensuring that the DC bias voltage applied to the DUT C4 has high purity and stability. The second capacitor C2 is connected in series between the output of the voltage divider network and the output of the bias module 1, and its other end is used to connect the AC test signal. The second capacitor C2 must have high withstand voltage characteristics, and its withstand voltage value directly determines the highest DC bias voltage that the circuit can withstand (for example, a capacitor with a withstand voltage of 5kV can meet the test requirements of most semiconductor detectors), thereby achieving high-voltage isolation: on the one hand, it isolates the subsequent detection circuit from the thousands of volts of DC high voltage, ensuring the safety of the test equipment and operators; on the other hand, it provides a low-impedance path for the AC test signal injected from the previous stage, ensuring that the test signal can be efficiently coupled to the high-voltage end of the DUT C4. This structure enables the entire measurement circuit to safely and accurately perform AC capacitance measurements while applying a kV-level DC bias.

[0060] In an optional embodiment, it further includes:

[0061] Voltage divider module 3 is connected between the signal injection terminal and the bias module 1. The input terminal of voltage divider module 3 is connected to the signal injection terminal to receive the test AC signal and to attenuate the test AC signal.

[0062] In this embodiment, the measurement circuit further includes a voltage divider module 3 connected between the signal injection terminal and the bias module 1. Its input terminal is connected to the signal injection terminal to receive test AC signals from an external signal source. The voltage divider module 3 is typically implemented using a resistor network composed of high-precision resistors, capable of precisely and adjustablely attenuating the amplitude of the original test AC signal. This attenuation ensures that the signal amplitude injected into the subsequent high-voltage measurement circuit is controlled within a predetermined range. This effectively prevents amplifier saturation of the detection module 2 due to excessively strong input signals, ensuring the linear operation of the signal processing link. Furthermore, by reducing the injected signal level, the dynamic range of signals that the detection module 2 can handle is broadened, enabling it to handle various amplitudes of the measured capacitor response, from weak to strong. This structure allows the entire system to flexibly adapt to external signal sources with different output amplitudes, significantly enhancing the applicability and reliability of the circuit while achieving high-precision measurement.

[0063] In an optional embodiment, the voltage divider module 3 may include:

[0064] The third resistor R3, one end of which serves as the input terminal of the voltage divider module 3;

[0065] The fourth resistor R4 has one end connected to the other end of the third resistor R3, which together serve as the output terminal of the third resistor R3 and is connected to the bias module 1; the other end of the fourth resistor R4 is grounded.

[0066] In this embodiment, the voltage divider module 3 employs a resistor voltage divider network consisting of a third resistor R3 and a fourth resistor R4. One end of the third resistor R3 serves as the input terminal of the voltage divider module 3, receiving the original test AC signal. One end of the fourth resistor R4 is grounded, and its other end is connected to the other end of the third resistor R3. This connection point serves as the output terminal of the voltage divider module 3, connected to the subsequent bias module 1. By precisely setting the resistance ratio of the third resistor R3 and the fourth resistor R4, this network can achieve stable and predictable amplitude attenuation of the input test AC signal. This pure resistive structure avoids introducing additional reactive components, ensuring a constant attenuation ratio over a wide frequency range, thereby maintaining the waveform characteristics of the test signal. Its simple structure and stable, reliable performance, along with the selection of high-precision, low-temperature-coefficient resistors, ensure the long-term accuracy and consistency of the attenuation coefficient, providing a stable and accurate excitation signal amplitude reference for the entire measurement system.

[0067] In an optional embodiment, the detection module 2 may include:

[0068] The fifth resistor R5, one end of which is connected to the second power supply;

[0069] Operational amplifier A1, the non-inverting input terminal of operational amplifier A1 is connected to the other end of the fifth resistor R5, and the inverting input terminal of operational amplifier A1 is connected to the bias voltage Bias;

[0070] Field-effect transistor Q1, the drain of which is connected to the other end of the fifth resistor R5, and the source of which is grounded;

[0071] The sixth resistor R6, one end of which is connected to the gate of the field-effect transistor Q1;

[0072] The third capacitor C3, one end of which is connected to one end of the sixth resistor R6 and the gate of the field-effect transistor Q1, together serves as the input terminal of the detection module 2. The other end of the third capacitor C3, the other end of the sixth resistor R6 and the output terminal of the operational amplifier A1, together serve as the output terminal of the detection module 2.

[0073] In this embodiment, the field-effect transistor is an N-channel field-effect transistor.

[0074] In this optional embodiment, the detection module 2 adopts an active closed-loop control architecture based on an operational amplifier and a field-effect transistor. The non-inverting input of the operational amplifier is connected to the second power supply through the fifth resistor R5, and its inverting input receives a precise bias setting voltage, thereby driving the field-effect transistor in its saturation region to achieve high input impedance, low noise, and stable transconductance, thus accurately converting the input charge into a voltage signal. A highly stable, low-noise, and continuously adjustable AC pulse signal is generated at the output through a network composed of the sixth resistor R6 and the third capacitor C3. The third capacitor C3 here performs functions such as "charge-voltage conversion (integration)," "bandwidth limiting and noise suppression," and, together with the sixth resistor R6, forms a reset path (in coordination with the feedback resistor). The detection module 2 is a charge-sensitive amplifier, the core of which includes a JFET (junction field-effect transistor) input stage, an operational amplifier, and a feedback capacitor (third capacitor C3) connected between the output and the inverting input, together forming a high-gain charge integrator. When an AC test signal is applied, the weak charge change induced on the device under test (DUT) C4 is almost entirely collected by the integrator and converted into a voltage across the feedback capacitor. Ultimately, the output voltage amplitude of the operational amplifier is proportional to the amount of injected charge, thus directly and linearly reflecting the capacitance value of DUT C4. This scheme combines precisely adjustable high-voltage bias generation with extremely sensitive charge detection technology, achieving accurate, online measurement of the junction capacitance of a semiconductor detector at a kilovolt DC operating point while ensuring electrical safety isolation. The output voltage signal exhibits good linearity and a high signal-to-noise ratio, facilitating subsequent direct acquisition and processing.

[0075] In an optional embodiment, the device under test C4 includes a capacitor under test and a reference element;

[0076] The capacitance measurement circuit also includes:

[0077] A switching unit is used to selectively switch the input terminal of the detection module 2 to the other end of the capacitor under test or the measurement terminal of the reference element;

[0078] When connected to the reference element, it is used to perform circuit verification or calibration; when connected to the capacitor under test, it is used to perform capacitance measurement.

[0079] In this embodiment, the measurement circuit is configured with a capacitor under test and a reference element with a known precise capacitance value. The circuit also includes a switching unit, such as a relay or multiplexer, whose common terminal is connected to the input of a charge-sensitive amplifier, and whose two selectable channels are connected to the measurement terminals of the capacitor under test and the reference element, respectively. Through a control signal, the input of the detection module 2 can be conveniently and selectively switched to either the capacitor under test or the reference element. When switched to the reference element, the system can obtain a reference output signal corresponding to a known standard capacitance value under identical excitation and measurement conditions. This signal can be used to verify in real time whether the entire measurement chain (including the signal source, bias module 1, detection module 2, etc.) is functioning correctly, and can be directly used to calibrate the system's transmission coefficient, effectively eliminating system errors introduced by factors such as temperature drift and component aging. After verification or calibration, the switching unit can switch the detection path back to the capacitor under test, thereby performing high-precision absolute capacitance measurement. This implementation scheme with integrated self-calibration significantly improves the long-term reliability and absolute accuracy of the measurement, and makes it possible to maintain consistent results in batch testing.

[0080] In the signal transmission path, the second capacitor C2 is connected in series with the device under test (DUT) C4 (either the DUT or a reference element) and then connected to the input of the charge-sensitive amplifier. Therefore, in a measurement mode with a high-voltage bias, the capacitance of the second capacitor C2 will be in series with the DUT, affecting the measurement results. By performing a numerical correction on the known capacitance of the second capacitor C2 in the back-end calculation, its influence can be eliminated, obtaining the accurate value of the DUT. In conventional capacitance measurement scenarios where a DC high voltage is not required, the second capacitor C2 can be removed from the signal path by bypassing or switching. In this case, the measurement results will no longer be affected by any series capacitor, thus simplifying the measurement process. Furthermore, the capacitance of the feedback capacitor in the charge-sensitive amplifier determines the charge-to-voltage conversion gain of the circuit (the gain is inversely proportional to the capacitance of the feedback capacitor). When the capacitance value of the capacitor under test is too large, the output signal is likely to reach the amplifier's saturation limit. In this case, a larger capacitance value feedback capacitor can be selected to reduce the circuit gain, thereby avoiding output distortion and expanding the range of measurable capacitors. Conversely, for capacitors under test with extremely small capacitance values, a small capacitance value feedback capacitor can be selected to improve gain and measurement sensitivity. This adjustable gain mechanism effectively optimizes the circuit's measurement dynamic range.

[0081] The measurement and calculation principle of the capacitance measurement circuit in this embodiment is as follows:

[0082]

[0083] Where Q represents the amount of charge, C represents the capacitance, and V represents the voltage.

[0084] This measurement circuit, based on an input signal of known amplitude, first calculates the amount of charge accumulated on the detector junction capacitance or a standard capacitor. This charge is almost entirely injected into the third capacitor C3 via a high-input-impedance front end, and a discharge path is formed through the sixth resistor R6. Finally, the corresponding signal voltage is detected at the output terminal Vout of bias module 1. By measuring the amplitude of this output voltage and combining it with the known input conditions, the capacitance C4 of the device under test (DUT) C4 can be calculated using the following formula:

[0085]

[0086]

[0087]

[0088] In actual measurement circuits, when the capacitance C4 of the device under test (DUT) C4 is large, the second capacitor C2 will affect the final test result. Since the second capacitor C2 and the capacitance C4 of the DUT C4 are connected in series, the input signal must pass through the second capacitor C2 and the DUT C4 sequentially before being injected into the third capacitor C3. Therefore, the capacitance actually involved in charge distribution is the equivalent series capacitance of the second capacitor C2 and the DUT C4, denoted as Ce, and its expression is:

[0089] ,

[0090] Substituting the charge-voltage relationship, we can obtain the following expression for the relationship between the output voltage Vout and the input voltage Vin (test AC signal):

[0091] ,

[0092] Therefore, given the second capacitor C2, the third capacitor C3, the input signal amplitude Vin, and the measured output signal amplitude Vout, the true capacitance value of the device under test C4 can be calculated using the following formula:

[0093] .

[0094] This corrected formula can effectively eliminate the influence of the second capacitor C2 on the measurement results in actual measurements, thereby improving the accuracy of the device's measurements.

[0095] The capacitance measurement circuit in this embodiment supports the measurement of detector junction capacitance under high-voltage bias, while also being compatible with conventional capacitance measurement functions. By optimizing the peripheral circuit parameters and combining them with appropriate formula correction, the system can achieve high-precision measurement over a wide dynamic range.

[0096] The capacitance measurement circuit in this embodiment achieves critical safety isolation through a series high-voltage filter capacitor: this capacitor allows thousands of kilovolt DC high voltage to be safely applied to the detector while protecting the precision measurement circuit at a safe ground potential and providing a coupling path for the tiny AC test signal; combined with the use of a charge-sensitive amplifier as the core detection unit, utilizing its high input impedance and charge integration characteristics, it can accurately capture the tiny charge changes generated by the response of the device under test C4 (detector junction capacitance) to the test signal, and linearly convert it into a voltage signal that can be accurately measured by subsequent circuits, thereby achieving high-precision capacitance measurement under high voltage while ensuring electrical safety.

[0097] like Figure 2 As shown, this application also provides a capacitance measurement method applied to the above-mentioned capacitance measurement circuit, comprising:

[0098] S1. Apply a DC operating voltage to one end of the device under test (DUT) C4 through the bias module 1, and introduce an AC signal to the DUT C4 through capacitive coupling.

[0099] S2. Inject a test AC signal into the signal injection terminal connected between the output terminal of the bias module 1 and one end of the device under test C4;

[0100] S3. The detection module 2 detects the charge change at the other end of the device under test C4 in response to the test AC signal and converts it into an output signal.

[0101] S4. Determine the electrical parameters of the device under test C4 based on the output signal.

[0102] In this embodiment, the capacitance measurement method, through the capacitance measurement circuit, first applies the high DC operating voltage required for actual operation to the device under test (DUT) C4 by the bias module 1, and safely introduces an AC component using capacitive coupling. Subsequently, a precise and controllable test AC signal is injected into the node between the bias output terminal and the DUT C4. The weak charge change generated by this signal on the DUT C4 is captured in real time by the subsequent detection module 2 (such as a charge-sensitive amplifier) ​​and converted into a high signal-to-noise ratio voltage output signal. Finally, by processing this output signal, the true capacitance value of the DUT C4 at the current high-voltage operating point can be accurately calculated. This method is performed online entirely under the actual kV-level DC bias applied to the device, and the obtained capacitance value can truly reflect the device characteristics under high-voltage conditions, solving the bottleneck that conventional instruments cannot measure under high voltage. At the same time, by combining high-voltage coupling and charge detection, safe and effective isolation between strong DC high voltage and weak AC signals is achieved, ensuring measurement accuracy and system safety. In addition, this method is also applicable to measurements under zero bias or low voltage conditions, demonstrating good versatility and flexibility.

[0103] In an optional embodiment, after injecting the test AC signal, the method further includes:

[0104] The test AC signal is attenuated by a voltage divider module 3 connected between the signal injection terminal and the bias module 1.

[0105] In this embodiment, after injecting the test AC signal into the signal injection terminal, the voltage divider module 3, located in the signal injection path, can controllably attenuate the signal amplitude. This step ensures that the original excitation signal, which may have a high amplitude, input from an external signal source is pre-conditioned to a suitable level before entering the precision measurement circuit containing high-voltage bias. By attenuating the signal, it is possible to effectively prevent the subsequent charge-sensitive amplifier and other detection circuits from entering the saturation region due to an excessively strong input signal, thereby ensuring that the entire signal processing link operates in a linear amplification state. This not only significantly widens the dynamic range of signals that the system can accurately process, enabling it to respond to various capacitance changes from weak to strong, but also improves its adaptability to external signal sources with different output amplitudes. Ultimately, this signal conditioning step enhances the overall robustness, measurement accuracy, and applicability of the measurement system.

[0106] In an optional embodiment, the device under test (DUT) C4 includes a capacitor under test and a reference element; the capacitance measurement method further includes:

[0107] By using the switching unit, the input terminal of the detection module 2 can be selectively connected to the other end of the capacitor under test or the reference element;

[0108] When connected to the reference element, the measurement circuit is verified or calibrated.

[0109] When connected to the capacitor under test, a capacitance measurement of the capacitor under test is performed.

[0110] In this embodiment, by controlling the switching unit, the input of the detection module 2 can be flexibly selected to either the capacitor under test or a reference element with a known capacitance value. When the detection path is switched to the reference element, the system obtains an output response corresponding to a known standard value under identical excitation and measurement conditions. This process completes real-time verification of the entire measurement chain and accurately calculates a system calibration coefficient, effectively eliminating system errors introduced by factors such as temperature drift, component aging, and circuit nonlinearity. Subsequently, the detection path is switched back to the capacitor under test, allowing high-precision absolute capacitance measurement to be performed using the calibrated system. This self-calibration mechanism integrated into the measurement process not only ensures the absolute accuracy of a single measurement result but also guarantees the consistency and reliability of results during long-term use and batch testing, significantly enhancing the practical value and reliability of the measurement system.

[0111] This application also provides an electrostatic capacitance measuring device, which includes the capacitance measuring circuit described above.

[0112] The electrostatic capacitance measurement device provided in this application integrates the aforementioned capacitance measurement circuit, forming a complete measurement system. Structurally, this device typically also includes a highly stable high-voltage bias power supply, a precision signal generator, a data acquisition unit, and a control and processing core. This application can safely apply a real-world DC bias voltage of up to several kilovolts to the semiconductor detector and other devices under test, and simultaneously perform high-precision AC capacitance measurements online under these high-voltage conditions, directly obtaining the junction capacitance value that accurately reflects the device's characteristics under high-voltage operating conditions. This device, through hardware and collaborative measurement methods, fundamentally solves the bottleneck of insufficient test voltage and inability to perform online measurements under high voltage in commercial instruments. Furthermore, through flexible configuration of its internal circuitry, the device can also perform conventional zero-bias or low-voltage capacitance measurements, achieving broad applicability from R&D testing to online diagnostics. Ultimately, this device provides reliable and critical process data support for accurate performance evaluation of semiconductor detectors, manufacturing process diagnostics, and product quality control.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A capacitance measurement circuit, characterized in that, include: The bias module has its output connected to one end of the device under test (DUT) and is used to apply a DC operating voltage to the DUT and to couple an AC signal through a second capacitor C2. The signal injection terminal is connected between the output terminal of the bias module and one end of the device under test, and is used to input a test AC signal. The detection module has its input end connected to the other end of the device under test (DUT) and is used to detect the charge change of the DUT and output a voltage signal in response to the test AC signal.

2. The capacitance measurement circuit according to claim 1, characterized in that, The bias module includes: A first resistor R1, one end of which is connected to a first power supply; The second resistor R2 has one end connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to one end of the second capacitor C2 to serve as the output terminal of the bias module. The other end of the second capacitor C2 is used to connect to the AC signal. The first capacitor C1 has one end grounded and the other end connected to the other end of the first resistor R1.

3. The capacitance measurement circuit according to claim 1, characterized in that, Also includes: A voltage divider module is connected between the signal injection terminal and the bias module. The input terminal of the voltage divider module is connected to the signal injection terminal to receive the test AC signal and to attenuate the test AC signal.

4. The capacitance measurement circuit according to claim 3, characterized in that, The voltage divider module includes: The third resistor R3, one end of which serves as the input terminal of the voltage divider module; The fourth resistor R4 has one end connected to the other end of the third resistor R3, which together serve as the output terminal of the third resistor R3 and is connected to the bias module; the other end of the fourth resistor R4 is grounded.

5. The capacitance measurement circuit according to claim 1, characterized in that, The detection module includes: The fifth resistor R5, one end of which is connected to the second power supply; An operational amplifier, wherein the non-inverting input terminal of the operational amplifier is connected to the other end of the fifth resistor R5, and the inverting input terminal of the operational amplifier is connected to a bias voltage; A field-effect transistor, wherein the drain of the field-effect transistor is connected to the other end of the fifth resistor R5, and the source of the field-effect transistor is grounded; The sixth resistor R6, one end of which is connected to the gate of the field-effect transistor; The third capacitor C3, one end of which is connected to one end of the sixth resistor R6 and the gate of the field-effect transistor, together serving as the input terminal of the detection module, and the other end of the third capacitor C3, which is connected to the other end of the sixth resistor R6 and the output terminal of the operational amplifier, together serving as the output terminal of the detection module.

6. The capacitance measurement circuit according to claim 1, characterized in that, The device under test includes a capacitor under test and a reference element; The capacitance measurement circuit also includes: A switching unit is used to selectively switch the input terminal of the detection module to the other end of the capacitor under test or the measurement terminal of the reference element; When connected to the reference element, it is used to perform circuit verification or calibration; when connected to the capacitor under test, it is used to perform capacitance measurement.

7. A capacitance measurement method, applied to the capacitance measurement circuit as described in claims 1-6, characterized in that, include: A DC operating voltage is applied to one end of the device under test through a bias module, and an AC signal is introduced into the device under test through capacitive coupling. A test AC signal is injected into the signal injection terminal connected between the output terminal of the bias module and one end of the device under test. The detection module detects the charge change of the device under test in response to the test AC signal and converts it into an output signal. The electrical parameters of the device under test are determined based on the output signal.

8. The capacitance measurement method according to claim 7, characterized in that, Following the injection of the test AC signal, the process also includes: The test AC signal is attenuated by a voltage divider module connected between the signal injection terminal and the bias module.

9. The capacitance measurement method according to claim 7, characterized in that, The device under test includes a capacitor under test and a reference element; The capacitance measurement method further includes: By using a switching unit, the input terminal of the detection module can be selectively connected to the other end of the capacitor under test or the reference element; When connected to the reference element, the measurement circuit is verified or calibrated. When connected to the capacitor under test, a capacitance measurement of the capacitor under test is performed.

10. An electrostatic capacitance measuring device, characterized in that, It includes a capacitance measurement circuit as described in any one of claims 1 to 6.

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