A chip model simulation calibration method and device and storage medium

Abstract

The application discloses a chip model simulation calibration method and device and a storage medium, relates to the chip architecture simulation field, and comprises the following steps: determining the simulation deviation of a specified function dimension according to system-level simulation results and operator-level simulation results for each target computation graph node; screening a target function dimension from the specified function dimension according to the simulation deviation, and acquiring a parameter set associated with the target function dimension in the target computation graph node; and performing hierarchical inverse labeling on the parameter set according to the simulation deviation of the target function dimension. The system-level simulation results are used to intelligently filter the operator-level simulation space, blind traversal of low-value invalid configurations is avoided, an error decomposition mechanism is introduced, estimated errors are attributed according to dimensions such as computation, memory access, communication and power consumption, directional inverse labeling instead of traditional global parameter fitting is realized, hierarchical inverse labeling strategies are used, parameter interference between different operator families is reduced, the model can adapt to various complex scenes, and parameter oscillation is avoided.

Description

Technical Field

[0001] This invention relates to the field of chip architecture simulation technology, and in particular to a simulation calibration method, apparatus and storage medium for a chip model. Background Technology

[0002] With the continuous growth in the scale and complexity of large AI models, AI system performance modeling faces a dilemma between accuracy and efficiency. Currently, AI performance modeling in the industry is usually divided into two independent levels: AI system-level simulation platforms and SOC operator-level simulation platforms. However, these two simulation platforms currently run independently without data interaction, causing system-level simulation results to rely on manual experience for calibration, thus reducing the accuracy of calibration. The cost estimation model of the AI ​​system-level simulation platform uses globally fixed parameters, which cannot accurately characterize the actual differences of different types of operators under mixed loads, resulting in poor generalization ability. Operator-level simulation cannot provide system-level guidance, blindly tracing a large number of invalid configurations, resulting in a waste of computing resources. When there is a deviation between system-level simulation results and operator-level simulation results, it is impossible to automatically trace the specific cause of the error, and only global parameter fitting can be performed, resulting in even worse generalization ability of the calibrated model. Existing calibration methods do not take into account the actual impact of power consumption constraints on performance, resulting in a systematic deviation between system-level estimation and real hardware performance in high-power scenarios. Therefore, existing chip model simulation calibration methods cannot meet the actual needs of users. Summary of the Invention

[0003] This invention provides a simulation calibration method, apparatus, and storage medium for chip models to achieve accurate simulation calibration calculations for chip models.

[0004] According to a first aspect of the present invention, a simulation calibration method for a chip model is provided, the method comprising: generating candidate deployment strategies based on a simulation request input by a user using an AI system-level simulation platform, constructing a computation graph corresponding to each of the deployment strategies, and determining the system-level simulation results of the nodes in the computation graph; Target computation graph nodes that require accurate simulation are selected from the computation graph, and the performance and power consumption of the target computation graph nodes are jointly simulated based on the SOC operator-level simulation platform to obtain operator-level simulation results. For each of the target computation graph nodes, the simulation deviation of a specified functional dimension is determined based on the system-level simulation results and the operator-level simulation results. The specified functional dimensions include computation dimension, memory access dimension, communication dimension, power consumption dimension, and inherent latency dimension. Based on the simulation deviation, a target functional dimension is selected from the specified functional dimensions, and the parameter set associated with the target functional dimension in the target computation graph node is obtained; The parameter set is back-calibrated hierarchically based on the simulation deviation of the target functional dimension. The simulation calibration is terminated when the simulation index of the target computation graph after parameter back-calibration meets the specified requirements.

[0005] According to another aspect of the present invention, a simulation calibration apparatus for a chip model is provided. The apparatus includes: a system-level simulation module, configured to generate candidate deployment strategies based on a simulation request input by a user using an AI system-level simulation platform, construct a computation graph corresponding to each of the deployment strategies, and determine the system-level simulation results of the computation graph nodes; The operator-level simulation module is used to select target computation graph nodes that need to be accurately simulated from the computation graph, and to perform joint performance and power consumption simulation on the target computation graph nodes based on the SOC operator-level simulation platform to obtain operator-level simulation results. The simulation deviation determination module is used to determine the simulation deviation of a specified functional dimension for each of the target computation graph nodes based on the system-level simulation results and the operator-level simulation results. The specified functional dimensions include computation dimension, memory access dimension, communication dimension, power consumption dimension, and inherent latency dimension. The parameter set acquisition module is used to filter out the target functional dimension from the specified functional dimensions based on the simulation deviation, and to acquire the parameter set associated with the target functional dimension in the target computation graph node; The hierarchical back-annotation module is used to perform hierarchical back-annotation on the parameter set according to the simulation deviation of the target functional dimension. When it is determined that the simulation index of the target computation graph after parameter back-annotation meets the specified requirements, the simulation calibration is terminated.

[0006] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: one or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any embodiment of the present invention.

[0007] According to another aspect of the present invention, a storage medium for computer-executable instructions is provided, on which a computer program is stored, which, when executed by a processor, implements the method as described in any of the embodiments of the present invention.

[0008] The technical solution of this invention uses system-level simulation results to intelligently filter the operator-level simulation space, avoiding blind traversal of low-value and ineffective configurations and improving resource utilization. By introducing an error decomposition mechanism, system-level estimation errors are attributed according to dimensions such as computation, memory access, communication, and power consumption, achieving targeted back-annotation instead of traditional global parameter fitting. Through a hierarchical back-annotation strategy, parameter interference between different operator families is reduced, enabling the model to flexibly adapt to various complex scenarios and avoiding parameter oscillations.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of a simulation calibration method for a chip model according to Embodiment 1 of the present invention; Figure 2 This is a flowchart of another simulation calibration method for a chip model provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of a simulation calibration device for a chip model according to Embodiment 3 of the present invention; Figure 4 This is a structural block diagram of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or terminal device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or terminal devices.

[0014] Example 1 Figure 1 This is a flowchart of a simulation calibration method for a chip model provided in Embodiment 1 of the present invention. This embodiment is applicable to the simulation calibration of chip models. The method can be executed by a simulation calibration device for a chip model. This device can be implemented in hardware and / or software, and can be integrated into an electronic device with data processing capabilities. Figure 1 As shown, the method includes: S101, based on the AI ​​system-level simulation platform, generates candidate deployment strategies for simulation requests input by users, constructs a computation graph corresponding to each deployment strategy, and determines the system-level simulation results of the computation graph nodes.

[0015] Optionally, the system-level simulation results based on the AI ​​system-level simulation platform for generating candidate deployment strategies for user-input simulation requests, constructing computational graphs corresponding to each deployment strategy, and determining the nodes of the computational graphs include: receiving user simulation requests through a cloud platform, wherein the simulation requests include AI models and target hardware architecture configurations; routing the simulation requests to the AI ​​system-level simulation platform, and generating candidate deployment strategies for the AI ​​models through the AI ​​system-level simulation platform using a low-level enumerator; constructing corresponding computational graphs for each candidate deployment strategy through the AI ​​system-level simulation platform, determining the cost of each computational graph node based on the target hardware architecture configuration using a cost estimation model, and using the cost as the system-level simulation result.

[0016] Specifically, in this embodiment, the AI ​​system-level simulation platform and the SOC operator-level simulation platform are connected to the cloud base and interact with each other based on the cloud base. The cloud base receives the user's simulation request through a web interface or API interface, and the simulation request includes information such as the AI ​​model and the target hardware architecture configuration. Since multiple heterogeneous platforms may be registered on the cloud base, the API interface can determine which system platform the user is accessing. When it is determined to be the AI ​​system-level simulation platform, the simulation request will be routed to the AI ​​system-level simulation platform. The AI ​​system-level simulation platform uses a computation graph description language to convert the AI ​​model computation graph into a directed acyclic graph (DAG). Each node in the DAG contains operator type, input / output tensor shape, data type, and operator attributes. Based on the underlying enumerator, the DAG is split to obtain an initial deployment strategy. A multi-dimensional intelligent pruning method is then used to filter the initial deployment strategy to obtain feasible candidate deployment strategies. The multi-dimensional intelligent pruning method includes on-chip memory constraint pruning, device number constraint pruning, and context parallelism convergence pruning. Of course, this embodiment is used for illustrative purposes only and does not limit the specific method of obtaining candidate deployment strategies.

[0017] The AI ​​system-level simulation platform constructs a corresponding computation graph for each candidate deployment strategy, and determines the feasible batch size for each deployment strategy through a cost estimation model based on the upper-layer solver. It then determines the cost of the computation graph node based on the feasible batch size and the target hardware architecture configuration, and uses the cost of the computation graph node as the system-level simulation result. Of course, this embodiment is only an example and does not limit the specific method of obtaining the system-level simulation result.

[0018] S102: Select the target computation graph nodes that need to be accurately simulated from the computation graph, and perform joint performance and power consumption simulation on the target computation graph nodes based on the SOC operator-level simulation platform to obtain operator-level simulation results.

[0019] Optionally, the target computation graph nodes requiring precise simulation are selected from the computation graph, including: preliminary screening of nodes in the computation graph based on pre-defined constraint rules to obtain a node candidate set, wherein the constraint rules include storage feasibility constraints, distributed partitioning constraints, and performance sensitivity constraints; extracting feature information of each node in the node candidate set and mapping the feature information to a unified operator description through a standardized mapping function; determining the hash value of each node based on the unified operator description; when no matching node is found in the calibration database based on the hash value, or when a matching node is found but the node's confidence is lower than the confidence threshold, obtaining the association information of the unified operator description, wherein the association information includes the overall network sensitivity, current confidence, version drift, and simulation cost estimate; determining the simulation priority score of the node corresponding to the unified operator description based on the association information, and selecting the computation graph nodes whose simulation priority scores meet the specified score threshold as target computation graph nodes.

[0020] Specifically, this implementation uses pre-defined constraint rules to initially screen nodes in the computation graph to obtain a candidate node set. These constraints include storage feasibility constraints, distributed partitioning constraints, and performance sensitivity constraints. Storage feasibility constraints filter operator nodes that exceed single-device storage limits; if an operator requires more GPU memory than the hardware can handle, it is discarded to avoid wasting time on simulation. Distributed partitioning constraints determine the actual shape of the operator based on the actual number of parallel operations, avoiding invalid simulations of unpartitioned shapes. In distributed training, large operators are partitioned and run on multiple chips. The system adjusts the operator's shape to the partitioned size based on the actual parallel strategy (e.g., partitioned into 8 parts). In this way, the simulator calculates the actual running size, rather than the huge original size, thus avoiding the waste of computing resources. The performance sensitivity constraint refers to prioritizing the triggering of high-precision simulation for highly sensitive operators based on the cost ratio of operator nodes. Therefore, not all operators need to occupy computing resources for precise calculation. The system will identify which operators are bottlenecks (the ones that take the longest time and have the largest proportion) and start high-precision simulation for these key operators.

[0021] In this embodiment, after obtaining the candidate node set, the feature information of each computation graph node in the set is extracted, and the feature information is mapped to a unified operator description through a standardized mapping function. Each operator instance is mapped as: USD = <op_type, shape_tuple, dtype, parallel_ctx, placement_ctx, dataflow_tag, hw_cfg, sw_cfg, version_tag> Here, op_type represents the operator operation type identifier (such as gemm, mla_mha, layernorm, topk, etc.), shape_tuple represents the input and output shape parameter list; dtype represents the data precision type; parallel_ctx represents the parallel context; placement_ctx represents the deployment context, including rank, die, and device mapping information; dataflow_tag represents optional dataflow configuration parameters (such as content quantization type); hw_cfg represents the target hardware configuration name tag; sw_cfg represents the compiler / kernel software version tag; and version_tag represents the overall version identifier. In addition, specific conversion rules are defined for different types of system-level operators. For example, for attention mechanism operators, key parameters such as batch size, sequence length, number of heads, and head dimension are extracted from the input tensor, and the operator operation type identifier op_type is determined according to the attention mode. For quantized linear layer operators, the BMN (batch size - number of rows in the output matrix - number of columns in the output matrix) matrix dimension parameter, grouped quantization K dimension parameter, and quantization type identifier are extracted to generate a quantized configuration dataflow_tag. For communication operators, the corresponding communication simulation parameters are determined according to the communication type and parallel strategy, including source / target device identifiers. Of course, this embodiment is only an example and does not limit the conversion method of feature information. As long as a unified description language can be established between the AI ​​system-level simulation platform and the SOC operator-level simulation platform to realize information interaction between the two heterogeneous simulation platforms, it is within the protection scope of this application.

[0022] It should be noted that, in order to achieve accurate comparison in this embodiment, the corresponding unified operator descriptions of each computation graph node system are packaged to generate hash values, and the hash values ​​are used as the unique identifiers of the computation graph nodes. This implementation will query the calibration database based on the hash value. The calibration database stores computation graph nodes that have undergone operator simulation, and each computation graph node is marked with a confidence level. The higher the confidence level, the more reliable the simulation result of the operator. Therefore, when a computation graph node matching the hash value is found in the calibration data and the confidence level is higher than the confidence level threshold, it means that the computation graph node has previously performed operator-level simulation and the simulation result is relatively accurate and reliable. It can be used directly without re-simulating through the SOC operator-level simulation platform. Otherwise, the association information of the unified operator description corresponding to the computation graph node is obtained. The association information includes network sensitivity X1, current confidence level X2, version drift X3, and simulation cost estimate X4. Among them, network sensitivity represents the impact of the computation graph node on the overall performance, current confidence level represents the reliability of the simulation result of the computation graph node, version drift represents the change range of the software and hardware environment, and simulation cost estimate represents the time required for one simulation. Specifically, the simulation priority score of the computation graph node corresponding to the unified operator description can be calculated using the following formula (1): P=a×X1-b×X2+c×X3-d×X4 (1); Where P represents the simulation priority score, X1 represents the associated information including overall network sensitivity, X2 represents the current confidence level, X3 represents version drift, X4 represents the estimated simulation cost, a represents the weight corresponding to overall network sensitivity, b represents the weight corresponding to the current confidence level, c represents the weight corresponding to version drift, and d represents the weight corresponding to the estimated simulation cost. After obtaining the simulation priority score of each computation graph node, computation graph nodes with simulation priority scores greater than a specified threshold are selected as target computation graph nodes. Subsequent operator-level simulations are mainly performed on the target computation graph nodes. Of course, this embodiment is only an example and does not limit the specific selection method of target computation graph nodes.

[0023] Optionally, performance and power consumption co-simulation of the target computation graph node is performed based on the SOC operator-level simulation platform to obtain operator-level simulation results. This includes: creating an operator-level simulation task for the target computation graph node, wherein the operator-level simulation task includes an operator type, which may include computation operators or communication operators; distributing the operator-level simulation task to the SOC operator-level simulation platform so that the SOC operator-level simulation platform can configure the corresponding simulation environment according to the operator type, and performing performance and power consumption co-simulation of the target computation graph node in conjunction with the heterogeneous simulation platform in the simulation environment, obtaining operator-level simulation results based on a multi-precision data fusion strategy, wherein the simulation accuracy of the heterogeneous simulation platform is higher than that of the SOC operator-level simulation platform.

[0024] Specifically, in this embodiment, the cloud platform creates operator-level simulation tasks for the target computation graph nodes. These tasks include operator types, such as computation operators or communication operators. The simulation tasks for computation operators mainly include specific configuration information such as operator name, shape, and data type. The simulation tasks for communication operators mainly include operator name, data transmission volume, data type, and explicit source and target device identifiers indicating cross-node / cross-device communication. This embodiment is merely illustrative and does not limit the specific content included in system-level simulation tasks. The cloud platform sends the operator-level simulation tasks to the SOC operator-level simulation platform. Upon receiving the tasks, the SOC operator-level simulation platform configures different simulation environments and resources based on the operator type. For example, for computation operators, it focuses on configuring simulation models of the computation units, paying attention to the instruction pipeline; for communication operators, it focuses on configuring simulation models of the memory subsystem, direct memory access, and on-chip networks, paying attention to bandwidth, latency, and data conflicts. The platform then performs joint performance and power consumption simulations of the target computation graph nodes in conjunction with the heterogeneous simulation platform within the simulation environment. In this implementation, the SOC operator-level simulation platform performs time-driven joint simulation of performance and power consumption. That is, the SOC operator-level simulation platform no longer separates performance (speed) and power consumption (power consumption), but uses the time axis as the core clue. While simulating the speed of operator operation, it accurately calculates the changes in current and voltage at each moment and the resulting heat and energy consumption. Because the higher the operator operating frequency and the faster the switching rate, the greater the dynamic power consumption, if the simulation finds that the power consumption is too high at a certain moment, causing the temperature to soar, the system will trigger the temperature control mechanism to force frequency reduction, thereby causing performance degradation. Therefore, by introducing joint simulation of performance and power consumption in this implementation, the simulation results obtained are closer to the real situation. In this simulation, the SOC operator-level simulation platform might be a relatively fast but moderately accurate simulator. To achieve higher accuracy, it calls upon a heterogeneous simulation platform with higher simulation accuracy. This heterogeneous simulation platform could be a hardware simulation accelerator or a register-transfer level simulator. While obtaining the first simulation result from the SOC operator-level simulation platform, it also obtains the second simulation result from the heterogeneous simulation platform. The first and second simulation results are then fused using multi-precision data to obtain the final operator-level simulation result. During multi-precision data fusion, different weights are configured for the two simulation platforms, with the heterogeneous simulation platform having a greater weight than the SOC operator-level simulation platform. Of course, this embodiment only illustrates high-precision simulation using data from two platforms. In practical applications, the specific number of heterogeneous simulation platforms can be determined based on the user's simulation accuracy requirements.

[0025] S103, for each target computation graph node, determine the simulation deviation of the specified functional dimension based on the system-level simulation results and the operator-level simulation results.

[0026] Specifically, for each target computation graph node, a system-level simulation result T_sys(i) and an operator-level simulation result T_ref(i) are obtained, where i is the identifier of the target computation graph node. The simulation deviation between the two simulation results is obtained as e(i) = T_sys(i) - T_ref(i). Furthermore, this embodiment decomposes the simulation deviation according to specified dimensions, including computation dimension, memory access dimension, communication dimension, power consumption dimension, and inherent latency dimension. That is, the simulation deviation is decomposed into e(i) = e(i)_computation + e(i)_memory access + e(i)_communication + e(i)_power consumption + e(i)_inherent latency dimension. The computation dimension refers to the comparison between the system-level estimated computation latency and the simulation output of various computing resource utilization rates and the actual number of multiply-accumulate (MAC) operations. The memory access dimension compares the system-level estimated memory access latency with the simulation output of bandwidth utilization and LLC read / write hit rates at each storage level (L0→DSM→SIC_IO→LLC→HBM), where L0 represents L1 cache, DSM represents distributed shared memory, SIC_IO represents chip-to-chip interconnect interface, LLC represents last-level cache, and HBM represents high-bandwidth memory. The communication dimension compares the system-level estimated communication latency with the simulation output of D2D (die-to-die) and Electronic System Level (ESL) cross-device interconnect actual latency. The power consumption dimension refers to the quantized electrical design current (Electrical Design...). The performance change caused by current (EDC) constraints: If the chip triggers the protection mechanism (EDC constraint) due to excessive instantaneous current, the frequency will be reduced, resulting in slower operation. The system calculates the "EDC penalty ratio" to evaluate the time increase caused by "throttling", which is the error in the power consumption dimension. The inherent latency dimension refers to the basic time overhead that is determined by hardware physical characteristics, algorithm structure or system underlying mechanism and cannot be eliminated by simple optimization.

[0027] S104: Based on the simulation deviation, filter out the target functional dimension from the specified functional dimensions, and obtain the parameter set associated with the target functional dimension in the target computation graph node.

[0028] Optionally, the target functional dimension can be selected from the specified functional dimensions based on the simulation deviation, including: obtaining the pre-set deviation threshold for each specified functional dimension; and selecting the specified functional dimension whose simulation deviation is greater than the corresponding deviation threshold as the target functional dimension.

[0029] Specifically, in this embodiment, after obtaining the simulation deviation of each functional dimension, the simulation deviation of each specified functional dimension is compared with the corresponding deviation threshold. The specified functional dimension that is greater than the corresponding deviation threshold is taken as the target functional dimension. Thus, when the error between the system-level simulation result and the operator-level simulation result is large, the contribution of each specified functional dimension to the error can be quickly determined, and the specified functional dimension with the largest contribution is taken as the main reason for the large error.

[0030] Once the target functional dimension with a large simulation deviation is identified, the system will obtain the parameter set associated with the target functional dimension in the target computation graph node. In other words, only the parameter set under the target functional dimension needs to be modified, thereby achieving accurate location and resolution of the error problem.

[0031] S105, perform hierarchical back-calibration of the parameter set according to the simulation deviation of the target functional dimension, and terminate the simulation calibration when it is determined that the simulation index of the target calculation graph after parameter back-calibration meets the specified requirements.

[0032] Optionally, the parameter set is hierarchically back-annotated based on the simulation deviation of the target functional dimension, including: determining the sub-parameters of different parameter dimensions contained in each parameter in the parameter set, wherein the parameter dimensions include operator type, hardware resources, deployment mode, and power consumption status; determining the error correction direction corresponding to each sub-parameter based on the simulation deviation, and obtaining the historical stability constraints, historical parameter values, and application scenario types corresponding to each sub-parameter, wherein the application scenario types include large language model inference scenario, model training scenario, hybrid expert model scenario, heterogeneous grain scenario, and topology scenario; and performing hierarchical back-annotation on each sub-parameter according to the error correction direction, historical stability constraints, and historical parameter values ​​under the application scenario type to obtain the back-annotated target computation graph nodes.

[0033] Specifically, in this implementation, after obtaining the parameter set corresponding to the target functional dimension, the parameter set is back-annotated hierarchically using simulation bias. Specifically, this involves determining the sub-parameters of different parameter dimensions contained in each parameter in the parameter set. That is, each parameter in the parameter set is organized as a four-dimensional matrix: θ={θ[op_family][resource_dim][deploy_mode][power_state]}, where [op_family] represents the operator type, such as matrix multiplication GEMM or layer normalization, and is calibrated independently for each user; [resource_dim] represents hardware resources, broken down into three independent dimensions: computational efficiency, memory access efficiency, and kernel startup latency; [deploy_mode] represents the deployment mode, such as single-card operation and multi-card distributed operation, and further distinguishes topology types under the multi-card distributed operation model; [power_state] represents the power consumption state, such as no power consumption constraints and EDC constraints in effect, because the impact of EDC frequency reduction on performance is non-linear, and therefore cannot be estimated using the same set of parameters.

[0034] In this embodiment, the error correction direction corresponding to each sub-parameter is determined based on the simulation deviation, and the historical stability constraints, historical parameter values ​​and application scenario types corresponding to each sub-parameter are obtained. Then, the parameters are updated using the following formula (2): θ_new =θ_old-η×∇L_local+λ×Reg(θ_old, θhist) (2); Where η is the learning rate, ∇L_local is the local loss gradient determined by the simulation deviation, -η ×∇L_local is used to indicate the error correction direction, θ_old represents the historical parameter value, which refers to the parameter value before the current iteration, λ is the regularization coefficient, θhist represents the old value, which refers to the historical version parameter or historical parameter set, Reg(θ_old, θhist) represents the historical stability constraint, which is to limit the current update from deviating too far from the historical experience. When the application scenario type is determined, θ_old can be updated according to the above formula (2) to obtain the updated parameter θ_new. After each parameter in the parameter set is updated in the above manner, the target computation graph node after back-annotation is obtained.

[0035] It should be noted that due to significant differences in operator performance characteristics across different scenarios, different calibration granularities and focuses are required. Application scenarios include large language model inference, model training, hybrid expert model, heterogeneous die, and topology scenarios. Specifically, large language model inference scenarios require independent calibration for two phases: Prefill (computationally intensive, potentially triggered by EDC constraints) and Decode (memory-intensive, typically not triggered by EDC). The Prefill phase requires focused calibration of power consumption parameters. Model training scenarios require independent calibration parameters for three phases: Forward Rendering (FWD), Backward Activation Gradient (BPI), and Backward Weight Gradient (BPK). Due to the consistently high power consumption in training, EDC effects may persist across all phases. Hybrid expert model scenarios require specific calibration for the load imbalance and additional communication overhead introduced by expert parallelism, particularly addressing the impact of power consumption differences between different experts on overall performance. Heterogeneous die scenarios involve differentiating calibration parameters based on die type when the target SoC contains multiple heterogeneous dies, and separately calibrating cross-die latency introduced by D2D interconnects. Different topology scenarios: In multi-device distributed mode, communication parameters are calibrated independently according to topology type. Of course, this implementation is only an example and does not limit the specific form of the application scenario.

[0036] Optionally, the simulation calibration is terminated when the simulation metrics of the target computation graph after parameter back-annotation meet the specified requirements. This includes: determining the target computation graph after back-annotation based on the nodes of the target computation graph after back-annotation; re-executing the system-level simulation of the target computation graph after back-annotation based on the AI ​​system-level simulation platform and obtaining the simulation metrics, which include the global average error, the historical near-term improvement gain, and the confidence of key operators; the simulation calibration is terminated when at least two of the simulation metrics meet the specified requirements, otherwise, iterative simulation of the target computation after back-annotation continues.

[0037] Optionally, the system-level simulation of the back-annotated target computation graph is re-executed based on an AI system-level simulation platform to obtain simulation metrics, including: obtaining simulation parameters of key computation graph nodes in the back-annotated target computation graph based on the AI ​​system-level simulation platform; calculating the confidence of key operators for each target computation graph node based on the simulation parameters, wherein the simulation parameters include data volume factor, coverage factor, convergence trend factor, and time decay factor; obtaining the global average error obtained from re-executing the system-level simulation and the first performance parameter of this simulation; obtaining the second performance parameter of historical simulations, and obtaining the improvement gain of historical adjacent rounds based on the first and second performance parameters.

[0038] Specifically, this implementation method determines the target computation graph after back-annotation based on the nodes of the target computation graph after back-annotation. The parameters of the nodes of the target computation graph after back-annotation have changed, but their positions and connections in the computation graph have not changed. The system-level simulation of the target computation graph after back-annotation is re-executed based on the AI ​​system-level simulation platform to obtain simulation indicators. During the re-execution, the confidence of key operators is calculated for each node of the target computation graph based on simulation parameters, such as data volume factor, coverage factor, convergence trend factor and time decay factor. This confidence is used to represent the reliability of the simulation results after re-execution of the simulation, and the confidence can be calculated using the following formula (3): C=w1×f(N)+w2×g(Coverage)+w3×h(Trend)+w4×decay(T) (3); Where f(N) represents the data volume factor, i.e., the number of times the operator has been accessed; g(Coverage) represents the coverage factor, i.e., the comprehensiveness of the measured shapes and data types; h(Trend) represents the convergence trend factor, i.e., whether the error has decreased or increased in recent calibration rounds; and decay(T) represents the time decay factor, i.e., how much time has passed since the last simulation. In addition, this embodiment also obtains the global average error obtained from re-executing the system-level simulation and the first performance parameter of the current simulation, obtains the second performance parameter of historical simulations, and obtains the improvement gain of historical adjacent rounds based on the first and second performance parameters. Simulation calibration terminates when at least two simulation indicators meet the specified requirements; otherwise, iterative simulation continues for the back-calibrated target calculation.

[0039] For example, this implementation uses large language model inference scenarios, model training scenarios, and heterogeneous grain scenarios as examples to illustrate the calibration process: For bidirectional calibration in large language model inference scenarios, specifically, a whole-network analysis can be performed on the target AI model through an AI system-level simulation platform to output candidate deployment schemes for the Prefill and Decode stages, and to identify the hotspot operators and their cost percentage rankings for each stage. For the hotspot operators (GEMM, FlashAttention) in the Prefill stage, USD is generated through normalized mapping: for example, FlashAttention is mapped as...<mla_mha, (B,S,H,D,KVH), fp16, TP=8, ...> The calibration database is queried using the USD hash key. Operator-level simulation is triggered only for GEMM / SDPA nodes with low confidence or no hit. The SOC operator-level simulation platform performs joint performance and power consumption simulation based on a 5-level full-layer hardware architecture model. For example, the output is: total delay = 80μs (without EDC) / 96μs (after EDC constraint), EDC frequency reduction ratio = 83.3%, delay increase = 20%; SIP domain power consumption = 45W, L1 domain = 8W, SOC domain = 12W, MEM domain = 15W, total power consumption = 80W, EDC threshold current = 100A. The system-level estimated total latency is 100μs. Simulation results without EDC are 80μs, and with EDC constraints, the latency is 96μs. If system-level EDC correction is not included, the total deviation is 4μs, with memory access contributing (40-25) = 15μs, computation contributing (60-55) = 5μs, and power consumption contributing -16μs. The system determines that the power consumption deviation is significant, requiring the addition of new EDC performance correction parameters. Only the memory access efficiency parameters and EDC performance correction coefficient ρedc of GEMM / SDPA in the Prefill stage are updated, while the computation efficiency parameters remain unchanged. After backcomputation, the end-to-end token latency is compared. The prediction error in the Prefill stage decreases from 25% to within 5%, and iterations until convergence.

[0040] For model training scenarios, the same operator is split into parameter clusters according to the forward / backward stages to avoid the forward parameters from polluting the backward parameters. Topology labels are added to the communication reoperators to distinguish the calibration parameters of different deployment modes.

[0041] The training scenario consistently exhibits high computational density, with EDC constraints frequently triggered during the FWD and BPK stages. For the BPK stage (backward weight gradient, the most computationally intensive), the EDC performance correction coefficient is calibrated to 0.85 (indicating that EDC causes approximately 15% performance loss). When the proportion of cross-device communication errors increases, only the communication parameter set is updated, and historical version parameters are used as regularization constraints (Reg(θ_old, θhist)) to suppress parameter oscillations.

[0042] For heterogeneous die scenarios, the SoC operator-level simulation platform adopts a chiplet architecture, including two compute dies (CoDs) and one IO die (IoD). Computationally intensive operators (GEMM, SDPA) are mainly executed on the CoDs, and calibration focuses on computational efficiency and memory access efficiency. Data transfer for communication-intensive operators passes through the D2D interconnect of the IoDs, requiring independent calibration of D2D transmission delay parameters. The latency of cross-CoD data transmission is determined by the bandwidth contention of the D2D interconnect. The calibration database maintains independent parameters according to the source CoD → target CoD path. When a new MOD (memory die) configuration is added, a new calibration branch is created for the high-bandwidth memory read / write bandwidth utilization parameters of the MOD, without affecting the calibration parameters of existing CoDs / IoDs. Of course, this implementation is only an example and does not limit the calibration process in different scenarios.

[0043] The technical solution of this invention uses system-level simulation results to intelligently filter the operator-level simulation space, avoiding blind traversal of low-value and ineffective configurations and improving resource utilization. By introducing an error decomposition mechanism, system-level estimation errors are attributed according to dimensions such as computation, memory access, communication, and power consumption, achieving targeted back-annotation instead of traditional global parameter fitting. Through a hierarchical back-annotation strategy, parameter interference between different operator families is reduced, enabling the model to flexibly adapt to various complex scenarios and avoiding parameter oscillations.

[0044] Example 2 Figure 2 This is a flowchart of another simulation calibration method for a chip model provided in this embodiment of the invention. Based on the above embodiment, after performing performance and power consumption co-simulation on the target computation graph using a SOC operator-level simulation platform to obtain operator-level simulation results, the method further includes: generating a system trace log based on the operator-level simulation results, wherein the system trace log includes metadata, a task list, operation behavior files, and storage access files; and sending the system trace log to a designated simulation platform, wherein the simulation accuracy of the designated simulation platform is greater than that of the SOC operator-level simulation platform, such as... Figure 2 As shown, the method includes: S201: Based on the AI ​​system-level simulation platform, candidate deployment strategies are generated for simulation requests input by users, a computation graph corresponding to each deployment strategy is constructed, and the system-level simulation results of the computation graph nodes are determined.

[0045] Optionally, the system-level simulation results based on the AI ​​system-level simulation platform for generating candidate deployment strategies for user-input simulation requests, constructing computational graphs corresponding to each deployment strategy, and determining the nodes of the computational graphs include: receiving user simulation requests through a cloud platform, wherein the simulation requests include AI models and target hardware architecture configurations; routing the simulation requests to the AI ​​system-level simulation platform, and generating candidate deployment strategies for the AI ​​models through the AI ​​system-level simulation platform using a low-level enumerator; constructing corresponding computational graphs for each candidate deployment strategy through the AI ​​system-level simulation platform, determining the cost of each computational graph node based on the target hardware architecture configuration using a cost estimation model, and using the cost as the system-level simulation result.

[0046] S202: Select the target computation graph nodes that need to be accurately simulated from the computation graph, and perform joint performance and power consumption simulation on the target computation graph nodes based on the SOC operator-level simulation platform to obtain operator-level simulation results.

[0047] Optionally, the target computation graph nodes requiring precise simulation are selected from the computation graph, including: preliminary screening of nodes in the computation graph based on pre-defined constraint rules to obtain a node candidate set, wherein the constraint rules include storage feasibility constraints, distributed partitioning constraints, and performance sensitivity constraints; extracting feature information of each node in the node candidate set and mapping the feature information to a unified operator description through a standardized mapping function; determining the hash value of each node based on the unified operator description; when no matching node is found in the calibration database based on the hash value, or when a matching node is found but the node's confidence is lower than the confidence threshold, obtaining the association information of the unified operator description, wherein the association information includes the overall network sensitivity, current confidence, version drift, and simulation cost estimate; determining the simulation priority score of the node corresponding to the unified operator description based on the association information, and selecting the computation graph nodes whose simulation priority scores meet the specified score threshold as target computation graph nodes.

[0048] Optionally, performance and power consumption co-simulation of the target computation graph node is performed based on the SOC operator-level simulation platform to obtain operator-level simulation results. This includes: creating an operator-level simulation task for the target computation graph node, wherein the operator-level simulation task includes an operator type, which may include computation operators or communication operators; distributing the operator-level simulation task to the SOC operator-level simulation platform so that the SOC operator-level simulation platform can configure the corresponding simulation environment according to the operator type, and performing performance and power consumption co-simulation of the target computation graph node in conjunction with the heterogeneous simulation platform in the simulation environment, obtaining operator-level simulation results based on a multi-precision data fusion strategy, wherein the simulation accuracy of the heterogeneous simulation platform is higher than that of the SOC operator-level simulation platform.

[0049] S203 generates system tracing logs based on operator-level simulation results and sends the system tracing logs to the specified simulation platform.

[0050] Specifically, this embodiment also acquires all simulation process parameters during the simulation process of the SOC operator-level simulation platform, and generates a system trace log (Trace) based on the operator-level simulation results and parameters. This is a structured data file (usually in JSON, CSV, or Protobuf format), which translates the core metrics of the operator-level simulation into a language that the system can understand. The system trace log includes metadata, task list, operation behavior file, and storage access file. Of course, this embodiment is only an example and does not limit the specific content contained in the system trace log.

[0051] In addition, the system trace logs obtained above will be sent to a designated simulation platform. The simulation accuracy of this platform must be greater than that of a SOC operator-level simulation platform, such as a system-level simulator. The purpose of sending the logs is as follows: By piecing together the local manifestations of thousands of operators, a panoramic view of the entire neural network or even the entire AI chip is created.

[0052] At the system level, when multiple operators run concurrently, will the overall performance degrade due to bandwidth contention (this cannot be observed in a single operator simulation)? Furthermore, only by sending logs to the platform can the platform compare the "system-level estimation" and the "operator-level simulation results" to calculate the error and trigger subsequent parameter back-annotation.

[0053] It should be noted that when the SOC operator-level simulation platform performs simulation, it exports traces through patch injection. These traces are organized into three types of engine tasks: XPU Action tasks (computation core sub-thread level operations), DTEAction tasks (data transfer engine operations), and ESL Action tasks (cross-device communication operations). Each type of task includes an operation behavior JSONL file (recording operation ID, dependencies, source / destination storage domains) and a storage access JSONL file (recording address, size, read / write type). The specified simulation platform receives and replays these data, outputting more accurate latency, bandwidth utilization, and cache behavior data, which is then sent back to the calibration database. When the calibration engine back-annotates, it prioritizes high-fidelity results; if unavailable, it reverts to operator-level results. Of course, this implementation is merely illustrative and does not limit the specific function of traces.

[0054] S204 determines the simulation deviation for a specified functional dimension for each target computation graph node based on system-level simulation results and operator-level simulation results.

[0055] S205, based on the simulation deviation, filter out the target functional dimension from the specified functional dimensions, and obtain the parameter set associated with the target functional dimension in the target computation graph node.

[0056] Optionally, the target functional dimension can be selected from the specified functional dimensions based on the simulation deviation, including: obtaining the pre-set deviation threshold for each specified functional dimension; and selecting the specified functional dimension whose simulation deviation is greater than the corresponding deviation threshold as the target functional dimension.

[0057] S206, perform hierarchical back-calibration of the parameter set according to the simulation deviation of the target functional dimension, and terminate the simulation calibration when it is determined that the simulation index of the target calculation graph after parameter back-calibration meets the specified requirements.

[0058] Optionally, the parameter set is hierarchically back-annotated based on the simulation deviation of the target functional dimension, including: determining the sub-parameters of different parameter dimensions contained in each parameter in the parameter set, wherein the parameter dimensions include operator type, hardware resources, deployment mode, and power consumption status; determining the error correction direction corresponding to each sub-parameter based on the simulation deviation, and obtaining the historical stability constraints, historical parameter values, and application scenario types corresponding to each sub-parameter, wherein the application scenario types include large language model inference scenario, model training scenario, hybrid expert model scenario, heterogeneous grain scenario, and topology scenario; and performing hierarchical back-annotation on each sub-parameter according to the error correction direction, historical stability constraints, and historical parameter values ​​under the application scenario type to obtain the back-annotated target computation graph nodes.

[0059] Optionally, the simulation calibration is terminated when the simulation metrics of the target computation graph after parameter back-annotation meet the specified requirements. This includes: determining the target computation graph after back-annotation based on the nodes of the target computation graph; re-executing the system-level simulation of the target computation graph after back-annotation based on the AI ​​system-level simulation platform and obtaining the simulation metrics, which include the global average error, the historical near-term improvement gain, and the confidence of key operators; and terminating the simulation calibration when at least two of the simulation metrics meet the specified requirements. Otherwise, iterative simulation is continued on the target computation graph after back-annotation.

[0060] Optionally, the system-level simulation of the back-annotated target computation graph is re-executed based on an AI system-level simulation platform to obtain simulation metrics, including: obtaining simulation parameters of key computation graph nodes in the back-annotated target computation graph based on the AI ​​system-level simulation platform; calculating the confidence of key operators for each target computation graph node based on the simulation parameters, wherein the simulation parameters include data volume factor, coverage factor, convergence trend factor, and time decay factor; obtaining the global average error obtained from re-executing the system-level simulation and the first performance parameter of this simulation; obtaining the second performance parameter of historical simulations, and obtaining the improvement gain of historical adjacent rounds based on the first and second performance parameters.

[0061] The technical solution of this invention uses system-level simulation results to intelligently filter the operator-level simulation space, avoiding blind traversal of low-value and ineffective configurations and improving resource utilization. By introducing an error decomposition mechanism, system-level estimation errors are attributed according to dimensions such as computation, memory access, communication, and power consumption, achieving targeted back-annotation instead of traditional global parameter fitting. Through a hierarchical back-annotation strategy, parameter interference between different operator families is reduced, enabling the model to flexibly adapt to various complex scenarios and avoiding parameter oscillations.

[0062] Example 3 Figure 3 This is a schematic diagram of a simulation calibration device for a chip model provided in an embodiment of the present invention. Figure 3 As shown, the device includes: a system-level simulation module 310, an operator-level simulation module 320, a simulation deviation determination module 330, a parameter set acquisition module 340, and a hierarchical back-annotation module 350.

[0063] Among them, the system-level simulation module 310 is used to generate candidate deployment strategies based on the simulation requests input by the user on the AI ​​system-level simulation platform, construct a computation graph corresponding to each deployment strategy, and determine the system-level simulation results of the computation graph nodes; The operator-level simulation module 320 is used to select target computation graph nodes that need to be accurately simulated from the computation graph, and to perform joint performance and power consumption simulation on the target computation graph nodes based on the SOC operator-level simulation platform to obtain operator-level simulation results. The simulation deviation determination module 330 is used to determine the simulation deviation of a specified functional dimension for each target computation graph node based on the system-level simulation results and the operator-level simulation results. The specified functional dimensions include computation dimension, memory access dimension, communication dimension, power consumption dimension and inherent latency dimension. The parameter set acquisition module 340 is used to filter out the target functional dimension from the specified functional dimensions based on the simulation deviation, and to acquire the parameter set associated with the target functional dimension in the target computation graph node; The hierarchical back-annotation module 350 is used to perform hierarchical back-annotation on the parameter set according to the simulation deviation of the target functional dimension. When it is determined that the simulation index of the target calculation graph after parameter back-annotation meets the specified requirements, the simulation calibration is terminated.

[0064] Optionally, a system-level simulation module 310 is used to receive simulation requests from users via a cloud platform, wherein the simulation requests include AI models and target hardware architecture configurations. The simulation request is routed to the AI ​​system-level simulation platform, and the AI ​​system-level simulation platform uses the underlying enumerator to generate candidate deployment strategies for the AI ​​model; The AI ​​system-level simulation platform constructs corresponding computational graphs for each candidate deployment strategy, uses a cost estimation model to determine the cost of each computational graph node based on the target hardware architecture configuration, and uses the cost as the system-level simulation result.

[0065] Optionally, the operator-level simulation module 320 includes a target computation graph node filtering unit, which is used to perform preliminary filtering of nodes in the computation graph based on pre-defined constraint rules to obtain a node candidate set. The constraint rules include storage feasibility constraints, distributed partitioning constraints, and performance sensitivity constraints. Extract the feature information of each node in the node candidate set, and map the feature information into a unified operator description through a standardized mapping function; The hash value of each node is determined based on the unified operator description. When no matching node is found in the calibration database based on the hash value, or a matching node is found but the node's confidence is lower than the confidence threshold, the association information of the unified operator description is obtained. The association information includes the overall network sensitivity, current confidence, version drift, and simulation cost estimate. Based on the association information, determine the simulation priority score of the node corresponding to the unified operator description, and take the computation graph node whose simulation priority score meets the specified score threshold as the target computation graph node.

[0066] Optionally, the operator-level simulation module 320 includes an operator-level simulation unit for creating operator-level simulation tasks for target computation graph nodes. The operator-level simulation task includes operator types, which may include computation operators or communication operators. The operator-level simulation task is sent to the SOC operator-level simulation platform so that the SOC operator-level simulation platform can configure the corresponding simulation environment according to the operator type. In the simulation environment, the target computation graph node is subjected to joint performance and power consumption simulation with the heterogeneous simulation platform. The operator-level simulation results are obtained based on the multi-precision data fusion strategy. The simulation accuracy of the heterogeneous simulation platform is higher than that of the SOC operator-level simulation platform.

[0067] Optionally, the parameter set acquisition module 340 is used to acquire the pre-set deviation threshold for each specified functional dimension; The specified functional dimension whose simulation deviation exceeds the corresponding deviation threshold is taken as the target functional dimension.

[0068] Optionally, the hierarchical back-annotation module 350 includes a hierarchical back-annotation unit for determining the sub-parameters of different parameter dimensions contained in each parameter in the parameter set, wherein the parameter dimensions include operator type, hardware resources, deployment mode and power consumption status. The error correction direction corresponding to each sub-parameter is determined based on the simulation deviation, and the historical stability constraints, historical parameter values ​​and application scenario types corresponding to each sub-parameter are obtained. The application scenario types include large language model inference scenario, model training scenario, hybrid expert model scenario, heterogeneous grain scenario and topology scenario. Under the application scenario type, each sub-parameter is back-annotated in layers according to the error correction direction, historical stability constraints and historical parameter values ​​to obtain the target computation graph nodes after back-annotation.

[0069] Optionally, the hierarchical back-annotation module 350 includes an iterative unit for determining the target computation graph after back-annotation based on the nodes of the target computation graph after back-annotation; Based on the AI ​​system-level simulation platform, the target computation graph after back-annotation is re-performed with system-level simulation and simulation indicators are obtained. The simulation indicators include global average error, historical near-term improvement gain and key operator confidence. The simulation calibration is terminated when at least two of the simulation indicators meet the specified requirements; otherwise, iterative simulation continues on the target calculation graph after back-calibration.

[0070] Optionally, an iterative unit is used to obtain the simulation parameters of key computation graph nodes in the target computation graph after back-annotation based on the AI ​​system-level simulation platform, and to calculate the confidence of key operators for each target computation graph node based on the simulation parameters. The simulation parameters include data volume factor, coverage factor, convergence trend factor and time decay factor. Obtain the global average error obtained from re-executing the system-level simulation and the first performance parameter of this simulation; Obtain the second performance parameter of the historical simulation, and obtain the improvement gain of the historical adjacent rounds based on the first and second performance parameters.

[0071] Optionally, the device also includes a system trace log sending module, used to generate system trace logs based on operator-level simulation results, wherein the system trace logs include metadata, task list, operation behavior file and storage access file; The system trace logs are sent to a designated simulation platform, where the simulation accuracy of the designated simulation platform is greater than that of the SOC operator-level simulation platform.

[0072] The chip model simulation calibration device provided in this embodiment of the invention can execute the chip model simulation calibration method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0073] Example 4 Figure 4A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0074] The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0075] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0076] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other electronic devices through computer networks such as the Internet and / or various telecommunications networks.

[0077] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as simulation calibration methods for chip models.

[0078] That is, based on the AI ​​system-level simulation platform, candidate deployment strategies are generated for the simulation requests input by the user, a computation graph corresponding to each deployment strategy is constructed, and the system-level simulation results of the computation graph nodes are determined; The target computation graph nodes that need to be accurately simulated are selected from the computation graph, and the performance and power consumption of the target computation graph nodes are jointly simulated based on the SOC operator-level simulation platform to obtain the operator-level simulation results. For each target computation graph node, the simulation deviation of the specified functional dimension is determined based on the system-level simulation results and the operator-level simulation results. The specified functional dimensions include computation dimension, memory access dimension, communication dimension, power consumption dimension and inherent latency dimension. Based on the simulation deviation, the target functional dimension is selected from the specified functional dimensions, and the parameter set associated with the target functional dimension in the target computation graph node is obtained; The parameter set is back-calibrated in layers according to the simulation deviation of the target functional dimension. The simulation calibration is terminated when the simulation index of the target computation graph after parameter back-calibration meets the specified requirements.

[0079] In some embodiments, the chip model simulation calibration method can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the chip model simulation calibration method described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the chip model simulation calibration method by any other suitable means (e.g., by means of firmware).

[0080] Various embodiments of the apparatuses and techniques described above herein can be implemented in digital electronic circuit devices, integrated circuit devices, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), device-on-a-chip (SoC) devices, complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable device including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage device, at least one input device, and at least one output device, and transmitting data and instructions to the storage device, the at least one input device, and the at least one output device.

[0081] Computer programs used to implement the simulation calibration method for the chip model of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to the processor of a general-purpose computer or a special-purpose computer, such that when executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer programs can be executed entirely on the machine, partially on the machine, or as a standalone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0082] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution apparatus, device, or electronic device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage electronics, magnetic storage electronics, or any suitable combination thereof.

[0083] To provide interaction with a user, the devices and techniques described herein can be implemented on an electronic device having: a display device (e.g., a touchscreen) for displaying information to the user; and buttons through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0084] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0085] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A simulation calibration method for a chip model, characterized in that, The method includes: Based on the AI ​​system-level simulation platform, candidate deployment strategies are generated for simulation requests input by users, a computation graph corresponding to each deployment strategy is constructed, and the system-level simulation results of the computation graph nodes are determined. Target computation graph nodes that require accurate simulation are selected from the computation graph, and the performance and power consumption of the target computation graph nodes are jointly simulated based on the SOC operator-level simulation platform to obtain operator-level simulation results. For each of the target computation graph nodes, the simulation deviation of a specified functional dimension is determined based on the system-level simulation results and the operator-level simulation results. The specified functional dimensions include computation dimension, memory access dimension, communication dimension, power consumption dimension, and inherent latency dimension. Based on the simulation deviation, a target functional dimension is selected from the specified functional dimensions, and the parameter set associated with the target functional dimension in the target computation graph node is obtained; The parameter set is back-calibrated hierarchically based on the simulation deviation of the target functional dimension. The simulation calibration is terminated when the simulation index of the target computation graph after parameter back-calibration meets the specified requirements.

2. The method according to claim 1, characterized in that, The AI-based system-level simulation platform generates candidate deployment strategies based on user-input simulation requests, constructs computation graphs corresponding to each deployment strategy, and determines the system-level simulation results for the computation graph nodes, including: The system receives simulation requests from users via a cloud platform, wherein the simulation requests include AI models and target hardware architecture configurations. The simulation request is routed to the AI ​​system-level simulation platform, and the AI ​​system-level simulation platform uses a low-level enumerator to generate the candidate deployment strategy for the AI ​​model; The AI ​​system-level simulation platform constructs corresponding computation graphs for each of the candidate deployment strategies, uses a cost estimation model to determine the cost of each computation graph node based on the target hardware architecture configuration, and uses the cost as the system-level simulation result.

3. The method according to claim 1, characterized in that, The step of selecting the target computation graph nodes that need to be accurately simulated from the computation graph includes: The nodes in the computation graph are initially screened based on pre-defined constraint rules to obtain a candidate set of nodes. The constraint rules include storage feasibility constraints, distributed partitioning constraints, and performance sensitivity constraints. The feature information of each node in the node candidate set is extracted, and the feature information is mapped to a unified operator description through a standardized mapping function; The hash value of each node is determined according to the unified operator description. When no matching node is found in the calibration database according to the hash value, or a matching node is found but the confidence of the node is lower than the confidence threshold, the association information of the unified operator description is obtained. The association information includes the overall network sensitivity, current confidence, version drift and simulation cost estimate. Based on the association information, the simulation priority score of the node corresponding to the unified operator description is determined, and the computation graph node whose simulation priority score in the computation graph meets the specified score threshold is taken as the target computation graph node.

4. The method according to claim 3, characterized in that, The process of performing joint performance and power consumption simulations on the target computation graph nodes based on the SOC operator-level simulation platform to obtain operator-level simulation results includes: An operator-level simulation task is created for the target computation graph node, wherein the operator-level simulation task includes an operator type, which includes a computation operator or a communication operator; The operator-level simulation task is sent to the SOC operator-level simulation platform so that the SOC operator-level simulation platform can configure the corresponding simulation environment according to the operator type, and perform joint performance and power consumption simulation on the target computation graph node in the joint heterogeneous simulation platform under the simulation environment. The operator-level simulation results are obtained based on the multi-precision data fusion strategy, wherein the simulation accuracy of the heterogeneous simulation platform is higher than that of the SOC operator-level simulation platform.

5. The method according to claim 1, characterized in that, The step of filtering the target functional dimension from the specified functional dimensions based on the simulation deviation includes: Obtain the pre-set deviation threshold for each of the specified functional dimensions; The specified functional dimension whose simulation deviation is greater than the corresponding deviation threshold is taken as the target functional dimension.

6. The method according to claim 1, characterized in that, The step of performing hierarchical back-annotation of the parameter set based on the simulation deviation of the target functional dimension includes: Determine the sub-parameters of different parameter dimensions contained in each parameter in the parameter set, wherein the parameter dimensions include operator type, hardware resources, deployment mode and power consumption status; The error correction direction corresponding to each sub-parameter is determined based on the simulation deviation, and the historical stability constraints, historical parameter values ​​and application scenario types corresponding to each sub-parameter are obtained. The application scenario types include large language model inference scenario, model training scenario, hybrid expert model scenario, heterogeneous grain scenario and topology scenario. Under the application scenario type, each of the sub-parameters is back-annotated in layers according to the error correction direction, the historical stability constraint and the historical parameter value to obtain the target computation graph node after back-annotation.

7. The method according to claim 1, characterized in that, The step of terminating simulation calibration when the simulation index of the target computation graph after parameter back-calibration meets the specified requirements includes: Determine the target calculation graph after back-annotation based on the nodes of the target calculation graph after back-annotation; The system-level simulation of the target computation graph after back-annotation is re-executed based on the AI ​​system-level simulation platform, and the simulation index is obtained. The simulation index includes global average error, historical near-round improvement gain and key operator confidence. The simulation calibration is terminated when at least two of the simulation indicators meet the specified requirements; otherwise, iterative simulation continues for the back-calibrated target calculation.

8. The method according to claim 7, characterized in that, The AI-based system-level simulation platform re-executes system-level simulation on the back-annotated target computation graph and obtains the simulation metrics, including: Based on the AI ​​system-level simulation platform, the simulation parameters of key computation graph nodes in the target computation graph after back-annotation are obtained. For each target computation graph node, the confidence of the key operator is calculated according to the simulation parameters. The simulation parameters include data volume factor, coverage factor, convergence trend factor and time decay factor. Obtain the global average error obtained from re-executing the system-level simulation and the first performance parameter of this simulation; Obtain the second performance parameter of the historical simulation, and obtain the improvement gain of the historical adjacent rounds based on the first performance parameter and the second performance parameter.

9. The method according to claim 1, characterized in that, After obtaining the operator-level simulation results by performing joint performance and power consumption simulation on the target computation graph based on the SOC operator-level simulation platform, the method further includes: A system tracing log is generated based on the operator-level simulation results, wherein the system tracing log includes metadata, a task list, an operation behavior file, and a storage access file; The system tracking logs are sent to a designated simulation platform, wherein the simulation accuracy of the designated simulation platform is greater than that of the SOC operator-level simulation platform.

10. A simulation calibration device for a chip model, characterized in that, The device includes: The system-level simulation module is used to generate candidate deployment strategies based on the simulation requests input by the user on the AI ​​system-level simulation platform, construct a computation graph corresponding to each deployment strategy, and determine the system-level simulation results of the computation graph nodes. The operator-level simulation module is used to select target computation graph nodes that need to be accurately simulated from the computation graph, and to perform joint performance and power consumption simulation on the target computation graph nodes based on the SOC operator-level simulation platform to obtain operator-level simulation results. The simulation deviation determination module is used to determine the simulation deviation of a specified functional dimension for each of the target computation graph nodes based on the system-level simulation results and the operator-level simulation results. The specified functional dimensions include computation dimension, memory access dimension, communication dimension, power consumption dimension, and inherent latency dimension. The parameter set acquisition module is used to filter out the target functional dimension from the specified functional dimensions based on the simulation deviation, and to acquire the parameter set associated with the target functional dimension in the target computation graph node; The hierarchical back-annotation module is used to perform hierarchical back-annotation on the parameter set according to the simulation deviation of the target functional dimension. When it is determined that the simulation index of the target computation graph after parameter back-annotation meets the specified requirements, the simulation calibration is terminated.

11. An electronic device, characterized in that, The electronic device includes: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-9.

12. A storage medium for computer-executable instructions, wherein a computer program is stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-9.

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