A single-pole double-throw switching circuit based on an enhanced GaN HEMT integrated device

Abstract

This invention discloses a single-pole double-throw switch circuit based on an enhancement-mode GaN HEMT integrated device, belonging to the field of radio frequency integrated circuits. It includes first and second switching units integrated on a high-resistivity SOI substrate. Each unit is composed of series and parallel connection of enhancement-mode GaN HEMTs. The device employs a finned active region combined with a gate-around structure, and a p-type doped layer is provided under the gate to achieve normally-off characteristics. A deep trench isolation structure penetrating to the buried oxide layer and having a recessed bottom is provided between adjacent devices. The circuit also includes an auxiliary RC linearization branch. This invention can enhance channel control and reduce on-resistance by using a gate-around structure, and significantly improve high-frequency isolation by utilizing deep trench isolation and cutting off parasitic paths with the SOI substrate. Simultaneously, the RC branch improves linearity under high power, achieving single positive power supply logic control, thus improving the integration and communication reliability of the RF front-end.

Description

Technical Field

[0001] This invention relates to the field of radio frequency microelectronics technology, and more specifically, to a single-pole double-throw switch circuit based on an enhanced GaN HEMT integrated device. Background Technology

[0002] With the commercialization of 5G, satellite IoT, and millimeter-wave radar technologies, radio frequency (RF) front-end modules are facing unprecedented performance challenges. As a key component in the RF front-end, the single-pole double-throw (SPDT) switch is responsible for signal routing between the antenna and the transmit / receive channel. Its performance directly determines the signal-to-noise ratio, transmission efficiency, and communication reliability of the entire system. An ideal high-performance SPDT switch must simultaneously meet the following requirements: extremely low insertion loss to reduce the receiver noise figure; high isolation to prevent transmitted signal leakage from damaging the receiver; high linearity and high power capacity to handle peak-to-average power ratio (PAPR) modulated signals; and a simplified control interface to achieve single-supply positive voltage logic control.

[0003] Currently, the design of single-pole double-throw switches is mainly developing along two technical routes, but each has insurmountable performance bottlenecks. On the one hand, while switches based on depletion-mode (D-mode) high electron mobility transistors (HEMTs) offer excellent RF performance, they require negative voltage control during operation, which increases the complexity of the system's power management circuitry. On the other hand, while switches based on enhancement-mode (E-mode) high electron mobility transistors can achieve single positive power supply control, traditional planar enhancement-mode devices are limited by their physical structure, resulting in high on-resistance and low breakdown voltage. This leads to high insertion loss, insufficient power handling capability, and poor linearity in high-frequency operating environments.

[0004] Traditional planar enhancement-mode high electron mobility transistors (HEMTs) struggle to achieve an ideal trade-off between on-resistance and turn-off capacitance, directly limiting the frequency characteristics and loss performance of switching circuits. Furthermore, substrate crosstalk between adjacent devices in integrated circuit manufacturing severely restricts the improvement of isolation in switch arrays. Existing semiconductor processes are increasingly unable to meet the dual demands of modern communication systems for high integration and high performance in RF switches. Therefore, a novel device structure and process solution is urgently needed to fundamentally improve the performance bottlenecks of HEMTs, simplifying control with a single positive power supply while enhancing the power characteristics, linearity, and circuit isolation of single-pole double-throw switches. Summary of the Invention

[0005] The purpose of this invention is to provide a single-pole double-throw switch circuit based on an enhanced GaN HEMT integrated device, which mainly solves the technical problems of existing enhanced GaN RF switches, such as high on-resistance, insufficient power handling capability, poor high-frequency linearity, severe crosstalk in the device substrate leading to limited isolation, and the need for additional negative voltage power supply for depletion-type devices, which increases system complexity.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A single-pole double-throw switch circuit based on an enhanced GaN HEMT integrated device includes a common terminal RF, a first output terminal RF1 and a second output terminal RF2, a first switching unit connected between the common terminal RF and the first output terminal RF1, and a second switching unit connected between the common terminal RF and the second output terminal RF2.

[0008] Both the first switching unit and the second switching unit include transistor devices, wherein the transistor devices are enhancement-mode GaN HEMT devices integrated on a high-resistivity SOI substrate; the enhancement-mode GaN HEMT devices include:

[0009] SOI substrate structure, from bottom to top, includes a bottom silicon substrate, a buried oxide layer and a top semiconductor layer;

[0010] The fin-shaped active region is formed on the top semiconductor layer of the SOI substrate structure, and includes a buffer layer, a channel layer and a barrier layer from bottom to top; the fin-shaped active region is etched to form a fin-shaped structure;

[0011] A gate surrounds the top and sidewalls of each fin-shaped active region, the gate comprising a gate dielectric layer and a gate metal layer;

[0012] The source and drain are formed at both ends of each fin-shaped active region and form an ohmic contact with the fin-shaped active region.

[0013] Furthermore, in this invention, the transistor devices in the first switching unit are a first series transistor M1 and a first parallel transistor M3. The source of the first series transistor M1 is connected to the common terminal RF, the drain is connected to the first output terminal RF1, and the gate serves as the first control terminal Vg1. The source of the first parallel transistor M3 is connected to the first output terminal RF1, the drain is grounded, and the gate is connected to the second control terminal Vg2. The first switching unit also includes a resistor R1 and a capacitor C1 connected in series between the drain of the first parallel transistor M3 and ground.

[0014] Furthermore, in this invention, the transistor devices in the second switching unit are a second series transistor M2 and a second parallel transistor M4; the source of the second series transistor M2 is connected to the common terminal RF, the drain is connected to the second output terminal RF2, and the gate is connected to the second control terminal Vg2; the source of the second parallel transistor M4 is connected to the second output terminal RF2, the drain is grounded, and the gate is connected to the first control terminal Vg1; the second switching unit also includes a resistor R2 and a capacitor C2 connected in series between the drain of the second parallel transistor M4 and ground.

[0015] Furthermore, in this invention, a p-type doped layer is further included between the gate dielectric layer and the barrier layer of the gate. The p-type doped layer depletes the two-dimensional electron gas in the channel under zero bias, thereby putting the device in a turn-off state.

[0016] Furthermore, in this invention, the width of each fin-shaped active region is 20 nm to 80 nm, and the height is 30 nm to 120 nm.

[0017] Furthermore, in this invention, a deep trench isolation structure is provided between adjacent enhancement-mode GaN HEMT devices. The deep trench isolation structure includes an isolation trench, an oxide layer, and an insulating dielectric, and is located between adjacent fin-shaped active regions of two enhancement-mode GaN HEMT devices to achieve electrical isolation between different enhancement-mode GaN HEMTs. The deep trench isolation structure penetrates the fin-shaped active regions and the top semiconductor layer, and extends to the buried oxide layer of the SOI substrate.

[0018] Furthermore, in this invention, the deep trench isolation structure is formed with a high aspect ratio isolation trench using BOSCH deep reactive ion etching process, the exposed buried oxide layer is etched using diluted hydrofluoric acid solution, an oxide layer is then thermally grown or deposited on the inner wall of the isolation trench, and finally an insulating medium is filled using a high-density plasma chemical vapor deposition process.

[0019] Furthermore, in this invention, a recessed structure is formed at the junction of the bottom of the deep trench isolation structure and the buried oxide layer, and the depth of the recessed structure entering the interior of the buried oxide layer is 15% to 25% of the total thickness of the buried oxide layer.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] (1) This invention adopts an enhanced GaN HEMT device structure with a p-type doped layer below the gate. It can deplete the two-dimensional electron gas in the channel under zero bias to achieve normally-off characteristics. No additional negative voltage power supply circuit is required. Switching logic control can be completed with only a single positive power supply, which greatly simplifies the power management architecture of the RF front-end system and reduces the overall system complexity and hardware cost. At the same time, the gate structure surrounding the fin-shaped active region enhances the modulation capability of channel carriers from multiple dimensions. While improving the device breakdown voltage, it effectively reduces the on-resistance, optimizes the performance trade-off relationship between on-resistance and turn-off capacitance, reduces switching insertion loss, and improves the power handling capability of the device.

[0022] (2) The present invention integrates enhanced GaN HEMT devices on a high-resistivity SOI substrate, and sets a deep trench isolation structure extending to the buried oxide layer and having a bottom recessed structure between adjacent devices. On the one hand, the buried oxide layer of the SOI substrate blocks the lateral parasitic conduction path inside the substrate. On the other hand, the bottom recessed structure of the deep trench isolation extends the charge crosstalk path between adjacent devices, which greatly reduces substrate loss and port crosstalk under high frequency operation, significantly improves the high frequency isolation of the switching circuit, provides process feasibility for high-density integration of multi-channel switching arrays, and meets the miniaturization integration requirements of RF front-end.

[0023] (3) In this invention, auxiliary linearization branches composed of RC series are set between the drains of the parallel transistors in the two switching units and ground, which can dynamically adjust the electric field distribution in the drain region of the transistors when high-power signals are input, absorb nonlinear transient charges, suppress harmonic distortion, improve the P1dB compression point of the switching circuit, and improve the linearity performance in high-power operating scenarios. At the same time, the symmetrical series-parallel switching topology and the cross-coupled control logic can simultaneously discharge the other output port to ground when one switch is turned on, further improving the port isolation effect, reducing the risk of signal leakage damaging the receiving channel, and improving the operational reliability of the communication system.

[0024] (4) The device structure of the present invention is compatible with existing mature semiconductor manufacturing processes. The deep trench isolation, atomic layer deposition gate dielectric, magnetron sputtering p-type doped layer and other process steps can all be adapted to the existing CMOS process platform. Mass production can be achieved without a major upgrade of production line hardware, which balances performance improvement and manufacturing cost. This is conducive to the commercial application of the switching circuit in multiple fields such as 5G communication, millimeter wave radar, and satellite Internet of Things. Attached Figure Description

[0025] Figure 1 This is a circuit diagram of a single-pole double-throw switch provided in an embodiment of the present invention.

[0026] Figure 2These are integrated cross-sectional views of two enhanced GaN HEMT devices provided in embodiments of the present invention.

[0027] Figure 3 yes Figure 2 A cross-sectional view along the aa' direction.

[0028] Figure 4 This is a fabrication diagram of a fin-shaped gate structure provided in an embodiment of the present invention.

[0029] The names corresponding to the reference numerals in the attached figures are as follows:

[0030] 101: Bottom silicon substrate; 102: Buried oxide layer; 103: Top semiconductor layer; 201: Buffer layer; 202: Channel layer; 203: Barrier layer; 301: P-type doped layer; 302: Gate dielectric layer; 303: Gate metal layer; 401: Isolation trench; 402: Oxide layer; 403: Insulating dielectric; 501: Source; 502: Drain. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0032] like Figure 1 As shown, this invention discloses a single-pole double-throw (SPDT) switch circuit based on an enhanced GaN HEMT integrated device. The circuit employs a symmetrical series-parallel structure in its overall topology, aiming to achieve high-efficiency, high-isolation switching of RF signals between the common terminal RF and the two output terminals. The first switching unit, acting as a bridge connecting the common terminal RF and the first output terminal RF1, is internally composed of a first series transistor M1 and a first parallel transistor M3. The source of the first series transistor M1 is electrically connected to the common terminal RF via a high-conductivity metal interconnect, its drain is connected to the first output terminal RF1, and its gate serves as the input node of the first control terminal Vg1. To enhance isolation performance, the source of the first parallel transistor M3 is electrically connected to the first output terminal RF1, its drain is reliably grounded through a metallized via structure, and its gate is controlled by the second control terminal Vg2. This configuration ensures that when M1 is on, M3 is in a cutoff state, and vice versa.

[0033] The corresponding second switching unit is responsible for path control between the common terminal RF and the second output terminal RF2. The source of the second series transistor M2 is also connected to the common terminal RF, the drain is connected to the second output terminal RF2, and its gate is connected to the second control terminal Vg2. The second parallel transistor M4 is connected between the second output terminal RF2 and ground, that is, its source is connected to the second output terminal RF2, its drain is grounded, and its gate is connected to the first control terminal Vg1. Through this cross-coupled control logic, the first control terminal Vg1 simultaneously drives the opening of the first series path and the discharge of the second parallel branch, while the second control terminal Vg2 synchronously drives the opening of the second series path and the discharge of the first parallel branch.

[0034] To further optimize linearity under large signals, this embodiment introduces an auxiliary linearization branch consisting of a resistor R1 and a capacitor C1 connected in series in the first switching unit. One end of this branch is connected to the drain of the first parallel transistor M3 (i.e., near the ground point or directly coupled to the drain electrode), and the other end is connected to ground potential. In actual wiring, R1 and C1 are physically located close to M3 to reduce parasitic inductance. Similarly, the second switching unit has an auxiliary linearization branch consisting of a resistor R2 and a capacitor C2, connected between the drain of the second parallel transistor M4 and ground. When the switching circuit is in high-power operation, the high-frequency swing of the RF signal will generate nonlinear charges at the drain of the transistor. At this time, the RC branch absorbs some transient charges and adjusts the electric field distribution in the drain region through dynamic clamping, thereby suppressing harmonic distortion and improving the P1dB compression point of the circuit.

[0035] Please see Figure 2 and Figure 3 In this invention, all transistors M1, M2, M3, and M4 employ a high-performance enhancement-mode GaN HEMT integrated device structure. This device is grown on a special SOI substrate. The SOI substrate, from bottom to top, comprises a bottom silicon substrate 101, a buried oxide layer 102, and a top semiconductor layer 103. The bottom silicon substrate 101 is made of high-resistivity single-crystal silicon (typically greater than 3000 Ω·cm) to reduce substrate loss. The buried oxide layer 102 (BOX layer) has a thickness between 100 nm and 2 μm, serving as electrical insulation and thermal barrier. The top semiconductor layer 103 serves as a template layer for subsequent GaN epitaxial growth. Multiple parallel fin-shaped active regions are formed on the top semiconductor layer 103 using a dry etching process.

[0036] Each fin-shaped active region contains a multilayer heterojunction epitaxial structure. The bottom layer is a buffer layer 201, which is made of any one or a combination of AlN, AlGaN, InGaN, and GaN, and its thickness can range from 1000 to 4000 nm. This buffer layer is used to mitigate lattice and thermal mismatches between GaN and the substrate. A channel layer 202 is grown on top of the buffer layer 201, typically an undoped, high-quality GaN thin film with a thickness ranging from 100 to 300 nm. Immediately following the channel layer 202 is a barrier layer 203, typically made of AlGaN or InAlN, with a thickness of 15 nm to 25 nm and an aluminum composition of 0.20 to 0.30. Due to the polarization effect (including spontaneous polarization and piezoelectric polarization) between the AlGaN barrier layer 203 and the GaN channel layer 202, a high concentration of two-dimensional electron gas (2DEG) is induced at their interface.

[0037] To achieve enhancement-mode characteristics, a p-type doped layer 301 is specifically formed on the surface of the barrier layer 203 below the gate. This p-type doped layer 301 is typically made of Mg-doped p-GaN or p-AlGaN material, with a thickness of 50 nm to 100 nm. The p-type doped layer 301 and the underlying AlGaN barrier layer 203 form a heterojunction with a built-in electric field, which raises the energy band at the channel layer 202. In equilibrium with a zero external gate voltage, the conduction band bottom of the channel region is raised above the Fermi level, physically depleting the two-dimensional electron gas that was originally concentrated there, resulting in a high blocking state between the source 501 and the drain 502. This design allows the circuit to operate with only a unipolar positive voltage, completely eliminating the negative voltage power supply circuit required by traditional depletion-mode GaN devices.

[0038] This embodiment employs an advanced gate-all-around structure to enhance gate controllability. For example... Figure 3 As shown, the gate surround consists of a gate dielectric layer 302 deposited on the surface of the fin-shaped active region and a gate metal layer 303 covering it. The gate dielectric layer 302 is typically formed using a high-k dielectric material such as Al2O3 or HfO2 by atomic layer deposition (ALD) process, which can effectively suppress gate leakage current. The gate metal layer 303 not only covers the top surface of the fin-shaped active region, but also wraps around the two vertical sides of the fin along the etched sidewalls. This three-sided wrapping structure allows the gate electric field to penetrate into the channel layer 202 from multiple dimensions, significantly enhancing the modulation capability of the two-dimensional electron gas concentration. Compared with the traditional planar structure, this fin structure increases the effective gate width per unit area, thereby significantly reducing the on-resistance when the device is turned on.

[0039] In terms of physical connection, the source 501 and drain 502 are distributed at both ends of the longitudinal direction of the finned active region. By trenching on the barrier layer 203 and depositing a stacked structure of metals such as Ti / Al / Ni / Au, followed by high-temperature rapid thermal annealing (RTA), the metal atoms undergo an alloying reaction with the underlying channel layer 202, forming a low-resistance ohmic contact. The gate is located between the source 501 and drain 502, and a precise photolithography alignment process ensures that it maintains a predetermined physical distance from the source and drain to balance the relationship between breakdown voltage and parasitic resistance.

[0040] Please see Figure 2 To address substrate crosstalk issues under high integration density, this invention introduces a deep trench isolation (DTI) structure between adjacent enhancement-mode GaNHEMT devices. This structure includes an isolation trench 401 formed using a BOSCH deep reactive ion etching process. The isolation trench 401 exhibits an extremely high aspect ratio in the vertical direction, completely penetrating the epitaxial layer and top semiconductor layer 103 of the finned active region, and its bottom extends into the buried oxide layer 102 of the SOI substrate. A dense oxide layer 402 is grown on the inner sidewalls and bottom of the isolation trench 401 using a thermal oxidation process to repair lattice damage generated during etching and passivate interface defects.

[0041] The isolation trench 401 is filled with a high-quality insulating dielectric 403, such as silicon dioxide filled by high-density plasma chemical vapor deposition (HDPCVD). Specifically, by controlling the etching time and the ratio of chemical reagents, this invention forms a bottom-recessed structure within the buried oxide layer 102. This recessed structure causes a certain degree of lateral expansion of the insulating dielectric within the buried oxide layer 102, forming a cross-sectional shape resembling a "dovetail" or "widened bottom." This bottom-recessed structure significantly increases the path length for charge exchange between adjacent devices through the depth of the substrate, effectively blocking the conduction path of high-frequency signals within the substrate.

[0042] In actual operation, the working principle of this single-pole double-throw switch circuit is as follows: When the system needs to transmit the radio frequency signal from the common terminal RF to the first output terminal RF1, the external control circuit applies a positive voltage (e.g., +3V or +5V) greater than the device turn-on voltage to the first control terminal Vg1, while simultaneously applying a zero level or a low level to the second control terminal Vg2. Under the action of the high level of Vg1, the energy band below the gate of the first series transistor M1 is depressed, and the two-dimensional electron gas re-accumulates in the channel layer 202, forming a low-resistance conductive channel, allowing the signal to pass through. At the same time, the second parallel transistor M4 is also controlled by Vg1 to enter the conducting state, quickly discharging any residual signal that may leak to the second output terminal RF2 to ground, thereby improving the isolation when the RF1 path is turned on. At this time, since Vg2 is at a low level, both the second series transistor M2 and the first parallel transistor M3 are in a depletion turn-off state, physically cutting off the path to RF2.

[0043] Conversely, when switching to the second output terminal RF2, Vg2 becomes high and Vg1 becomes low. At this time, M2 and M3 are turned on, while M1 and M4 are turned off. The RF signal flows from the common terminal RF to the second output terminal RF2, while the RF1 port is short-circuited to ground through the turned-on M3, ensuring high isolation characteristics of the output port. Throughout the switching process, due to the use of an SOI substrate combined with a deep trench isolation structure, the parasitic capacitance when the device is turned off is greatly compressed. In particular, the drain-source parasitic capacitance is significantly reduced because, due to the presence of the buried oxide layer 102 and the insulating dielectric 403, most of the electric field lines pass through the low dielectric constant dielectric region rather than the high-loss semiconductor region, thus significantly reducing signal leakage at high frequencies.

[0044] In this invention, the geometry of the finned active region significantly affects circuit performance. The fin width is typically controlled between 20 nm and 80 nm to ensure complete volume control of the gate. The fin height is set between 30 nm and 120 nm based on the thickness of the epitaxial layer. Limiting the fin width to the nanoscale aims to fully deplete the two-dimensional electron gas in the channel by utilizing the three-dimensional encapsulation effect of the gate, thereby achieving a positive threshold voltage. The fin height determines the height of the sidewall conductive channels; higher fins are beneficial for increasing the effective channel width and reducing on-resistance.

[0045] Regarding the manufacturing process, this invention provides a method for fabricating an enhanced GaN HEMT device for a single-pole double-throw switch. As an example and not a limitation, this method can be used to fabricate the aforementioned device. The method may include steps S501-S508, which are described below.

[0046] S501, Epitaxial Layer Growth: The SOI substrate surface is cleaned using a standard RCA cleaning process to remove organic contaminants and particles. A buffer layer, channel layer, and barrier layer are sequentially grown on the SOI substrate using metal-organic chemical vapor deposition (MOCVD).

[0047] S502, Fin Structure Formation: A 50nm to 100nm layer of SiO2 or Si3N4 is deposited on the epitaxial layer as a hard mask. The fin-shaped active region pattern is defined using photolithography. Reactive ion etching (RIE) is used to transfer the photoresist pattern to the hard mask layer. Inductively Coupled Plasma Etching (ICP-RIE) is then used to etch the GaN-based epitaxial layer with a Cl2 / Ar or Cl2 / BCl3 mixed gas to form a fin-shaped active region with a height of 80nm to 150nm. The etching is ensured to stop within a buffer layer, while maintaining sufficient fin height.

[0048] S503, Deep Trench Isolation Structure Formation: The photolithography process defines the deep trench isolation region. Using BOSCH deep reactive ion etching (DRIE) technology, high aspect ratio deep trenches are etched to ensure penetration of the GaN epitaxial layer and the top semiconductor layer, extending to the buried oxide layer. The exposed buried oxide layer is lightly etched for 20 to 40 seconds using a diluted hydrofluoric acid solution (HF:H2O=1:100), causing a 10nm to 20nm indentation. This step increases the effective thickness of the isolation oxide layer at the trench bottom corners, improving the breakdown voltage of the isolation structure. A dense SiO2 layer with a thickness of 50nm to 100nm is grown on the inner wall of the trench using a thermal oxidation process. SiO2 is deposited using high-density plasma chemical vapor deposition (HDP-CVD) to completely fill the deep trench. A chemical mechanical polishing process is used, with the SiNx or SiO2 at the top of the finned active region as a stop layer, to remove excess surface filler material, forming a planarized deep trench isolation structure.

[0049] S504, p-type doped layer deposition: Reactive sputtering using a high-purity ceramic NiO target or a metallic Ni target. A 2-5 nm ultrathin SiO2 layer is deposited using ALD or PECVD as a sacrificial layer to protect the surface of the finned active region (optional). The wafer is loaded into a magnetron sputtering apparatus and evacuated to a base vacuum level ≤ 5 × 10⁻⁵. -4 Pa. The substrate temperature can be selected from room temperature to 400℃. Introduce a mixture of Ar and O2 gas into the growth chamber, turn on the sputtering power supply, and after pre-sputtering for 5-10 minutes, open the baffle to deposit p-NiO. x The deposition time for the thin film is adjusted according to the target thickness. If film properties need to be adjusted, annealing can be performed at 300°C to 500°C in an O2 or N2 atmosphere for 10 to 30 minutes.

[0050] S505, Gate Dielectric Deposition: Before depositing the gate dielectric, the surface of the finned active region is pretreated by immersing it in dilute hydrochloric acid for 2-5 minutes to remove native oxides. The wafer is then transferred to the ALD reaction chamber and heated to 300-400℃ under vacuum conditions for 10-30 minutes to remove adsorbed moisture and impurities. An atomic layer deposition process is then used, with a deposition temperature of 250℃ to 350℃, employing trimethylaluminum and H2O or O2 as precursors to deposit the Al2O3 gate dielectric layer.

[0051] S506, Gate Deposition: The gate region is defined using photolithography. The sample is placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 5 × 10⁻⁶. -6 After the torsion process, gate metal Ni / Au is deposited in the gate and photoresist areas, with Ni / Au thicknesses of 50 / 100 nm, respectively.

[0052] S507, Etching source and drain trenches: The source and drain trenches are defined using photolithography, and the trench areas are etched using ICP process, with the etching depth reaching the channel layer.

[0053] S508, Source and Drain Deposition: The source and drain regions are defined using photolithography. Then, ohmic contact metals for the source and drain are deposited using electron beam evaporation. The multilayer metal used, from bottom to top, is Ti / Al / Ni / Au, with thicknesses of 20 / 100 / 50 / 100 nm for Ti / Al / Ni / Au, respectively. The source and drain electrodes are formed through a lift-off process. Finally, the sample is placed in a nitrogen or oxygen atmosphere, with an annealing temperature of 400-800℃ and an annealing time of 30-200 s.

[0054] The integration of the single-pole double-throw switch in this invention not only reduces the physical size of the RF front-end, but more importantly, it perfectly combines the high breakdown electric field and high saturation velocity characteristics of enhancement-mode GaN devices with the low parasitic and high isolation characteristics of SOI substrates. In the millimeter-wave band, this structure can effectively cope with signal attenuation caused by substrate losses, enabling the single-pole double-throw switch to maintain extremely low insertion loss while possessing power handling capabilities and linearity performance exceeding those of traditional bulk silicon or GaAs processes.

[0055] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A single-pole double-throw switching circuit based on an enhanced GaN HEMT integrated device, characterized in that, It includes a common terminal RF, a first output terminal RF1 and a second output terminal RF2, a first switching unit connected between the common terminal RF and the first output terminal RF1, and a second switching unit connected between the common terminal RF and the second output terminal RF2; Both the first switching unit and the second switching unit include transistor devices, which are enhancement-mode GaN HEMT devices integrated on a high-resistivity SOI substrate; The enhanced GaN HEMT device includes: The SOI substrate structure consists of a bottom silicon substrate (101), a buried oxide layer (102), and a top semiconductor layer (103) from bottom to top. The fin-shaped active region is formed on the top semiconductor layer of the SOI substrate structure, and includes a buffer layer (201), a channel layer (202) and a barrier layer (203) from bottom to top; the fin-shaped active region is etched to form a fin-shaped structure; A gate surrounds the top and sidewalls of each fin-shaped active region, the gate comprising a gate dielectric layer (302) and a gate metal layer (303). The source (501) and drain (502) are formed at both ends of each fin-shaped active region and form an ohmic contact with the fin-shaped active region.

2. The single-pole double-throw switch circuit based on an enhanced GaN HEMT integrated device according to claim 1, characterized in that, The transistor devices in the first switching unit are a first series transistor M1 and a first parallel transistor M3. The source of the first series transistor M1 is connected to the common terminal RF, the drain is connected to the first output terminal RF1, and the gate serves as the first control terminal Vg1. The source of the first parallel transistor M3 is connected to the first output terminal RF1, the drain is grounded, and the gate is connected to the second control terminal Vg2. The first switching unit also includes a resistor R1 and a capacitor C1 connected in series between the drain of the first parallel transistor M3 and ground.

3. The single-pole double-throw switch circuit based on an enhanced GaN HEMT integrated device according to claim 1, characterized in that, The transistor devices in the second switching unit are a second series transistor M2 and a second parallel transistor M4; the source of the second series transistor M2 is connected to the common terminal RF, the drain is connected to the second output terminal RF2, and the gate is connected to the second control terminal Vg2; the source of the second parallel transistor M4 is connected to the second output terminal RF2, the drain is grounded, and the gate is connected to the first control terminal Vg1; the second switching unit also includes a resistor R2 and a capacitor C2 connected in series between the drain of the second parallel transistor M4 and ground.

4. A single-pole double-throw switching circuit based on an enhanced GaN HEMT integrated device according to claim 1, characterized in that, The gate dielectric layer (302) and the barrier layer (203) of the gate also include a p-type doped layer (301), which depletes the two-dimensional electron gas in the channel under zero bias, so that the device is in the off state.

5. A single-pole double-throw switching circuit based on an enhanced GaN HEMT integrated device according to claim 1, characterized in that, Each of the fin-shaped active regions has a width of 20 nm to 80 nm and a height of 30 nm to 120 nm.

6. A single-pole double-throw switching circuit based on an enhanced GaN HEMT integrated device according to claim 1, characterized in that, A deep trench isolation structure is provided between adjacent enhancement-mode GaN HEMT devices. The deep trench isolation structure includes an isolation trench (401), an oxide layer (402), and an insulating dielectric (403). It is located between adjacent fin active regions of two enhancement-mode GaN HEMT devices to achieve electrical isolation between different enhancement-mode GaN HEMTs. The deep trench isolation structure penetrates the fin active region and the top semiconductor layer and extends to the buried oxide layer of the SOI substrate.

7. A single-pole double-throw switch circuit based on an enhanced GaN HEMT integrated device according to claim 6, characterized in that, The deep trench isolation structure is formed by using BOSCH deep reactive ion etching process to form a high aspect ratio isolation trench (401), and the exposed buried oxide layer (102) is etched by dilute hydrofluoric acid solution. Then, an oxide layer (402) is thermally grown or deposited on the inner wall of the isolation trench (401), and finally, an insulating medium (403) is filled by high density plasma chemical vapor deposition process.

8. A single-pole double-throw switching circuit based on an enhanced GaN HEMT integrated device according to claim 7, characterized in that, A recessed structure is formed at the junction of the bottom of the deep trench isolation structure and the buried oxide layer (102), and the depth of the recessed structure into the buried oxide layer (102) is 15% to 25% of the total thickness of the buried oxide layer (102).

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