An implementation method for a universal test chip architecture compatible with multi-protocol SerDes

Abstract

This invention discloses an implementation method for a universal test chip architecture compatible with multiple SerDes protocols, relating to the field of high-speed communication technology. The method includes: dynamically configuring the working mode of the SerDes IP core based on the target communication protocol and collecting multi-dimensional performance parameters; calling a performance analysis model to perform correlation analysis and generate anomaly diagnostic results containing root cause localization information; based on the target performance, using an optimization algorithm to intelligently search within the configurable parameter space of the SerDes IP core to obtain the optimal parameter combination; reconfiguring the SerDes IP core using the optimal parameter combination and performing verification tests. This invention achieves full-process coverage from automated testing and intelligent diagnosis to parameter optimization, improving the universality, intelligence level, and debugging efficiency of multi-protocol SerDes testing.

Description

Technical Field

[0001] This invention relates to the field of high-speed communication technology, and specifically to an implementation method for a multi-protocol compatible SerDes universal test chip architecture. Background Technology

[0002] In the field of high-speed data transmission, SerDes, or serial-to-deserializer technology, has become a core infrastructure supporting artificial intelligence, cloud computing, and high-performance computing. With the diversification and evolution of communication protocol standards, the design and verification of general-purpose SerDes IP cores supporting multiple protocols has become crucial. This involves not only ensuring the chip meets performance standards under a single protocol but also requiring it to flexibly switch between different protocols while maintaining optimal performance.

[0003] Currently, testing and verification of multi-protocol compatible SerDes IPs face two main technical bottlenecks. Firstly, traditional testing methods heavily rely on engineers' existing experience and manual trial and error, repeatedly adjusting numerous configuration parameters within SerDes to approximate performance targets. This process is not only inefficient and time-consuming but also struggles to guarantee a globally optimal solution, especially when multiple performance metrics need to be balanced. Secondly, most testing solutions only provide limited macro-level criteria, lacking the ability to accurately pinpoint the root causes of anomalies or performance bottlenecks. This leads to a complex and uncertain troubleshooting process, ultimately resulting in high costs, increased risks, and extended development cycles for the research and testing of multi-protocol SerDes. Summary of the Invention

[0004] This invention addresses the technical problems of low testing efficiency, difficulty in diagnosing the root causes of performance anomalies, and reliance on manual experience for parameter tuning in multi-protocol scenarios, lacking autonomous optimization capabilities in existing technologies. It provides an implementation method for a universal test chip architecture compatible with multiple protocols, SerDes.

[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: This invention provides an implementation method for a multi-protocol SerDes universal test chip architecture, comprising: Based on the target communication protocol, the working mode of the SerDes IP core is dynamically configured, and test operations are performed to collect multiple performance parameters of the SerDes IP core during the test process. The performance analysis model is invoked to perform correlation analysis on the multiple performance parameters, and based on the deviation between the correlation analysis results and the preset benchmark, an abnormal diagnosis result containing root cause localization information is generated. Based on the target performance, an optimization algorithm is used to search within the configurable parameter space of the SerDes IP core to obtain the optimal parameter combination; The SerDes IP core is reconfigured using the optimal parameter combination, and verification tests are performed.

[0006] The beneficial effects of this invention are: Compared to existing technologies, this invention establishes a complete autonomous process from data acquisition and intelligent diagnosis to automatic optimization, deeply integrating unsupervised learning and parameter optimization closed-loop into the SerDes testing field, achieving automated and precise localization of performance anomalies. Secondly, by constructing and calling a performance prediction model to guide the optimization algorithm search, it reduces reliance on human experience and can autonomously and efficiently find the optimal configuration combination that meets multiple performance requirements in a broad parameter space, greatly improving testing and tuning efficiency. Thirdly, the design includes a verification phase, enabling the test system to update the diagnosis and constrain the search space using new data when the initial optimization fails to meet expectations, thus possessing robustness in continuously approaching the optimal solution. This invention is compatible with multiple high-speed communication protocols, providing a unified, intelligent, and efficient solution for verifying multi-protocol SerDes IPs. Attached Figure Description

[0007] Figure 1 A flowchart illustrating an implementation method for a multi-protocol SerDes universal test chip architecture provided by the present invention; Figure 2 This is a schematic diagram illustrating the process of searching within a configurable parameter space to obtain the optimal parameter combination, as provided by the present invention. Detailed Implementation

[0008] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0009] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0010] In the description of this invention, the term "for example" is used to mean "used as an example, illustration, or description." Any embodiment described as "for example" in this invention is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0011] Example 1, as Figure 1 As shown, this embodiment of the invention provides an implementation method for a multi-protocol SerDes universal test chip architecture, including: S10: Based on the target communication protocol, dynamically configure the working mode of the SerDes IP core, execute test operations, and collect multiple performance parameters of the SerDes IP core during the test process; Specifically, based on the target communication protocol, the operating mode of the SerDes IP core is dynamically configured, and test operations are performed to collect multiple performance parameters of the SerDes IP core during the test process, including: Based on the target communication protocol, determine the configuration parameters of the SerDes IP core; Write the configuration parameters into the SerDes IP core to set the working mode of the SerDes IP core; Inject test data streams into the configured SerDes IP core; During the processing of the test data stream by the SerDes IP core, multiple performance parameters are collected, including at least eye diagram feature parameters, bit error rate, and jitter parameters.

[0012] First, based on the physical layer specifications and electrical requirements of the target communication protocol, the SerDes IP core, i.e., the serializer / deserializer IP core, is analyzed and its required configuration parameters to support the target communication protocol. Specifically, the target communication protocol refers to a high-speed data transmission interface standard developed and published by an international standardization organization or industry association, such as a high-speed interface standard for peripheral component interconnection, Ethernet standards, Universal Serial Bus standards, or Serial Advanced Technology Annex (SATTA) standards. Each target communication protocol explicitly defines the mandatory parameter set and optional parameter range for physical layer operation through its specification document.

[0013] The configuration parameters of a SerDes IP core precisely define its internal operating state, including data transmission rate, signal coding scheme, equalizer coefficients, clock recovery loop bandwidth, and transmitter pre-emphasis and de-emphasis strength. The data transmission rate parameter determines the symbol transmission speed on the serial link, and its value must strictly match the specific generation or channel rate mode specified by the target communication protocol. The signal coding scheme parameter controls the encoding rules used before data serialization, such as scrambling or specific line coding methods, to meet the protocol's requirements for DC balance, clock recovery, or error detection. The equalizer coefficient parameter configures the frequency response characteristics of the receiver equalizer to compensate for high-frequency losses and inter-symbol interference suffered by the signal in the transmission medium. The clock recovery loop bandwidth parameter sets the dynamic tracking capability of the receiver's clock data recovery circuit, directly affecting its tolerance to input signal jitter and locking speed. The transmitter pre-emphasis and de-emphasis strength parameters adjust the enhancement level of high-frequency components and the attenuation level of low-frequency components in the transmitted signal, respectively, aiming to improve the eye diagram quality of the signal at the end of the channel. Determining the configuration parameters of the SerDes IP core essentially involves mapping the requirements of the target communication protocol into a set of numerical control instructions with clear physical meaning that can be directly written to the internal registers of the SerDes IP core.

[0014] Secondly, the aforementioned configuration parameters are completely and accurately written into the corresponding function registers of the SerDes IP core via the chip's internal configuration bus or dedicated interface. This writing action directly sets the operating mode of the SerDes IP core, ensuring its physical layer behavior aligns with the requirements of the target communication protocol, thus preparing for the execution of test operations conforming to the target communication protocol standard.

[0015] Next, a test data stream is injected into the SerDes IP core that has completed its working mode configuration. This test data stream is a preset pseudo-random binary sequence or a data packet containing a specific training sequence, designed to simulate the data load under real communication scenarios, so as to stimulate the actual working state of the SerDes IP core on the complete signal link, such as signal conversion, clock recovery, and equalization processing, and provide a real signal environment for performance evaluation.

[0016] Specifically, during the processing of the injected test data stream by the SerDes IP core, multi-dimensional performance parameters are collected in parallel. Specifically, the collection of performance parameters is achieved through the chip's built-in measurement circuitry and external testing equipment, focusing on key indicators characterizing the signal integrity and data transmission reliability of the high-speed serial link. The collected performance parameters include at least eye diagram characteristic parameters that directly reflect signal quality and noise tolerance, such as the height and width of the eye diagram opening; the bit error rate, which measures the accuracy of data transmission; and jitter parameters that evaluate signal timing stability, such as total jitter, random jitter, and deterministic jitter. These performance parameters together constitute a quantitative description of the current operating performance of the SerDes IP core, and also provide input data for subsequent in-depth analysis and intelligent diagnostics.

[0017] S20: Call the performance analysis model to perform correlation analysis on the multiple performance parameters, and generate an abnormal diagnosis result containing root cause localization information based on the deviation between the correlation analysis result and the preset benchmark. Specifically, the performance analysis model is invoked to perform correlation analysis on the multiple performance parameters, including: The multiple performance parameters are input into the performance analysis model constructed based on an unsupervised learning algorithm; The performance analysis model is used to analyze the inherent correlation characteristics among the multiple performance parameters and obtain the correlation analysis results.

[0018] First, data input is performed, transmitting the previously collected performance parameters as input data to the pre-trained performance analysis model. This performance analysis model is a data-driven mathematical model built upon unsupervised learning algorithms. It characterizes and learns the inherent statistical relationships and potential patterns among the performance parameters of the SerDes IP core under normal operating conditions. This allows for the automatic identification of the overall deviation between the current performance parameter set and historical normal states, providing quantitative analytical basis for subsequent anomaly detection and root cause analysis.

[0019] Specifically, the configuration steps of the performance analysis model include: Multiple sets of historical performance parameters of the SerDes IP core under normal test conditions were collected to form a training dataset; Based on the unsupervised learning algorithm, the model is trained using the training dataset to mine the inherent correlation patterns of the multiple sets of historical performance parameters under normal conditions, and obtain the performance analysis model.

[0020] First, a training dataset is constructed. Specifically, multiple test operations need to be performed on the SerDes IP core under known normal test conditions. Each test collects a complete set of performance parameters, including eye diagram feature parameters, bit error rate parameters, and jitter parameters, thereby forming multiple sets of historical performance parameters, which constitute the training dataset for training the performance analysis model.

[0021] Secondly, after obtaining the training dataset, the model training phase begins. Specifically, based on the training dataset, a specific unsupervised learning algorithm is selected as the core modeling method. During training, the unsupervised learning algorithm performs in-depth statistical analysis on multiple sets of historical performance parameters, autonomously discovering and learning the inherent and stable intrinsic correlation patterns of these parameters under normal conditions. Unsupervised learning algorithms refer to a class of machine learning methods that can learn structures from data without relying on pre-labeled output data, including clustering algorithms, principal component analysis, isolated forests, and autoencoders. This unsupervised learning algorithm, through iterative optimization of its internal parameters and data structure, can gradually establish mathematical and statistical models that can accurately represent the complex multidimensional correlations between historical normal performance parameters. This completes the feature extraction and pattern encapsulation of the SerDes IP core's baseline working state, resulting in a trained performance analysis model capable of analyzing deviations between new input performance parameter sets and the baseline state.

[0022] For example, since there are complex multidimensional relationships among the various performance parameters of the SerDes IP core, and the principal component analysis algorithm has the advantages of high computational efficiency and strong interpretability in revealing the main variation direction of high-dimensional data and achieving effective dimensionality reduction, the principal component analysis algorithm can be selected to construct this performance analysis model.

[0023] Specifically, model training begins with data standardization preprocessing. Using a training dataset under historical normal conditions, the mean and standard deviation of each performance parameter dimension are calculated, and this is used to standardize the training dataset, ensuring that each dimension has zero mean and unit variance, thereby eliminating the influence of dimensional differences between performance parameters on the model. Next, the covariance matrix is ​​calculated based on the standardized training data. This covariance matrix fully characterizes the linear correlation between pairs of performance parameters. Eigenvalue decomposition is then performed on the covariance matrix to obtain a sequence of eigenvectors arranged in descending order of eigenvalues. Each eigenvector represents a major direction of data variation, and the magnitude of its corresponding eigenvalue represents the amount of variance information contained in that direction.

[0024] After completing the eigenvalue decomposition, the key structural parameters of the model, namely the number of principal components, need to be determined. Based on a preset cumulative variance contribution rate threshold, such as 95%, eigenvalues ​​are selected from largest to smallest, ensuring that the cumulative variance contribution rate of the selected eigenvalues ​​reaches or exceeds this threshold for the first time. The number of eigenvalues ​​selected at this point is denoted as k. The k corresponding eigenvectors are normalized and then combined column-wise to form a projection matrix. This projection matrix is ​​the essential parameter set of the trained performance analysis model, defining the linear projection relationship from the original performance parameter space to the k-dimensional principal component space.

[0025] The output of the performance analysis model is the correlation analysis result, which is generated as follows: For a newly input performance parameter vector, it is first standardized using the mean and standard deviation stored during the training phase. Next, the standardized parameter vector is multiplied by the projection matrix, and a linear transformation is performed. The transformation result is a k-dimensional real vector, which is the correlation analysis result. Each scalar element in this correlation analysis result is called a principal component score. The first principal component score corresponds to the projection direction with the largest data variance, the second principal component score corresponds to the projection direction orthogonal to the first direction and with the largest remaining variance, and so on for subsequent scores.

[0026] Therefore, the correlation analysis result is a quantified low-dimensional vector, which accurately represents the distribution coordinates of the original multidimensional performance parameters on the most important variation patterns of the data with a set of ordered scalar values, providing a direct mathematical basis for subsequent anomaly quantification judgment.

[0027] Multiple performance parameters are input into a performance analysis model, which analyzes the inherent correlation characteristics among these parameters to obtain correlation analysis results. This process is automatically executed by the performance analysis model, which internally uses a mathematical mechanism built on an unsupervised learning algorithm to perform calculations and analyses on the input multidimensional performance parameters. It quantitatively evaluates the degree of matching between the current set of performance parameters and the joint distribution pattern of performance parameters learned under historical normal conditions, and comprehensively examines the statistical dependencies and cooperative changes among all performance parameters.

[0028] The final correlation analysis results can objectively reflect whether the current performance parameter set deviates from the normal correlation pattern and the degree of deviation, thus providing a data correlation-based decision-making basis for subsequent anomaly diagnosis and root cause localization.

[0029] Furthermore, based on the deviation between the correlation analysis results and the preset benchmark, abnormal diagnostic results containing root cause localization information are generated, including: Based on the correlation analysis results, the comprehensive deviation between the correlation analysis results and the preset benchmark is calculated; When the overall deviation exceeds a preset deviation threshold, an anomaly is determined. Analyze the contribution of each of the multiple performance parameters to the overall deviation. Based on the contribution value, the main contribution performance parameters are determined, root cause localization information containing at least one main contribution performance parameter is generated, and anomaly diagnosis results are obtained.

[0030] First, the overall deviation between the correlation analysis results and the preset benchmark is calculated. The preset benchmark is a quantitative representation of the correlation pattern learned by the performance analysis model from historical normal data; for example, in principal component analysis, it is represented by the multivariate distribution center of the normal score vector. The overall deviation is a scalar value obtained by calculating the difference between the current correlation analysis results and this preset benchmark, such as by calculating their Mahalanobis distance. This overall deviation comprehensively reflects the degree of deviation of the current overall state of all performance parameters from the normal pattern.

[0031] Secondly, the calculated overall deviation is compared with a pre-set deviation threshold. This pre-set deviation threshold is a scalar threshold determined based on the statistical distribution of historical normal data, representing the maximum statistical fluctuation boundary allowed by the normal performance correlation pattern. The pre-set deviation threshold is set according to the distribution of overall deviation values ​​of a large number of samples under historical normal conditions, for example, taking the 99th percentile of this distribution. When the overall deviation exceeds this pre-set deviation threshold, the performance status of the current SerDes IP core is determined to be abnormal, indicating that the overall correlation characteristics between the currently collected multiple performance parameters have significantly deviated from their historical normal pattern, posing a risk of performance degradation or functional failure.

[0032] Furthermore, after identifying the anomaly, parameter contribution analysis is needed to pinpoint the main influencing factors causing the abnormal performance correlation pattern. Specifically, sensitivity analysis can be used to quantify the impact of each input performance parameter, including eye diagram feature parameters, bit error rate parameters, and jitter parameters, on the final comprehensive deviation value, i.e., the contribution value of each performance parameter. Sensitivity analysis is a method to assess the dependence of the model output on changes in input parameters. It is implemented by sequentially perturbing the value of each input performance parameter and observing the corresponding change in the comprehensive deviation. The contribution value of each performance parameter to the comprehensive deviation is a scalar value, representing the relative importance of that performance parameter in the overall abnormal deviation under the current state.

[0033] Finally, anomaly diagnostic results containing root cause localization information are generated. First, based on the calculated contribution values ​​of each performance parameter, all performance parameters involved in the analysis are sorted in descending order of their contribution values. Then, the sorted contribution values ​​are compared with a preset contribution threshold. This preset contribution threshold is an absolute value threshold pre-set based on historical diagnostic experience or statistical analysis, for example, set as the value corresponding to the top 20% percentile in the contribution value ranking. When the contribution value of a performance parameter exceeds this preset contribution threshold, that performance parameter is determined to be the major contributing performance parameter.

[0034] The final anomaly diagnosis result is a structured report, which includes at least an ordered list of the identified major contributing performance parameters, the specific contribution value of each parameter, and can be further correlated with their original measurements. The anomaly diagnosis result clearly identifies which specific performance parameter plays a dominant role in the abnormal deviation of the performance correlation pattern across multiple dimensions, such as eye diagram feature parameters, bit error rate parameters, and jitter parameters. This provides precise root cause localization guidance for subsequent targeted optimization and debugging, completing the diagnostic process from anomaly detection to preliminary root cause localization.

[0035] S30: Based on the target performance, an optimization algorithm is used to search within the configurable parameter space of the SerDes IP core to obtain the optimal parameter combination; Specifically, such as Figure 2 As shown, based on the target performance, an optimization algorithm is used to search within the configurable parameter space of the SerDes IP core to obtain the optimal parameter combination, including: A first parameter combination is randomly generated within the configurable parameter space; Invoke the performance prediction model, input the first parameter combination into the performance prediction model, and predict the first performance prediction data of the first parameter combination; Calculate the first fitness score between the first performance prediction data and the target performance; Based on the first fitness score, the first parameter combination is adjusted to obtain the second parameter combination; Perform iterative optimization until convergence to obtain the optimal parameter combination.

[0036] First, initialization is performed within the configurable parameter space, randomly generating a set of parameter values ​​to form the initial search starting point, denoted as the first parameter combination. The configurable parameter space is a high-dimensional search domain comprised of all adjustable internal configuration parameters of the SerDes IP core and their respective effective numerical ranges. This includes the transmitter pre-emphasis coefficient, receiver equalizer parameters, differential output voltage amplitude, common-mode voltage level, and termination impedance matching value. This configurable parameter space is set by referring to the SerDes IP core's design specifications and register configuration mapping table. For example, the adjustable range of the transmitter pre-emphasis coefficient is 0 to 15 levels, the gain adjustment range of the receiver continuous-time linear equalizer is 0 to 12 dB, the adjustment range of the differential output voltage amplitude is 200 mV to 1200 mV, the adjustment range of the common-mode voltage level is 0.5 V to 1.2 V, and the selectable range of the termination impedance matching value is 40 ohms to 60 ohms.

[0037] Secondly, the pre-trained performance prediction model is invoked for evaluation. The generated first parameter combination is input into the performance prediction model, which is a regression model built based on machine learning technology. It establishes a non-linear mapping relationship from the configuration parameter space of the SerDes IP core to the key performance indicator space. It can infer and predict the working performance of the SerDes IP core under this parameter combination and output the first performance prediction data, including eye diagram height, eye diagram width, and bit error rate.

[0038] Specifically, the configuration steps of the performance prediction model include: Collect the sample configuration parameter set and the corresponding sample measured performance dataset; The performance prediction model is constructed based on machine learning; The performance prediction model is trained in a supervised manner using the sample configuration parameter set as input data and the sample measured performance dataset as supervised data. Training is completed after the performance prediction model meets the prediction accuracy requirements, and the performance prediction model is obtained.

[0039] First, a data acquisition process was performed, involving extensive testing and measurement of the SerDes IP core. During testing, multiple different combinations of configuration parameters were pre-defined, forming a sample configuration parameter set. For each set of configuration parameters, the SerDes IP core was run under target operating conditions, and its key performance indicators were actually measured to obtain the corresponding sample measured performance dataset. The performance indicators in this sample measured performance dataset include eye diagram feature parameters, bit error rate, and jitter parameters.

[0040] Secondly, an initial performance prediction model is constructed based on machine learning methods, such as deep neural networks, gradient boosting decision trees, or support vector regression machines. Supervised learning is employed, using the sample configuration parameter set as input data and the corresponding measured performance dataset as supervised data (i.e., the training objective) to train the performance prediction model. During training, the prediction accuracy of the performance prediction model is continuously evaluated. This accuracy can be quantified using metrics such as mean squared error (MSE) and mean absolute error (MAE). When the prediction error of the performance prediction model falls below a pre-set accuracy threshold, such as an MSE below 0.5% or an MAE below 0.2%, the performance prediction model is deemed to meet the accuracy requirements, and the training process terminates, thus obtaining a performance prediction model suitable for inference.

[0041] For example, since there is a highly nonlinear and complex correlation between the configuration parameters of the SerDes IP core and the measured performance indicators, and deep neural network models have significant advantages in multi-level feature abstraction and complex pattern recognition, deep neural network models can be selected to construct this performance prediction model.

[0042] Specifically, the performance prediction model mainly consists of an input layer, a feature abstraction layer, and a performance output layer. The input layer receives a standardized configuration parameter vector, which includes configuration parameters across multiple dimensions, such as the transmitter pre-emphasis coefficients, receiver equalizer parameters, differential output voltage amplitude, common-mode voltage level, and terminal impedance matching value. The feature abstraction layer employs a multi-layer fully connected neural network structure. The number of hidden layer neurons is adaptively configured according to the dimensions of the input features. Each neural network layer uses the ReLU activation function to introduce non-linear transformation capabilities, and Dropout layers are embedded between network layers with a dropout rate set between 0.1 and 0.3 to effectively suppress model overfitting and improve its generalization performance. The output layer uses a linear activation function to map the final abstract features into a continuous performance index vector, serving as the predicted eye diagram height, eye diagram width, and bit error rate.

[0043] During training, key hyperparameters included a learning rate of 0.001, 200 training epochs, and a batch size of 128. The learning rate was set to balance training stability and convergence speed; the number of training epochs ensured the model fully learned the complex mapping between configuration parameters and performance metrics; and the batch size balanced training efficiency with computational resource consumption. Specifically, a supervised learning approach was used, with the sample configuration parameter set as the input sample set and the actual sample performance dataset as the supervision data to form the sample label set. The input sample set and the corresponding label sample set were divided into training, validation, and test sets in a 7:2:1 ratio.

[0044] Furthermore, the sample configuration parameter vectors in the training set are used as input, and the corresponding measured performance data vectors are used as supervision signals. The network weight parameters are iteratively optimized using the backpropagation algorithm and the Adam optimizer. The mean squared error loss function is used to measure the deviation between the predicted performance vector and the measured performance vector. The training process is monitored using a validation set. When the validation set loss function value no longer decreases for several consecutive rounds and the model prediction accuracy reaches a predetermined threshold, such as a mean squared error below 0.5%, training is terminated, resulting in a converged performance prediction model. This performance prediction model can effectively capture the complex nonlinear relationship between configuration parameters and measured performance indicators, achieving accurate performance prediction.

[0045] Furthermore, the first parameter combination is input into the performance prediction model, which calculates and outputs the first performance prediction data for that parameter combination. This first performance prediction data includes quantitative predictions of the SerDes IP core's performance under this parameter combination configuration, such as eye diagram feature parameters, bit error rate, and jitter parameters. This prediction process utilizes the complex mapping relationship from the configuration space to the performance space learned by the performance prediction model, enabling rapid and low-cost evaluation of the expected performance of a specific parameter combination without the need for actual hardware testing. This provides crucial data input for subsequent fitness scoring and optimization iterations.

[0046] Then, a first fitness score is calculated between the first performance prediction data and the preset target performance. Here, the target performance is the set of performance indicators to be achieved. The first fitness score is calculated using a negative weighted Euclidean distance, specifically using the following formula: ,in This represents the predicted value of the i-th performance metric in the first performance prediction data; This represents the target value of the i-th performance metric in the target performance set; This represents the preset weighting coefficient of the i-th performance indicator, used to reflect its relative importance in the comprehensive evaluation; This represents the total number of performance metrics. Specifically, the weighting coefficients are set according to the specific constraints and optimization priorities of each performance metric based on the target communication protocol. For example, in the application of the PCIExpress protocol, the bit error rate metric has the highest constraint priority and can be assigned a weighting coefficient of 0.5; the eye diagram height metric involves signal amplitude integrity and can be assigned a weighting coefficient of 0.3; the eye diagram width metric involves timing tolerance and can be assigned a weighting coefficient of 0.2.

[0047] The fitness score measures the degree of closeness between the predicted performance and the target performance. The higher the fitness score, the smaller the overall deviation between the predicted performance and the target performance, that is, the better the matching degree, indicating that the performance predicted by the current combination of first parameters is closer to the expected ideal working state.

[0048] Secondly, based on the calculated first fitness score, the current first parameter combination is adjusted to generate a new second parameter combination.

[0049] Specifically, based on the first fitness score, the first parameter combination is adjusted to obtain a second parameter combination, including: Based on the first fitness score, adjust the step size of the configuration parameters; The parameter adjustment step size is used to adjust the parameter values ​​in the first parameter combination to obtain the second parameter combination.

[0050] First, the parameter adjustment step size is configured based on the first fitness score. The core of this step is to establish a mapping relationship between the fitness score and the parameter adjustment range. Specifically, a lower fitness score indicates that the predictive performance of the current parameter combination deviates significantly from the target performance. In this case, a larger parameter adjustment step size can be used to explore more extensively within the configurable parameter space and accelerate the search speed. Conversely, a higher fitness score indicates that the target region is approaching. In this case, a smaller parameter adjustment step size should be used to achieve fine-tuning of the parameters and avoid oscillations near the optimal solution. Parameter adjustment step size = base step size × (score decay base)^(-first fitness score). Wherein, the base step size is the initial adjustment range preset according to the physical adjustment range and accuracy requirements of each configured parameter of the SerDes IP core. For example, for a pre-emphasis coefficient in units of levels, the base step size can be set to 2. The score decay base is a decay constant that controls the rate of change of the step size with the fitness score. It is set according to the balance requirements of global exploration and local optimization in the optimization process. For example, it can be set to 0.9.

[0051] Secondly, the specific parameter values ​​in the first parameter combination are adjusted using the configured parameter adjustment step size. Specifically, the adjustment operation is performed according to the rules of the selected optimization algorithm. For example, when using stochastic gradient descent, the adjustment direction is determined by the performance gradient direction output by the performance prediction model, and each parameter value moves a distance determined by the step size along the negative gradient direction. After this adjustment process, each configured parameter in the first parameter combination, such as the transmitter pre-emphasis coefficient or the receiver equalizer gain, updates its value according to its corresponding rules and step size, ultimately forming a new and different parameter combination, namely the second parameter combination. This second parameter combination is used for performance prediction and evaluation in the next iteration, thereby driving the optimization process to continue.

[0052] Finally, the evaluation, scoring, and adjustment process is repeated iteratively for optimization. In each iteration, a new combination is generated and evaluated, using the parameter combination from the previous iteration as the starting point, continuously updating the currently found optimal parameter combination. The iterative process continues until a preset convergence condition is met, such as the improvement in the highest fitness score being less than 1% for ten consecutive iterations, or the total number of iterations reaching the preset maximum of 1000 iterations. When the convergence condition is met, the parameter combination with the highest fitness score recorded during the iteration process is determined as the optimal parameter combination.

[0053] S40: Reconfigure the SerDes IP core using the optimal parameter combination and perform verification tests.

[0054] Finally, the SerDes IP core is reconfigured using the optimal parameter combination, and verification tests are performed, including: The SerDes IP core is reconfigured using the optimal parameter combination described above; Based on the updated SerDes IP core, the test operation was re-executed, and performance parameters were collected and verified. The verification performance parameters are compared with the target performance. If the comparison result meets the preset verification conditions, the optimization is deemed successful.

[0055] First, a reconfiguration operation is performed, writing the optimized parameter combination into the corresponding configuration register of the SerDes IP core to update its internal operating parameters and complete the hardware operating state switch. Second, based on the reconfigured SerDes IP core, the same test operations as the initial test are re-executed, i.e., injecting a standard test data stream into the SerDes IP core and collecting actual verification performance parameters during data stream processing. The types of verification performance parameters collected are consistent with those in the initial test phase, including at least eye diagram feature parameters, bit error rate parameters, and jitter parameters.

[0056] Then, the collected verification performance parameters are compared and analyzed with the preset target performance. Specifically, a specific standard for successful comparison is defined through preset verification conditions, such as requiring all verification performance parameter values ​​to be better than or equal to the target performance value. If the comparison result meets the preset verification conditions, it is determined that the parameter optimization for the current target communication protocol is successful, indicating that the optimal parameter combination can enable the SerDes IP core to achieve the expected performance target in actual operation.

[0057] Furthermore, reconfiguring the SerDes IP core using the optimal parameter combination and performing verification tests also includes: If the comparison result does not meet the preset verification conditions, the verification performance parameters are added to the abnormal diagnosis result, and the root cause localization information is updated. Based on the updated root cause localization information, the configurable parameter space of the SerDes IP core is constrained; Within the constrained configurable parameter space, the optimization algorithm is retried to search for a new optimal parameter combination. The SerDes IP core is reconfigured using the new optimal parameter combination, and verification tests are performed.

[0058] If the comparison results do not meet the preset verification conditions, the following extended steps are performed to complete the closed-loop optimization. First, the collected verification performance parameters are integrated into the existing anomaly diagnosis results. By analyzing the relationship between the verification performance parameters and the main contributing performance parameters, the root cause localization information is updated and corrected, thereby forming a more accurate fault or performance bottleneck indication.

[0059] Secondly, based on the updated root cause localization information, constraints are imposed on the configurable parameter space of the SerDes IP core. This constraint operation aims to narrow the search scope, focusing on a subset of parameters or specific numerical ranges related to the identified root causes. For example, if the root cause localization information indicates that the anomaly is mainly caused by insufficient equalization at the receiver, the optimization search can be mainly constrained within the range of equalizer-related parameters, while relaxing or fixing the values ​​of other non-critical parameters. Then, within the new configurable parameter space, the optimization algorithm is re-triggered to search for parameters. Because the configurable parameter space is significantly reduced and more targeted, the optimization algorithm can explore more efficiently, thereby obtaining a parameter combination that is better evaluated under the new constraints—the new optimal parameter combination.

[0060] Finally, using the obtained new optimal parameter combination, the SerDes IP core is reconfigured and verified again, forming a feedback loop of diagnosis and re-optimization until the verification test results meet the preset verification conditions, thereby ensuring that the final parameter configuration can reliably achieve the target performance in actual hardware testing.

[0061] In summary, the embodiments of this application have at least the following technical effects: Compared to existing technologies, this application first overcomes the limitations of traditional fixed testing modes in flexibly adapting to different protocols by dynamically configuring and collecting multi-dimensional performance parameters based on the target protocol. By constructing and applying an unsupervised performance analysis model, it achieves quantitative analysis of the intrinsic correlations between complex performance parameters and automatic location of anomaly root causes, solving the problems of low efficiency and insufficient accuracy of manual experience-based diagnosis. Furthermore, by introducing a machine learning-based performance prediction model and adaptive optimization algorithm, it intelligently searches for the optimal configuration combination, improving the efficiency and accuracy of parameter tuning and avoiding blind trial and error. Finally, by designing a closed-loop process including reconfiguration, experimental verification, and feedback iteration, it ensures the reliability and effectiveness of the optimization results on actual hardware, forming a complete automated link from test diagnosis to parameter optimization.

[0062] In summary, this application achieves efficient and accurate performance evaluation and parameter optimization of SerDes IP cores.

[0063] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0064] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0065] This specification and accompanying drawings are merely illustrative examples of this application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Therefore, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. An implementation method for a multi-protocol SerDes universal test chip architecture, characterized in that, The method includes: Based on the target communication protocol, the working mode of the SerDes IP core is dynamically configured, and test operations are performed to collect multiple performance parameters of the SerDes IP core during the test process. The performance analysis model is invoked to perform correlation analysis on the multiple performance parameters, and based on the deviation between the correlation analysis results and the preset benchmark, an abnormal diagnosis result containing root cause localization information is generated. Based on the target performance, an optimization algorithm is used to search within the configurable parameter space of the SerDes IP core to obtain the optimal parameter combination; The SerDes IP core is reconfigured using the optimal parameter combination, and verification tests are performed.

2. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 1, characterized in that, Based on the target communication protocol, the operating mode of the SerDes IP core is dynamically configured, and test operations are performed to collect multiple performance parameters of the SerDes IP core during the test process, including: Based on the target communication protocol, determine the configuration parameters of the SerDes IP core; Write the configuration parameters into the SerDes IP core to set the working mode of the SerDes IP core; Inject test data streams into the configured SerDes IP core; During the processing of the test data stream by the SerDes IP core, multiple performance parameters are collected, including at least eye diagram feature parameters, bit error rate, and jitter parameters.

3. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 1, characterized in that, The performance analysis model is invoked to perform a correlation analysis on the multiple performance parameters, including: The multiple performance parameters are input into the performance analysis model constructed based on an unsupervised learning algorithm; The performance analysis model is used to analyze the inherent correlation characteristics among the multiple performance parameters and obtain the correlation analysis results.

4. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 3, characterized in that, The configuration steps for the performance analysis model include: Multiple sets of historical performance parameters of the SerDes IP core under normal test conditions were collected to form a training dataset; Based on the unsupervised learning algorithm, the model is trained using the training dataset to mine the inherent correlation patterns of the multiple sets of historical performance parameters under normal conditions, and obtain the performance analysis model.

5. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 1, characterized in that, Based on the deviation between the correlation analysis results and the preset benchmark, abnormal diagnostic results containing root cause localization information are generated, including: Based on the correlation analysis results, the comprehensive deviation between the correlation analysis results and the preset benchmark is calculated; When the overall deviation exceeds a preset deviation threshold, an anomaly is determined. Analyze the contribution of each of the multiple performance parameters to the overall deviation. Based on the contribution value, the main contribution performance parameters are determined, root cause localization information containing at least one main contribution performance parameter is generated, and anomaly diagnosis results are obtained.

6. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 1, characterized in that, Based on the target performance, an optimization algorithm is used to search within the configurable parameter space of the SerDes IP core to obtain the optimal parameter combination, including: A first parameter combination is randomly generated within the configurable parameter space; Invoke the performance prediction model, input the first parameter combination into the performance prediction model, and predict the first performance prediction data of the first parameter combination; Calculate the first fitness score between the first performance prediction data and the target performance; Based on the first fitness score, the first parameter combination is adjusted to obtain the second parameter combination; Perform iterative optimization until convergence to obtain the optimal parameter combination.

7. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 6, characterized in that, The configuration steps for the performance prediction model include: Collect the sample configuration parameter set and the corresponding sample measured performance dataset; The performance prediction model is constructed based on machine learning; The performance prediction model is trained in a supervised manner using the sample configuration parameter set as input data and the sample measured performance dataset as supervised data. Training is completed after the performance prediction model meets the prediction accuracy requirements, and the performance prediction model is obtained.

8. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 6, characterized in that, Based on the first fitness score, the first parameter combination is adjusted to obtain a second parameter combination, including: Based on the first fitness score, adjust the step size of the configuration parameters; The parameter adjustment step size is used to adjust the parameter values ​​in the first parameter combination to obtain the second parameter combination.

9. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 1, characterized in that, The SerDes IP core is reconfigured using the optimal parameter combination, and verification tests are performed, including: The SerDes IP core is reconfigured using the optimal parameter combination described above; Based on the updated SerDes IP core, the test operation was re-executed, and performance parameters were collected and verified. The verification performance parameters are compared with the target performance. If the comparison result meets the preset verification conditions, the optimization is deemed successful.

10. The implementation method of a multi-protocol SerDes universal test chip architecture according to claim 9, characterized in that, The process of reconfiguring the SerDes IP core using the optimal parameter combination and performing verification tests also includes: If the comparison result does not meet the preset verification conditions, the verification performance parameters are added to the abnormal diagnosis result, and the root cause localization information is updated. Based on the updated root cause localization information, the configurable parameter space of the SerDes IP core is constrained; Within the constrained configurable parameter space, the optimization algorithm is retried to search for a new optimal parameter combination. The SerDes IP core is reconfigured using the new optimal parameter combination, and verification tests are performed.

Images