3D memory device and preparation process thereof

Abstract

This application relates to the field of semiconductor memory device technology, and discloses a 3D memory device and its fabrication process. The 3D memory device includes a substrate, a multilayer stacked structure, a contact lead-out structure, a via, a resistive switching functional layer, and a top electrode. The multilayer stacked structure includes multiple alternating layers of two-dimensional conductive material and multiple layers of insulating dielectric material arranged in a vertical direction. The two-dimensional conductive material layers serve as interlayer contact electrodes or memory cell electrodes. The via penetrates at least a portion of the multilayer stacked structure and exposes the edge regions of the two-dimensional conductive material layers. The resistive switching functional layer is disposed on the inner wall and / or inside the via and contacts the edge regions of the two-dimensional conductive material layers. The top electrode is electrically connected to the resistive switching functional layer. This structure utilizes the two-dimensional conductive material layers to reduce the vertical thickness of the interlayer electrodes and forms multiple resistive switching memory cells on the sidewalls of the vias, thereby increasing the storage density of the 3D memory device.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory device technology, specifically a 3D memory device and its fabrication process. Background Technology

[0002] Resistive switching memory (RSM) is a type of non-volatile memory device based on the reversible transition between high-resistivity and low-resistivity states of resistive switching materials under an applied electric field. These devices are characterized by relatively simple structure, good miniaturization, fast read / write speeds, and data retention after power loss, thus being considered a key candidate technology for high-density non-volatile memory and storage-class memory. As the demands for storage capacity, access speed, and energy efficiency continue to increase in artificial intelligence computing, server data centers, and high-performance computing systems, memory devices need to integrate more storage cells within a limited chip area while maintaining low manufacturing costs.

[0003] In traditional two-dimensional planar structures, memory cells are mainly arranged along the substrate surface. As device feature sizes shrink to a certain extent, further improvements in memory density through planar size reduction become limited by factors such as lithography precision, linewidth control, parasitic effects, and process costs. To further increase memory capacity per unit area, vertical 3D memory structures are gaining attention. These structures increase memory capacity without significantly increasing the chip's planar area by stacking multiple memory layers vertically and utilizing through-holes to form vertical memory channels.

[0004] For vertical 3D resistive switching memory devices, the number of stackable layers is closely related to the via etching capability and the thickness of a single layer. Vias typically need to penetrate multiple conductive and dielectric layers, and the etching depth is limited by aspect ratio, mask selectivity, and the ability to control sidewall morphology. With a fixed via diameter, the deeper the via, the more difficult the etching becomes, and the harder it is to control sidewall perpendicularity and the quality of the via opening. Therefore, with a limited total etching height, a larger thickness for a single memory layer reduces the number of memory layers that can be integrated.

[0005] In existing vertical 3D resistive switching memory devices, the interlayer conductive electrodes are typically made of metal thin films or metal compound thin films. While these electrodes offer good conductivity and process compatibility, they still occupy a certain thickness in the vertical direction. As the number of stacked layers increases, the proportion of the metal electrode thickness in the total stack height gradually increases, making it difficult to further reduce the spacing between individual layers. Even if the thickness of the isolation dielectric layer and the resistive switching functional layer has been reduced, the interlayer metal electrodes still limit the number of layers that can be integrated in the vertical direction, thus restricting further increases in the storage density of 3D memory devices.

[0006] Furthermore, a relatively large contact interface is typically formed between traditional metal electrodes and the resistive switching functional layer. During device setup and reset, oxygen ion migration and oxygen vacancy accumulation within the resistive switching functional layer occur at different locations within the interface, resulting in a degree of randomness in the formation and rupture of conductive channels. This phenomenon can easily lead to fluctuations in operating voltage between different memory cells and between different cycles of the same memory cell, affecting the consistency of resistive switching. For multilayer 3D arrays, as the number of memory cells increases, this dispersion of electrical parameters further impacts the array's read / write window and addressing reliability.

[0007] To reduce the thickness of interlayer electrodes, two-dimensional conductive materials with atomic or nanometer-scale thicknesses can be considered to replace traditional metal electrodes. However, the thinness of two-dimensional conductive materials limits the contact area between them and external metal interconnects or test terminals. Directly connecting external interconnect structures to the edges of the two-dimensional conductive material can easily lead to high interfacial contact resistance and cause edge damage during processing or probe contact. For multilayer stacked structures, it is also necessary to address how to independently lead out and stably address two-dimensional conductive material layers at different heights.

[0008] Therefore, it is necessary to provide a new 3D memory device structure and its fabrication method, which can reduce the vertical thickness of the interlayer electrodes, enable the two-dimensional conductive material layer to form effective contact with the resistive switching functional layer, and realize the independent connection of the multilayer electrodes through a reasonable contact lead-out structure, thereby improving the device storage density and the electrical stability of the multilayer array. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this application provides a 3D memory device and its fabrication process, which solves the problem that the interlayer electrode thickness is large and the number of vertically stacked layers is limited in existing vertical 3D resistive switching memory devices, making it difficult to further improve the storage density.

[0010] To achieve the above objectives, this application provides the following technical solution:

[0011] In a first aspect, this application provides a 3D storage device, which adopts the following technical solution: A 3D memory device includes a substrate, a multilayer stacked structure, contact lead-out structures, vias, a resistive switching functional layer, and a top electrode. The multilayer stacked structure is disposed on the substrate, and includes multiple layers of two-dimensional conductive material and multiple layers of insulating dielectric layers, which are arranged alternately in a vertical direction. The two-dimensional conductive material layers are used to form interlayer contact electrodes or memory cell electrodes at different heights, and the insulating dielectric layers are used to isolate adjacent two-dimensional conductive material layers. The contact lead-out structures are electrically connected to the two-dimensional conductive material layers, allowing the two-dimensional conductive material layers at different heights to be connected to external circuits.

[0012] Through-holes are formed in a multi-layer stacked structure, exposing the edge region of at least one two-dimensional conductive material layer. A resistive switching functional layer is disposed on the inner wall or inside the through-hole and contacts the edge region of the two-dimensional conductive material layer. The top electrode is electrically connected to the resistive switching functional layer. Thus, at different height positions of the through-hole, the two-dimensional conductive material layer, the resistive switching functional layer, and the top electrode together form multiple resistive switching memory cells.

[0013] By adopting the above technical solution, a two-dimensional conductive material layer replaces conventional thick metal electrodes as interlayer contact electrodes or memory cell electrodes. The thickness of the two-dimensional conductive material layer in the vertical direction can reach the nanometer or atomic level, thus reducing the vertical space occupied by a single memory layer. For vertical 3D memory devices, the via etching depth is usually limited by etching equipment, mask selectivity, and aspect ratio capabilities. With the same total etching depth, reducing the thickness of the interlayer conductive electrode allows for the arrangement of more memory layers within the same vertical height, thereby increasing storage density and reducing the manufacturing cost per bit.

[0014] Simultaneously, the via allows the edge region of the two-dimensional conductive material layer to contact the resistive switching functional layer. Compared to conventional planar contact structures, the contact area formed by the two-dimensional conductive material layer at the sidewall of the via is thinner, making it easier for the electric field distribution in the resistive switching functional layer to concentrate near this edge region. During device writing, oxygen ion migration and oxygen vacancy aggregation in the resistive switching material preferentially occur in this local region, restricting the formation location of conductive channels and thus reducing the probability of multiple conductive channels randomly competing for formation in a large-area interface. During device erasure, oxygen ions migrate back and recombine with oxygen vacancies, breaking the conductive channel and restoring the memory cell to a high-resistivity state. This improves the consistency of the resistive switching position and reduces the dispersion of the operating voltage.

[0015] The two-dimensional conductive material layer can be selected from one or more of the following: monolayer graphene, few-layer graphene, carbon nanotube films, conductiveized molybdenum disulfide films, and conductiveized transition metal chalcogenide films. For molybdenum disulfide films and transition metal chalcogenide films, their intralayer carrier transport capability can be improved through doping, metallization, phase engineering, or composite treatment with conductive materials. The thickness of the two-dimensional conductive material layer can range from 0.3 nm to 20 nm. Using this thickness range, the two-dimensional conductive material layer can balance conductivity and vertical thinning effect.

[0016] The isolation dielectric layer can be selected from one or more of the following: silicon oxide layer, silicon nitride layer, aluminum oxide layer, silicon oxynitride layer, and low dielectric constant dielectric layer. The thickness of the isolation dielectric layer can be from 10 nm to 500 nm. This thickness range can provide electrical isolation between adjacent two-dimensional conductive material layers while still allowing the via etching process to be implemented. The substrate can be an insulating substrate, a semiconductor substrate, or a semiconductor substrate with an insulating layer on its surface. In one embodiment, the substrate is a SiO2 substrate or a silicon substrate with a SiO2 layer on its surface.

[0017] The contact lead-out structure can employ one or more of the following: a contact metal layer, a lateral extension region, a local opening, a contact hole, a metal plug, or a stepped structure. The contact metal layer can be disposed at the edge region of the two-dimensional conductive material layer, allowing the atomically or nanometer-thick two-dimensional conductive material layer to connect with the external interconnect structure through a larger metal contact area. This structure can reduce the contact resistance between the two-dimensional conductive material layer and the external interconnect structure, and reduce localized damage caused by external probes or interconnect metals directly acting on the edge of the two-dimensional conductive material layer. The contact metal layer can be selected from one or more of Pd, Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Co, TiN, TaN, WN, basic conductive materials, TiON, TaON, and AlON, with a thickness ranging from 1 nm to 10 nm.

[0018] In one embodiment, the contact metal layers of different layers are staggered in the vertical projection direction to form stepped contact leads. This structure allows two-dimensional conductive material layers at different heights to be exposed and independently connected to external circuits. Compared to structures that directly expose the edges of the two-dimensional conductive material layers, stepped contact leads can increase the contact area and improve the addressing reliability of electrodes in each layer of the array.

[0019] The resistive switching functional layer can be made of a metal oxide material that can undergo a reversible resistance change under an applied electric field. Specific materials include HfO2, SiO2, TiO2, ZrO2, Al2O3, WO3, and TaO. x One or more of the following materials can be used: Ta2O5, NbOx, VOx, HfSiO, HfTaO, HfZrO, and HfAlO. These materials can also form a stack, a mixed layer, or a composite structure consisting of an oxygen-deficient layer and an oxygen-rich layer. When the resistive switching functional layer is a single-layer structure, its thickness can be 1 nm to 20 nm; when the resistive switching functional layer is a multilayer composite structure, the thickness of each sublayer can be 1 nm to 20 nm.

[0020] By employing the aforementioned resistive switching functional layer, the device can achieve switching between high-resistivity and low-resistivity states based on mechanisms such as oxygen vacancy migration, conductive channel formation and breakage, and interface barrier modulation. When the resistive switching functional layer is disposed on the inner wall of the via, it forms contact interfaces with the edge regions of each two-dimensional conductive material layer, thereby forming multiple vertically distributed memory cells within the same via structure. This structure helps reduce planar area occupation and increases the number of memory cells integrated in the vertical direction.

[0021] In one embodiment, the resistive switching functional layer includes TaO. x An oxygen-deficient layer and a Ta₂O₅ oxygen-rich layer. The Ta₂O₅ oxygen-rich layer is used to provide the active region for the resistive switch, while the TaO₂O₅ oxygen-rich layer... x The oxygen-deficient layer provides an oxygen vacancy regulation region. During device setup, some oxygen ions in the Ta₂O₅ oxygen-rich layer migrate under the influence of an electric field, forming continuous or quasi-continuous oxygen vacancy channels within the active region, causing the memory cell to transition from a high-resistivity state to a low-resistivity state. During device reset, oxygen ions migrate back to the oxygen vacancy channel region and recombine, breaking the conductive channel and causing the memory cell to transition from a low-resistivity state to a high-resistivity state. TaO x The anoxic layer can buffer the migration range of oxygen ions and reduce the probability of irreversible diffusion of oxygen ions into the surrounding medium or electrode interface, thereby improving the resistance switching stability after multiple cycles.

[0022] The top electrode can be selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Co, TiN, TaN, WN, conductive-treated AlN, TiON, TaON, and AlON. The top electrode can cover the surface of the resistive switching layer or fill the via. When the top electrode fills the via, the conductive path in the via is more continuous, which helps reduce the series resistance introduced by the top electrode itself. When the top electrode covers the surface of the resistive switching layer, an electrode structure extending vertically can be formed on the sidewall of the via, forming multiple memory cells with two-dimensional conductive material layers of different heights.

[0023] Vias can penetrate the entire multilayer stacked structure or only a portion of it. When a via penetrates the entire multilayer stacked structure, the edge regions of multiple two-dimensional conductive material layers can be exposed simultaneously in a single etching process. When a via penetrates only a portion of the multilayer stacked structure, it is suitable for segmented stacking, local addressing, or multi-level array structures. Vias can stop at the bottom electrode layer, bottom insulating layer, etch stop layer, or pre-defined support layer. Edge contacts, local sidewall contacts, local surface contacts, or combinations thereof can be formed between the two-dimensional conductive material layer and the resistive switching functional layer. When the two-dimensional conductive material layer is a single layer of graphene, a single-atom-layer edge contact structure can be formed at the sidewall of the via, which can further enhance the local electric field effect.

[0024] The number of two-dimensional conductive material layers in a multilayer stacked structure can be two or more, and can be expanded to 4, 8, 16, 32, 64, 128 or more layers depending on storage capacity requirements. By repeatedly forming two-dimensional conductive material layers, contact lead-out structures and isolation dielectric layers, storage structures with tens or hundreds of stacked layers can be obtained. This type of storage device has non-volatile storage characteristics, retaining data even after power loss. Its read / write performance and manufacturing cost are between DRAM and NAND flash memory, making it suitable for storage-class memory. This device is suitable for artificial intelligence model training and inference, server data centers, high-performance computing, real-time database processing, and enterprise-level storage systems.

[0025] Secondly, this application provides a method for fabricating a 3D storage device, employing the following technical solution: A method for fabricating a 3D storage device includes the following steps: Provide substrate; A multilayer stacked structure is obtained by alternately forming two-dimensional conductive material layers and isolation dielectric layers on a substrate. A contact lead-out structure is formed in a predetermined area of ​​the two-dimensional conductive material layer, enabling the two-dimensional conductive material layer to be electrically connected to an external circuit. Etching is performed on the multilayer stacked structure to form vias, and the vias expose the edge regions of at least one two-dimensional conductive material layer; A resistive switching functional layer is formed inside the through hole, so that the resistive switching functional layer is in contact with the edge region of the two-dimensional conductive material layer. The upper electrode is formed and electrically connected to the resistive switching functional layer.

[0026] By employing the above technical solution, two-dimensional conductive material layers and isolation dielectric layers are first formed alternately along the vertical direction, and then the two-dimensional conductive material layers at different heights are simultaneously exposed through a via etching process. Compared with the method of processing memory cells layer by layer, this method can define multiple vertically distributed memory cells using the same via, reducing the difficulty of pattern alignment in multilayer structures. After the via is formed, the resistive switching functional layer is deposited along the inner wall of the via and contacts the edge regions of each two-dimensional conductive material layer. The upper electrode is then connected to the resistive switching functional layer, thereby forming multiple resistive switching memory cells at different heights of the via.

[0027] Two-dimensional conductive material layers can be formed using one or more of the following methods: chemical vapor deposition (CVD), physical vapor deposition (PVD), transfer processes, coating processes, spraying processes, and spin coating processes. Isolation dielectric layers can be formed using one or more of the following methods: plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). Resistive switching functional layers can be formed using one or more of the following methods: atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), reactive sputtering, and plasma-enhanced deposition (PED). The upper electrode and contact lead-out structures can be formed using one or more of the following methods: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, and electroless plating.

[0028] By employing the above film formation methods, appropriate processes can be selected based on different materials. For via structures with large aspect ratios, atomic layer deposition (ALD) can improve the uniformity of resistive switching layer coverage at the via sidewalls by relying on surface self-limiting reactions. For metal electrodes and contact metal layers, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, or electroless plating processes can form continuous conductive layers that are compatible with subsequent interconnection processes.

[0029] In one embodiment, the two-dimensional conductive material layer is a single-layer graphene or few-layer graphene. When forming the graphene layer, graphene can first be grown on a metal catalytic substrate using chemical vapor deposition, then a polymer support layer can be formed on the graphene surface. The graphene with the polymer support layer is then peeled off from the metal catalytic substrate and transferred to the target surface, and finally the polymer support layer is removed. The metal catalytic substrate can be a platinum sheet or copper foil, the polymer support layer can be a polymethyl methacrylate layer, and the peeling method can be electrolytic bubbling peeling.

[0030] By employing the above-described graphene formation method, graphene films with relatively small thickness and good continuity can be obtained. During the electrolytic bubble exfoliation process, the metal catalytic substrate acts as the cathode. Water in the electrolyte is reduced at the cathode surface, generating hydrogen gas. This hydrogen gas gradually forms bubbles between the graphene and the metal catalytic substrate, thereby promoting the separation of the graphene from the substrate. This method does not require complete dissolution of the metal catalytic substrate, reducing residual metal ions and minimizing chemical damage to the graphene film during exfoliation.

[0031] In one embodiment, the multilayer stacked structure includes alternating graphene layers and SiO2 insulating dielectric layers. After forming each graphene layer, a contact metal layer is formed at its edge region, and the contact metal layers of different layers are staggered in the vertical projection direction. Subsequently, a SiO2 insulating dielectric layer is formed, and the process of forming the next graphene layer, contact metal layer, and SiO2 insulating dielectric layer is repeated. After completing the predetermined number of layers, vias are formed by dry etching, penetrating the SiO2 insulating dielectric layer and the graphene layer. TaO is then sequentially formed within the vias. xAn oxygen-deficient layer and a Ta₂O₅ oxygen-rich layer are formed, and then a Pt top electrode is formed. After the film covering the contact metal layer is removed, the contact metal layers at different heights are exposed, forming a stepped contact lead-out terminal.

[0032] By employing the above preparation method, contact lead-out structures for each two-dimensional conductive material layer can be pre-formed during the multilayer stacking process, avoiding direct contact processing of single-atom-layer or nanometer-thick two-dimensional conductive material layers after the deep structure is completed. After dry etching to form vias, the graphene layer forms edge-exposed regions on the sidewalls of the vias. TaO x After the oxygen-deficient layer and the Ta2O5 oxygen-rich layer are formed in the through-hole, they can contact the exposed area at the edge, forming a resistive switching memory cell with the graphene edge as the local electrode interface.

[0033] In one embodiment, the SiO2 insulating dielectric layer can be formed by plasma-enhanced chemical vapor deposition. The reactant gases may include SiH4 and N2O, with SiH4 flow rate ranging from 10 sccm to 50 sccm, N2O flow rate ranging from 100 sccm to 500 sccm, RF power ranging from 20 W to 100 W, reaction chamber pressure ranging from 50 Pa to 200 Pa, and substrate temperature ranging from 200°C to 350°C. Forming the SiO2 insulating dielectric layer under these conditions allows for obtaining a dielectric film layer that meets interlayer insulation requirements at a lower temperature, reducing the impact of high-temperature processes on the underlying two-dimensional conductive material layer.

[0034] In one embodiment, the vias can be formed using inductively coupled plasma reactive ion etching (ICP-IR). For the SiO2 insulating dielectric layer, a fluorine-containing gas system can be used for etching, which may include CF4, CHF3, and Ar. For the graphene layer or carbon nanotube film, an oxygen plasma system can be used for etching, which may include O2 and Ar. By switching the etching gas system for different materials, the control over the via sidewall morphology can be improved, and the two-dimensional conductive material layer can form an edge region at the via sidewall that can contact the resistive switching functional layer.

[0035] In one embodiment, the Ta2O5 oxygen-rich layer can be formed using atomic layer deposition (ALD). The ALD precursor can be tantalum pentaethoxylate, the oxidant can be deionized water or ozone, and the deposition temperature can be 200°C to 300°C. The ALD process can form a continuous tantalum oxide film covering the sidewalls of the vias, enabling memory cells at different heights to achieve a more consistent resistive switching material thickness.

[0036] In one embodiment, when exposing the contact metal layer, dry etching can be used to remove a portion of the film layer above the contact metal layer. For TaO... xThe Ta2O5 and Ta2O5 layers can be etched using a chlorine-based gas system containing Cl2, BCl3, and Ar. The contact metal layer can serve as an etching stop or buffer structure, reducing further damage to the underlying two-dimensional conductive material layer during the etching process. In this way, stepped contact leads that can be used for external connections can be obtained after forming the through-hole resistive switching structure.

[0037] This application provides a 3D storage device and its fabrication process. It has the following beneficial effects: 1. This application employs a two-dimensional conductive material layer as the interlayer contact electrode or memory cell electrode in a multilayer stacked structure, and alternates between the two-dimensional conductive material layer and the isolation dielectric layer in the vertical direction. Because the two-dimensional conductive material layer has a small vertical thickness, it can reduce the amount of single-layer stack thickness occupied by the interlayer electrodes. Under conditions where the via etching depth is limited, this structure is advantageous for arranging more memory layers within the same vertical height, thereby increasing the storage density of 3D memory devices.

[0038] 2. This application exposes the edge region of the two-dimensional conductive material layer through vias, and makes the resistive switching functional layer contact this edge region. During device operation, the edge contact region of the two-dimensional conductive material layer allows the electric field distribution in the resistive switching functional layer to concentrate in a localized area, which is beneficial for the formation of oxygen vacancies and the establishment of conductive channels. Compared with large-area planar contact structures, this structure can reduce the probability of random formation of conductive channels, thereby improving the consistency of resistive switching.

[0039] 3. This application provides contact lead-out structures at each layer of two-dimensional conductive material, and allows for independent lead-out of electrode layers of different heights through contact metal layers, stepped contact leads, contact holes, or metal plugs. This structure can reduce the contact resistance between the two-dimensional conductive material layer and the external interconnect structure, and reduce damage caused by direct contact with the edges of the two-dimensional conductive material, which is beneficial to improving the addressing reliability of multilayer memory arrays. Attached Figure Description

[0040] Figure 1 This is a diagram of the 3D storage film material and device structure provided in the embodiments of this application; Figure 2 A flowchart of the preparation method provided in the embodiments of this application; Figure 3 Comparison of basic resistive switching characteristic test results of 3D memory devices prepared based on different embodiments of this application; Figure 4 The statistical distribution of operating voltages of Example 1 and the two comparative devices in Test Example 2 provided for the embodiments of this application during the initial activation and subsequent cycling process; Figure 5The resistance evolution curve of the device in Test Example 3 provided in the embodiments of this application for high-frequency pulse cycle endurance test; Figure 6 A comparison chart of contact resistance and array operating yield of the three-dimensional storage device contact leads in Test Example 4 provided in the embodiments of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] For ease of explanation, the following description will first focus on the device structure of this application, outlining each functional layer and its optional materials. The materials, thicknesses, and process parameters listed in the subsequent specific fabrication examples and embodiments are intended to illustrate some preferred implementations of this application and do not imply that this application can only employ the corresponding specific combinations.

[0043] The 3D memory device of this application typically includes a substrate, a multilayer stacked structure disposed on the substrate, a via penetrating at least a portion of the multilayer stacked structure, a resistive switching functional layer disposed within the via, and an upper electrode electrically connected to the resistive switching functional layer.

[0044] The substrate can be an insulating substrate, a semiconductor substrate, or a semiconductor substrate with an insulating layer on its surface that can support a multilayer stacked structure and is compatible with semiconductor processes. Preferably, the substrate is a SiO2 substrate or a silicon substrate with a SiO2 layer formed on its surface.

[0045] The multilayer stacked structure includes alternating two-dimensional conductive material layers and insulating dielectric layers arranged vertically. The two-dimensional conductive material layers serve as interlayer contact electrodes or memory cell electrodes, while the insulating dielectric layers provide electrical isolation between adjacent two-dimensional conductive material layers. After a via penetrates at least a portion of the two-dimensional conductive material layers, an edge region of the two-dimensional conductive material layer is exposed at the via sidewall, allowing this edge region to contact the resistive switching functional layer, thereby forming multiple resistive switching memory cells at different height positions.

[0046] The two-dimensional conductive material layer can be a conductive thin film with nanometer-scale thickness capable of transporting charge carriers within the layer. For example, the two-dimensional conductive material layer can be monolayer graphene, few-layer graphene, carbon nanotube thin film, conductiveized molybdenum disulfide thin film, conductiveized transition metal chalcogenide thin film, or a combination thereof. The conductive treatment can be doping, metallization, phase engineering, or composite treatment with a conductive material. Preferably, the thickness of the two-dimensional conductive material layer is from a single atomic layer to 20 nm, more preferably 0.3 nm to 10 nm. Because the thickness of the two-dimensional conductive material layer is much smaller than that of conventional metal electrode layers, the single-layer stacking thickness of the device in the vertical direction can be reduced, increasing the number of stackable layers under the same via etching depth limitation.

[0047] The insulating dielectric layer can be selected from dielectric materials capable of providing electrical isolation between adjacent two-dimensional conductive material layers. For example, the insulating dielectric layer can be a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, a low-dielectric-constant dielectric layer, or a combination thereof. Preferably, the insulating dielectric layer is a SiO2 layer. The thickness of the insulating dielectric layer can be selected according to the interlayer insulation requirements and via etching capability, for example, from 10 nm to 500 nm.

[0048] Each two-dimensional conductive material layer can be connected to an external circuit via a contact metal layer or other contact lead-out structures. The contact metal layer can be disposed in the edge region of the two-dimensional conductive material layer to reduce the contact resistance between the two-dimensional conductive material layer and the external interconnect structure. The contact metal layer can be selected from metals, metal nitrides, metal oxynitrides, conductive carbon materials, or combinations thereof. For example, the contact metal layer may include one or more of Pd, Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Co, TiN, TaN, WN, AlN, TiON, TaON, and AlON. The thickness of the contact metal layer is preferably 1 nm to 10 nm.

[0049] In a preferred structure, the contact metal layers of different heights are staggered in vertical projection, forming stepped contact leads. This structure exposes contact metal layers at different heights, facilitating independent addressing of each two-dimensional conductive material layer. In other implementations, each two-dimensional conductive material layer can be electrically connected through lateral extension areas, partial openings, contact holes, metal plugs, stepped steps, or combinations thereof. Any contact lead structure in this application can be used as long as it allows the two-dimensional conductive material layers at different heights to be connected to external circuits.

[0050] A resistive switching layer is disposed on the inner wall and / or inside the via, and in contact with the two-dimensional conductive material layer exposed on the sidewall of the via. The resistive switching layer can be made of a resistive switching material capable of undergoing a reversible resistance change under an applied electric field. For example, the resistive switching layer may include HfO2, SiO2, TiO2, ZrO2, Al2O3, WO3, TaO2, etc. x The resistive switching material can be one or more of the following: Ta₂O₅, NbO₂, VO₂, HfSiO, HfTaO, HfZrO, and HfAlO. It can also be a stacked, mixed-layer, or oxygen-deficient / oxygen-rich composite structure formed from the above materials. The resistive switching functional layer can be a single-layer structure or a multi-layer composite structure; when the resistive switching functional layer is a single-layer structure, its thickness can be 1 nm to 20 nm; when the resistive switching functional layer is a multi-layer composite structure, the thickness of each sublayer can be 1 nm to 20 nm. The above-mentioned resistive switching materials can achieve reversible switching between high-resistivity and low-resistivity states through oxygen vacancy migration, the formation and breakage of conductive filaments, interfacial barrier modulation, or a combination thereof.

[0051] In a preferred structure, the resistive switching functional layer is a composite resistive switching functional layer, comprising an oxygen-deficient oxide layer disposed near the two-dimensional conductive material layer and an oxygen-rich oxide layer disposed near the upper electrode. The oxygen-deficient oxide layer can serve as an oxygen vacancy reservoir layer, and the oxygen-rich oxide layer can serve as the active layer of the resistive switch. More preferably, the oxygen-deficient oxide layer is TaO. x The oxygen-rich oxide layer is a Ta2O5 layer. By combining the oxygen-deficient oxide layer and the oxygen-rich oxide layer, the migration and recombination behavior of oxygen ions and oxygen vacancies can be adjusted during device setup and reset, thereby improving the stability of resistive switching.

[0052] The upper electrode is electrically connected to the resistive switching functional layer and can cover the surface of the resistive switching functional layer or fill the interior of the via. The upper electrode can be a metal, a metal nitride, a metal oxynitride, or a combination thereof. For example, the upper electrode may include one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Co, TiN, TaN, WN, conductive-treated AlN, TiON, TaON, and AlON. Preferably, the upper electrode is a Pt electrode.

[0053] Vias can penetrate the entire multilayer stacked structure and expose the substrate surface, or they can only penetrate part of the multilayer stacked structure, or stop at the bottom electrode layer, bottom insulating layer, etch stop layer, or other predetermined support layer. As long as the via can expose the edge region of at least one two-dimensional conductive material layer and make the resistive switching functional layer contact the edge region, a resistive switching memory cell can be formed at the corresponding height position.

[0054] Edge contacts, local sidewall contacts, local surface contacts, or combinations thereof can be formed between the two-dimensional conductive material layer and the resistive switching functional layer. Preferably, when the two-dimensional conductive material layer is a single-layer graphene, the single-layer graphene forms a single-atom-layer edge contact structure at the sidewall of the through-hole, thereby creating a strong electric field concentration effect in a local area, which is beneficial for reducing the ion migration barrier in the resistive switching material.

[0055] The number of two-dimensional conductive material layers in a multilayer stacked structure can be two or more, such as 2, 4, 8, 16, 32, 64, 128, or more layers. By repeatedly forming two-dimensional conductive material layers, contact metal layers, and insulating dielectric layers, 3D memory devices can be scaled up to tens or hundreds of layers. Because the two-dimensional conductive material layers have nanometer- or atomic-level thicknesses, more memory layers can be integrated within a limited vertical height compared to structures using conventional metal electrode layers, thereby increasing memory density.

[0056] In terms of fabrication processes, the two-dimensional conductive material layer can be formed through chemical vapor deposition, physical vapor deposition, transfer processes, coating processes, spraying processes, spin coating processes, or combinations thereof; the insulating dielectric layer can be formed through plasma-enhanced chemical vapor deposition, chemical vapor deposition, atomic layer deposition, physical vapor deposition, or combinations thereof; the resistive switching functional layer can be formed through atomic layer deposition, physical vapor deposition, chemical vapor deposition, reactive sputtering, plasma-enhanced deposition, or combinations thereof; the upper electrode and contact metal layers can be formed through physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, electroless plating, or combinations thereof. For through-hole structures with a large aspect ratio, atomic layer deposition is preferred for forming the resistive switching functional layer to improve the conformal coverage of the film layer at the through-hole sidewalls.

[0057] Based on the above device structure and material selection, several examples of the fabrication of two-dimensional conductive material layers are first given below. Then, the fabrication process and structural features of the 3D memory device of this application are illustrated with specific embodiments. The specific materials, parameters, and steps in each fabrication example and embodiment are used to illustrate the preferred embodiments of this application and do not exclude the use of other optional materials and processes to form the corresponding functional layers.

[0058] Preparation Examples 1-5: Preparation Example 1: This preparation example provides a method for preparing monolayer graphene, including the following steps: Platinum catalytic substrates were placed in a tube furnace of a chemical vapor deposition system. After evacuation, a mixture of hydrogen and argon was introduced and annealed at 1000°C. The system temperature was maintained at 1000°C, and methane gas with a flow rate of 10 sccm was introduced. The growth time was controlled at 20 min. After growth, the temperature was lowered to room temperature under a protective atmosphere to obtain platinum sheets with a single layer of graphene grown on the surface. A 3% polymethyl methacrylate solution was spin-coated onto the surface of a platinum sheet with a single layer of graphene. The sheet was then placed in a 0.5 mol / L sodium hydroxide aqueous solution, and a 3.5 V DC voltage was applied with the platinum sheet as the cathode for electrolytic bubbling peeling. The monolayer graphene with polymethyl methacrylate (PMMA) after peeling was transferred to the surface of the target substrate. The PMMA was removed by dissolving it with acetone solution, and the substrate was cleaned and dried with isopropanol to obtain a pure monolayer graphene film.

[0059] Preparation Example 2: This preparation example provides a method for preparing monolayer graphene, including the following steps: The copper foil catalytic substrate was placed in a tube furnace of a chemical vapor deposition system. After evacuation, a mixture of hydrogen and argon was introduced and annealed at 900°C. The system temperature was maintained at 900°C, and methane gas with a flow rate of 1 sccm was introduced. The growth time was controlled at 10 min. After the growth was completed, the temperature was lowered to room temperature under a protective atmosphere to obtain a copper foil with a single layer of graphene grown on its surface. A 2% polymethyl methacrylate solution was spin-coated onto the surface of a copper foil with a single layer of graphene. The foil was then placed in a 0.1 mol / L sodium hydroxide aqueous solution. A DC voltage of 2.0 V was applied with the copper foil as the cathode to perform electrolytic bubbling peeling. The monolayer graphene with polymethyl methacrylate (PMMA) after peeling was transferred to the surface of the target substrate. The PMMA was removed by dissolving it with acetone solution, and the substrate was cleaned and dried with isopropanol to obtain a pure monolayer graphene film.

[0060] Preparation Example 3: This preparation example provides a method for preparing monolayer graphene, including the following steps: Platinum catalytic substrates were placed in a tube furnace of a chemical vapor deposition system. After evacuation, a mixture of hydrogen and argon was introduced and annealed at 1050°C. The system temperature was kept at 1050℃, methane gas was introduced at a flow rate of 20 sccm, and the growth time was controlled at 30 min. After the growth was completed, the temperature was lowered to room temperature under a protective atmosphere to obtain a platinum sheet with a single layer of graphene grown on its surface. A 5% polymethyl methacrylate solution was spin-coated onto the surface of a platinum sheet with a single layer of graphene. The sheet was then placed in a 1.0 mol / L sodium hydroxide aqueous solution, and a 5.0 V DC voltage was applied with the platinum sheet as the cathode for electrolytic bubbling peeling. The monolayer graphene with polymethyl methacrylate (PMMA) after peeling was transferred to the surface of the target substrate. The PMMA was removed by dissolving it with acetone solution, and the substrate was cleaned and dried with isopropanol to obtain a pure monolayer graphene film.

[0061] Preparation Example 4: This preparation example provides a method for preparing molybdenum disulfide thin films, including the following steps: Molybdenum trioxide powder is placed in the central temperature zone of the tube furnace of the chemical vapor deposition system, sublimated sulfur powder is placed in the upstream low temperature zone of the tube furnace, and a cleaned silicon dioxide substrate is placed downstream of the molybdenum trioxide powder. Argon gas was introduced as a carrier gas, and the temperature of the central temperature zone was raised to 850°C and the temperature of the upstream low temperature zone was raised to 200°C. The reaction was held at this temperature for 15 minutes. After the reaction was completed, the mixture was naturally cooled to room temperature under the protection of argon gas to obtain a molybdenum disulfide film on the surface.

[0062] Preparation Example 5: This preparation example provides a method for preparing carbon nanotube thin films, including the following steps: A silica substrate was placed in a tube furnace of a chemical vapor deposition system, with ethylene as the carbon source gas, a mixture of ferrocene and thiophene as the catalyst precursor, and hydrogen and argon as the carrier gas. At a reaction temperature of 750℃, ethylene and the gasified catalyst precursor were continuously fed into a tube furnace and reacted for 20 min. After the reaction was completed, the mixture was naturally cooled to room temperature under a protective atmosphere to obtain a carbon nanotube film on the surface.

[0063] Examples 1-4: Example 1: See attached document Figure 1 and attached Figure 2 This embodiment provides a method for fabricating a 3D storage device, including the following steps: A cleaned silica substrate is provided, and four layers of two-dimensional conductive material and four layers of silica insulating dielectric are alternately formed on the silica substrate to form a multilayer alternating stacked structure, wherein the two-dimensional conductive material layer is the single layer of graphene obtained in Preparation Example 1. After forming each monolayer of graphene, a 5nm thick palladium metal contact layer is formed at its edge region using photolithography and physical vapor deposition. The contact metal layers are staggered in a stepped arrangement in vertical projection. Subsequently, a 100nm thick silicon dioxide isolation dielectric layer is deposited using plasma-enhanced chemical vapor deposition. The process parameters are: silane flow rate of 30sccm, nitrous oxide flow rate of 300sccm, RF power of 60W, reaction chamber pressure of 120Pa, and substrate temperature of 280℃. Inductively coupled plasma reactive ion etching is used to etch through the multilayer silicon dioxide isolation dielectric layer and the monolayer graphene, forming through-holes that expose the bottom silicon dioxide substrate. The silicon dioxide insulating dielectric layer is etched using a fluorine-based gas system, in which the flow ratio of carbon tetrafluoride, trifluoromethane and argon is 35:20:30 sccm. The monolayer graphene is etched using an oxygen plasma system, in which the flow ratio of oxygen and argon is 35:20 sccm. TaO with a thickness of 10 nm and an atomic ratio of x=1.5 was conformally deposited sequentially on the inner wall and bottom of the through-hole. x An oxygen-deficient layer and a 10 nm thick Ta₂O₅ oxygen-rich layer are used to form a composite resistive switching functional layer. TaO₂ is deposited using physical vapor deposition. x An oxygen-deficient layer was formed, followed by the deposition of a Ta2O5 oxygen-rich layer using atomic layer deposition (ALD) with tantalum pentaethoxy as the precursor, deionized water as the oxidant, and the deposition temperature controlled at 250°C. A patterned platinum top electrode was formed by filling the interior of the through-hole and above the composite resistive switching functional layer using physical vapor deposition. Dry etching was performed using a chlorine-based gas system containing chlorine, boron trichloride, and argon, with a flow rate ratio of 20:20:25 sccm. Each contact metal layer served as a natural etching stop layer. The Ta₂O₅ oxygen-rich layer and TaO₂ layer covering the contact metal layers were removed. x The oxygen-deficient layer fully exposes the surfaces of the contact metal layers, forming stepped contact leads.

[0064] Example 2: This example provides a method for fabricating a 3D storage device, including the following steps: A cleaned silica substrate is provided. Two two-dimensional conductive material layers and two silica isolation dielectric layers are alternately formed on the silica substrate to form a multi-layer alternating stacked structure. The two-dimensional conductive material layer is the monolayer graphene obtained in Preparation Example 2. After forming each monolayer graphene layer, a 1nm thick ruthenium metal is formed as a contact metal layer in its edge region by photolithography and physical vapor deposition. The contact metal layers are staggered in vertical projection and arranged in a stepped manner. Subsequently, a 10nm thick silica isolation dielectric layer is deposited by plasma-enhanced chemical vapor deposition. The process parameters are: silane flow rate of reaction gas is 10sccm, nitrous oxide flow rate is 100sccm, radio frequency power is 20W, reaction chamber pressure is 50Pa, and substrate temperature is 200℃. Inductively coupled plasma reactive ion etching (ICP-IR) was used to etch through multiple layers of silicon dioxide insulating dielectric and monolayer graphene, forming through-holes that exposed the bottom silicon dioxide substrate. A fluorine-based gas system was used for etching the silicon dioxide insulating dielectric, with a flow rate ratio of carbon tetrafluoride, trifluoromethane, and argon of 20:10:10 sccm. An oxygen plasma system was used for etching the monolayer graphene, with a flow rate ratio of oxygen to argon of 20:10 sccm. A 1 nm thick TaOx oxygen-deficient layer with an atomic ratio of x=1.0 and a 1 nm thick Ta2O5 oxygen-rich layer were conformally deposited sequentially on the inner wall and bottom of the through-hole to form a composite resistive switching functional layer. Atomic layer deposition (ALD) was then used to deposit TaOx. xThe oxygen-deficient layer and the Ta2O5 oxygen-rich layer were constructed using tantalum pentaethoxy as a precursor and ozone as an oxidant, with the deposition temperature controlled at 200℃. A patterned platinum top electrode with a thickness of 1 nm was formed inside the through-hole and above the composite resistive switching functional layer using physical vapor deposition. Dry etching was performed using a chlorine-based gas system containing chlorine, boron trichloride, and argon, with a flow rate ratio set to 10:10:10 sccm. Each contact metal layer served as a natural etching stop layer, and the Ta2O5 oxygen-rich layer and TaO covering the contact metal layers were removed. x The oxygen-deficient layer fully exposes the surfaces of the contact metal layers, forming stepped contact leads.

[0065] Example 3: This example provides a method for fabricating a 3D storage device, including the following steps: A cleaned silica substrate is provided. Eight layers of two-dimensional conductive material and eight layers of silica insulating dielectric layer are alternately formed on the silica substrate to form a multilayer alternating stacked structure. The two-dimensional conductive material layer is a conductive molybdenum disulfide thin film obtained in Preparation Example 4. The conductive treatment can be doping, metallization, or phase engineering to improve the intralayer carrier transport capability of the molybdenum disulfide thin film. After forming each layer of molybdenum disulfide thin film, a 10 nm thick tungsten metal is formed as a contact metal layer in its edge region by photolithography and physical vapor deposition. The contact metal layers are staggered in vertical projection and arranged in a stepped manner. Subsequently, a 500 nm thick silica insulating dielectric layer is deposited by plasma-enhanced chemical vapor deposition. The process parameters are: silane flow rate of 50 sccm, nitrous oxide flow rate of 500 sccm, RF power of 100 W, reaction chamber pressure of 200 Pa, and substrate temperature of 350 °C. Inductively coupled plasma reactive ion etching (ICP-IR) was used to etch through multiple layers of silicon dioxide insulating dielectric layer and molybdenum disulfide film, forming through-holes that exposed the bottom silicon dioxide substrate. A fluorine-based gas system was used for continuous etching of the silicon dioxide insulating dielectric layer and molybdenum disulfide film, with a flow rate ratio of carbon tetrafluoride, trifluoromethane, and argon of 50:30:50 sccm. A 20 nm thick TaOx oxygen-deficient layer with an atomic ratio of x=2.4 and a 20 nm thick Ta2O5 oxygen-rich layer were conformally deposited sequentially on the inner wall and bottom of the through-hole to form a composite resistive switching functional layer. Atomic layer deposition (ALD) was then used to deposit TaOx. x For the oxygen-deficient layer and the Ta2O5 oxygen-rich layer, tantalum pentaethoxy was used as the precursor, deionized water was used as the oxidant, and the deposition temperature was controlled at 300℃. A 10 nm thick patterned platinum top electrode was formed inside the through-hole and above the composite resistive switching functional layer using physical vapor deposition. Dry etching was performed using a chlorine-based gas system containing chlorine, boron trichloride, and argon, with a flow rate ratio of 30:30:40 sccm. Each contact metal layer served as a natural etching stop layer, and the Ta2O5 oxygen-rich layer and TaO covering the contact metal layers were removed. x The oxygen-deficient layer fully exposes the surfaces of the contact metal layers, forming stepped contact leads.

[0066] Example 4: This example provides a method for fabricating a 3D storage device, including the following steps: A cleaned silica substrate is provided. Four layers of two-dimensional conductive material and four layers of silica insulating dielectric are alternately formed on the silica substrate to form a multilayer alternating stacked structure. The two-dimensional conductive material layer is the carbon nanotube film obtained in Preparation Example 5. After forming each carbon nanotube film, a titanium nitride layer with a thickness of 3 nm is formed at its edge region as a contact metal layer by photolithography and physical vapor deposition. The contact metal layers are staggered and arranged in a stepped manner in vertical projection. Subsequently, a silica insulating dielectric layer with a thickness of 200 nm is deposited by plasma-enhanced chemical vapor deposition. The process parameters are: silane flow rate of reaction gas 25 sccm, nitrous oxide flow rate 200 sccm, RF power 50 W, reaction chamber pressure 100 Pa, and substrate temperature 300 °C. Inductively coupled plasma reactive ion etching (ICP-IR) was used to etch through multiple layers of silicon dioxide insulating dielectric layer and carbon nanotube film to form through-holes exposing the bottom silicon dioxide substrate. A fluorine-based gas system was used for etching the silicon dioxide insulating dielectric layer, with a flow rate ratio of carbon tetrafluoride, trifluoromethane and argon of 40:25:40 sccm. An oxygen plasma system was used for etching the carbon nanotube film, with a flow rate ratio of oxygen to argon of 30:20 sccm. TaO with a thickness of 5 nm and an atomic ratio of x=2.0 was conformally deposited sequentially on the inner wall and bottom of the through-hole. x An oxygen-deficient layer and a 15 nm thick Ta₂O₅ oxygen-rich layer are used to form a composite resistive switching functional layer. TaO₂ is deposited using physical vapor deposition. xAn oxygen-deficient layer was first formed, followed by the deposition of a Ta₂O₅ oxygen-rich layer using atomic layer deposition (ALD) with tantalum pentaethoxy as the precursor and ozone as the oxidant. The deposition temperature was controlled at 280°C. A 5nm thick patterned platinum top electrode was formed inside the through-holes and above the composite resistive switching functional layer using physical vapor deposition (PVD). Dry etching was performed using a chlorine-based gas system containing chlorine, boron trichloride, and argon, with a flow rate ratio of 15:25:30 sccm. The contact metal layers of each layer served as natural etch stop layers, removing the portion of the Ta₂O₅ oxygen-rich layer and TaO₂ layer covering the contact metal layers. x The oxygen-deficient layer fully exposes the surfaces of the contact metal layers, forming stepped contact leads.

[0067] Comparative Examples 1-5: Comparative Example 1: Compared with Example 1, the difference is that a single layer of graphene was not used as the two-dimensional conductive material layer. Instead, a titanium nitride thin film with a thickness of 30 nm was deposited as the conductive layer using physical vapor deposition. All other aspects are the same.

[0068] Comparative Example 2: Compared with Example 1, the difference is that the process of alternating multilayer stacking and etching through-holes was not used. Instead, a composite resistive switching functional layer and a platinum on-electrode were deposited sequentially on the surface of a single layer of graphene in a plane to form a traditional planar cross array structure (two-dimensional planar physical contact). All other aspects are the same.

[0069] Comparative Example 3: Compared with Example 1, the difference is that only a 20 nm thick Ta2O5 oxygen-rich layer was deposited on the inner wall and bottom of the through-hole, and no TaO was deposited. x The oxygen-deficient layer, also known as the resistive switching functional layer, is a thin film made of a single material, while the rest are the same.

[0070] Comparative Example 4: The difference compared to Example 1 is the deposition of TaO. x When the oxygen-deficient layer is used, the process parameters are adjusted to make its atomic ratio x=2.5, that is, the layer is a stoichiometric Ta2O5 film without oxygen vacancies, and the rest are the same.

[0071] Comparative Example 5: Compared with Example 1, the difference is that after forming each monolayer graphene, palladium metal was not prepared as a contact metal layer in its edge region. The subsequent dry etching step directly exposed the edge of the monolayer graphene as the lead-out end. All other aspects are the same.

[0072] It should be noted that the following test examples are mainly used to verify the use of single-layer graphene as a two-dimensional conductive material layer and TaO2. xThe performance effect of the preferred embodiment using a Ta2O5 composite layer as the resistive switching functional layer and Pt as the top electrode. The specific materials, thicknesses, process parameters, test conditions, and test results in the following test examples are only used to illustrate the technical effects that can be obtained by the preferred embodiment of this application, and should not be construed as limiting the scope of protection of this application.

[0073] For embodiments employing other resistive switching materials, top electrode materials, contact metal materials, or two-dimensional conductive material layers, those skilled in the art can select based on the process compatibility and electrical performance requirements of the resistive switching memory device. The aforementioned alternatives do not alter the basic structure where the two-dimensional conductive material layer serves as the interlayer contact electrode, and the resistive switching functional layer is disposed within the via and contacts each of the two-dimensional conductive material layers to form the memory cell.

[0074] Test Examples 1-4: Test Example 1: The multilayer alternating stacked structure wafer sample containing 3D memory devices was placed on the probe stage of a semiconductor parameter tester. The test environment was controlled at room temperature and normal pressure. With the aid of a microscope, the test probes were inserted into the platinum top electrode and the bottom step contact lead of the device.

[0075] The DC voltage scanning mode of the tester is set. For each embodiment sample, a unidirectional positive bias voltage scan of 0V to 2.5V is applied before the first test to activate and shape the device. During the test, a compliant current of 1mA is set to limit the device to thermal breakdown failure.

[0076] After activation, a cyclic DC scan bias voltage is applied to the device. The scan voltage path is set to increase from 0V to the upper limit voltage in the positive voltage direction, then scan back to 0V, then decrease to the lower limit voltage in the negative voltage direction, and finally scan back to 0V. The leakage current value corresponding to each voltage node is recorded.

[0077] Extract key electrical parameters from the hysteresis curve, read the positive critical bias voltage when the device transitions from a high resistance state to a low resistance state as the set voltage, and read the negative critical bias voltage when the device abruptly returns from a low resistance state to a high resistance state as the reset voltage.

[0078] Under a constant read voltage of 0.1V, the stable read current of the device after the set operation and after the reset operation is measured respectively. The corresponding low-resistance state resistance value and high-resistance state resistance value are calculated and extracted according to Ohm's law, and the data of typical cycle period are recorded.

[0079] Table 1. Extraction of basic resistive characteristic parameters of devices in Examples 1 to 4

[0080] in conclusion: Figure 3Subgraph (a) shows a typical DC voltage scan test hysteresis curve of the device in Example 1. The horizontal axis represents the bias voltage applied across the electrodes, and the vertical axis represents the absolute value of the read current. Different line shapes in the figure correspond to the preceding and following scan paths of voltage change over time within the test cycle, fully demonstrating the device's transition from an insulating state to a conductive state and the subsequent reset and breakage process. Figure 3 Subplot (b) shows the resistance distribution of the devices in Examples 1 to 4 under a fixed bias voltage of 0.1V. The square dot areas correspond to the resistance levels of the devices in the high resistance state, and the triangular dot areas correspond to the resistance levels of the devices in the low resistance state, reflecting the differences in the separation between high and low resistance states in each example.

[0081] According to the data in Table 1, the 3D memory devices prepared in Examples 1 to 4 all exhibit typical bipolar resistive switching characteristics, enabling physical switching between high-resistivity and low-resistivity states under DC bias. This result verifies that an effective conductive filamentary path can be formed at the interface between the fractured sidewalls of the two-dimensional material and the composite oxide thin film in a multilayer stacked structure.

[0082] Examples 1 and 2 use monolayer graphene as the conductive layer. Its atomic-level thickness induces electrostatic field distortion and localized electric field convergence at the fracture edge cross-section. Compared to the three-atom-thick molybdenum disulfide in Example 3, the graphene edge has a smaller radius of curvature and a higher electric field enhancement factor, allowing oxygen anions to... x The migration barrier between the device and the Ta2O5 layer is reduced, enabling the device to be set at a positive bias of around 0.8V and to complete reset and breakage at a negative bias of up to -0.7V, thus reducing operating power consumption.

[0083] The resistance ratio of the high-resistivity state to the low-resistivity state in each embodiment reached approximately three orders of magnitude, demonstrating that TaO with a thickness distribution in the range of 1 nm to 20 nm... x The thin film acts as a stable oxygen vacancy reservoir, absorbing and releasing oxygen ions to maintain the stoichiometric balance of the conductive filaments in the Ta2O5 layer, avoiding random diffusion of the filaments during multiple breakages and growth processes, and ensuring readout window margin.

[0084] Test Example 2: 3D memory device wafer samples prepared in Example 1, Comparative Example 1, and Comparative Example 2 were selected and placed in the probe station test cavity. For each sample's memory array, five different memory cell locations were selected and marked using a random number generator as independent test nodes. The tungsten probes of the probe station contacted the top electrode and bottom lead-out terminal of the selected cells, respectively.

[0085] Configure the test program for the semiconductor parameter analyzer, setting the compliance current to 1mA. Apply a forward DC voltage scan to the device in its initial high-resistivity state, increasing the voltage from 0V in 0.05V increments, and monitor real-time current changes. When the current experiences a step change of more than three orders of magnitude and reaches the compliance current limit, record the current voltage value as the device's forming voltage.

[0086] The bias voltage of the molding operation is removed, and the device enters a low-resistance conducting state. Subsequently, a complete DC scan cycle test is performed on the same memory cell for 100 consecutive cycles. The voltage path for each cycle is set from 0V to the upper limit of the positive flip, scan back to 0V, continue scanning to the lower limit of the negative flip, and then scan back to 0V.

[0087] The electrical parameters of each test unit were extracted over 100 cycles, and the activation data from the first 5 cycles in an unstable state were discarded. The critical point at which the high-resistance state transitioned to the low-resistance state in each cycle was recorded as the set voltage, and the critical point at which the low-resistance state transitioned to the high-resistance state was recorded as the reset voltage. The voltage data extracted from each unit were randomly sampled and recorded.

[0088] Table 2 Random sampling test data of operating voltage in Example 1 and Comparative Example

[0089] in conclusion: Figure 4 Subplot (a) shows the distribution range of the forming voltage required for the initial high-resistivity device to form a conducting filament. The horizontal axis represents different device structure categories, and the vertical axis is the measured forming voltage value. The scatter points in the figure represent the specific data of each random test unit, and the thick black horizontal line marks the mean center position of the data set. Figure 4 Subplot (b) shows the dispersion of the absolute values ​​of the set and reset voltages of the device over the subsequent 100 consecutive DC scan cycles. Hollow primitives represent the set of positive set voltage distributions when transitioning from a high-resistance state to a low-resistance state, while solid primitives represent the set of negative reset voltage distributions when abruptly returning from a low-resistance state to a high-resistance state. Different primitive shapes are used to distinguish specific device groups.

[0090] According to the data in Table 2, the molding voltage of Example 1 is mainly distributed in the range of 1.5V to 1.8V, the set voltage during the cycling process is stable at around 0.8V, and the reset voltage is around -0.7V. Comparative Example 1 uses a 30nm thick titanium nitride film to replace the single-layer graphene as the conductive layer, and its molding voltage rises to over 4.5V, with the absolute values ​​of both the set and reset operation voltages exceeding 2.1V. This is because the thick titanium nitride metal film prepared by physical vapor deposition has a larger radius of curvature at the etched section, and the electric field lines at the interface are uniformly distributed without local enhancement.

[0091] In Comparative Example 2, the planar structure results in a perpendicular and uniform electric field distribution on both sides of the resistive switching layer. This large-area contact area easily induces the random growth and competition of multiple filaments, increasing the dispersion of the operating voltage. In Example 1, the monolayer graphene possesses a sub-nanometer physical thickness, forming extremely sharp geometric features at the fractured sidewalls of the through-holes.

[0092] When an external bias voltage is applied across the electrodes, severe electrostatic field distortion occurs at the fracture edges of the graphene, resulting in a significant local electric field convergence effect. This strong local electric field lowers the activation energy and migration barrier of oxygen negative ions within the composite resistive switching functional layer, enabling the growth and fracture-reorganization of oxygen vacancy filaments within the insulating dielectric layer under a relatively low macroscopic bias voltage. This structural design reduces the energy consumption required for device initialization and activation, limits the growth range of conductive filaments at the interface, and improves the energy efficiency and stability of the device during operation.

[0093] Test Example 3: The 3D memory device wafer samples prepared in Example 1, Comparative Example 3 and Comparative Example 4 were placed in a probe station equipped with a high-frequency microwave probe. The probe was connected to an arbitrary waveform generator and a semiconductor parameter analyzer using a coaxial cable. The entire test was conducted in a room-temperature shielded darkroom.

[0094] The initial activation shaping operation is completed by applying a DC scan bias voltage to the selected memory cell, and then switching to pulse test mode. The set pulse amplitude is set to +1.5V and the pulse width is 50ns, and the reset pulse amplitude is set to -1.5V and the pulse width is 50ns.

[0095] Initiate a continuous alternating pulse cycle sequence, alternately applying set and reset pulses to the device. Pause the write pulse at the set logarithmic cycle number nodes (such as the 10th, 100th, 1000th, etc.), and immediately apply a non-destructive read pulse with an amplitude of 0.1V and a pulse width of 1 microsecond.

[0096] Record the response current under each read pulse and calculate the corresponding high-resistance and low-resistance resistances. Continuously run this pulse cycle sequence until the high-to-low resistance ratio of the device degrades to less than 10 times, or the resistance value becomes fixed and cannot be flipped. At this point, the device is considered to have experienced fatigue failure, and the number of cycles at this point is recorded as the ultimate durability.

[0097] For each type of sample, five storage cells were randomly selected in different array regions to repeat the above test, and representative data on the evolution of resistance with the number of cycles were extracted.

[0098] Table 3. Resistance Evolution of Durability Cyclic Tests in Example 1 and Comparative Examples

[0099] Note: The symbol "-" indicates a lack of valid test data, meaning the device failed before reaching the required number of cycles, and the test is terminated.

[0100] in conclusion: Figure 5 Subplot (a) in the figure records the evolution of the resistive state of the device in Example 1 under alternating pulse drive as the number of write cycles increases. The horizontal axis represents the number of cycles on a logarithmic scale, and the vertical axis represents the read resistance value. The black solid triangles and gray solid circles in the figure represent the distribution patterns of the low-resistance and high-resistance states of the device, respectively, and the solid lines are the smoothed fitting trend lines of the corresponding data. This figure shows that the device has undergone 1e 10 The resistive variable window remains recognizable even after the operation. Figure 5 Subplot (b) shows the fatigue degradation paths of Comparative Example 3 and Comparative Example 4 devices lacking an effective reservoir layer design. The gray hollow dotted lines correspond to the test data for Comparative Example 3, and the black solid dotted lines correspond to the test data for Comparative Example 4. This figure reflects the fatigue degradation paths of the comparative group devices at 1e... 4 After the second cycle, the resistance deteriorated sharply, reaching 1e. 5 The failure process of closing the high and low resistance state window within the secondary cycle interval.

[0101] According to the data in Table 3, the 3D storage device prepared in Example 1 underwent 10... 10 After cycling with a sub-high frequency alternating pulse, its low-resistivity state resistance stabilized between 1 and 3 kΩ, while its high-resistivity state resistance remained above 500 kΩ. The margin between the high and low resistance states remained at more than two orders of magnitude, and no significant performance degradation occurred. Comparative Example 3 lacked TaO. x Thin film, Comparative Example 4: TaO x The layer was replaced with a stoichiometric Ta₂O₅ thin film containing no oxygen vacancies. Both devices achieved a cycle life of 10... 4 After that, the low-resistance state resistance rapidly increased, while the high-resistance state resistance dropped sharply, reaching 10... 5 The device fails due to a hard breakdown near the next cycle when the resistive state closes.

[0102] During repeated set and reset operations, oxygen ions in resistive switching memory devices need to undergo long-distance directional migration under an alternating electric field. Single-component Ta₂O₅ films or defect-free stoichiometric oxide films lack structures capable of buffering oxygen ion concentration gradients. After multiple cycles, locally migrated oxygen ions are prone to irreversible oxidation reactions at the electrode interface or dissipate into the surrounding environment, leading to a decrease in the overall oxygen vacancy concentration within the film. When the conductive filaments break, they cannot obtain sufficient oxygen vacancies for reconstruction, resulting in a gradual increase in resistance in the low-resistivity state until failure.

[0103] Example 1 employs a composite resistive switching functional layer composed of 10 nm oxygen-deficient TaOx (x=1.5) and 10 nm oxygen-rich Ta2O5. x The layer naturally contains a high density of oxygen vacancies, serving as an internal reservoir of oxygen ions and vacancies. Under the drive of a pulsed electric field, oxygen ions in TaO... x Local exchange occurs between the reservoir layer and the Ta2O5 active layer, preventing excessive escape of oxygen ions into the external environment. The reservoir layer dynamically replenishes the oxygen vacancies required to form conductive filaments, inhibiting excessive breakage or depletion of the filaments, and ensuring the high-frequency fatigue resistance and durability of the device from a physical mechanism perspective.

[0104] Test Example 4: The wafer sample containing the three-dimensional storage array of Example 1 and Comparative Example 5 was fixed on the vacuum chuck of the semi-automatic probe station. The four tungsten test probes were aligned with and inserted into the adjacent contact pads of the same layer of the device's stepped lead-out end using a microscopic system.

[0105] The transmission line model was used to test the structure. A low bias voltage was applied between adjacent probes using a semiconductor parameter analyzer, and the current value was measured at different spacings to extract the intrinsic contact resistance at the interface between the two-dimensional conductive material and the lead-out electrode.

[0106] Replace the array test probe card and align and press it with the contact pads of the 10×10 scale memory subarray on the wafer. Then, use the switch matrix module to achieve random addressing of 100 independent memory cells in the array.

[0107] For each addressed memory cell, a standard set and reset DC voltage scan is performed to read its resistance values ​​in both high-resistance and low-resistance states. The judgment criteria are set as follows: a device is considered a valid good product if the ratio of its high to low resistance states is greater than 10 and the low-resistance state read current is greater than 1 microamp.

[0108] Five independent array regions were randomly selected from four different quadrants at the center and edge of the same wafer. The above process of contact resistance extraction and array yield statistics was repeated, and the original test data were recorded.

[0109] Table 4. Contact resistance and array yield test distribution of Example 1 and Comparative Example 5

[0110] in conclusion: Figure 6 Subplot (a) shows the distribution of intrinsic contact resistance of leads extracted from five random test areas on the wafer surface of Example 1 and Comparative Example 5. The vertical axis is a logarithmic coordinate axis, with dark gray solid circles corresponding to the data of Example 1 containing a palladium contact metal layer, and light gray solid squares corresponding to the data of Comparative Example 5 directly led out without a contact metal layer. Figure 6Subplot (b) shows the statistical results of the 10×10 array yield in the corresponding region mentioned above. The dark bars represent the percentage of effective working cells in Example 1, and the light bars represent the percentage of effective working cells in Comparative Example 5, which intuitively reflects the impact of the microscopic lead-out interface structure on the macroscopic array connectivity and device reliability.

[0111] According to the data in Table 4, the contact resistance of the test area in Example 1 ranged from 280Ω to 430Ω, and the average yield of the corresponding memory array remained at around 95%. In Comparative Example 5, without a contact metal layer, the contact resistance at the lead-out terminals rose sharply to hundreds of kiloohms or even exceeded one megaohm, the array yield dropped to below 15%, and many devices exhibited open-circuit failure or current polarization. Two-dimensional materials such as monolayer graphene possess sub-nanometer physical thicknesses.

[0112] In Comparative Example 5, macroscopic probes or metal interconnects were directly pressed onto the exposed cross-sectional edge of the two-dimensional material, resulting in a scale mismatch in the physical contact area between the two. Under mechanical stress, the edge of the two-dimensional film is prone to physical tearing and structural damage. Direct contact between the metal probe and graphene generates a severe Fermi level pinning effect at the interface, forming a high-barrier Schottky junction that hinders carrier injection. In Example 1, a 5nm thick palladium metal layer was pre-fabricated as a buffer contact metal layer in the edge region of monolayer graphene, with each contact metal layer arranged staggered in vertical space to form a stepped structure.

[0113] The work function of palladium matches that of graphene, reducing the interfacial contact barrier and expanding the microscopic charge injection channel, which is only one atom thick, into a macroscopic solid metal pad. This stepped lead design withstands mechanical damage from external probe crimping and subsequent interconnect processes, eliminating series resistance overload and signal attenuation caused by poor interfacial contact in two-dimensional materials, and ensuring addressing connectivity and high yield of the device in large-scale array integration.

Claims

1. A 3D storage device, characterized in that, include: Substrate; A multilayer stacked structure is disposed on the substrate. The multilayer stacked structure includes multiple layers of two-dimensional conductive material and multiple layers of isolation dielectric layer alternately arranged in a vertical direction. The two-dimensional conductive material layer serves as an interlayer contact electrode or a memory cell electrode. The contact lead-out structure is electrically connected to each of the two-dimensional conductive material layers and is used to lead out the two-dimensional conductive material layers at different height positions to the external circuit. A via, penetrating at least a portion of the multilayer stacked structure and exposing the edge region of at least one layer of the two-dimensional conductive material; A resistive switching functional layer is disposed on the inner wall and / or inside the through hole, and in contact with the edge region of the two-dimensional conductive material layer; The upper electrode is electrically connected to the resistive switching functional layer; The two-dimensional conductive material layer, the resistive switching functional layer, and the upper electrode form multiple resistive switching memory cells at different height positions.

2. The 3D storage device according to claim 1, characterized in that, The two-dimensional conductive material layer includes one or more of the following: monolayer graphene, few-layer graphene, carbon nanotube film, conductive molybdenum disulfide film, and conductive transition metal chalcogenide film. The thickness of the two-dimensional conductive material layer is 0.3 nm to 20 nm; The isolation dielectric layer includes one or more of the following: silicon oxide layer, silicon nitride layer, aluminum oxide layer, silicon oxynitride layer, and low dielectric constant dielectric layer, and the thickness of the isolation dielectric layer is 10 nm to 500 nm.

3. A 3D storage device according to claim 1, characterized in that, The contact lead-out structure includes one or more of the following: a contact metal layer, a lateral extension area, a partial opening, a contact hole, a metal plug, and a stepped step; The contact metal layer is connected to the edge region of the two-dimensional conductive material layer, and the contact metal layer includes one or more of metal, metal nitride, metal oxynitride, and conductive carbon material; The contact metal layer includes one or more of Pd, Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Co, TiN, TaN, WN, conductive treated AlN, TiON, TaON, and AlON, and the thickness of the contact metal layer is 1 nm to 10 nm.

4. A 3D storage device according to claim 1, characterized in that, The resistive switching functional layer includes a metal oxide resistive switching material that can undergo reversible resistance change under the action of an applied electric field; The resistive switching functional layer includes HfO2, SiO2, TiO2, ZrO2, Al2O3, WO3, and TaO. x One or more of Ta2O5, NbOx, VOx, HfSiO, HfTaO, HfZrO, and HfAlO, or a multilayer, mixed layer, or oxygen-deficient / oxygen-rich layer composite structure formed by the above materials; When the resistive switching functional layer is a single-layer structure, its thickness is 1nm to 20nm; When the resistive switching functional layer is a multilayer composite structure, the thickness of each sublayer is 1nm to 20nm.

5. A 3D storage device according to claim 1, characterized in that, The upper electrode comprises one or more of a metal, a metal nitride, and a metal nitride. The upper electrode includes one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Co, TiN, TaN, WN, conductive treated AlN, TiON, TaON, and AlON; The upper electrode covers the surface of the resistive switching functional layer or fills the interior of the through-hole.

6. A 3D storage device according to claim 1, characterized in that, The via may penetrate the entire multilayer stacked structure and expose the substrate surface, or it may only penetrate a portion of the multilayer stacked structure and stop at the bottom electrode layer, bottom insulating layer, etch stop layer, or preset support layer. The two-dimensional conductive material layer and the resistive switching functional layer form edge contact, local sidewall contact, local surface contact or a combination thereof; When the two-dimensional conductive material layer is a single-layer graphene, the single-layer graphene forms a single-atom-layer edge contact structure at the sidewall of the through hole; The number of two-dimensional conductive material layers in the multi-layer stacked structure is two or more.

7. A fabrication process for a 3D storage device, characterized in that, The fabrication of a 3D storage device as described in any one of claims 1-6 comprises the following steps: Provide substrate; A multilayer stacked structure is formed on the substrate, the multilayer stacked structure comprising multiple layers of two-dimensional conductive material and multiple layers of insulating dielectric material alternately arranged in a vertical direction; A contact lead-out structure is formed that is electrically connected to each of the two-dimensional conductive material layers; Etching forms vias that penetrate at least a portion of the multilayer stacked structure, and exposes the edge regions of at least one layer of the two-dimensional conductive material; A resistive switching functional layer is formed on the inner wall and / or inside the through hole, so that the resistive switching functional layer is in contact with the edge region of the two-dimensional conductive material layer. An upper electrode is formed that is electrically connected to the resistive switching functional layer.

8. The preparation process according to claim 7, characterized in that, The two-dimensional conductive material layer is formed by one or more of the following methods: chemical vapor deposition, physical vapor deposition, transfer process, coating process, spraying process, and spin coating process. The isolation medium layer is formed by one or more of the following methods: plasma-enhanced chemical vapor deposition, chemical vapor deposition, atomic layer deposition, and physical vapor deposition. The resistive switching functional layer is formed by one or more of the following methods: atomic layer deposition, physical vapor deposition, chemical vapor deposition, reactive sputtering, and plasma-enhanced deposition. The upper electrode and / or contact lead-out structure are formed by one or more of the following methods: physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, and electroless plating.

9. The preparation process according to claim 7, characterized in that, The two-dimensional conductive material layer is a single-layer graphene or few-layer graphene, and the steps for forming the two-dimensional conductive material layer include: Graphene was grown on a metal catalytic substrate using chemical vapor deposition. A polymer support layer is formed on the surface of the graphene; The graphene with the polymer support layer is peeled off from the metal catalytic substrate and transferred to the target surface; Remove the polymer support layer; The metal catalytic substrate includes a platinum sheet or copper foil, the polymer support layer includes a polymethyl methacrylate layer, and the peeling is an electrolytic bubbling peeling.

10. The preparation process according to claim 7, characterized in that, The multilayer stacked structure includes alternating graphene layers and SiO2 insulating dielectric layers; After each graphene layer is formed, a contact metal layer with a thickness of 1 nm to 10 nm is formed in its edge region, and the contact metal layers are staggered in vertical projection to form a stepped contact lead-out end. The vias are formed by a dry etching process, and the etching penetrates the SiO2 isolation dielectric layer and the graphene layer. The resistive switching functional layer includes TaO. x Anoxic layer and Ta2O5 oxygen-rich layer, wherein TaO x The thickness of the oxygen-deficient layer is 1 nm to 20 nm, and the thickness of the Ta2O5 oxygen-rich layer is 1 nm to 20 nm. The upper electrode is a Pt upper electrode; Wherein, the TaO x The anoxic layer serves as an oxygen vacancy reservoir, while the Ta2O5 oxygen-rich layer serves as the active layer of the resistive switching device.

Images