Method of reducing metal gate resistance

Abstract

This application provides a method for reducing the resistance of a metal gate, comprising: step one, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming trenches in the interlayer dielectric layer; step two, forming a work function metal layer within the trenches; step three, after wetting the substrate, forming a W nucleation layer on the work function metal layer, which is composed of multiple B2H6-based nucleation layers and SiH4-based nucleation layers stacked from bottom to top; and step four, forming a W film layer on the W nucleation layer to complete the fabrication of the metal gate. According to this application, the metal gate resistance is reduced while avoiding the formation of annular void defects in the work function metal layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for reducing the resistance of a metal gate. Background Technology

[0002] As device size decreases, the requirements for the material of the metal gate, as well as its resistance and resistance uniformity, become increasingly stringent. Currently, advanced semiconductor device processes use tungsten (W) as the gate material. Tungsten deposition is divided into two stages: nucleation (W Nuc, high resistance) and film growth (W Bulk, low resistance). Therefore, reducing the metal gate resistance means focusing on reducing the resistance of W Nuc.

[0003] Existing W Nucs are SiH4 Nuc and B2H6 Nuc. The crystal structures of W Nucs obtained by the SiH4 / B2H6 and WF6 reactions are different. SiH4 Nuc is a polycrystalline material with a strong (110) orientation, while B2H6 Nuc is an amorphous structure. The difference in the crystal structure of W Nuc has a significant impact on the growth of W bulk. The resistivity of W bulk grown on SiH4 Nuc is higher than that of W bulk grown on B2H6 Nuc. However, B2H6 Nuc is more susceptible to corrosion by the polishing slurry used in the chemical mechanical polishing after W bulk growth, forming annular void defects that affect the underlying work function metal layer and thus the electrical properties of the device. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for reducing the metal gate resistance, in order to solve the problem that the high resistivity of W Nuc in the prior art prevents the metal gate resistance from being further reduced.

[0005] To achieve the above and other related objectives, this application provides a method for reducing the resistance of a metal gate, comprising: Step 1: Provide a substrate, and form an interlayer dielectric layer on the substrate, with trenches formed in the interlayer dielectric layer; Step 2: Form a functional metal layer within the trench; Step 3: After wetting the substrate, a W nucleation layer is formed on the work function metal layer, which consists of multiple B2H6-based nucleation layers and SiH4-based nucleation layers stacked from bottom to top. Step four: Form a W film layer on the W nucleation layer to complete the fabrication of the metal gate.

[0006] Preferably, the medium used for wetting the substrate is B2H6.

[0007] Preferably, the formation of the W nucleation layer is as follows: after wetting the substrate, WF6 is first introduced into the chamber, and WF6 reacts with B2H6 to form a B2H6-based nucleation layer. Then, SiH4 is introduced, and SiH4 reacts with WF6 to form a SiH4-based nucleation layer. This process is repeated multiple times until a W nucleation layer with a set thickness is formed.

[0008] Preferably, the W nucleation layer is formed by a spatial atomic layer deposition process.

[0009] Preferably, a W film layer is formed on the W nucleation layer by chemical vapor deposition.

[0010] Preferably, after the W film layer is formed, chemical mechanical polishing is performed to remove the W film layer outside the groove.

[0011] Preferably, before forming the power function metal layer, the method further includes the step of sequentially forming a high dielectric constant dielectric layer and a capping layer on the sidewalls and bottom of the trench.

[0012] Preferably, the material of the coating layer includes titanium nitride.

[0013] Preferably, a power function metal layer is formed using a deposition process.

[0014] Preferably, the work function metal layer of the PMOS metal gate device is made of titanium nitride, and the work function metal layer of the NMOS metal gate device is made of titanium aluminum.

[0015] As described above, the method for reducing metal gate resistance provided in this application has the following beneficial effects: reducing metal gate resistance while avoiding the formation of annular void defects in the work function metal layer. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 The flowchart shown is a method for reducing metal gate resistance provided in an embodiment of this application. Figure 2 The diagram shows a comparison of the resistivity of metal gate resistors formed based on existing technologies and the methods for reducing metal gate resistance provided in the embodiments of this application. Detailed Implementation

[0018] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0023] Currently, the growth method for W nucleation layer (W Nuc) is to first perform B2H6 wetting to reduce the pretreatment time of the substrate, and then grow SiH4 Nuc. However, SiH4 Nuc has high resistivity, which is not conducive to further reducing the metal gate resistance.

[0024] To address this issue, this application provides a method for reducing the resistance of a metal gate.

[0025] Please see Figure 1The diagram illustrates a flowchart of a method for reducing metal gate resistance provided in an embodiment of this application.

[0026] like Figure 1 As shown, the method for reducing the metal gate resistance includes the following steps: Step 1: Provide a substrate, and form an interlayer dielectric layer on the substrate, with trenches formed in the interlayer dielectric layer; Step 2: Form a functional metal layer within the trench; Step 3: After wetting the substrate, a W nucleation layer is formed on the work function metal layer, which consists of multiple B2H6-based nucleation layers and SiH4-based nucleation layers stacked from bottom to top. Step four: Form a W film layer on the W nucleation layer to complete the fabrication of the metal gate.

[0027] In step one, a substrate is provided. Optionally, the substrate may be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the substrate material may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the substrate material according to the type of device structure formed on the substrate, therefore the type of substrate should not limit the scope of protection of this invention.

[0028] Optionally, the material of the interlayer dielectric layer may include, but is not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constants (<3.9).

[0029] For example, an interlayer dielectric layer is formed using a chemical vapor deposition process.

[0030] For example, the step of forming a trench in the interlayer dielectric layer includes: forming a photoresist layer on the interlayer dielectric layer by a coating process; exposing and developing the photoresist layer by a photolithography process to form a photoresist layer with a dummy gate pattern; using the photoresist layer with the dummy gate pattern as a mask, etching the exposed dummy gate by a plasma etching process to form a trench in the interlayer dielectric layer; and removing the photoresist layer with the dummy gate pattern by an ashing process.

[0031] In step two, before forming the functional metal layer, a high-k dielectric layer and a capping layer are sequentially formed on the sidewalls and bottom of the trench. For example, the high-k dielectric layer may be made of hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium dioxide (ZrO2), or hafnium zirconium oxide (HfZrOx), and the capping layer may be made of titanium nitride (TiN).

[0032] For example, a work function metal layer is formed using a deposition process. The material of the work function metal layer for a PMOS metal gate device includes titanium nitride, and the material of the work function metal layer for an NMOS metal gate device includes aluminum titanium (TiAl).

[0033] In step three, the medium used for wetting the substrate is B2H6, which can shorten the incubation time before the growth of the W nucleation layer.

[0034] The W nucleation layer formed on the work function metal layer is composed of multiple B2H6-based nucleation layers and SiH4-based nucleation layers stacked from bottom to top. The formation method is as follows: after the substrate is wetted, WF6 is first introduced into the chamber. WF6 and B2H6 react to form a B2H6-based nucleation layer. Then SiH4 is introduced. SiH4 and WF6 react to form a SiH4-based nucleation layer. After multiple cycles, a W nucleation layer with a set thickness is formed.

[0035] For example, the above-mentioned W nucleation layer is formed by a spatial atomic layer deposition (SALD) process.

[0036] In step four, a W film (W Bulk) is formed on the W nucleation layer using a chemical vapor deposition (CVD) process. After the W film is formed, chemical mechanical polishing is performed to remove the W film outside the trenches.

[0037] like Figure 2 As shown, compared with the prior art, the resistivity of the metal gate formed by the method for reducing metal gate resistance provided in this application is reduced by 8.3%.

[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] In summary, the method for reducing metal gate resistance provided in this application reduces the metal gate resistance while avoiding the formation of annular void defects in the work function metal layer. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0040] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for reducing the resistance of a metal gate, characterized in that, The method includes: Step 1: Provide a substrate, and form an interlayer dielectric layer on the substrate, wherein trenches are formed in the interlayer dielectric layer; Step 2: Form a functional metal layer within the trench; Step 3: After wetting the substrate, a W nucleation layer is formed on the work function metal layer, which is composed of multiple B2H6-based nucleation layers and SiH4-based nucleation layers stacked from bottom to top. Step four: A W film layer is formed on the W nucleation layer to complete the fabrication of the metal gate.

2. The method according to claim 1, characterized in that, The medium used to wet the substrate is B2H6.

3. The method according to claim 1, characterized in that, The W nucleation layer is formed as follows: after wetting the substrate, WF6 is first introduced into the chamber, and WF6 reacts with B2H6 to form a B2H6-based nucleation layer. Then, SiH4 is introduced, and SiH4 reacts with WF6 to form a SiH4-based nucleation layer. This process is repeated multiple times until the W nucleation layer with a set thickness is formed.

4. The method according to claim 1 or 3, characterized in that, The W nucleation layer is formed by a spatial atomic layer deposition process.

5. The method according to claim 1, characterized in that, The W film layer is formed on the W nucleation layer by chemical vapor deposition.

6. The method according to claim 5, characterized in that, After the W film layer is formed, chemical mechanical polishing is performed to remove the W film layer outside the trench.

7. The method according to claim 1, characterized in that, Before forming the work function metal layer, the method further includes the step of sequentially forming a high dielectric constant dielectric layer and a capping layer on the sidewalls and bottom of the trench.

8. The method according to claim 7, characterized in that, The material of the coating layer includes titanium nitride.

9. The method according to claim 1, characterized in that, The work function metal layer is formed using a deposition process.

10. The method according to claim 1 or 9, characterized in that, The work function metal layer of a PMOS metal gate device is made of titanium nitride, and the work function metal layer of an NMOS metal gate device is made of titanium aluminum.

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