Systems and methods for high stiffness substrate integration in semiconductor packaging

Abstract

This technology relates to systems and methods for high-stiffness substrate integration in semiconductor packaging. In one embodiment, the technology provides an apparatus comprising a substrate including a first metallic material and a first layer coupled to the substrate. The apparatus further includes a second layer coupled to the substrate via the first layer. The second layer comprises an organic material. The first layer comprises: a third layer including a first adhesive material configured to couple to the organic material; a fourth layer including a second adhesive material; and a fifth layer including a third adhesive material configured to couple to the first metallic material. This multilayer adhesive system achieves reliable bonding between organic and metallic components, thereby ensuring robust mechanical and electrical performance of the system. Other embodiments also exist.

Description

Technical Field

[0001] This technology relates to semiconductor devices. Background Technology

[0002] Semiconductor packaging is a fundamental component that provides physical support and electrical connectivity for integrated circuits. Semiconductor packages protect circuits from environmental factors and facilitate the routing of electrical signals between circuits and external systems. With the continuous development of electronic devices, the demand for semiconductor packages that can adapt to high-power applications and higher integration levels is constantly growing. These applications typically require larger package sizes to accommodate complex circuit systems and multiple interconnect components, thus placing higher demands on the structure and thermal performance of the substrates used in these packages.

[0003] Due to the affordability and compatibility with standard manufacturing processes, some semiconductor packages utilize organic or polymer substrates. However, these substrates typically lack the mechanical stiffness and thermal conductivity required for advanced applications, especially in large-scale packaging. Warpage and mechanical instability can occur, particularly when there is significant thermal stress or coefficient of thermal expansion (CTE) mismatch between different materials within the package. This mechanical instability can lead to component misalignment and potential electrical failures.

[0004] Various methods have been explored to mitigate warpage and improve the mechanical stability of semiconductor packages, but these methods have proven insufficient. It is important to recognize the need for new and improved systems and methods. Summary of the Invention

[0005] In one aspect, this disclosure relates to an apparatus comprising: a substrate including a first metallic material; a first layer coupled to the substrate; and a second layer coupled to the substrate via the first layer, the second layer comprising an organic material and configured to provide electrical connectivity to the substrate; wherein the first layer is configured to couple the second layer to the substrate, the first layer comprising: a third layer coupled to the second layer, the third layer comprising a first adhesive material configured to couple to the organic material; and a fourth layer coupled to the third layer, the fourth layer comprising a second adhesive material.

[0006] In another aspect, this disclosure relates to an apparatus comprising: a substrate including a first metallic material, the substrate including a first via extending through the substrate; a first layer coupled to the substrate; and a second layer coupled to the substrate via the first layer, the second layer comprising an organic material and configured to provide electrical connectivity to the substrate; wherein the first layer is configured to couple the second layer to the substrate, the first layer including a third layer coupled to the second layer, and the third layer including a first adhesive material configured to couple to the organic material.

[0007] In another aspect, this disclosure relates to an apparatus comprising: a substrate including a first metallic material; a first layer coupled to the substrate; and a second layer coupled to the substrate via the first layer, the second layer comprising an organic material and configured to provide electrical connectivity to the substrate; wherein the first layer is configured to couple the second layer to the substrate, the first layer comprising: a third layer coupled to the second layer, the third layer comprising a first adhesive material configured to couple to the organic material; and a fourth layer coupled to the third layer, the fourth layer comprising a second adhesive material, the fourth layer being configured to provide electrical isolation between the second layer and the substrate. Attached Figure Description

[0008] A further understanding of the nature and advantages of particular embodiments can be achieved by referring to the remainder of the specification and accompanying drawings, wherein the same element symbols are used to refer to similar components. In some examples, sublabels are associated with element symbols to indicate one of a plurality of similar components. When an element symbol is referenced without specifying an existing sublabel, it is intended to refer to all such plurality of similar components.

[0009] Figure 1 This is a simplified cross-sectional view illustrating an embodiment of the semiconductor device according to the present technology.

[0010] Figures 2A to 2F This is a simplified diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present technology. Detailed Implementation

[0011] This technology relates to semiconductor devices and methods of fabrication thereof. In one embodiment, the technology provides a device comprising a substrate including a first metallic material and a first layer coupled to the substrate. The device further includes a second layer coupled to the substrate via the first layer. The second layer comprises an organic material. The first layer comprises: a third layer including a first adhesive material configured to couple to the organic material; a fourth layer including a second adhesive material; and a fifth layer including a third adhesive material configured to couple to the first metallic material. This multilayer adhesive system achieves reliable bonding between organic and metallic components, thereby ensuring robust mechanical and electrical performance of the system. Other embodiments also exist.

[0012] As previously mentioned, organic substrates are widely used in semiconductor packaging to provide mechanical support and electrical connectivity. However, as packages become increasingly larger (e.g., exceeding 100 mm x 100 mm), these substrates exhibit significant limitations. For example, their relatively low elastic modulus leads to mechanical instability and warpage, with deformation levels exceeding 400 μm in some cases. Warpage can be caused by thermal stress resulting from the mismatch of the coefficients of thermal expansion (CTE) between different materials within the package, where CTE values ​​can range from 3 to 36 ppm. These mechanical instabilities can lead to component misalignment, unreliable electrical connections, and ultimately render the package unmanufacturable.

[0013] Several approaches have been explored to address these challenges. For example, some methods involve using glass substrates with high elastic moduli (e.g., 50 GPa to 150 GPa). While glass substrates offer improved stiffness, they are prone to crosstalk between conductive traces due to their dielectric properties. Other approaches rely on metallic substrates to improve mechanical stability and thermal conductivity. However, bonding organic materials to metallic substrates presents significant challenges due to thermal expansion mismatch and differences in adhesive properties. These issues can lead to delamination, cracking, and reduced reliability during thermal cycling or under mechanical stress. Furthermore, the use of metallic substrates introduces additional complexities, such as incompatibility with existing manufacturing processes and the need for advanced cooling technologies, making widespread implementation challenging.

[0014] In various embodiments, this technology provides semiconductor devices integrating high-stiffness metal substrates using a multilayer bonding system. The bonding system comprises one or more layers designed to bond dissimilar materials, thereby facilitating integration of the metal substrate with organic dielectric materials. The combined use of the high-stiffness substrate and the multilayer bonding system reduces warpage and enhances the mechanical stability of the semiconductor package, enabling the production of larger packages (e.g., exceeding 100 mm x 100 mm) without compromising manufacturability. The high elastic modulus of the metal substrate minimizes deformation under thermal and mechanical stresses, thereby maintaining the alignment and reliability of the packaged components. Furthermore, the improved thermal conductivity of the metal substrate promotes efficient heat dissipation, supporting the performance of high-power applications and preventing heat-related failures.

[0015] The following description is presented to enable those skilled in the art to make and use the invention and to incorporate it into a particular application context. Those skilled in the art will readily understand various modifications and uses in different applications, and the general principles defined herein are applicable to a wide range of embodiments. Therefore, the invention is not intended to be limited to the presented embodiments, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

[0016] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without being limited to these specific details. In other instances, well-known structures and apparatuses are shown in block diagram form rather than in detail in order to avoid obscuring the invention.

[0017] Readers should note all papers and documents submitted with and made publicly available with this specification, the contents of which are incorporated herein by reference. All features disclosed in this specification (including any appended claims, abstracts, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise. Therefore, unless expressly stated otherwise, each disclosed feature is merely one instance of a general set of equivalent or similar features.

[0018] Furthermore, any element not expressly referred to in the claims as a “component” for performing the specified function or a “step” for performing a particular function shall not be construed as a “component” or “step” as specified in paragraph 6 of Section 112 of 35 U.S.C. Specifically, the use of “step” or “action” in the claims herein is not intended to invoke the provisions of paragraph 6 of 35 U.S.C. 112.

[0019] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to the other element or that there may be an intermediary element between the elements. In contrast, when an element is referred to herein as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in the “direct” connection between the elements. However, the presence of a direct connection does not preclude the possibility of other connections in which intermediary elements may exist.

[0020] When an element is referred to herein as being "positioned" relative to another element in a certain way (e.g., positioned on, between, under, adjacent to, or otherwise relative to another element), it should be understood that the element may be positioned directly relative to the other element (e.g., directly on the other element) or that there may be an intervening element between the elements. In contrast, when an element is referred to as being "directly positioned" relative to another element, it should be understood that in the "direct" instance, there is no intervening element. However, the presence of direct positioning does not preclude other instances in which intervening elements may be present.

[0021] Similarly, when an element is referred to herein as being “joined” to another element, it should be understood that the element may be directly joined to the other element (without any intermediary element) or that there may be an intermediary element between the joined elements. In contrast, when an element is referred to as being “directly joined” to another element, it should be understood that there is no intermediary element in the “direct” joint between the elements. However, the presence of a direct joint does not preclude other forms of joint in which intermediary elements may be present.

[0022] Similarly, when an element is referred to herein as a “layer,” it should be understood that the layer may be a single layer or comprise multiple layers. For example, a conductive layer may comprise multiple or multiple layers of different conductive materials, and a dielectric layer may comprise multiple or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it should be understood that the coupled or connected layer may contain intermediary elements present between the coupled or connected layers. In contrast, when an element is referred to as being “directly” connected or coupled to another layer, it should be understood that there are no intermediary elements between the layers. However, the presence of a directly coupled or connected layer does not preclude the existence of other connections where intermediary elements may be present.

[0023] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for interpretive purposes only and are not limited to any fixed direction or orientation. Specifically, they are used merely to indicate the relative position and / or orientation between various parts of an object and / or component.

[0024] Furthermore, for ease of description, the methods and processes described herein may be described in a specific order. However, it should be understood that, unless the context otherwise requires, intermediate processes may occur before and / or after any part of the described process, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0025] Unless otherwise indicated, all figures used herein to express quantity, size, etc., should be understood to be modified by the term “about” in all instances. In this application, unless specifically stated otherwise, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms “and” and “or” means “and / or”. Furthermore, the use of the terms “including” and “having”, as well as other forms (e.g., “includes”, “included”, “has”, “have”, and “had”), should be considered non-exclusive. Moreover, terms such as “element” or “component” cover both elements and components comprising one unit and elements and components comprising more than one unit, unless specifically stated otherwise.

[0026] As used herein, the phrase “at least one of…” following a series of items (where the terms “and” or “or” are used to separate any one of the items) modifies the entire list, not each member of the list (i.e., each item). The phrase “at least one of…” does not require selection of at least one of every listed item; rather, the phrase allows for the inclusion of at least one of any of the items and / or at least one of any combination of items. For example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; and / or any combination of A, B, and C. This is explicitly stated in examples where the intention is to select “at least one of each of A, B, and C” or alternatively, “at least one of A, at least one of B, and at least one of C.”

[0027] One general aspect includes an apparatus comprising a substrate comprising a first metallic material. The apparatus further includes a first layer coupled to the substrate and a second layer coupled to the substrate via the first layer. The second layer comprises an organic material and is configured to provide electrical connectivity to the substrate. The first layer is configured to couple the second layer to the substrate. The first layer includes a third layer coupled to the second layer. The third layer includes a first adhesive material configured to couple to the organic material. The first layer further includes a fourth layer coupled to the third layer. The fourth layer includes a second adhesive material.

[0028] The implementation may include one or more of the following features. The first layer further includes a fifth layer coupled to the fourth layer and the substrate, the fifth layer including a third adhesive material configured to couple to the first metallic material. The substrate is characterized by a first thickness, the fifth layer by a second thickness, and the ratio of the first thickness to the second thickness is greater than or equal to 10:1. The ratio of the first thickness to the second thickness is less than or equal to 5000:1. The third adhesive material includes at least one of titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiO2), tantalum (Ta), or titanium tungsten nitride (TiWN). The substrate includes a first via extending through the substrate, the first via including the first metallic material. The substrate further includes a sixth layer coupled to the first via, the sixth layer being configured to provide electrical isolation between the first via and the substrate. The first via is characterized by a first diameter, the fourth layer by a third thickness, and the ratio of the third thickness to the first diameter is less than or equal to 250:1. The first adhesive material includes at least one of organosiloxane, hexamethyldisilazane (HMDS), or aminosilane. The second adhesive material includes at least one of silicon oxide (SiO2), silicon nitride (SiN), or silicon carbonitride (SiCN).

[0029] According to another embodiment, the present technology provides an apparatus including a substrate, the substrate comprising a first metallic material. The substrate includes a first via extending through the substrate. The apparatus further includes a first layer coupled to the substrate and a second layer coupled to the substrate via the first layer. The second layer comprises an organic material and is configured to provide electrical connectivity to the substrate. The first layer is configured to couple the second layer to the substrate, the first layer includes a third layer coupled to the second layer, and the third layer includes a first adhesive material configured to couple to the organic material.

[0030] The implementation may include one or more of the following features: The first layer further includes a fourth layer coupled to the third layer, the fourth layer including a second adhesive material, and the second adhesive material including at least one of silicon oxide (SiO2), silicon nitride (SiN), or silicon carbonitride (SiCN). The first layer further includes a fifth layer coupled to the fourth layer and the substrate, and the fifth layer including a third adhesive material configured to couple to the first metallic material. The substrate is characterized by a first thickness, the fifth layer by a second thickness, and the ratio of the first thickness to the second thickness is greater than or equal to 10:1. The first via is characterized by a first diameter, the fourth layer by a third thickness, and the ratio of the third thickness to the first diameter is less than or equal to 250:1. The first adhesive material includes at least one of organosiloxane, hexamethyldisilazane (HMDS), or aminosilane. The first metallic material includes at least one of molybdenum, copper, aluminum, tungsten, titanium, nickel, or vanadium.

[0031] According to another embodiment, the present technology provides an apparatus comprising: a substrate including a first metallic material; a first layer coupled to the substrate; and a second layer coupled to the substrate via the first layer. The second layer includes an organic material and is configured to provide electrical connectivity to the substrate. The first layer is configured to couple the second layer to the substrate, and the first layer includes a third layer coupled to the second layer. The third layer includes a first adhesive material configured to couple to the organic material. The first layer includes a fourth layer coupled to the third layer, the fourth layer including a second adhesive material, and the fourth layer is configured to provide electrical isolation between the second layer and the substrate. In some embodiments, the first layer further includes a fifth layer coupled to the fourth layer and the substrate, the substrate being characterized by a first thickness, the fifth layer being characterized by a second thickness, and the ratio of the first thickness to the second thickness being greater than or equal to 10:1. The substrate includes a first via extending through the substrate, the first via being characterized by a first diameter, the fourth layer being characterized by a third thickness, and the ratio of the third thickness to the first diameter being less than or equal to 250:1. The first adhesive material includes at least one of organosiloxane, hexamethyldisilazane (HMDS), or aminosilane.

[0032] Figure 1This is a simplified cross-sectional view illustrating a semiconductor device 100 according to an embodiment of the present technology. This figure is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art.

[0033] As shown, semiconductor device 100 includes substrate 101. For example, the term "substrate" can refer to a material or structure that supports or carries other components or devices. Substrate 101 may be configured to provide mechanical support for other layers or components and form portions of electrical and thermal paths in the device. Substrate 101 may be a packaging substrate, an interposer, a printed circuit board, and / or the like. Substrate 101 may contain, but is not limited to, one or more materials, such as metals, silicon, organic materials, ceramics, diamond, or any combination thereof. In some instances, substrate 101 contains a first metallic material. The metallic material may contain, but is not limited to, one or more materials, such as molybdenum, copper, aluminum, tungsten, titanium, nickel, or alloys thereof.

[0034] In some embodiments, substrate 101 comprises a high-stiffness metal substrate designed to reduce warpage and enhance the mechanical stability of large-scale semiconductor packages. For example, the elastic modulus of substrate 101 may be in the range of 100 GPa to 500 GPa, enabling it to resist deformation and maintain package reliability during thermal cycling or high-power operation. Using a metal substrate with a high elastic modulus (e.g., molybdenum with approximately 300 GPa) allows substrate 101 to maintain alignment and structural integrity under thermal and mechanical stress. Depending on application and design requirements, substrate 101 may be characterized by a thickness ranging from approximately 0.1 mm to 10 mm.

[0035] In some embodiments, substrate 101 includes a first side 111 and a second side 112. The first side 111 may be positioned relative to the second side 112. For the purposes of this description, the first side may also be referred to as the top side, upper side, or upper surface. The second side may be referred to as the bottom side, lower side, bottom side, or back side. These terms are used interchangeably throughout this description to describe various embodiments and are not intended to limit the scope of the technology. In various embodiments, both the first side 111 and the second side 112 of substrate 101 may include corresponding multilayer structures that facilitate bonding, electrical connectivity, and thermal management within the semiconductor device 100. For example, the first side may include layers 102a, 103a, 104a, and 105a and an interconnect 106a, while the second side may include corresponding layers 102b, 103b, 104b, and 105b and an interconnect 106b. Depending on the embodiment, these layers may be positioned on either side of substrate 101 to facilitate efficient integration of stacked layers and interconnects within the semiconductor device 100.

[0036] In various embodiments, the semiconductor device 100 further includes a first layer 110 coupled to a substrate 101. For example, the first layer 110 may be coupled to a first side of the substrate 101. In some instances, a second layer 105a may be coupled to the substrate 101 via the first layer 110. The second layer 105a may be configured to provide electrical connectivity and signal transmission within the semiconductor device 100. The second layer 105a may also facilitate the overall stacking structure of the semiconductor package, thereby enabling the integration of additional functional layers and components. Depending on the application, the second layer 105a may be characterized by a thickness ranging from about 200 nm to 50 μm.

[0037] In some embodiments, the second layer 105a may include conductive paths and interconnect structures, such as the first connector 106a. For example, the term "connector" may refer to a conductive feature that facilitates electrical communication between different layers or components of a semiconductor device. Connectors may include, but are not limited to, vias, conductive traces, pads, solder joints, and / or the like. In various instances, the first connector 106a may include a conductive material such as copper, tungsten, or aluminum, and may be configured to electrically couple the second layer 105a to other components of the semiconductor device 100, such as the substrate 101 or external components.

[0038] In some embodiments, the second layer 105a may further comprise an organic material configured to provide electrical insulation between conductive paths and interconnect structures within the second layer 105a. Examples of organic materials may include, but are not limited to, Ajinomoto laminate (ABF), polyimide, epoxy resin, and / or the like. In some cases, the organic material may be used as part of the laminate structure to support multilayer interconnects and enable the integration of complex circuit paths.

[0039] However, bonding an organic second layer (e.g., second layer 105a) to a metal substrate (e.g., substrate 101) presents significant challenges due to differences in material properties. For example, CTE mismatch between the organic material and the metal substrate can lead to mechanical instability during operation or thermal cycling, which can result in delamination, cracking, or warping, ultimately affecting the reliability and performance of the semiconductor package. Furthermore, organic materials often exhibit poor adhesion to metal surfaces, leading to weak interfaces and potential failures under mechanical or thermal stress.

[0040] To address these challenges, the first layer 110 can be used as an adhesive layer to facilitate bonding of the second layer 105a to the substrate 101. Depending on the implementation, the first layer 110 may comprise one or more layers, each designed to bond different materials, thereby facilitating the integration of the metallic substrate with the organic material. For example, the first layer 110 may comprise at least one of a third layer 104a, a fourth layer 103a, a fifth layer 102a, and / or the like. The specific configuration of the first layer 110 may vary based on design requirements and performance considerations. In some implementations, the third layer 104a and / or the fifth layer 102a may be optional. For example, the first layer 110 may comprise a fourth layer 103a, or may comprise a combination of layers tailored to specific bonding, electrical, or thermal requirements.

[0041] In some embodiments, the third layer 104a is coupled to the second layer 105a and includes a first adhesive material configured to effectively bond with the organic material of the second layer 105a. Examples of the first adhesive material may include, but are not limited to, organosiloxanes, hexamethyldisilazane (HMDS), aminosilanes, polymeric adhesives, and / or the like. These materials enhance adhesive strength through chemical or physical interaction with the organic dielectric material of the second layer 105a.

[0042] In various embodiments, the fourth layer 103a may be coupled to the third layer 104a and serve as an intermediate layer providing electrical insulation and thermal stress management. For example, the fourth layer 103a is configured to provide electrical isolation between the second layer 105a and the substrate 101. In some embodiments, the fourth layer 104a may contain a second adhesive material. For example, the second adhesive material may contain a silicon-based dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), or alloys thereof. The second adhesive material ensures compatibility between the organic stacked layer (e.g., the second layer 105a) and the substrate (e.g., the substrate 101) by reducing stress concentration at the interface and managing differences in CTE. In various embodiments, the first adhesive material of the third layer 104a improves the adhesion between the organic material of the second layer 105a and the silicon-based dielectric material within the fourth layer 103a, thereby achieving smooth integration of the adhesive system. Depending on the implementation, the third layer 104a may be characterized by a thickness ranging from thin to monolayer or sub-monolayer to several nanometers.

[0043] In some embodiments, the fifth layer 102a may be coupled to the fourth layer 103a and the substrate 101. The fifth layer 102a may be configured to interface with a first metal material of the substrate 101, thereby providing a robust mechanical bond between the stacked layer (e.g., the second layer 105a) and the substrate (e.g., the substrate 101). The fifth layer 102a may include a third adhesive material, which may be configured to couple to the first metal material. Examples of the third adhesive material may include, but are not limited to, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiO2), tantalum (Ta), or titanium tungsten nitride (TiWN). These materials provide strong adhesion to the metal substrate (e.g., the substrate 101) through chemical and / or physical bonding mechanisms (e.g., chemical bonding or mechanical interlocking). The third adhesive material may be designed to allow good adhesion between the metal substrate and the silicon-based dielectric material in the fourth layer 103a, thereby ensuring compatibility across the adhesive system. Depending on the implementation, the fifth layer 102a can be used as a conductor to provide a conductive path for electrical signals, or as an insulator to ensure reliable electrical isolation.

[0044] In various embodiments, the thickness of substrate 101 is characterized by a first thickness, and the thickness of the fifth layer 102a is characterized by a second thickness. In some instances, the ratio of the first thickness to the second thickness may be greater than or equal to 10:1 and / or less than or equal to 5000:1. For example, the ratio may be in the range of 10:1 to 50:1, 100:1 to 500:1, or 1000:1 to 3000:1. This ensures that substrate 101 provides sufficient structural support and thermal conductivity, while the fifth layer 102a remains thin enough to maintain efficient bonding without adding excessive volume to the overall package.

[0045] According to some embodiments, substrate 101 may include one or more vias (e.g., first via 107a, second via 107b, etc.). For example, the term "via" may refer to a conductive path connecting different layers of the substrate. These vias may be configured to provide various functions, including but not limited to vertical interconnects, signal transmission, power distribution, heat dissipation, mechanical support, or the like. These vias enable vertical electrical or thermal connectivity, thereby ensuring efficient signal transmission and heat dissipation across multiple layers. The vias may contain conductive materials such as molybdenum, copper, aluminum, tungsten, titanium, nickel, or alloys thereof.

[0046] In some instances, the first via 107a and / or the second via 107b may extend vertically through the substrate 101, thereby facilitating connectivity between the stacked layer (e.g., the second layer 105a) and external components. For example, the first via 107a may be coupled to a first connector 106a configured to transmit electrical signals or power to an external circuit system or device. These vias enable vertical electrical or thermal connectivity, ensuring efficient signal transmission and heat dissipation across multiple layers.

[0047] Depending on the implementation, the material composition of the vias may match or differ from that of the substrate 101. For example, the first via 107a may contain a first metallic material (e.g., molybdenum, copper, or aluminum) that ensures compatibility with the substrate in terms of thermal expansion and conductivity. In some cases, the second via 107b may contain a second metallic material different from the first metallic material. This facilitates adjusting the effective CTE of the substrate 101, thereby reducing stress at the interface during thermal cycling. Furthermore, changing the material composition allows for optimization of the resistance within the vias, enabling designs to be adapted to specific performance requirements, such as minimizing signal loss in high-frequency applications or managing power dissipation in high-current paths.

[0048] In various embodiments, the first via 107a is characterized by a first diameter, and the fourth layer 103a is characterized by a third thickness. The ratio of the first diameter to the third thickness can be greater than or equal to 1:1 and / or less than or equal to 250:1. This ensures that the via has a sufficient cross-sectional area to conduct electrical signals or effectively dissipate heat, while the thickness of the fourth layer 103a provides sufficient electrical isolation and mechanical stress distribution. Furthermore, the diameter of the via can vary depending on the implementation. For example, the first via 107a can have a larger diameter to support high current power delivery, while the second via 107b can have a smaller diameter optimized for signal routing.

[0049] To ensure proper electrical insulation and mechanical stability, substrate 101 may further include an insulating layer (e.g., a sixth layer 108) coupled to the first via 107a. The sixth layer 108 may surround the first via 107a to electrically isolate it from adjacent conductive structures within substrate 101. In some instances, the sixth layer 108 may comprise a material such as silicon dioxide, silicon nitride, or other dielectric materials. The sixth layer 108 may act as a barrier to prevent electrical short circuits between the conductive via and the substrate material. Additionally, the sixth layer 108 may provide mechanical support for the via (e.g., the first via 107a), distributing stress caused by thermal cycling. In high-power applications, the sixth layer 108 may also function as a thermal barrier to manage heat flow between substrate 101 and via 107a to maintain optimal device performance.

[0050] In various embodiments, the second side 112 of substrate 101 may include a structure that is a mirror image of the multilayer arrangement on the first side 111, including layers such as a second layer 105b, a third layer 104b, a fourth layer 103b, and a fifth layer 102b. These layers collectively form part of a double-sided bonding and stacking system, thereby achieving electrical connectivity, thermal management, and mechanical stability on both sides of substrate 101. In some embodiments, semiconductor device 100 further includes interconnects 109. For example, the term "interconnect" may refer to a structure or mechanism that electrically connects two or more layers or components in a semiconductor device. Interconnect 109 may include, but is not limited to, metal traces, solder bumps, conductive adhesives, wire bonds, ball grid arrays (BGAs), and / or the like. In some cases, interconnect 109 may be coupled to the second layer 105b, thereby facilitating connectivity between the second layer 105b and other components within the package (e.g., a ground plane or external structures).

[0051] It should be understood that the semiconductor device 100 incorporates a high-stiffness substrate and a multilayer bonding system to achieve reliable bonding and mechanical stability in large-scale semiconductor packaging. The use of a high-stiffness substrate minimizes warpage, thereby ensuring structural integrity and alignment during thermal cycling and under mechanical stress.

[0052] Figures 2A to 2F These are simplified diagrams illustrating a method 200 for fabricating a semiconductor device according to embodiments of the present technology. These diagrams are merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art.

[0053] In various implementations, method 200 can be used to fabricate semiconductor devices, for example... Figure 1 The semiconductor device 100 described herein can be used across a wide range of applications, including high-power electronics, large-scale packaging, high-density integrated circuits, and / or the like. In some embodiments, method 200 may incorporate a high-stiffness substrate to minimize warpage and deformation under thermal and mechanical stress. The method may also employ a multilayer bonding system to facilitate adhesion between different materials (e.g., a metal substrate and an organic dielectric layer) to ensure reliable mechanical stability and electrical connectivity of the entire device.

[0054] like Figure 2AAs shown, method 200 begins with the fabrication of substrate 201. Substrate 201 may comprise a high-stiffness metal substrate designed to reduce warpage and enhance the mechanical stability of large-scale semiconductor packages. For example, substrate 201 comprises a first metallic material, which may include, but is not limited to, one or more materials, such as molybdenum, copper, aluminum, tungsten, titanium, nickel, or alloys thereof. Substrate 201 includes a first side 211 and a second side 212, each of which may support a multilayer structure for bonding, signal routing, and thermal management. In some cases, a temporary bonding adhesive may be used to mount substrate 201 onto a carrier to stabilize it during subsequent fabrication steps.

[0055] In some implementations, the adhesive layer (e.g., Figure 1 A first layer 110 is deposited on one or both sides of the substrate 101 to facilitate bonding of subsequent stacked layers. Depending on the embodiment, the adhesive layer may comprise one or more layers. For example, fifth layers 202a and 202b may be deposited on the first side 211 and the second side 212 of the substrate 201, respectively. These layers may include a third adhesive material, such as titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiO2), tantalum (Ta), or titanium tungsten nitride (TiWN). These materials effectively bond to the metal surface of the substrate through chemical and / or physical bonding mechanisms, thereby providing a strong bond between the substrate 101 and subsequent layers.

[0056] The deposition of the fifth layers 202a and 202b can be performed using various techniques, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, and / or similar methods. In some cases, it may be desirable to prepare the surface of the substrate 101 before beginning the deposition process. For example, preparation may include surface polishing or planarization to remove irregularities and produce a smooth surface. Polishing can be performed using hot rolling, mechanical polishing, chemical mechanical planarization (CMP), or other abrasive techniques.

[0057] In various embodiments, such as Figure 2B As shown, one or more vias (e.g., first via 207a and second via 207b) can be formed in substrate 201. For example, these vias are etched through the substrate material to create vertical paths that enable electrical and thermal connectivity between multilayer structures on a first and second side of substrate 201. Depending on the substrate material and the desired properties of the vias, various techniques can be used to form the first via 207a and second via 207b, including but not limited to laser drilling, mechanical drilling, chemical etching, die sintering, 3D printing, or the like. In some cases, photolithography can be used to define precise patterns on the surface of substrate 201.

[0058] After etching the vias, a pad oxide may be deposited to coat the inner surface of the vias. For example, a sixth layer 208 may be coupled to the first via 207a to provide electrical insulation and prevent direct contact between the conductive material to be filled later and the substrate material. In some instances, the sixth layer 208 may comprise a material such as silicon dioxide, silicon nitride, or other dielectric materials. The deposition of the sixth layer 208 may be performed using various techniques, such as spin coating, plasma-enhanced chemical vapor deposition (PECVD), subatmospheric pressure chemical vapor deposition (SACVD), photolithography, dry etching, and / or the like. The number and configuration of vias may vary depending on the specific implementation. For example, the first via 207a and the second via 207b may comprise different geometries, such as straight, inclined, angled, curved, or stepped sidewalls.

[0059] like Figure 2C As shown, method 200 further includes depositing fourth layers 203a and 203b. For example, fourth layers 203a and 203b may be coupled to fifth layers 202a and 202b, respectively. Fourth layers 203a and 203b may include a second adhesive material. For example, the second adhesive material may include a silicon-based dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), or alloys thereof. Fourth layers 203a and 203b may be configured to provide electrical insulation, thermal stress management, and bonding between the substrate 201 and subsequent stacked layers. The deposition of fourth layers 203a and 203b may be performed using techniques such as PECVD, PVD, photolithography, dry etching, wet etching, and / or similar techniques. In some instances, the fourth layers 203a and 203b may have thicknesses ranging from 20 nm to 5 μm.

[0060] In some embodiments, if the fourth layers 203a and 203b are thin enough, they can partially coat the inner surfaces of the vias lined with oxide layers (e.g., the sixth layer 208). This allows direct contact between the silicon-based dielectric adhesive layer and the pad oxide, eliminating the need for additional patterning. Alternatively, the vias can be etched after depositing adhesive layers (e.g., the fourth layers 203a to b and / or the fifth layers 202a to b) on both sides of the substrate 201 to ensure uniform coverage and strong adhesion across all interfaces.

[0061] After depositing the fourth layers 203a to 203b, the vias can be filled with a conductive material (e.g., copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, or the like) to ensure conductivity and structural integrity. The filling process can be performed using various techniques, such as electroplating, electroless plating, CVD, PVD, and / or the like. In some cases, a seed layer can be deposited first using sputtering or CVD to promote uniform deposition of the conductive material. Depending on the implementation, the material composition of the vias can match or differ from the material of the substrate 201. For example, the first via 207a may contain a first metallic material, while the second via 207b may contain a second metallic material different from the first metallic material. In some cases, excess material deposited during this process is subsequently removed using techniques such as CMP or etching to ensure a smooth and uniform surface for further processing.

[0062] like Figure 2D As shown, method 200 further includes depositing a third layer 204a. For example, the third layer 204a may be deposited on the first side 211 and coupled to the fourth layer 203a. In some embodiments, the third layer 204a serves as an adhesive interface between a silicon-based dielectric layer (e.g., the fourth layer 203a) and subsequent stacked layers. For example, the third layer 204a may contain a first adhesive material configured to effectively bond with an organic material. Examples of the first adhesive material may include, but are not limited to, organosiloxanes, hexamethyldisilazane (HMDS), aminosilanes, polymer adhesives, and / or the like. The deposition of the third layer 204a may be performed using techniques such as spin coating, vapor primer, CVD, PECVD, and / or the like. Depending on the embodiment, the third layer 204a may be characterized by a thickness ranging from thin to monolayer or sub-monolayer to several nanometers.

[0063] After depositing the third layer 204a, one or more stacked layers can be formed to achieve wiring, insulation, and thermal management. For example, a second layer 205a can be deposited on the first side 211 and coupled to the third layer 204a. The deposition of the second layer 205a can be performed using techniques such as spin coating, lamination, CVD, and / or similar methods. Depending on the design and application, the second layer 205a can have a thickness ranging from about 200 nm to 50 μm. In some instances, the second layer 205a may contain an organic material configured to provide electrical insulation between conductive paths and interconnect structures within the second layer 205a. Examples of organic materials may include, but are not limited to, Ajinomoto laminate (ABF), polyimide, epoxy resin, and / or the like.

[0064] In some embodiments, organic materials may be used as part of a stacked structure to support multilayer interconnects and enable the integration of complex circuit paths. For example, a first connector 206a may be formed in a second layer 205a to establish electrical paths between different layers or components of a semiconductor device. The first connector 206a may include conductive features such as vias, conductive traces, pads, solder joints, and / or the like. The first connector 206a may contain conductive materials such as copper, tungsten, aluminum, and / or the like. In various embodiments, the formation of the first connector 206a may involve processes such as electroplating, sputtering, or PVD, followed by photolithography and etching to define precise geometries.

[0065] Similarly, such as Figure 2E As shown, a third layer 204b and a second layer 205b may be formed on a second side 212 of the substrate 201. For example, the third layer 204b may act as an adhesive layer to facilitate strong bonding between the fourth layer 203b and subsequent stacked layers (e.g., the second layer 205b). In some instances, a second connector 206b may be formed within the second layer 205b to enable electrical pathways on the second side 212.

[0066] like Figure 2F As shown, method 200 further includes forming interconnects 209, which can be configured to couple substrate 201 to external components. Interconnects 209 may include, but are not limited to, metal traces, solder bumps, conductive adhesives, wire bonding, ball grid arrays (BGAs), and / or the like. In some instances, interconnects 209 may include conductive materials such as copper, aluminum, gold, silver, solder alloys (e.g., tin-lead alloys or lead-free alloys), and / or the like. The formation of interconnects 209 may involve various techniques, such as thermocompression bonding, reflow soldering, electroplating, and / or the like.

[0067] Method 200 incorporates the use of high-stiffness substrates and multilayer bonding systems to achieve reliable bonding and electrical connectivity between different materials, such as metals and organic dielectrics. These features enhance mechanical stability and minimize warpage, making the method ideal for large-scale semiconductor packaging and high-density applications. Furthermore, the process's compatibility with standard fabrication techniques, such as PECVD, PVD, and electroplating, supports efficient integration into existing manufacturing workflows, thereby promoting widespread adoption across a variety of applications.

[0068] While the foregoing is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the above description and illustrations should not be construed as limiting the scope of the invention as defined by the appended claims.

Claims

1. An apparatus comprising: A substrate comprising a first metallic material; The first layer is coupled to the substrate; as well as A second layer, coupled to the substrate via the first layer, the second layer comprising an organic material and configured to provide electrical connectivity to the substrate; The first layer is configured to couple the second layer to the substrate, and the first layer includes: A third layer, coupled to the second layer, and the third layer includes a first adhesive material configured to couple to the organic material; as well as A fourth layer, which is coupled to the third layer, the fourth layer comprising a second adhesive material.

2. The device according to claim 1, wherein: The first layer further includes a fifth layer coupled to the fourth layer and the substrate, the fifth layer including a third adhesive material configured to couple to the first metallic material; and The substrate is characterized by a first thickness, the fifth layer is characterized by a second thickness, and the ratio of the first thickness to the second thickness is greater than or equal to 10:

1.

3. The device according to claim 2, wherein the ratio of the first thickness to the second thickness is less than or equal to 5000:

1.

4. The device according to claim 2, wherein the third adhesive material comprises at least one of titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiO2), tantalum (Ta), or titanium tungsten nitride (TiWN).

5. The device of claim 1, wherein the substrate includes a first through-hole extending through the substrate, the first through-hole comprising the first metallic material.

6. The device of claim 5, wherein the substrate further includes a sixth layer coupled to the first via, the sixth layer being configured to provide electrical isolation between the first via and the substrate.

7. The device according to claim 5, wherein the first through hole is characterized by a first diameter, the fourth layer is characterized by a third thickness, and the ratio of the third thickness to the first diameter is less than or equal to 250:

1.

8. The device according to claim 1, wherein the first adhesive material comprises at least one of organosiloxane, hexamethyldisilazane (HMDS), or aminosilane.

9. The device according to claim 1, wherein the second adhesive material comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), or silicon carbonitride (SiCN).

10. An apparatus comprising: A substrate comprising a first metallic material, the substrate including a first through-hole extending through the substrate; The first layer is coupled to the substrate; as well as A second layer, coupled to the substrate via the first layer, the second layer comprising an organic material and configured to provide electrical connectivity to the substrate; The first layer is configured to couple the second layer to the substrate, the first layer includes a third layer coupled to the second layer, and the third layer includes a first adhesive material configured to couple to the organic material.

11. The device of claim 10, wherein the first layer further comprises a fourth layer coupled to the third layer, the fourth layer comprising a second adhesive material, and the second adhesive material comprising at least one of silicon oxide (SiO2), silicon nitride (SiN), or silicon carbonitride (SiCN).

12. The device of claim 11, wherein the first layer further comprises a fifth layer coupled to the fourth layer and the substrate, and the fifth layer comprises a third adhesive material configured to couple to the first metallic material.

13. The device of claim 12, wherein the substrate is characterized by a first thickness, the fifth layer is characterized by a second thickness, and the ratio of the first thickness to the second thickness is greater than or equal to 10:

1.

14. The device of claim 11, wherein the first through hole is characterized by a first diameter, the fourth layer is characterized by a third thickness, and the ratio of the third thickness to the first diameter is less than or equal to 250:

1.

15. The device of claim 10, wherein the first adhesive material comprises at least one of organosiloxane, hexamethyldisilazane (HMDS), or aminosilane.

16. The device of claim 10, wherein the first metallic material comprises at least one of molybdenum, copper, aluminum, tungsten, titanium, nickel, or vanadium.

17. An apparatus comprising: A substrate comprising a first metallic material; The first layer is coupled to the substrate; as well as A second layer, coupled to the substrate via the first layer, the second layer comprising an organic material and configured to provide electrical connectivity to the substrate; The first layer is configured to couple the second layer to the substrate, and the first layer includes: A third layer, coupled to the second layer, and the third layer includes a first adhesive material configured to couple to the organic material; as well as A fourth layer coupled to the third layer, the fourth layer including a second adhesive material, the fourth layer being configured to provide electrical isolation between the second layer and the substrate.

18. The device of claim 17, wherein the first layer further comprises a fifth layer coupled to the fourth layer and the substrate, the substrate being characterized by a first thickness, the fifth layer being characterized by a second thickness, and the ratio of the first thickness to the second thickness being greater than or equal to 10:

1.

19. The device of claim 17, wherein the substrate includes a first via extending through the substrate, the first via being characterized by a first diameter, the fourth layer being characterized by a third thickness, and the ratio of the third thickness to the first diameter being less than or equal to 250:

1.

20. The device of claim 17, wherein the first adhesive material comprises at least one of organosiloxane, hexamethyldisilazane (HMDS), or aminosilane.

Images