A heterogeneous die system integration chip and method of fabrication

Abstract

This invention relates to the field of advanced semiconductor packaging and chiplet integration technology, specifically disclosing a heterogeneous die system-on-a-chip and its fabrication method. The method includes: S1: providing an adapter board, the top surface of which is provided with a first I / O pad, and forming a first metal interconnect region above the first I / O pad, or using the first I / O pad as the first metal interconnect region; S2: providing a chiplet, the top surface of which is provided with a second I / O pad, and fabricating a second metal interconnect region on the top surface of the chiplet. This invention achieves self-aligned interconnection of the metal interconnect regions between the chiplet and the adapter board by combining an open area on the top surface of the adapter board with selective deposition, eliminating the need for high-precision photolithography alignment and significantly reducing process complexity. Simultaneously, this method supports multi-layer PAD expansion, multi-array parallel interconnection, wafer-level batch integration, and various layout methods, achieving high-density, low-latency, and high-reliability chiplet interconnection.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging and chiplet integration technology, specifically to a chip and its fabrication method that achieves high-density electrical interconnection between the chiplet and the adapter board through top edge interconnection. Background Technology

[0002] In the post-Moore's Law era, chip integration technology, by integrating chips (chips) with different process nodes and functions into a single package, has become a key means of improving system performance. Current chip integration methods mostly employ 2.5D silicon interposers or 3D stacking technology, which suffer from the following bottlenecks: 1. Limited interconnect density: Although the through silicon via (TSV) technology is mature, it has a large aspect ratio, complex process and high cost.

[0003] 2. Difficulty in sidewall integration: Existing technologies rarely involve direct electrical interconnection between chips using chip sidewalls, mainly due to the difficulty of sidewall processing and the alignment accuracy problem under small pitch.

[0004] 3. High process complexity: Traditional sidewall wiring requires multiple photolithography and etching processes, making it difficult to achieve precise docking of the sidewall electrodes of the mother core and the daughter core.

[0005] Therefore, there is an urgent need for a chip sidewall interconnect technology that can simplify the process and achieve high density and low cost. Summary of the Invention

[0006] To address the aforementioned problems, the present invention aims to provide a method for fabricating a heterogeneous die system-on-a-chip, comprising the following steps: S1: Provide an adapter board, the top surface of which is provided with a first I / O pad, and a first metal interconnect area is formed above the first I / O pad or the first I / O pad is used as the first metal interconnect area; S2: A core is provided, the top surface of which is provided with a second I / O pad, a second metal interconnect region is prepared on the top surface of the core, and the second I / O pad is electrically led to the edge of the top surface of the core, so that the second metal interconnect region is located at the edge of the top surface of the core. S3: The core particle and the adapter plate are bonded and fixed together by a bonding layer, so that the second metal interconnect area located at the edge of the top surface of the core particle and the first metal interconnect area located on the top surface of the adapter plate are opposite each other in the horizontal direction with a gap, and both the first metal interconnect area and the second metal interconnect area are exposed. S4: Perform a selective metal deposition process, causing the metal material to nucleate and grow only on the exposed surfaces of the first and second metal interconnect regions, and to bridge and fuse within the horizontal gap to form a horizontally oriented electrical interconnect structure.

[0007] Optionally, the first metal interconnect region is at least one of the following: The first I / O pad itself is a protruding structure and directly serves as the first metal interconnect area; The first I / O pad is a planar structure, and metal is grown on its surface through a metal deposition process. The resulting metal structure and the first I / O pad together constitute the first metal interconnect region. An insulating layer is deposited above the first I / O pad, interconnect vias are etched to expose the pads, and metal fills the interconnect vias and extends above the insulating layer to form a protruding first metal interconnect region. The sidewalls of the first I / O pad are exposed in the narrow slit.

[0008] Optionally, the method for fabricating the second metal interconnect region on the top surface of the core includes: An insulating layer is deposited over the second I / O pad, and photolithography is used to form interconnect vias to expose the pads. Metal-filled interconnect vias form vertical interconnects; A metal layer is deposited and patterned above the insulating layer to form a metal wiring layer extending to the edge of the top surface of the core. The metal wiring layer is electrically connected to the interconnect to form a second metal interconnect region.

[0009] Optionally, the first metal interconnect region and / or the second metal interconnect region are multi-layer structures, respectively corresponding to the multi-layer I / O pads of the adapter board or the core, and multi-layer interconnection is achieved through the fabrication of multi-layer interconnects and multi-layer metal wiring layers.

[0010] Optionally, the first metal interconnect region and the second metal interconnect region are arranged in multiple arrays, each corresponding to multiple I / O channels. In step S4, multiple interconnect structures are formed simultaneously in multiple horizontal gaps, which are respectively connected to the corresponding first metal interconnect region and the second metal interconnect region to realize multi-channel parallel signal transmission.

[0011] Optionally, the adapter board is a mother wafer, on which multiple mother granules are integrated; the granules are sub-granules, and multiple sub-granules are integrated in parallel on the mother wafer using the method described above.

[0012] Optionally, the core is located in the middle region of the adapter plate, the first metal interconnect area is distributed around the outer edge of the top surface of the adapter plate, and the second metal interconnect area is located at the edge of the top surface of the core, with the two corresponding to each other in the horizontal direction.

[0013] A heterogeneous die system-on-a-chip, fabricated by the method described above, includes: The adapter board has a first metal interconnection area on its top surface, and the first metal interconnection area is electrically connected to the internal circuit of the adapter board. The core has a second metal interconnect area on its top edge. The second metal interconnect area is electrically connected to the internal circuit of the core. The core is bonded and fixed to the adapter plate through a bonding layer. The second metal interconnect area and the first metal interconnect area are opposite to each other in the horizontal direction and have a gap. A horizontal interconnect structure, located within the gap, forms a metallurgical bond with the first and second metal interconnect regions, thereby achieving an electrical connection between the adapter plate and the core.

[0014] Optionally, the first metal interconnect region and the second metal interconnect region are arranged in multiple arrays, and there are multiple horizontal interconnect structures, which are respectively connected to the corresponding first metal interconnect region and the second metal interconnect region to form a multi-channel parallel interconnect.

[0015] Optionally, the first metal interconnect region and / or the second metal interconnect region are multi-layer structures, respectively corresponding to the multi-layer I / O pads of the adapter board or the core chip, and the horizontal interconnect structure is multi-layered, respectively connecting the first metal interconnect region and the second metal interconnect region of the corresponding layer to realize multi-layer interconnection.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. Fundamentally solve the defects of slot plating: Change the metal deposition area from a closed slot to an open top horizontal area, which greatly improves the flow of plating solution, results in uniform metal deposition, low void ratio, and facilitates subsequent inspection and testing. 2. The first metal interconnect area can be implemented in a flexible manner: it can be implemented in various ways, such as using original raised pads, growing planar pads upwards, or using interconnect vias (VIA) to bring out the protrusions, to adapt to different process requirements; 3. L-shaped bridge interconnect structure: Planar solder pads can form L-shaped bridge interconnects by growing metal upwards, reducing the process requirements of the adapter board; 4. Compatible with multi-layer PAD expansion: Enables horizontal synchronous interconnection of multi-layer PADs to meet high-density integration requirements; 5. Supports multi-array parallel interconnect: significantly improves I / O density to meet the needs of high-bandwidth applications; supports wafer-level batch integration: the mother wafer solution can realize the parallel integration of multiple sub-chips, resulting in high production efficiency; 6. Flexible layout: The chip can be centered or at the edge, and the interconnect area can be distributed around the perimeter or on one side, adapting to different chip layouts. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the fabrication method of the heterogeneous die system-integrated chip of the present invention; Figure 2 This is a schematic diagram of the adapter plate processing in step S1 of Embodiment 1 of the present invention; Figure 2-1 This is a schematic diagram of the structure in Embodiment 1 of the present invention, showing the etching of the first VIA hole to expose the first I / O pad; Figure 2-2 This is a schematic diagram of the structure of the vertical interconnect channel formed by metal filling VIA holes in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the core processing in step S2 of Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the bonding of the core to the adapter plate in step S3 of Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the heterogeneous die system-integrated chip of the present invention; Figure 6 This is a schematic diagram of the structure of the multilayer PAD extension (before bonding) in Embodiment 2 of the present invention; Figure 6-1 This is a schematic diagram of the structure of the multilayer PAD extension (after bonding) in Embodiment 2 of the present invention; Figure 7 This is a schematic diagram of the parallel interconnection structure of multiple array PADs in Embodiment 3 of the present invention.

[0019] Figure Labels

[0020] 100 - Adapter board; 110 - First dielectric layer; 1101 - First I / O pad; 111 - First VIA hole; 1110 - Metal block; 112 - First metal interconnect region; 200 - Core; 210 - Second I / O pad; 211 - Second VIA hole; 212 - Second metal interconnect region; 300 - Bonding layer; 400 - Bridge interconnect structure. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be noted that these embodiments are only for explaining the invention and not for limiting it; all other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the protection scope of this invention.

[0022] Example 1: Single-layer PAD interconnect

[0023] like Figure 1As shown, this embodiment provides a method for fabricating a heterogeneous die system-on-a-chip, including the following steps: S1: Provide an adapter board 100, the top surface of the adapter board 100 is provided with a first I / O pad, and a first metal interconnect area 112 is formed above the first I / O pad or the first I / O pad is used as the first metal interconnect area 112. S2: Provide a core 200, wherein a second I / O pad 210 is provided on the top surface of the core 200, a second metal interconnect region 212 is prepared on the top surface of the core 200, and the second I / O pad 210 is electrically led to the edge of the top surface of the core 200, so that the second metal interconnect region 212 is located at the edge of the top surface of the core 200. S3: The core 200 and the adapter plate 100 are bonded and fixed together by a bonding layer, so that the second metal interconnect area 212 located at the edge of the top surface of the core 200 and the first metal interconnect area 112 located on the top surface of the adapter plate 100 are opposite each other in the horizontal direction and have a gap, and both the first metal interconnect area 112 and the second metal interconnect area 212 are exposed. S4: Perform a selective metal deposition process to nucleate and grow metal material only on the exposed surfaces of the first metal interconnect region 112 and the second metal interconnect region 212, and bridge and fuse them within the horizontal gap to form a horizontal electrical interconnect structure.

[0024] First, the adapter board 100 is processed in one of the following ways: the first metal interconnect region 112 is prepared in one of the following manner: like Figure 2 As shown, the adapter plate 100 is processed to prepare a first metal interconnect region 112 on its top surface.

[0025] Originally protruding type: If the first I / O pad of the adapter board 100 is itself a protruding structure (such as copper pillar, aluminum pillar, gold bump, solder bump, etc.), then no additional process is required, and the protruding pad can be directly used as the first metal interconnect area 112.

[0026] Planar pad upward growth type: If the first I / O pad has a planar structure (flush with the passivation layer), metal is grown on its surface through a subsequent metal deposition process. During the selective metal deposition process in step S4, the metal grows in an umbrella-like pattern along the exposed surface of the I / O pad, that is, the metal grows not only into the horizontal gaps but also upwards from the surface of the first I / O pad, forming vertical metal pillars, which together with the horizontally grown metal constitute an L-shaped bridge interconnect structure. These vertically grown metal pillars and the first I / O pad together constitute the first metal interconnect region 112.

[0027] By simultaneously growing vertical metal pillars during the interconnection process, not only is the lack of structural height compensated, but a unique L-shaped bridge interconnection is also formed, which enhances the mechanical strength and contact reliability of the interconnection.

[0028] VIA (Vertical Interconnect Via) with raised type: A raised metal block 1110 is fabricated using VIA. like Figure 2-1 As shown, a first dielectric layer 110 is deposited over the first I / O pad 1101; Etch the first VIA hole 111 to expose the first I / O pad 1101; like Figure 2-2 As shown, metal-filled VIA vias form vertical interconnect channels; A metal layer is deposited and patterned over the first dielectric layer 110 to form a protruding metal block 1110 connected to the first VIA hole 111, serving as the first metal interconnect region 112.

[0029] By using a rewiring layer process, interconnect points can be moved from their original solder pad locations and repositioned. This allows for more flexible I / O layout matching between the adapter board 100 and the core 200, and lays the foundation for achieving multi-layer stacked interconnects.

[0030] Furthermore, the implementation of the first metal interconnect region 112 also includes: when the sidewall of the first I / O pad 1101 is exposed in the narrow gap (i.e., horizontal gap) between the core 200 and the adapter plate 100, the exposed sidewall can also serve as a growth substrate for metal deposition. During the selective metal deposition process in step S4, the metal material nucleates and grows on the surface of the exposed sidewall and extends into the horizontal gap, fusing with the metal bridge grown on the surface of the second metal interconnect region 212. In this manner, the first I / O pad 1101 itself constitutes a part of the first metal interconnect region 112.

[0031] Next, the middle PAD of core 200 is led to the top edge, as shown. Figure 3 As shown, the core 200 is processed to prepare a second metal interconnect region 212 that is electrically connected to the internal circuitry at the edge of its top surface.

[0032] Step 1: Substrate Pretreatment

[0033] Clean the surface of the second I / O pad 210 of the core chip 200 to remove the oxide layer and contaminants. Immerse in diluted hydrofluoric acid for 30 seconds to remove the natural oxide layer, then rinse with deionized water and dry with nitrogen.

[0034] Step 2: Deposit an insulating layer

[0035] A passivation layer or insulating dielectric such as polyimide, approximately 1-2 μm thick, is deposited above the core 200 to cover the second I / O pad 210. In this embodiment, silicon dioxide is deposited using PECVD as the second dielectric layer.

[0036] Step 3: VIA Lithography and Etching

[0037] Photoresist is applied, and a second VIA hole 211 is defined on the second dielectric layer using photolithography, aligning with the underlying second I / O pad 210. The second VIA hole 211 is then etched using dry etching, exposing the underlying second I / O pad 210.

[0038] Step 4: VIA metal filling

[0039] A barrier / seed layer is deposited using physical vapor deposition, followed by copper metal filling via electroplating, and finally planarization using chemical mechanical polishing to make the VIA metal flush with the surface of the second dielectric layer.

[0040] Step 5: Deposit the top metal layer

[0041] An aluminum layer of approximately 1-2 μm thickness is deposited by sputtering, covering the second dielectric layer and VIA.

[0042] Step 6: Photolithography and Etching of Metal Blocks

[0043] Photoresist is coated on the aluminum layer, and a metal cube pattern is defined by photolithography. This metal cube needs to extend to the top edge of the chip 200. The aluminum metal cube is etched out using dry etching and connected to the underlying VIA to form the second metal interconnect region 212 located at the top edge of the chip 200.

[0044] Step 7: Post-processing

[0045] Remove the photoresist and clean the surface.

[0046] It should be noted that aluminum is used as an exemplary material for the top metal layer in this embodiment, but it is not limited to this. Those skilled in the art can select other suitable metal materials based on actual process compatibility, electrical performance requirements, and cost considerations, including but not limited to: copper (Cu), titanium (Ti), tungsten (W), nickel (Ni), gold (Au), silver (Ag), or alloys of the above metals and their stacked structures (such as Ti / Al / Ti, Ti / Cu / Ti, etc.). Any metal material that can achieve electrical interconnection and is compatible with subsequent selective deposition processes can be used as the constituent material of the second metal interconnect region of this invention.

[0047] Then attach the core 200 to the adapter plate 100, as follows: Figure 4 As shown, the processed core 200 is mounted onto the adapter plate 100.

[0048] Step 1: Preprocessing

[0049] Clean the core 200 and adapter plate 100 to remove surface contaminants and oxide layers, ensuring clear alignment marks.

[0050] Step 2: Apply bonding layer

[0051] A bonding layer 300 is coated on the front bonding area of ​​the adapter board 100. In this embodiment, a dry film is used, which is attached by a lamination process, with a thickness of 20 μm. Key control: The bonding layer 300 only covers the front bonding area and must not cover the areas where the first metal interconnect region 112 and the second metal interconnect region 212 are located, ensuring that the interconnect areas are completely open.

[0052] Step 3: High-precision placement

[0053] Using a pick-and-place machine and visual alignment marks, the core 200 is precisely placed onto the corresponding position on the adapter plate 100, ensuring that the second metal interconnect area 212 located at the top edge of the core 200 is precisely aligned horizontally with the first metal interconnect area 112 located on the top surface of the adapter plate 100, forming a horizontal gap between them. The alignment accuracy is controlled within ±1μm.

[0054] Step 4: Cure Bonding

[0055] like Figure 4 As shown, a suitable curing method is selected based on the bonding layer material. In this embodiment, UV exposure curing of the dry film is used to firmly bond the core 200 to the adapter plate 100.

[0056] Finally, selective metal deposition forms horizontal interconnects, such as Figure 5 As shown, selective metal deposition is performed in the open top horizontal region to form a horizontal interconnect structure.

[0057] Step 1: Preprocessing

[0058] Exposed metal interconnect areas can be cleaned and activated as needed, but this is not a mandatory step.

[0059] Step 2: Selective Metal Deposition

[0060] This embodiment employs an electroless nickel plating process. The component is immersed in an electroless nickel plating solution. Because the surfaces of the first metal interconnect region 112 and the second metal interconnect region 212 have catalytic activity, nickel ions undergo reduction and nucleation only on the exposed metal surfaces; while the bonding layer, insulating layer, and other surfaces have no catalytic activity and no metal deposition occurs, thus achieving selective growth.

[0061] For planar pad upward growth type, metal deposition exhibits a unique L-shaped growth process: The metal simultaneously nucleates and grows on the surface of the second metal interconnect region 212 and the first I / O pad. The metal growing from the surface of the first I / O pad extends upward to form a vertical metal pillar; The metal grown from the surface of the second metal interconnect region 212 extends into the horizontal gap; It also begins to grow horizontally from the top of the vertical metal column; The horizontally grown metals on both sides meet and fuse within the gap, forming a complete L-shaped bridge interconnect structure 400.

[0062] Step 3: Post-processing

[0063] After deposition is complete, the component is removed, cleaned with deionized water, and dried with nitrogen.

[0064] Step 4: Detection

[0065] The morphology of the interconnect structure was observed using a scanning electron microscope to check the void ratio; the on-resistance was tested using the four-probe method.

[0066] The resulting heterogeneous die system-on-a-chip, such as Figure 5 As shown, the heterogeneous die system-on-a-chip finally fabricated in this embodiment includes: The adapter board 100 has a first metal interconnection area 112 on its top surface, and the first metal interconnection area 112 is electrically connected to the internal circuit of the adapter board 100. The core 200 has a second metal interconnect region 212 on its top edge. The second metal interconnect region 212 is electrically connected to the internal circuit of the core 200. The core 200 is attached and fixed to the adapter plate 100 through a bonding layer. The second metal interconnect region 212 and the first metal interconnect region 112 are opposite to each other in the horizontal direction and have a gap. A horizontal interconnect structure is located within the gap and forms a metallurgical bond with the first metal interconnect region 112 and the second metal interconnect region 212 to achieve a horizontal electrical connection between the adapter plate 100 and the core 200.

[0067] Example 2: Multi-layer PAD Expansion

[0068] The difference between this embodiment and Embodiment 1 is that the core 200 and the adapter board 100 are interconnected using a multi-layer PAD scheme.

[0069] like Figure 6 and Figure 6-1 As shown, the core 200 has multiple I / O pads, corresponding to the fabrication of multiple VIA layers and multiple top metal layers, forming multiple second metal interconnects. The adapter board 100 correspondingly fabricates multiple first metal interconnect regions 112.

[0070] After mounting, the metal interconnect regions of each layer correspond one-to-one in the horizontal direction. During selective metal deposition, a multi-layer interconnect structure is simultaneously formed within the horizontal gaps between each layer, with the layers isolated by an insulating layer.

[0071] By expanding vertically in multiple layers, this embodiment increases interconnect bandwidth and density by an order of magnitude without sacrificing horizontal area, while retaining the simplicity of self-aligned interconnects, providing a practical technical path for high-bandwidth demand scenarios such as high-performance computing and artificial intelligence.

[0072] Example 3: Parallel Interconnection of Multiple Array PADs

[0073] This embodiment is an implementation scheme for parallel interconnection of multiple array PADs.

[0074] like Figure 7 As shown, the top edge of the core 200 has multiple arrays of second metal interconnect regions 212, and the top surface of the adapter plate 100 has correspondingly multiple arrays of first metal interconnect regions 112. The array size can reach 8×8 or larger.

[0075] During selective metal deposition, multiple independent interconnect structures are formed simultaneously within all horizontal gaps, enabling multi-channel parallel signal transmission.

[0076] This embodiment expands the interconnect channels from a "single lane" to a "multi-lane parallel" through arrayed arrangement and parallel synchronous growth, achieving an order-of-magnitude leap in I / O bandwidth while maintaining the process efficiency of "one-time deposition, all-round formation", providing an ideal interconnect solution for high-throughput data interaction.

[0077] Example 4: Integration of multiple sub-chips on a mother wafer

[0078] This embodiment demonstrates a mother wafer solution.

[0079] Multiple master chips are integrated on the master wafer, and each master chip has a corresponding first metal interconnect region around it. Multiple sub-chips are respectively mounted on the corresponding positions on the master wafer.

[0080] Multiple sub-chips are simultaneously mounted using a multi-nozzle pick-and-place machine. Then, the entire mother wafer is immersed in a plating solution, and metal is grown simultaneously on the interconnect areas of all sub-chips, achieving batch integration.

[0081] This embodiment achieves efficient batch integration of sub-chips by extending the integration scale from the chip level to the wafer level, utilizing multi-nozzle parallel mounting and whole-wafer immersion batch deposition. This approach increases production efficiency by tens of times, reduces manufacturing costs, and ensures consistent interconnect quality, providing a practical technical path for large-scale industrial applications. Furthermore, a centered sub-chip with peripheral interconnects can be used to achieve high-density interconnects around the periphery, doubling the number of I / O channels.

[0082] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for fabricating a heterogeneous bare die system-on-a-chip, characterized in that, Includes the following steps: S1: Provide an adapter board, the top surface of which is provided with a first I / O pad, and a first metal interconnect area is formed above the first I / O pad or the first I / O pad is used as the first metal interconnect area; S2: A core is provided, the top surface of which is provided with a second I / O pad, a second metal interconnect region is prepared on the top surface of the core, and the second I / O pad is electrically led to the edge of the top surface of the core, so that the second metal interconnect region is located at the edge of the top surface of the core. S3: The core and the adapter plate are bonded and fixed together by a bonding layer, so that the second metal interconnect area located at the edge of the top surface of the core and the first metal interconnect area located on the top surface of the adapter plate are opposite each other in the horizontal direction with a gap, and both the first metal interconnect area and the second metal interconnect area are exposed. S4: Perform a selective metal deposition process to nucleate and grow metal materials only on the exposed surfaces of the first and second metal interconnect regions, and bridge and fuse them within the horizontal gap to form a horizontal electrical interconnect structure.

2. The manufacturing method as described in claim 1, characterized in that, The first metal interconnect region is at least one of the following: The first I / O pad itself is a protruding structure and directly serves as the first metal interconnect area; The first I / O pad is a planar structure, and metal is grown on its surface through a metal deposition process. The resulting metal structure and the first I / O pad together constitute the first metal interconnect region. An insulating layer is deposited above the first I / O pad, interconnect vias are etched to expose the pads, and metal fills the interconnect vias and extends above the insulating layer to form a protruding first metal interconnect region. The sidewalls of the first I / O pad are exposed in the narrow slit.

3. The manufacturing method as described in claim 1, characterized in that, The method for fabricating the second metal interconnect region on the top surface of the core includes: An insulating layer is deposited over the second I / O pad, and photolithography is used to form interconnect vias to expose the pads. Metal-filled interconnect vias form vertical interconnects; A metal layer is deposited and patterned above the insulating layer to form a metal wiring layer extending to the edge of the top surface of the core. The metal wiring layer is electrically connected to the interconnect to form a second metal interconnect region.

4. The manufacturing method as described in claim 1, characterized in that, The first metal interconnect region and / or the second metal interconnect region are multi-layer structures, respectively corresponding to the multi-layer I / O pads of the adapter board or the core chip. Multi-layer interconnection is achieved through the fabrication of multi-layer interconnects and multi-layer metal wiring layers.

5. The manufacturing method as described in claim 1, characterized in that, The first metal interconnect region and the second metal interconnect region are arranged in multiple arrays, each corresponding to multiple I / O channels. In step S4, multiple interconnect structures are formed simultaneously in multiple horizontal gaps, which are respectively connected to the corresponding first metal interconnect region and the second metal interconnect region to realize multi-channel parallel signal transmission.

6. The manufacturing method as described in claim 1, characterized in that, The adapter board is a master wafer, on which multiple master granules are integrated; each granule is a sub-granule, and multiple sub-granules are integrated in parallel on the master wafer using the method described above.

7. The manufacturing method as described in claim 1, characterized in that, The core is located in the middle area of ​​the adapter plate. The first metal interconnect area is distributed on the outer periphery of the top edge of the adapter plate, and the second metal interconnect area is located on the top edge of the core. The two correspond to each other in the horizontal direction.

8. A heterogeneous die system-on-a-chip, characterized in that, Prepared by the method according to any one of claims 1 to 7, comprising: The adapter board has a first metal interconnection area on its top surface, and the first metal interconnection area is electrically connected to the internal circuit of the adapter board. The core has a second metal interconnect area on its top edge. The second metal interconnect area is electrically connected to the internal circuit of the core. The core is bonded and fixed to the adapter plate through a bonding layer. The second metal interconnect area and the first metal interconnect area are opposite to each other in the horizontal direction and have a gap. A horizontal interconnect structure, located within the gap, forms a metallurgical bond with the first and second metal interconnect regions, thereby achieving an electrical connection between the adapter plate and the core.

9. The heterogeneous die system-on-a-chip as described in claim 8, characterized in that, The first metal interconnect region and the second metal interconnect region are arranged in multiple arrays, and there are multiple horizontal interconnect structures, which are respectively connected to the corresponding first metal interconnect region and the second metal interconnect region to form a multi-channel parallel interconnect.

10. The heterogeneous die system-on-a-chip as described in claim 8, characterized in that, The first metal interconnect region and / or the second metal interconnect region are multi-layered structures, corresponding to the multi-layered I / O pads of the adapter board or the core chip, respectively. The horizontal interconnect structure is multi-layered, connecting the first metal interconnect region and the second metal interconnect region of the corresponding layer, respectively, to achieve multi-layer interconnection.

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