Semiconductor package and method of manufacturing the same
By employing a multi-layer structure design of a base substrate, an intermediate substrate, and a graphics processing unit in the semiconductor package, and using conductive blocks for electrical connection, the problems of high cost and low yield are solved, achieving low-cost and high-yield semiconductor packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ORIENT SEMICONDUCTOR ELECTRONICS LTD
- Filing Date
- 2025-01-15
- Publication Date
- 2026-07-17
AI Technical Summary
High-performance semiconductor packages are expensive to manufacture and have low yield rates.
It adopts a multi-layer structure design consisting of a base substrate, an intermediate substrate, and a graphics processing unit. Electrical connections are made between the layers through conductive blocks to form a complex circuit network.
This enables low-cost and high-yield semiconductor packaging, improving the overall performance of the product.
Smart Images
Figure CN122421789A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor package and its manufacturing method, and more particularly to a high-performance semiconductor package and its manufacturing method. Background Technology
[0002] Currently, the manufacturing cost of high-performance semiconductor packages is too high, and the yield is also difficult to control. Summary of the Invention
[0003] In view of this, the present invention provides a semiconductor package and a method for manufacturing the same, in order to solve the above problems.
[0004] To achieve the above objectives, the semiconductor package of the present invention includes: a base substrate; an intermediate substrate disposed on the base substrate; a plurality of first conductive blocks sandwiched between the base substrate and the intermediate substrate and electrically connected to the base substrate and the intermediate substrate; a graphics processing unit disposed on the intermediate substrate; and a plurality of second conductive blocks sandwiched between the intermediate substrate and the graphics processing unit and electrically connected to the intermediate substrate and the graphics processing unit. The plurality of second conductive blocks are electrically connected to the plurality of first conductive blocks through the intermediate substrate.
[0005] The method for manufacturing a semiconductor package of the present invention includes: forming a plurality of first conductive blocks on an intermediate substrate; disposing the intermediate substrate on a base substrate, such that the plurality of first conductive blocks are sandwiched between the base substrate and the intermediate substrate and electrically connected to the base substrate and the intermediate substrate; forming a plurality of second conductive blocks on a graphics processing unit; and disposing the graphics processing unit on the intermediate substrate, such that the plurality of second conductive blocks are sandwiched between the intermediate substrate and the graphics processing unit and electrically connected to the intermediate substrate and the graphics processing unit. The plurality of second conductive blocks are electrically connected to the plurality of first conductive blocks through the intermediate substrate.
[0006] The semiconductor package according to the present invention has lower manufacturing costs and higher yield.
[0007] To make the above and other objects, features and advantages of the present invention more apparent, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0008] The nature of this disclosure is best understood by reading in conjunction with the accompanying drawings and the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of explanation.
[0009] Figure 1 This is a schematic diagram of the semiconductor package of the present invention.
[0010] Figures 2 to 9 show Figure 1 The method for manufacturing the semiconductor package shown.
[0011] Symbol explanation:
[0012] 110 Baseboard
[0013] 111 First Surface
[0014] 112 Second Surface
[0015] 113 Conductive circuit
[0016] 114 Conductive circuit
[0017] 115 Electroplated Through Hole
[0018] 120 Intermediate substrate
[0019] 121 First Surface
[0020] 122 Second Surface
[0021] 123 Conductive circuit
[0022] 124 Conductive circuit
[0023] 125 Conductive plated through-hole
[0024] 131 First Conductive Block
[0025] 132 Second Conductive Block
[0026] 133 Third Conductive Block
[0027] 150 chips
[0028] 160 Semiconductor Memory Stack
[0029] 180 Passive Components
[0030] 190 Tin Balls Detailed Implementation
[0031] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first member on or above a second member may include embodiments where the first member and the second member are formed in direct contact, and may also include embodiments where additional members may be formed between the first member and the second member such that the first member and the second member are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0032] In addition, for ease of description, spatial relative terms such as “under,” “below,” “lower,” “overlapping,” “upper,” and similar terms may be used herein to describe the relationship between one component or member and one or more components or members as illustrated in the figures. Besides the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.
[0033] Please refer to Figure 1 The semiconductor package of the present invention includes a base substrate 110 having opposing first surfaces 111 and second surfaces 112, wherein the first surface 111 and the second surface 112 are located in different planes, for example, the first surface 111 is the top surface and the second surface 112 is the bottom surface, but not limited thereto. Conductive lines 113 and 114 are respectively formed on the first surface 111 and the second surface 112 of the base substrate 110, and the conductive lines 113 and 114 are electrically connected by a plurality of conductive plated through-holes 115 penetrating the first surface 111 and the second surface 112 of the base substrate 110. Passive components 180 may also be disposed on the first surface 111 of the base substrate 110 as needed.
[0034] In one embodiment, the base substrate 110 may be a single-layer or multi-layer circuit board, redistribution layer (RDL) substrate, or glass substrate.
[0035] An intermediate substrate 120 is provided on the first surface 111 of the base substrate 110, which has a first surface 121 and a second surface 122 opposite to each other, and the first surface 121 and the second surface 122 are located in different planes, for example, the first surface 121 is the top surface and the second surface 122 is the bottom surface, but not limited thereto.
[0036] In one embodiment, the intermediate substrate 120 may be a silicon substrate.
[0037] Conductive lines 123 and 124 are formed on the first surface 121 and the second surface 122 of the intermediate substrate 120, respectively. The conductive lines 123 and 124 are electrically connected by a plurality of conductive plated through holes 125 penetrating the first surface 121 and the second surface 122 of the intermediate substrate 120.
[0038] In this invention, the conductive lines 123 include arithmetic processor and memory connection lines as well as logic lines for high-performance memory.
[0039] The second surface 122 of the intermediate substrate 120 is provided with a plurality of first conductive blocks 131, which are sandwiched between the intermediate substrate 120 and the base substrate 110. The intermediate substrate 120 is electrically connected to the base substrate 110 through the plurality of first conductive blocks 131. The gap between the intermediate substrate 120 and the base substrate 110 can be filled with underfill to cover the plurality of first conductive blocks 131.
[0040] In one embodiment, the intermediate substrate 120 can be formed by cutting a silicon wafer, and conductive lines are provided on both opposite surfaces of the silicon wafer to form conductive lines 123 and 124 on the first surface 121 and the second surface 122 of the intermediate substrate 120, respectively.
[0041] In another embodiment, the plurality of first conductive blocks 131 are metal bumps, formed on the second surface 122 of the intermediate substrate 120 using a bumping process. The plurality of first conductive blocks 131 can be composed of eutectic alloy, lead-free, high-lead materials, or copper pillars. The intermediate substrate 120 is attached to the first surface 111 of the base substrate 110 using flip-chip technology.
[0042] A chip 150 is disposed on the first surface 121 of the intermediate substrate 120, having an active surface and a back surface opposite to the active surface. A plurality of second conductive blocks 132 are disposed on the active surface of the chip 150, and the plurality of second conductive blocks 132 are electrically connected to the chip 150. The plurality of second conductive blocks 132 are sandwiched between the chip 150 and the intermediate substrate 120. The plurality of second conductive blocks 132 are electrically connected to the plurality of first conductive blocks 131 through conductive lines 123 and 124 on the first surface 121 and the second surface 122 of the intermediate substrate 120, thereby enabling the chip 150 to be electrically connected to the base substrate 110. The gap between the chip 150 and the intermediate substrate 120 can be filled with adhesive to cover the plurality of second conductive blocks 132.
[0043] In this invention, the chip 150 can be a graphics processing unit (GPU).
[0044] In one embodiment, the plurality of second conductive blocks 132 are metal bumps formed on the active surface of the chip 150 using a bumping process. The plurality of second conductive blocks 132 can be composed of eutectic alloys, lead-free materials, high-lead materials, or copper pillars. The chip 150 is attached to the first surface 121 of the intermediate substrate 120 using flip-chip technology.
[0045] A semiconductor memory stack 160, consisting of at least a plurality of memory chips, is also disposed on the first surface 121 of the intermediate substrate 120. The semiconductor memory stack 160 is arranged side by side with the chip 150.
[0046] In one embodiment, the semiconductor memory stack 160 is a high-bandwidth memory (HBM) stack.
[0047] The semiconductor memory stack 160 has a plurality of third conductive blocks 133 at its bottom, which are electrically connected to the semiconductor memory stack 160. The plurality of third conductive blocks 133 are sandwiched between the semiconductor memory stack 160 and the interposer substrate 120. The plurality of third conductive blocks 133 are electrically connected to a plurality of first conductive blocks 131 via conductive lines 123 and 124 on the first surface 121 and the second surface 122 of the interposer substrate 120, thereby enabling the semiconductor memory stack 160 to be electrically connected to the base substrate 110. The gap between the semiconductor memory stack 160 and the interposer substrate 120 can be filled with adhesive to cover the plurality of third conductive blocks 133.
[0048] A plurality of solder balls 190 are provided on the second surface 112 of the base substrate 110, and the plurality of solder balls 190 are electrically connected to the base substrate 110. The plurality of solder balls 190 are electrically connected to the plurality of first conductive blocks 131 through the conductive lines 113, 114 and the plurality of conductive plated vias 115 on the base substrate 110, thereby enabling the chip 150 and the semiconductor memory stack 160 to be electrically connected to external circuits through the intermediary substrate 120 and the base substrate 110 using the plurality of solder balls 190.
[0049] Please refer to Figures 2 to 9 Its display Figure 1 The method for manufacturing the semiconductor package shown is illustrated. Figure 2As shown, a base substrate 110 is prepared, which has a first surface 111 and a second surface 112 opposite to each other, and the first surface 111 and the second surface 112 are located in different planes, for example, the first surface 111 is the top surface and the second surface 112 is the bottom surface, but not limited thereto. Conductive lines 113 and 114 are respectively formed on the first surface 111 and the second surface 112 of the base substrate 110, and the conductive lines 113 and 114 are electrically connected by a plurality of conductive plated through holes 115 penetrating the first surface 111 and the second surface 112 of the base substrate 110.
[0050] In one embodiment, the base substrate 110 may be a single-layer or multi-layer circuit board, redistribution layer (RDL) substrate, or glass substrate.
[0051] like Figure 3 As shown, a passive component 180 may then be disposed on the first surface 111 of the base substrate 110 as needed.
[0052] like Figure 4 As shown, an intermediate substrate 120 is prepared, which may be made of silicon. The intermediate substrate 120 has a first surface 121 and a second surface 122 opposite to each other, and the first surface 121 and the second surface 122 are located in different planes, for example, the first surface 121 is the top surface and the second surface 122 is the bottom surface, but not limited thereto. Conductive lines 123 and 124 are respectively formed on the first surface 121 and the second surface 122 of the intermediate substrate 120, and the conductive lines 123 and 124 are electrically connected by a plurality of conductive plated through-holes 125 penetrating the first surface 121 and the second surface 122 of the intermediate substrate 120.
[0053] like Figure 5 As shown, a plurality of first conductive blocks 131 are then formed on the second surface 122 of the intermediate substrate 120, and the plurality of first conductive blocks 131 are electrically connected to the intermediate substrate 120.
[0054] In one embodiment, the intermediate substrate 120 can be formed by dicing a silicon wafer, and conductive lines are provided on both opposing surfaces of the silicon wafer to form conductive lines 123 and 124 on the first surface 121 and the second surface 122 of the intermediate substrate 120, respectively. In this invention, the conductive lines 123 include processor-to-memory interconnects and high-performance memory logic lines.
[0055] In another embodiment, the plurality of first conductive blocks 131 are metal bumps formed on the second surface 122 of the intermediate substrate 120 using a bumping process. The plurality of first conductive blocks 131 can be composed of eutectic alloy, lead-free, high-lead materials, or copper pillars.
[0056] like Figure 6 As shown, the intermediate substrate 120 is then attached to the first surface 111 of the base substrate 110 using flip-chip technology, so that the plurality of first conductive blocks 131 are sandwiched between the intermediate substrate 120 and the base substrate 110. The intermediate substrate 120 is electrically connected to the base substrate 110 through the plurality of first conductive blocks 131. The gap between the intermediate substrate 120 and the base substrate 110 can be filled with underfill to cover the plurality of first conductive blocks 131.
[0057] like Figure 7 As shown, a chip 150 is then prepared, having an active side and a back side opposite to the active side. A plurality of second conductive blocks 132 are formed on the active side of the chip 150, and these second conductive blocks 132 are electrically connected to the chip 150. Next, the chip 150 is attached to the first surface 121 of the interposer substrate 120 using flip-chip technology, with the plurality of second conductive blocks 132 sandwiched between the chip 150 and the interposer substrate 120. The plurality of second conductive blocks 132 are electrically connected to the plurality of first conductive blocks 131 through conductive lines 123 and 124 on the first surface 121 and the second surface 122 of the interposer substrate 120, thereby enabling the chip 150 to be electrically connected to the base substrate 110. The gap between the chip 150 and the interposer substrate 120 can be filled with adhesive to cover the plurality of second conductive blocks 132.
[0058] In this invention, the chip 150 can be a graphics processing unit.
[0059] In one embodiment, the plurality of second conductive blocks 132 are metal bumps formed on the active surfaces of the chip 150 using a bumping process. The plurality of second conductive blocks 132 can be composed of eutectic alloys, lead-free materials, high-lead materials, or copper pillars.
[0060] like Figure 8 As shown, a semiconductor memory stack 160 is then prepared, which is composed of at least a plurality of memory chips stacked together. A plurality of third conductive blocks 133 are formed at the bottom of the semiconductor memory stack 160, and the plurality of third conductive blocks 133 are electrically connected to the semiconductor memory stack 160.
[0061] In one embodiment, the semiconductor memory stack 160 is a high-bandwidth memory stack.
[0062] Next, the semiconductor memory stack 160 is attached to the first surface 121 of the interposer substrate 120 using flip-chip technology, so that the plurality of third conductive blocks 133 are sandwiched between the semiconductor memory stack 160 and the interposer substrate 120. The semiconductor memory stack 160 and the chip 150 are arranged side by side.
[0063] The plurality of third conductive blocks 133 are electrically connected to the plurality of first conductive blocks 131 through conductive lines 123 and 124 on the first surface 121 and the second surface 122 of the intermediate substrate 120, thereby enabling the semiconductor memory stack 160 to be electrically connected to the base substrate 110. The gap between the semiconductor memory stack 160 and the intermediate substrate 120 can be filled with adhesive to cover the plurality of third conductive blocks 133.
[0064] like Figure 9 As shown, a plurality of solder balls 190 are then formed on the second surface 112 of the base substrate 110, and the plurality of solder balls 190 are electrically connected to the base substrate 110 to form as shown. Figure 1 The semiconductor package shown.
[0065] The plurality of solder balls 190 are electrically connected to the plurality of first conductive blocks 131 through the conductive lines 113, 114 and the plurality of conductive plated vias 115 on the base substrate 110, thereby enabling the chip 150 and the semiconductor memory stack 160 to be electrically connected to an external circuit via the plurality of solder balls 190 through the intermediary substrate 120 and the base substrate 110.
[0066] The semiconductor package according to the present invention has lower manufacturing costs and higher yield.
[0067] While the present invention has been disclosed through the foregoing embodiments, it is not intended to limit the invention. Anyone skilled in the art to which this invention pertains can make various modifications and alterations without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.
Claims
1. A semiconductor package, characterized in that, Include: Base plate; An intermediate substrate is disposed on the base substrate; A plurality of first conductive blocks are sandwiched between the base substrate and the intermediate substrate, and are electrically connected to the base substrate and the intermediate substrate; A graphics processing unit is disposed on the intermediate substrate; and A plurality of second conductive blocks are sandwiched between the intermediate substrate and the graphics processing unit, and are electrically connected to the intermediate substrate and the graphics processing unit. The plurality of second conductive blocks are electrically connected to the plurality of first conductive blocks through the intermediate substrate.
2. The semiconductor package as described in claim 1, characterized in that, Also includes: A semiconductor memory stack is disposed on the interposer substrate; A plurality of third conductive blocks are sandwiched between the interposer substrate and the semiconductor memory stack, and are electrically connected to the interposer substrate and the semiconductor memory stack. The plurality of third conductive blocks are electrically connected to the plurality of first conductive blocks through the intermediate substrate.
3. The semiconductor package as described in claim 1, characterized in that, The intermediate substrate is made of silicon.
4. The semiconductor package as described in claim 1, characterized in that, The semiconductor memory stack is a high-bandwidth memory stack.
5. The semiconductor package as described in claim 1, characterized in that, The interposer substrate has opposing first and second surfaces, and the semiconductor package further comprises: A first conductive line is formed on the first surface and electrically connected to the plurality of second conductive blocks; A second conductive line is formed on the second surface and electrically connected to the plurality of first conductive blocks; as well as A plurality of conductive plated vias are formed within the intermediate substrate and electrically connected to the first conductive line and the second conductive line.
6. A method for manufacturing a semiconductor package, characterized in that, Include: A complex number of first conductive blocks are formed on the intermediate substrate; The intermediate substrate is disposed on the base substrate, such that the plurality of first conductive blocks are sandwiched between the base substrate and the intermediate substrate and are electrically connected to the base substrate and the intermediate substrate. A complex number of second conductive blocks are formed on the graphics processing unit; as well as The graphics processing unit is disposed on the intermediate substrate, and the plurality of second conductive blocks are sandwiched between the intermediate substrate and the graphics processing unit, and are electrically connected to the intermediate substrate and the graphics processing unit. The plurality of second conductive blocks are electrically connected to the plurality of first conductive blocks through the intermediate substrate.
7. The method for manufacturing a semiconductor package as described in claim 6, characterized in that, Also includes: A complex third conductive block is formed on the semiconductor memory stack; The semiconductor memory stack is disposed on the intermediate substrate, and the plurality of third conductive blocks are sandwiched between the intermediate substrate and the semiconductor memory stack, and electrically connected to the intermediate substrate and the semiconductor memory stack. The plurality of third conductive blocks are electrically connected to the plurality of first conductive blocks through the intermediate substrate.
8. The method for manufacturing a semiconductor package as described in claim 6, characterized in that, The intermediate substrate is made of silicon.
9. The method for manufacturing a semiconductor package as described in claim 6, characterized in that, The semiconductor memory stack is a high-bandwidth memory stack.
10. The method for manufacturing a semiconductor package as described in claim 6, characterized in that, The intermediate substrate has opposing first and second surfaces, and the method for manufacturing the semiconductor package further includes: A first conductive line is formed on the first surface, and the first conductive line is electrically connected to the plurality of second conductive blocks; A second conductive line is formed on the second surface, and the second conductive line is electrically connected to the plurality of first conductive blocks; as well as A plurality of conductive plated vias are formed in the intermediate substrate, and the plurality of conductive plated vias are electrically connected to the first conductive line and the second conductive line.