Prefetch dynamic control based on prefetch accuracy in a computing system

Abstract

Disclosed are prefetch dynamic control based on prefetch accuracy in a computing system, and related methods and computer-readable media. The computing system includes a processor including one or more central processing unit (CPU) cores each having an associated cache memory. The CPU cores are configured to generate a value indicative of a prefetch accuracy of the CPU cores, the prefetch accuracy being for prefetching data, instructions, or both data and instructions from a system memory external to the processor to store in the cache memory for the CPU cores, and to control the prefetching by the CPU cores based on the value indicative of the prefetch accuracy. In this way, when the prefetch accuracy is less than a particular threshold, the number of memory access requests for prefetching is reduced, which in turn relieves memory bandwidth contention, particularly in a multi-CPU core processor.

Description

Technical Field

[0001] The technology disclosed herein relates to a computing system including a central processing unit (CPU) (i.e., a processor) and a memory system for storing and accessing data. Background Technology

[0002] Computing systems that include one or more central processing units (CPUs) or microprocessors typically use prefetching of data, instructions, or both to reduce memory latency. Using data prefetching as an example, the CPU prefetches data from a relatively slow-access portion of the memory system associated with the CPU (e.g., main memory) and stores the prefetched data in a relatively fast-access portion of the memory system (e.g., a Level 1 (L1) cache) before the time it takes for a program executing on the CPU to need the prefetched data. This way, when the program needs the data, the CPU can retrieve it from the faster-access portion of the memory system, avoiding the need to wait to retrieve data from the slower-access portion, thus improving CPU execution speed.

[0003] However, when aggressive prefetching is performed, especially in multi-CPU systems where multiple CPU cores use shared memory, the CPU cores may issue a large number of prefetch requests, leading to significant memory bandwidth contention and consequently longer memory latency. Therefore, there is a need for systems and methods to reduce the number of prefetch requests while preserving the benefits of prefetching. Summary of the Invention

[0004] The aspects disclosed herein include dynamically controlling prefetching in a computing system based on prefetch accuracy. Related methods and computer-readable media are also disclosed. In an exemplary aspect, a computing system is provided, comprising a processor including one or more central processing unit (CPU) cores having associated cache memories. At least one of the CPU cores is configured to control the prefetching of data and / or instructions from memory to the associated cache memory based on prefetch accuracy. In an exemplary embodiment, the CPU core generates a value indicating prefetch accuracy based on prefetch line fill and demand hits in the cache memory. More specifically, in an exemplary embodiment, for each instance of prefetch line fill, in which data is prefetched from a memory line in memory and stored in the cache memory, the generated value is adjusted (e.g., decreased) by a first value, and for each instance of a demand hit accessing prefetched data from the cache memory, the generated value is adjusted (e.g., decreased) by a second value. Based on the value indicating the prefetch accuracy, when the prefetch accuracy is less than a certain accuracy threshold, prefetching is deactivated or partially deactivated. In this way, the number of prefetch requests when the prefetch accuracy is low can be reduced, thereby reducing memory bandwidth utilization and reducing contention for memory bandwidth among multiple CPU cores in the case of a multi-CPU processor.

[0005] In this regard, in one exemplary aspect, a computing system is provided. The computing system includes a processor, which includes a CPU core and a cache memory for the CPU core. The CPU core is configured to generate a value indicating a prefetch accuracy for prefetching data, instructions, or both data and instructions from system memory outside the processor for storage in the cache memory for the CPU core, and to control prefetching performed by the CPU core based on the value indicating the prefetch accuracy.

[0006] In one embodiment, the value indicating the prefetch accuracy of the CPU core is an unsigned saturation counter value, and the CPU core adjusts the unsigned saturation counter value by a first value for each instance of prefetch line filling, in which prefetched memory lines are stored in the cache memory for the CPU core, and by adjusting the unsigned saturation counter value by a second value for each instance of a hit in the prefetched memory line in the cache memory, thereby generating the value indicating the prefetch accuracy of the CPU core. In one embodiment, the first value is smaller than the second value. In one embodiment, the second value is a fixed value, and the first value is a function of the CPU core's target prefetch accuracy. In another embodiment, the prefetch request originates from a memory line of the computing system's memory stored in the cache memory, and one or both of the first and second values ​​are a function of the amount of bandwidth for processing memory access requests from the CPU core and one or more additional CPU cores of the computing system that are being used. In one embodiment, the CPU core adjusts the unsigned saturation counter value by increasing the first value for each instance of prefetch line filling, in which prefetched memory lines are stored in the cache memory for the CPU core, thereby adjusting the first value of the unsigned saturation counter value, and by decreasing the unsigned saturation counter value by decreasing the second value for each instance of a hit of a prefetched memory line in the cache memory, thereby adjusting the second value of the unsigned saturation counter value.

[0007] In one embodiment, to control prefetching of a CPU core, the CPU core is further configured to determine, based on the value indicating the prefetch accuracy, that the prefetch accuracy of the CPU core is less than a first prefetch accuracy threshold, and to partially deactivate the prefetching of the CPU core in response to the prefetch accuracy being less than the first prefetch accuracy threshold. In one embodiment, when prefetching is partially deactivated, the CPU core issues fewer prefetch requests than when prefetching is activated. In one embodiment, the CPU core is further configured to update the value indicating the prefetch accuracy of the CPU core when prefetching is partially deactivated; to activate the prefetching of the CPU core, determine, based on the updated value, that the prefetch accuracy of the CPU core has increased to or greater than a second prefetch accuracy threshold; and to activate the prefetching of the CPU core in response to the prefetch accuracy having increased to or greater than the second prefetch accuracy threshold. In one embodiment, the first prefetch accuracy threshold is equal to the second prefetch accuracy threshold. In another embodiment, the first prefetch accuracy threshold is less than the second prefetch accuracy threshold.

[0008] In another exemplary aspect, a method is provided for controlling prefetching performed by a CPU core of a processor in a computer system. The method includes generating a value indicating the prefetch accuracy of the CPU core for prefetching data, instructions, or both data and instructions from system memory outside the processor to be stored in a cache memory of the CPU core within the processor, and controlling the prefetching performed by the CPU core based on the value indicating the prefetch accuracy.

[0009] In one embodiment, the value indicating the prefetch accuracy of the CPU core is an unsigned saturation counter value, and generating the value indicating the prefetch accuracy of the CPU core includes adjusting the unsigned saturation counter value by a first value for each instance of prefetch line filling, in which prefetched memory lines are stored in the cache memory for the CPU core; and adjusting the unsigned saturation counter value by a second value for each instance of a hit of the prefetched memory line in the cache memory. In one embodiment, the first value is smaller than the second value. In another embodiment, the second value is a fixed value, and the first value is a function of the target prefetch accuracy of the CPU core. In another embodiment, the prefetch request of the CPU core originates from memory lines of the computing system's memory stored in the cache memory, and one or both of the first and second values ​​are a function of the amount of bandwidth for processing memory access requests from the CPU core and one or more additional CPU cores of the computing system that are being used. In one embodiment, adjusting the first value of the unsigned saturation counter includes increasing the first value of the unsigned saturation counter for each instance of prefetch line filling, in which prefetched memory lines are stored in the cache memory for the CPU core, and adjusting the second value of the unsigned saturation counter includes decreasing the second value of the unsigned saturation counter for each instance of a hit of a prefetched memory line in the cache memory.

[0010] In one embodiment, controlling the prefetching of the CPU core includes determining, based on the value indicating the prefetch accuracy, that the prefetch accuracy of the CPU core is less than a first prefetch accuracy threshold, and partially deactivating the prefetching of the CPU core in response to the prefetch accuracy being less than the first prefetch accuracy threshold. In one embodiment, when prefetching is partially deactivated, the CPU core issues fewer prefetch requests than when prefetching is activated. In one embodiment, the method further includes updating the value indicating the prefetch accuracy of the CPU core when prefetching is partially deactivated; determining, based on the updated value, that the prefetch accuracy of the CPU core has increased to or greater than a second prefetch accuracy threshold in order to activate the prefetching of the CPU core; and activating the prefetching of the CPU core in response to the prefetch accuracy being increased to or greater than the second prefetch accuracy threshold. In one embodiment, the first prefetch accuracy threshold is equal to the second prefetch accuracy threshold. In another embodiment, the first prefetch accuracy threshold is less than the second prefetch accuracy threshold.

[0011] In another exemplary aspect, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores computer-executable instructions that, when executed by a processor, cause the processor to generate a value indicating a prefetch accuracy rate performed by a CPU core of the processor, and to control the prefetch performed by the CPU core based on the value indicating the prefetch accuracy rate.

[0012] Those skilled in the art will understand the scope of this disclosure and recognize other aspects of it after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0014] Figure 1 This is a block diagram of an exemplary computing system according to an embodiment of the present disclosure, the computing system including a processor including one or more central processing unit (CPU) cores, the CPU cores dynamically controlling prefetching based on prefetch accuracy;

[0015] Figure 2 A prefetcher for dynamically controlling the prefetching of CPU cores based on prefetch accuracy, according to embodiments of the present disclosure, is shown.

[0016] Figure 3 yes Figure 2 A block diagram of an exemplary embodiment of a prefetch accuracy tracker for a prefetcher;

[0017] Figure 4This is a flowchart illustrating a process for dynamically controlling the prefetching of a CPU core of a processor in a computing system according to embodiments of the present disclosure;

[0018] Figure 5 Showing Figure 4 An exemplary embodiment of the process; and

[0019] Figure 6 This is a block diagram of an exemplary computer system, which includes a processor comprising multiple CPU cores and peripheral devices and other resources, including a memory system accessed via an internal coherent architecture bus, wherein the memory system supports address range memory mirroring. Detailed Implementation

[0020] The aspects disclosed herein include dynamically controlling prefetching in a computing system based on prefetch accuracy. Related methods and computer-readable media are also disclosed. In an exemplary aspect, a computing system is provided, comprising a processor including one or more central processing unit (CPU) cores having associated cache memories. At least one of the CPU cores is configured to control the prefetching of data and / or instructions from memory to the associated cache memory based on prefetch accuracy. In an exemplary embodiment, the CPU core generates a value indicating prefetch accuracy based on prefetch line filling and demand hits in the cache memory. More specifically, in an exemplary embodiment, for each instance of prefetch line filling, in which data is prefetched from a memory line in memory and stored in the memory line of the cache memory, the generated value is adjusted (e.g., decreased) by a first value, and for each instance of a demand hit accessing prefetched data from the cache memory, the generated value is adjusted (e.g., decreased) by a second value. Based on the indicated prefetch accuracy value, prefetching is deactivated or partially deactivated when the prefetch accuracy is less than a certain accuracy threshold. This reduces the number of prefetch requests when the prefetch accuracy is low, thereby reducing memory bandwidth utilization and, in the case of multi-CPU processors, reducing contention for memory bandwidth among multiple CPU cores.

[0021] In this regard, in one exemplary aspect, a computing system is provided. The computing system includes a CPU core and a cache memory for the CPU core. The CPU core is configured to generate a value indicating a prefetch accuracy performed by the CPU core, and to control the prefetch performed by the CPU core based on the value indicating the prefetch accuracy.

[0022] in this regard, Figure 1This is a block diagram of an exemplary computing system 100, which includes a processor 102 configured to perform computational tasks based on the execution of program code. The processor 102 in this example includes one or more corresponding CPU cores 104(1) to 104(N), where “N” is a positive integer representing the number of CPU cores included in the processor 102. As discussed in more detail below, one or more of the CPU cores 104(1) to 104(N) can be configured to generate a value indicating a prefetch accuracy performed by the CPU core, and to control the prefetching performed by the CPU core based on the value indicating the prefetch accuracy. The processor 102, along with other specific computing resources, can be packaged in an integrated circuit (IC) chip 106, such as to provide a system-on-a-chip (SoC). The CPU cores 104(1) to 104(N) in the processor 102 are configured to issue memory access requests (i.e., data read requests and data write requests) to a memory system 108, which is part of the computing system 100.

[0023] Memory system 108 includes cache memory system 110 and main memory 112 as system memory. In this example, main memory 112 is a separate memory external to IC chip 106. For example, main memory 112 may be random access memory (RAM), such as one or more DDR dynamic RAM (DRAM) chips. Main memory 112 is memory that is fully addressable by the physical address (PA) space of computing system 100. In the example shown, cache memory system 110 includes cache memories 114(1) to 114(N) dedicated to the respective CPU cores 104(1) to 104(N) (e.g., level 1 (L1) cache) and a shared cache memory 116 shared by CPU cores 104(1) to 104(N), for example, as level 2 (L2) or level 3 (L3) cache. In the example shown, shared cache memory 116 is separate from processor 102 but located within IC chip 106. It should be noted that the shared cache memory 116 is optional. It should also be noted that, in an alternative embodiment, cache memories 114(1) to 114(N) are not included in the cache memory system 110, and CPU cores 104(1) to 104(N) share the shared cache memory 116 (e.g., as a shared L1 cache). In this alternative embodiment, the shared cache memory 116 may alternatively be implemented within the processor 102, rather than outside the processor 102. Furthermore, it should be noted that embodiments of this disclosure are not limited to any particular cache or memory organization or hierarchy, and can be applied to any cache or memory level.

[0024] Continue to refer to Figure 1The computing system 100 also includes a memory controller 118, which controls access to memory lines 120(1) to 120(L) in main memory 112 (i.e., memory locations of a specific size, such as the size of cache lines in cache memory system 110) in response to receiving a memory access request. For example, any of the CPU cores 104(1) to 104(N) can, as a requesting device, issue a memory access request to read data from main memory 112, for example, in response to processing a load instruction or a store instruction. The memory access request includes the target address of the data to be read from main memory 112. Using CPU core 104(1) as an example, if the requested data is not in cache memory 114(1) (i.e., a cache miss for cache memory 114(1), which can be considered an L1 cache memory), cache memory 114(1) sends a memory access request to shared cache memory 116 via interconnect bus 122 in this example. The shared cache memory can be an L2 or L3 cache memory. If the requested data is not in the shared cache memory 116 (i.e., a cache miss occurs in the shared cache memory 116), the shared cache memory 116 sends a memory access request to the main memory 112 via the memory controller 118. Finally, the requested data is returned from the memory system 108 to the CPU core 104 (1).

[0025] According to embodiments of this disclosure, computing system 100 uses prefetching of data, instructions, or both. For the remainder of the description, embodiments of this disclosure are described with respect to prefetching of data; however, it should be understood that the embodiments described herein are equally applicable to prefetching of instructions. In this respect, CPU cores 104(1) to 104(N) include corresponding prefetchers 124(1) to 124(N) that operate to issue prefetch requests (i.e., memory access requests for prefetching purposes) before the executing program needs data to store the requested (i.e., prefetched) data in corresponding cache memories 114(1) to 114(N). Prefetchers 124(1) to 124(N) are circuitry within the corresponding CPU cores 104(1) to 104(N) and, by way of example, can be implemented as part of the instruction pipelines of CPU cores 104(1) to 104(N). As described in detail below, taking prefetcher 124(1) as an example, prefetcher 124(1) dynamically controls prefetching based on prefetch accuracy. As used herein, the “prefetch accuracy” of a CPU core is a measure of whether prefetched data is used (i.e., accessed) by that CPU core, for example, before the prefetched data is evicted from the cache or before some other time-dependent condition occurs. If the measured prefetch accuracy is equal to or greater than a specific prefetch accuracy threshold (e.g., 90%), prefetching is enabled. Conversely, if the measured prefetch accuracy is less than a specific prefetch accuracy threshold or less than a different specific smaller prefetch accuracy threshold, prefetching is partially or fully disabled. In a preferred embodiment, prefetching is only partially disabled such that prefetch accuracy continues to be measured while prefetching is partially disabled, and if the prefetch accuracy increases to or greater than the specific prefetch accuracy threshold, prefetching is re-enabled. Thus, prefetching is dynamically controlled based on prefetch accuracy. In other words, the number of prefetch requests issued by CPU core 104(1) is dynamically controlled based on prefetch accuracy. Prefetching can be controlled in the same way at other CPU cores 104(2) to 104(N). As a result, when the corresponding prefetch accuracy is low, the number of prefetch requests issued by CPU cores 104(1) to 104(N) is significantly reduced, which in turn reduces memory bandwidth contention among CPU cores 104(1) to 104(N).

[0026] As an example, Figure 2A prefetcher 124(1) according to an embodiment of the present disclosure is shown in more detail. This description also applies to other prefetchers 124(2) to 124(N). As shown, prefetcher 124(1) includes a prefetch request generator 200 and a prefetch accuracy tracker 202. Prefetch request generator 200 generates prefetch requests 204 for data (and / or instructions) and sends prefetch requests 204 to memory system 108. In this example, prefetch request 204 is sent to main memory 112; however, prefetch request 204 may be sent to some higher-level cache (e.g., a level 3 (L3) cache) or may be sent from an L1 prefetcher to fetch data from an L2 cache. For each prefetch request 204, data is requested from a specific memory line 120(1) to 120(L) of main memory 112 and the data is stored in a memory line within cache memory 114(1). Bits or other indicators associated with the memory line within cache memory 114(1) are set to indicate that the memory line is a prefetched memory line. This action is called prefetch (PF) line filling. For each instance of PF line filling, prefetch request generator 200 provides PF line filling indicator 206 to prefetch accuracy tracker 202. In one embodiment, the PF line filling indicator 206 is a single bit set to a first state (e.g., logic "1") to indicate PF line filling and otherwise set to a second state (e.g., logic "0"). Additionally, for each memory access request 208 from CPU core 104(1), if a hit exists in cache memory 114(1) containing a memory line (i.e., a PF line) containing prefetched data, a demand hit indicator 210 is provided to prefetcher 124(1). Again, a memory line within cache memory 114(1) containing prefetched data can be indicated by associated bits or indicators within cache memory 114(1). In one embodiment, the demand hit indicator 210 is a single bit that is set to a first state (e.g., logic "1") to indicate a hit on a prefetched line stored in cache memory 114(1), and is otherwise set to a second state (e.g., logic "0").

[0027] The prefetch accuracy tracker 202 generates a metric for the prefetch accuracy of CPU core 104(1) (i.e., prefetcher 124(1) for CPU core 104(1)) based on the PF fill line indicator 206 and the demand hit indicator 210. More specifically, the prefetch accuracy tracker 202 maintains an unsigned saturating counter (CNT) that is dynamically updated in response to PF line fills indicated by the PF fill line indicator 206 and demand hits indicated by the demand hit indicator 210. To update the unsigned saturating counter (CNT), the prefetch accuracy tracker 202 adjusts (e.g., increases) a first value (n) of the unsigned saturating counter (CNT) for each PF line fill and adjusts (e.g., decreases) a second value (m) of the unsigned saturating counter (CNT) for each demand hit. The first value (n) and the second value (m) are non-zero integer values ​​where |n| < |m|. According to an exemplary embodiment described herein, the prefetch accuracy tracker 202 adjusts the unsigned saturation counter (CNT) by increasing the CNT by a first value (n) for each PF row fill and decreasing the CNT by a second value (m) for each demand hit. In this case, the first value (n) and the second value (m) are positive non-zero integer values, where n < m, and the ratio of n / m represents an accuracy threshold such that if the prefetch accuracy is less than the accuracy threshold, the value of CNT will tend to increase, and if the prefetch accuracy is greater than the accuracy threshold, the value of CNT will tend to decrease. Thus, the value of CNT can serve as a measure of prefetch accuracy.

[0028] In one embodiment, the second value (m) is a fixed value, such as 100, and the first value (n) is configured based on the desired prefetch accuracy. For example, if the desired prefetch accuracy is 90% (i.e., 90% of the demand hits of the prefetched memory rows will be met), the first value (n) can be configured as n = 0.9m. Thus, if m = 100, then n = 90. It should be noted that, to avoid non-integer values ​​for n, the value of n can be calculated as n = ceil(A*m) or n = floor(A*m), where A is the desired threshold accuracy, ceil() is the ceiling function, and floor is the floor function. Alternatively or in one embodiment, the first value (n), the second value (m), or both the first value (n) and the second value (m) are dynamically configured based on memory bandwidth utilization (e.g., typically configured by CPU core 104(1) or processor 102), such that the accuracy threshold is dynamically controlled based on memory bandwidth utilization. Memory bandwidth utilization can be provided by memory system 108, or it can be determined based on or corresponding to the number of memory access requests made by CPU core 104(1) or all CPU cores 104(1) to 104(N) within a defined time period, based on the running average number of memory access requests over a defined time window, etc.

[0029] The prefetch accuracy tracker 202 further operates to dynamically control prefetching (i.e., control the operation of the prefetch request generator 200) based on the prefetch accuracy of CPU core 104(1) as indicated by the unsigned saturation counter (CNT). More specifically, prefetching is enabled if the prefetch accuracy of the measurement indicated by the unsigned saturation counter (CNT) is equal to or greater than a specific prefetch accuracy threshold (e.g., accuracy threshold TH1, which may be, for example, 90%). Conversely, prefetching is disabled or partially disabled if the prefetch accuracy of the measurement indicated by the unsigned saturation counter (CNT) is less than a specific prefetch accuracy threshold (e.g., accuracy threshold TH1 or alternatively, accuracy threshold TH2 less than TH1). As described in more detail below, the CNT threshold (also referred to herein as the "timeliness threshold") is used to determine when prefetching is partially or fully disabled or enabled based on the CNT value.

[0030] When the prefetch accuracy tracker 202 decides to partially disable prefetching based on the CNT value and a timeliness threshold, prefetching is partially disabled by activating a mechanism to reduce the number of prefetch requests issued by the prefetcher 124(1) (e.g., by the prefetch request generator 200). Ideally, the number of prefetch requests issued by the prefetcher 124(1) when prefetching is partially disabled is much smaller than the number of prefetch requests issued by the prefetcher 124(1) when prefetching is activated. For example, prefetching can be partially disabled by filtering the prefetch requests 204 generated by the prefetch request generator 200, such that only a subset of the generated prefetch requests 204 (e.g., prefetch requests 204 for a subset of memory locations within main memory 112) is sent to main memory 112. In a preferred embodiment, prefetching is only partially disabled, such that prefetch accuracy continues to be measured based on a reduced number of prefetch requests issued by prefetcher 124(1), and prefetching is re-enabled if the prefetch accuracy increases to or exceeds a specific prefetch accuracy threshold (e.g., TH1).

[0031] Figure 3 This is a block diagram of an exemplary embodiment of the prefetch accuracy tracker 202. As shown, to maintain the unsigned saturation counter (CNT), the prefetch accuracy tracker 202 includes a multiplexer (MUX) 300, a register 302 referred to herein as "CNT register 302," and adders 304 and 306. Adder 308 is optional and may be included in an implementation of the computation system 100 whereby the filling of a PF line of one memory line and the demand hit of another memory line can occur simultaneously. In operation, the CNT register 302 is initialized to an initial value, which is 0 in this example. In this example, the PF row fill indicator 206 (a single bit in this example) is provided to the "1" control input of the MUX 300, the demand hit indicator 210 (a single bit in this example) is provided to the "0" control input of the MUX 300, the CNT value is provided to the "0" input of the MUX 300, CNT+n output by adder 304 is provided to the "1" input of the MUX 300, CNT-m output by adder 306 is provided to the "2" input of the MUX 300, and optionally, CNT+nm output by adder 308 is provided to the "3" input of the MUX 300. Therefore, in this example, the output of the MUX 300 is:

[0032] ●CNT, if both the PF row fill indicator 206 and the demand hit indicator 210 are "0" (i.e., if neither a PF row fill nor a demand hit occurred during the previous clock cycle).

[0033] ●CNT+n, if the PF row fill indicator 206 is "1" and the demand hit indicator 210 is "0" (i.e., if the PF row fill occurred during the previous clock cycle).

[0034] ●CNT-m, if demand hit indicator 210 is "1" and PF row fill indicator 206 is "0" (i.e., if a demand hit occurred during the previous clock cycle).

[0035] ● (Optional) CNT+nm, if both the PF row fill indicator 206 and the demand hit indicator 210 are "1" (i.e., if both the PF row fill and the demand hit occurred during the previous clock cycle).

[0036] On the rising edge of the clock (CLK), CNT register 302 is updated to store the value of the MUX 300's output. This continues for each clock cycle, dynamically updating CNT for each PF line fill and for each demand hit of the prefetched cache line.

[0037] The value CNT is a measure of the prefetch accuracy of prefetcher 124(1). More specifically, if the prefetch accuracy is less than a prefetch accuracy threshold defined by the ratio n / m (i.e., the expected prefetch accuracy), the value of CNT will trend in one direction (e.g., increase), otherwise it will trend in the opposite direction (e.g., decrease). Figure 3 In the examples, smaller CNT values ​​indicate a prefetch accuracy greater than a prefetch accuracy threshold, while larger CNT values ​​indicate a prefetch accuracy less than a prefetch accuracy threshold. Table 1 shows an example where the CNT value is updated over time, for example, where CNT is initialized to 0, n = 90, and m = 100. As can be seen from Table 1, for each PF row fill, CNT increases by 90, and for each demand hit for a prefetched row, CNT decreases by 100, where CNT saturates at 0 (i.e., cannot be less than 0). If the prefetch accuracy is equal to or greater than 90%, the CNT value will saturate at 0 over time; otherwise, the CNT value will continue to increase over time.

[0038]

[0039] Table 1

[0040] The prefetch accuracy tracker 202 also includes a comparator 310 that compares the value of the CNT to a specific threshold, which may be predefined (e.g., static) or configurable. This threshold is also referred to herein as the “timeliness threshold” because it allows a specific number of prefetches to occur before a demand hit is reached, prior to a declared low prefetch accuracy. If the value of the CNT is greater than the CNT threshold, the prefetcher accuracy is considered low, and prefetching is therefore disabled or at least partially disabled (e.g., an indication is sent to the prefetch request generator 200 to disable or partially disable prefetch request generation). Conversely, if the value of the CNT is not greater than the CNT threshold, the prefetch accuracy is considered high, and prefetching is enabled (i.e., on or fully activated). Table 2 shows an example where the CNT is initialized to 0, n = 90, m = 100, and the CNT threshold (i.e., the timeliness threshold) is 900. In the example in Table 2, the CNT increases to greater than the 900 threshold at time 108, and in response, prefetching is partially deactivated. When prefetching is partially deactivated, prefetch request generator 200 continues to output a small number of prefetch requests, and prefetch accuracy tracker 202 continues to update CNT. Then, in the example in Table 2, at time 174, CNT decreases to less than the 900 threshold, and as a result, prefetching is (fully) activated. It should be noted that although in Figure 3 The same CNT (i.e., timeliness threshold) is used in the examples and specific examples in Table 2 to determine when to activate prefetch and when to partially deactivate prefetch. However, in alternative embodiments, different CNT (i.e., timeliness) thresholds are used for activation and deactivation (e.g., CNT threshold X for activation and CNT threshold Y for deactivation / partial deactivation, where X and Y are positive integer values ​​and Y < X). Furthermore, regarding partial or complete deactivation, in one exemplary embodiment, different timeliness thresholds may be used, where a first CNT threshold may be used for partial deactivation and a second CNT threshold may be used for complete deactivation. Additionally or alternatively, other criteria may be considered when determining whether to partially or completely deactivate prefetch. Such criteria may include, for example, memory bandwidth utilization (e.g., complete deactivation if memory utilization is greater than a specific memory bandwidth utilization threshold).

[0041]

[0042] Table 2

[0043] It should be noted that Figure 3The exemplary embodiment of the prefetch accuracy tracker 202 shown is merely an example. However, various modifications will be apparent to those skilled in the art. For example, the PF row fill indicator 206 may alternatively be provided to the "0" control input of the MUX 300, and the demand hit indicator 210 may alternatively be provided to the "1" control input of the MUX 300, in which case the output of adder 304 will alternatively be provided to the "2" input of the MUX 300, and the output of adder 306 will alternatively be provided to the "1" input of the MUX 300.

[0044] As another example, in Figure 3 In one embodiment, a small value of CNT indicates a large prefetch accuracy, and a large value of CNT indicates a small prefetch accuracy. However, in an exemplary alternative embodiment, a large value of CNT indicates a large prefetch accuracy, and a small value of CNT indicates a small prefetch accuracy. In this alternative, CNT is initialized to a large value (e.g., the maximum value of an unsigned saturation counter), a first value (n) is decreased for each PF row, and a second value (m) is increased for each demand hit. The CNT value is then compared to a threshold; if it is less than the threshold, prefetching is deactivated or partially deactivated.

[0045] As yet another example, although in the exemplary embodiments described above, when the prefetch accuracy is low, prefetching is preferably partially disabled, such that prefetch accuracy continues to be monitored (i.e., CNT continues to be updated) while prefetching is partially disabled, this disclosure is not limited thereto. For example, in an exemplary alternative embodiment, prefetching is fully deactivated in response to determining that the prefetch accuracy is low (e.g., CNT drops below a certain threshold). In this case, prefetching can subsequently be reactivated based on the occurrence of one or more conditions, such as, for example, the expiration of a defined or configured amount of time after prefetching has been fully deactivated, a drop in memory bandwidth utilization below a defined or configured bandwidth utilization threshold, a decrease in CNT value to below a threshold due to a mechanism that reduces the value of CNT over time in a predefined or predetermined manner (e.g., CNT decreases by X every Y amount of time), and so on.

[0046] As yet another example, while a single accuracy threshold defined by a ratio of n / m is used in the exemplary embodiments described above, this disclosure is not limited thereto. For example, separate unsigned saturation counters with different n and / or m values ​​can be used to monitor prefetch accuracy relative to a first prefetch accuracy threshold for partially disabling prefetching and a second prefetch accuracy threshold for completely disabling prefetching. As a specific, non-limiting example, prefetching can be partially disabled when a first CNT value used to monitor the first accuracy threshold is less than a first timeliness threshold, and prefetching can be completely disabled when a second CNT value used to monitor the second accuracy is less than a second timeliness threshold, wherein the first accuracy threshold is greater than the second accuracy threshold.

[0047] Up to this point, the description has focused on computing system 100. The description will now turn to a process for dynamically controlling prefetching in a computing system (e.g., computing system 100) according to embodiments of the present disclosure. At this point, Figure 4 This is a flowchart illustrating a prefetching process for dynamically controlling a computing system (e.g., computing system 100) according to embodiments of the present disclosure. Optional actions are... Figure 4 The dashed line / box indicates this. Furthermore, although... Figure 4 The actions shown occur in a specific order, but these actions can be performed in any suitable order unless otherwise specified or explicitly required. In one example, Figure 4 The process is performed separately by each of the prefetchers 124(1) to 124(N) of the corresponding CPU cores 104(1) to 104(N). For the purposes of this description, Figure 4 The process is described as being performed by CPU core 104(1), and more specifically, by prefetcher 124(1) of CPU core 104(1).

[0048] As shown in the figure, CPU core 104(1) generates a value (e.g., CNT) indicating the prefetch accuracy of a prefetch performed by CPU core 104(1) (Action 400). In one embodiment, the value indicating the prefetch accuracy of a subsequent prefetch performed by CPU core 104(1) is an unsigned saturation counter (CNT) value, and generating the value indicating the prefetch accuracy of a prefetch performed by CPU core 104(1) includes adjusting the unsigned saturation counter (CNT) value (Action 400A) to a first value for each instance of prefetch line filling in which prefetched memory lines are stored in cache memory for CPU core 104(1); and adjusting the unsigned saturation counter (CNT) value (Action 400B) to a second value for each instance of a hit on a prefetched memory line in cache memory. In one embodiment, the first value is smaller than the second value. The first and second values ​​can be chosen to be proportional to each other, wherein at least one of the first and second values ​​is also chosen to be proportional to the target prefetch accuracy of CPU core 104(1) (e.g., the ratio of the first value to the second value defines the target prefetch accuracy or accuracy threshold). The selection of the first and second values ​​can further take into account the size of the unsigned saturation counter. In one embodiment, the second value is a configurable or predefined value, and the first value is a function of the target prefetch accuracy of CPU core 104(1). In one embodiment, prefetch requests from CPU core 104(1) originate from memory lines of the memory of computing system 100 (e.g., main memory 112) stored in cache memory (e.g., cache memory 114(1)), and one or both of the first and second values ​​are a function of the amount of bandwidth for processing memory access requests from CPU core 104(1) and one or more additional CPU cores of computing system 100 that are currently in use.

[0049] In one embodiment, adjusting the unsigned saturation counter (CNT) in action 400A includes increasing the unsigned saturation counter (CNT) by a first value (n) for each instance of prefetch line filling in which prefetched memory lines are stored in cache memory for CPU core 104 (1) (action 400A1), and adjusting the unsigned saturation counter (CNT) value by a second value in action 400B includes decreasing the unsigned saturation counter (CNT) by a second value (m) for each instance of a hit of a prefetched memory line in cache memory (action 400B1).

[0050] CPU core 104(1) controls prefetching performed by CPU core 104(1) based on a value indicating prefetch accuracy (e.g., CNT) (action 402). In one embodiment, controlling prefetching includes determining, based on the value indicating prefetch accuracy, that the prefetch accuracy of CPU core 104(1) is less than a first prefetch accuracy threshold (action 402A; yes), and, in response to the prefetch accuracy of CPU core 104(1) being less than the first prefetch accuracy threshold, at least partially deactivating prefetching of CPU core 104(1) (action 402B). It should be noted that in the above exemplary embodiment, the prefetch accuracy is determined to be less than the first prefetch accuracy when the CNT value is less than a specific CNT threshold (also referred to herein as a timeliness threshold). When prefetching is partially deactivated, CPU core 104(1) issues fewer prefetch requests than when prefetching is activated. In this example, if the prefetch accuracy indicated by the value is not less than the threshold accuracy, prefetching is enabled when needed (e.g., if currently partially deactivated) (action 402C). The process then returns to action 400 and is repeated.

[0051] In one embodiment, if prefetching is partially deactivated in action 402B, CPU core 104(1) will continue to update the value indicating prefetch accuracy (e.g., CNT). When it is determined in action 402A that the prefetch accuracy indicated by this value is no longer less than the threshold accuracy (action 402A, No), CPU core 104(1) fully reactivates (i.e., enables) prefetching in action 402C. In the example above, when the CNT value is less than the CNT threshold, it can be determined that the prefetch accuracy is less than the accuracy threshold.

[0052] If the prefetch is fully deactivated in action 402B, the prefetch may subsequently be reactivated based on the occurrence of one or more conditions, such as, for example, the expiration of a defined or configured amount of time after the prefetch is fully deactivated, the memory bandwidth utilization dropping to less than a defined or configured bandwidth utilization threshold, the CNT decreasing to less than a threshold due to a mechanism that reduces the value of CNT over time in a predefined or predetermined manner (e.g., CNT decreases by X every Y amount of time), and so on.

[0053] exist Figure 4In the example, in action 402A, the CNT (or timeliness) threshold used for partially deactivating or deactivating the prefetch is the same as the CNT (or timeliness) threshold used to determine when to reactivate the prefetch. However, in an exemplary alternative embodiment, different CNT thresholds are used instead, where a first CNT threshold (TH1) is used to determine when to deactivate or partially deactivate the prefetch, and a second CNT threshold (TH2) is used to determine when to (re)activate the prefetch, where TH1 < TH2. By using separate CNT thresholds, the ping-pong effect can be avoided, in which CPU core 104(1) switches back and forth between a state where the prefetch is deactivated or partially deactivated and a state where the prefetch is activated when the value (CNT) is close to the CNT threshold.

[0054] Figure 5 This is a flowchart illustrating a process for dynamically controlling a prefetch in a computing system (e.g., in computing system 100) according to embodiments of the present disclosure, wherein a value indicating prefetch accuracy is an unsigned saturation counter (CNT), which is incremented by a first value (n) for each instance of PF row filling, and decremented by a second value (m) for each instance of a demand hit in the cache memory of the prefetched memory row. Optional actions are... Figure 5 The dashed line / box is used to indicate this. Figure 5 The process is Figure 4 An exemplary embodiment of the process. Furthermore, although... Figure 5 The actions shown occur in a specific order, but these actions can be performed in any suitable order unless otherwise specified or explicitly required. In one example, Figure 5 The process is performed separately by each of the prefetchers 124(1) to 124(N) of the corresponding CPU cores 104(1) to 104(N). For the purposes of this description, Figure 5 The process is described as being performed by CPU core 104(1), and more specifically, by prefetcher 124(1) of CPU core 104(1).

[0055] As shown in the figure, if CPU core 104(1) performs PF row filling (Action 500, Yes), then CPU core 104(1) increases CNT by a first value (n) (Action 502). If there is a demand hit in cache memory 114(1) for a prefetched row (e.g., prefetched data) (Action 504, Yes), then CPU core 104(1) decreases CNT by a second value (m) (Action 506). CPU core 104(1) determines whether CNT is greater than a specific CNT threshold (Action 508). If yes (Action 508, Yes), then CPU core 104(1) deactivates or partially deactivates the prefetch, as described above (Action 510). Otherwise, if CNT is not greater than the specific threshold (Action 508, No), then CPU core 104(1) may activate (i.e., fully activate) the prefetch when needed (e.g., if the prefetch was previously deactivated or partially deactivated) (Action 512). It should be noted that although in Figure 5 In the example, the same CNT threshold is used to determine when to activate prefetch and when to partially or completely deactivate prefetch. However, in exemplary alternative embodiments, different CNT thresholds are used for activation and deactivation (e.g., CNT threshold X for activation and CNT threshold Y for deactivation / partial deactivation, where X and Y are positive integer values ​​and Y < X). Furthermore, regarding partial or complete deactivation, in one exemplary embodiment, different CNT thresholds can be used, where a first CNT threshold can be used for partial deactivation, and, for example, a second CNT threshold can be used for complete deactivation if the CNT value continues to increase. Additionally or alternatively, other criteria can be considered when determining whether to partially or completely deactivate prefetch. Such criteria may include, for example, memory bandwidth utilization (e.g., complete deactivation if memory utilization is greater than a specific memory bandwidth utilization threshold).

[0056] Figure 6 An example of a processor-based system 600 is shown, which can be used as an example. Figure 1 The computing system 100 is the same as or similar to the processor-based system 600. The processor-based system 600 includes a processor 602, which includes CPU cores 604(1) to 604(N). The processor 602 has a coupled cache memory 606 for fast access to temporarily stored data. The processor 602 is coupled to a system bus 608 and can interconnect devices included in the processor-based system 600. Although Figure 6Not shown, but multiple system buses 608 may be provided, each of which constitutes a different architecture. It is well known that processor 602 communicates with these other devices by exchanging address, control, and data information on system buses 608. For example, processor 602 may transmit memory write and read requests to memory system 610. Memory system 610 includes memory controller 612 and memory 614, which may be disposed in one or more memory chips, such as one or more DRAM chips for storing data. CPU cores 604(1) to 604(N) include prefetchers 616(1) to 616(N) that operate as described above with respect to prefetchers 124(1) to 124(N) to prefetch data and / or instructions from memory 614 and store the prefetched data and / or instructions in cache memory 606. According to references herein... Figures 1 to 5 In any of the embodiments described, CPU cores 604(1) to 604(N) operate to dynamically control prefetching based on prefetch accuracy.

[0057] Other devices can be connected to system bus 608. For example... Figure 6 As illustrated, these devices may include one or more input devices 618, one or more output devices 620, one or more network interface devices 622, and one or more display controllers 624. Input devices 618 may include any type of input device, including but not limited to input buttons, switches, voice processors, etc. Output devices 620 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 622 may be any device configured to allow data exchange to and from network 626. Network 626 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless LANs (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. Network interface devices 622 may be configured to support any desired type of communication protocol.

[0058] Processor 602 may also be configured to access display controller 624 via system bus 608 to control information sent to one or more displays 628. Display controller 624 sends information to be displayed to displays 628 via one or more video processors 630, which process the information to be displayed into a format suitable for displays 628. Displays 628 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. Processor 602 and its cache memory 606, memory system 610 and / or network 626 may include computer instructions 632, as an example, serving as a non-transitory computer-readable medium 634, to control the functions of processor 602 and CPU cores 604(1) to 604(N). Any of the functions described above for the prefetchers 616(1) to 616(N) (i.e., prefetchers 114(1) to 114(N)) may be the result of the prefetchers 616(1) to 616(N) and / or other controllers in the processor 602 executing computer instructions 632.

[0059] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the apparatus described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly demonstrate this interchangeability, the various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How this functionality is implemented depends on the specific application, design options, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0060] The various exemplary logic blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or carried out using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors combined with a DSP core, or any other such configuration).

[0061] The aspects disclosed herein can be embodied in hardware and instructions stored in that hardware, and can reside in, for example, RAM, flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of non-transitory computer-readable medium known in this art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0062] It should also be noted that the operational steps described in any of the exemplary aspects herein are for illustrative and descriptive purposes. The described operations can be performed using many different sequences besides those shown. Furthermore, the operation described in a single operational step may actually be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that those skilled in the art will readily appreciate that the operational steps shown in the flowcharts can be modified in many different ways. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0063] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A computing system, characterized in that, include: The processor includes a central processing unit (CPU) core and a cache memory for the CPU core; The CPU core is configured as follows: Generate a value indicating the prefetch accuracy of the CPU core, the prefetch accuracy being for prefetching data, instructions, or both data and instructions from system memory outside the processor to store in the cache memory for the CPU core; as well as The prefetching performed by the CPU core is controlled based on the value indicating the prefetch accuracy.

2. The computing system according to claim 1, characterized in that, The value indicating the prefetch accuracy of the CPU core is an unsigned saturation counter value, and the CPU core adjusts the unsigned saturation counter value by a first value for each instance of prefetch line filling, in which prefetched memory lines are stored in the cache memory for the CPU core, and adjusts the unsigned saturation counter value by a second value for each instance of a hit on a prefetched memory line in the cache memory, thereby generating the value indicating the prefetch accuracy of the CPU core.

3. The computing system according to claim 2, characterized in that, The size of the first value is smaller than the size of the second value.

4. The computing system according to claim 3, characterized in that, The second value is a fixed value, and the first value is a function of the target prefetch accuracy of the CPU core.

5. The computing system according to claim 3, characterized in that, The prefetch request originates from a memory row of the computing system's memory, which is stored in the cache memory, and one or both of the first and second values ​​are functions of the amount of bandwidth for processing memory access requests from the CPU core and one or more additional CPU cores of the computing system that are currently in use.

6. The computing system according to claim 3, characterized in that, Adjusting the unsigned saturation counter value to the first value includes increasing the unsigned saturation counter by the first value for each instance of prefetch line filling, in which prefetched memory lines are stored in the cache memory for the CPU core, and adjusting the unsigned saturation counter value to the second value includes decreasing the unsigned saturation counter by the second value for each instance of a hit of a prefetched memory line in the cache memory.

7. The computing system according to claim 1, characterized in that, In order to control the prefetching of the CPU core, the CPU core is further configured to: Based on the value indicating the prefetch accuracy, it is determined that the prefetch accuracy of the CPU core is less than a first prefetch accuracy threshold; and In response to determining that the prefetch accuracy of the CPU core is less than the first prefetch accuracy threshold, the prefetch of the CPU core is partially deactivated.

8. The computing system according to claim 7, characterized in that, When prefetching is partially deactivated, the CPU core issues fewer prefetch requests than when prefetching is activated.

9. The computing system according to claim 7, characterized in that, The CPU core is further configured as follows: When the prefetch is partially deactivated, update the value indicating the prefetch accuracy of the CPU core; In order to activate the prefetch of the CPU core, it is determined that the prefetch accuracy of the CPU core has increased to or greater than a second prefetch accuracy threshold based on the updated value; as well as In response to determining that the prefetch accuracy of the CPU core has increased to or greater than the second prefetch accuracy threshold, the prefetching of the CPU core is activated.

10. The computing system according to claim 9, characterized in that, The first prefetch accuracy threshold is equal to the second prefetch accuracy threshold.

11. The computing system according to claim 9, characterized in that, The first prefetch accuracy threshold is less than the second prefetch accuracy threshold.

12. A method for controlling prefetching performed by the central processing unit (CPU) core of a processor in a computing system, characterized in that, The method includes: Generate a value indicating the prefetch accuracy of the CPU core, the prefetch accuracy being for prefetching data, instructions, or both data and instructions from system memory outside the processor to be stored in the cache memory of the CPU core within the processor; and The prefetching performed by the CPU core is controlled based on the value indicating the prefetch accuracy.

13. The method according to claim 12, characterized in that, The value indicating the prefetch accuracy of the CPU core is an unsigned saturation counter value, and generating the value indicating the prefetch accuracy of the CPU core includes: For each instance of prefetch line filling, the unsigned saturation counter value is adjusted to a first value, in which prefetched memory lines are stored in the cache memory for the CPU core; and For each instance of a hit in the prefetched memory row of the cache memory, the unsigned saturation counter value is adjusted to a second value.

14. The method according to claim 13, characterized in that, The size of the first value is smaller than the size of the second value.

15. The method according to claim 14, characterized in that, The second value is a fixed value, and the first value is a function of the target prefetch accuracy of the CPU core.

16. The method according to claim 14, characterized in that, The prefetch request of the CPU core originates from a memory line of the computing system's memory stored in the cache memory, and one or both of the first and second values ​​are functions of the amount of bandwidth for processing memory access requests from the CPU core and one or more additional CPU cores of the computing system that are currently in use.

17. The method according to claim 14, characterized in that: Adjusting the unsigned saturation counter value to the first value includes increasing the unsigned saturation counter by the first value for each instance of prefetch line filling, in which prefetched memory lines are stored in the cache memory for the CPU core; as well as Adjusting the unsigned saturation counter value to the second value includes decreasing the unsigned saturation counter value by the second value for each instance of a hit of a prefetched memory line in the cache memory.

18. The method according to claim 12, characterized in that, The prefetching of the CPU core includes: Based on the value indicating the prefetch accuracy, it is determined that the prefetch accuracy of the CPU core is less than a first prefetch accuracy threshold; and In response to determining that the prefetch accuracy of the CPU core is less than the first prefetch accuracy threshold, the prefetch of the CPU core is partially deactivated.

19. The method according to claim 18, characterized in that, When prefetching is partially deactivated, the CPU core issues fewer prefetch requests than when prefetching is activated.

20. The method according to claim 18, characterized in that, Further includes: When the prefetch is partially deactivated, update the value indicating the prefetch accuracy of the CPU core; In order to activate the prefetch of the CPU core, it is determined that the prefetch accuracy of the CPU core has increased to or greater than a second prefetch accuracy threshold based on the updated value; as well as In response to determining that the prefetch accuracy of the CPU core has increased to or greater than the second prefetch accuracy threshold, the prefetching of the CPU core is activated.

21. The method according to claim 20, characterized in that, The first prefetch accuracy threshold is equal to the second prefetch accuracy threshold.

22. The method according to claim 20, characterized in that, The first prefetch accuracy threshold is less than the second prefetch accuracy threshold.

23. A non-transitory computer-readable medium, characterized in that, The non-transitory computer-readable medium stores computer-executable instructions that, when executed by a processor, cause the processor to: Generate a value indicating the prefetch accuracy of the central processing unit (CPU) core of the processor, the prefetch accuracy being for prefetching data, instructions, or both data and instructions from system memory outside the processor to store in a cache memory within the processor for the CPU core; as well as The prefetching performed by the CPU core is controlled based on the value indicating the prefetch accuracy.

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