Branch execution method under single instruction multiple thread architecture and general purpose graphic processor

Abstract

This application provides a branch execution method under a single-instruction multithreaded architecture and a general-purpose graphics processor. The method is applied to a general-purpose graphics processor (GPGPU), which includes a processing unit and a circuit unit. The method includes: the processing unit identifies a thread branch and acquires branch information, including a convergence point thread mask, a first branch count, a first branch thread mask, a second branch count, and a second branch thread mask; the processing unit inputs the branch information to the circuit unit, causing the circuit unit to complete a first setting, which includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to a first stack layer, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask; the processing unit executes a first target branch program; after the first target branch program is executed, the processing unit triggers the circuit unit to complete a second setting, which includes setting the program counter to the second branch count and the thread mask to the second branch thread mask based on the data saved in the first stack layer; the processing unit executes a second target branch program. By utilizing this branch execution method under the single instruction multithreaded architecture and the general-purpose graphics processor, good processing performance can still be maintained under the SIMT architecture with the low hardware complexity of GPGPU.

Description

Technical Field

[0001] This application belongs to the field of computer technology, specifically relating to a branch execution method, apparatus, and computer-readable storage medium under a single instruction multithreaded architecture. Background Technology

[0002] In the architecture of general-purpose computing on graphics processing units (GPGPU) chips, the Single Instruction, Multiple Data (SIMD) architecture has relatively low flexibility, while the Single Instruction, Multi-Thread (SIMT) architecture can balance user programming flexibility with application performance. Currently, the SIMT architecture can be implemented in two ways: firstly, through hardware, by creating a pipeline for each thread and controlling the branching and aggregation of threads within a thread bundle through specific instructions; however, this approach increases hardware area overhead and complexity. Secondly, it can be implemented in software, with the compiler controlling thread branching and aggregation through a software stack. However, the software solution reduces branch execution efficiency, increases program execution time, and degrades application performance.

[0003] Therefore, how to maintain good processing performance under the SIMT architecture while keeping the hardware complexity of GPGPU relatively low is an urgent problem to be solved. Summary of the Invention

[0004] To address the problems existing in the prior art, a branch execution method and a general-purpose graphics processor under a single instruction multithreaded architecture are proposed. By using this branch execution method and general-purpose graphics processor under a single instruction multithreaded architecture, good processing performance can still be maintained under the SIMT architecture with the premise of low hardware complexity of GPGPU.

[0005] This application provides the following solutions.

[0006] In a first aspect, this application provides a branch execution method under a single-instruction multithreaded architecture, characterized in that the method is applied to a general-purpose graphics processing unit (GPGPU), which includes processing units and circuit units, and the method includes:

[0007] If the processing unit identifies a thread branch, it obtains the branch information, which includes the convergence point thread mask, the first branch count, the first branch thread mask, the second branch count, and the second branch thread mask. The processing unit inputs branch information into the circuit unit, enabling the circuit unit to complete the first setting. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask into the first stack layer of the stack, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask. The processing unit executes the first target branch program; After the processing unit completes the execution of the first target branch program, it triggers the circuit unit to complete the second setting. The second setting includes setting the program counter to the second branch count according to the data stored in the first stack layer, and setting the thread mask to the second branch thread mask. The processing unit executes the second target branch program.

[0008] In some possible embodiments, the method further includes: After the processing unit completes the execution of the second target branch program, it inputs the preset count into the circuit unit, causing the circuit unit to complete the third setting. The third setting includes setting the program counter to the preset count, setting the thread mask to the convergence point thread mask according to the data stored in the first stack layer, and deleting the branch information in the stack.

[0009] In some possible embodiments, the general-purpose graphics processor is also provided with a circuit triggering unit, and the branch information also includes a branch level number, which indicates the function nesting level corresponding to the second branch program; After the processing unit completes the execution of the first target branch program, the trigger circuit triggers the unit, including: After the processing unit completes the execution of the first target branch program, it inputs the current level number corresponding to the current program into the circuit trigger unit, so that the circuit trigger unit can complete the level comparison. The level comparison involves comparing the current level number with the branch level number. If the current level number matches the branch level number, the circuit unit is triggered.

[0010] In some possible embodiments, the circuit unit can complete the first setting, the second setting, or the third setting within one clock cycle, and the circuit triggering unit can complete the hierarchical comparison within one clock cycle.

[0011] In some possible embodiments, the stack is a last-in, first-out (LIFO) stack; The first setup includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to the top of the stack.

[0012] In some possible embodiments, the method further includes: If a thread branch is identified during the execution of the first target branch program or the second target branch program by the processing unit, the sub-branch information is obtained. The sub-branch information includes the sub-convergence point thread mask, the first sub-branch count, the first sub-branch thread mask, the second sub-branch count, and the second sub-branch thread mask. The processing unit inputs the sub-branch information into the circuit unit, enabling the circuit unit to complete the first sub-setting. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask into the second stack layer of the stack, setting the program counter to the first sub-branch count, and setting the thread mask to the first sub-branch thread mask. The processing unit executes the first sub-target branch program; After the processing unit completes the execution of the first sub-target branch program, it triggers the circuit unit to complete the second sub-setting. The second sub-setting includes setting the program counter to the second sub-branch count according to the data stored in the second stack layer, and setting the thread mask to the second sub-branch thread mask. The processing unit executes the second sub-target branch program; After the processing unit completes the execution of the second sub-target branch program, it inputs the sub-preset count into the circuit unit, enabling the circuit unit to complete the third sub-setting. The third sub-setting includes setting the program counter to the sub-preset count, setting the thread mask to the sub-convergence point thread mask according to the data stored in the second stack layer, and deleting the sub-branch information in the stack.

[0013] In some possible embodiments, the stack is a last-in, first-out (LIFO) stack; The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask to the top of the stack, and pushing the branch information onto the next stack level. The third sub-setting involves deleting sub-branch information from the stack, causing the branch information to return to the top of the stack.

[0014] Secondly, this application provides a general-purpose graphics processor, which includes a processing unit and a circuit unit. The processing unit is used to identify thread branches and then obtain branch information, including the convergence point thread mask, the first branch count, the first branch thread mask, the second branch count, and the second branch thread mask. The processing unit is used to input branch information into the circuit unit, so that the circuit unit completes the first setting. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask into the first stack layer of the stack, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask. The processing unit is used to execute the first target branch program; The processing unit is used to trigger the circuit unit after the first target branch program is executed, so that the circuit unit completes the second setting. The second setting includes setting the program counter to the second branch count according to the data saved in the first stack layer, and setting the thread mask to the second branch thread mask. The processing unit is used to execute the second target branch program.

[0015] In some possible embodiments, the processing unit is configured to input a preset count into the circuit unit after the second target branch program has been executed, so that the circuit unit completes a third setting. The third setting includes setting the program counter to a preset count, setting the thread mask to a convergence point thread mask according to the data stored in the first stack layer, and deleting the branch information in the stack.

[0016] In some possible embodiments, the general-purpose graphics processor is also provided with a circuit triggering unit, and the branch information also includes a branch level number, which indicates the function nesting level corresponding to the second branch program; The processing unit is used to input the current level number corresponding to the current program into the circuit trigger unit after the first target branch program is executed, so that the circuit trigger unit can complete the level comparison. The level comparison involves comparing the current level number with the branch level number. If the current level number matches the branch level number, the circuit unit is triggered.

[0017] In some possible embodiments, the circuit unit can complete the first setting, second setting, or third setting within one clock cycle, and the circuit triggering unit can complete the hierarchy comparison within one clock cycle. In some possible embodiments, the stack is a last-in-first-out stack; The first setup includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to the top of the stack.

[0018] In some possible embodiments, if the processing unit identifies a thread branch during the execution of the first target branch program or the second target branch program, the processing unit is further configured to obtain sub-branch information, which includes a sub-convergence point thread mask, a first sub-branch count, a first sub-branch thread mask, a second sub-branch count, and a second sub-branch thread mask. The processing unit is used to input sub-branch information into the circuit unit, so that the circuit unit completes the first sub-setting. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask into the second stack layer of the stack, setting the program counter to the first sub-branch count, and setting the thread mask to the first sub-branch thread mask. The processing unit is used to execute the first sub-target branch program; The processing unit is used to trigger the circuit unit after the first sub-target branch program is executed, so that the circuit unit completes the second sub-setting. The second sub-setting includes setting the program counter to the second sub-branch count according to the data saved in the second stack layer, and setting the thread mask to the second sub-branch thread mask. The processing unit is used to execute the second sub-target branch program; The processing unit is used to input the sub-preset count into the circuit unit after the second sub-target branch program is executed, so that the circuit unit can complete the third sub-setting. The third sub-setting includes setting the program counter to the sub-preset count, setting the thread mask to the sub-convergence point thread mask according to the data stored in the second stack layer, and deleting the sub-branch information in the stack.

[0019] In some possible embodiments, the stack is a last-in, first-out (LIFO) stack; The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask to the top of the stack, and pushing the branch information onto the next stack level. The third sub-setting involves deleting sub-branch information from the stack, causing the branch information to return to the top of the stack.

[0020] One of the advantages of the above embodiments is that by setting up a processing unit and a circuit unit in the GPGPU, the processing unit is used to execute the program and does not perform data setting. It does not need to consider the specific details of data setting, so there is no need to write a complex quantization program for the processing unit. The circuit unit is only used to perform data setting, so its hardware complexity is relatively low. Thus, the technical solution of this application can maintain good processing performance under the SIMT architecture with low hardware complexity of the GPGPU.

[0021] Other advantages of this application will be explained in more detail with reference to the following description and figures.

[0022] It should be understood that the above description is merely an overview of the technical solution of this application, so as to enable a clearer understanding of the technical means of this application and thus allow for its implementation in accordance with the contents of the specification. To make the above and other objects, features, and advantages of this application more apparent and understandable, specific embodiments of this application are illustrated below. Attached Figure Description

[0023] By reading the detailed description of the exemplary embodiments below, those skilled in the art will understand the advantages and benefits described herein, as well as other advantages and benefits. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart illustrating a branch execution method under a single-instruction multithreaded architecture provided in an embodiment of this application; Figure 2 An example diagram of a branch procedure provided for an embodiment of this application; Figure 3 A schematic diagram of the top of a SIMT stack provided in an embodiment of this application; Figure 4 A flowchart illustrating another branch execution method under a single-instruction multithreaded architecture provided in this application embodiment; Figure 5 This is a schematic diagram of a general-purpose graphics processor provided in an embodiment of this application.

[0024] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0025] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0026] In the description of embodiments of this application, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the disclosed features, figures, steps, behaviors, components, portions or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, figures, steps, behaviors, components, portions or combinations thereof.

[0027] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A alone, A and B at the same time, and B alone.

[0028] The terms "first," "second," etc., are used only for ease of description to distinguish identical or similar technical features and should not be construed as indicating or implying the relative importance or number of these technical features. Therefore, a feature defined by "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, the term "multiple" means two or more.

[0029] It should also be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] like Figure 1As shown, the branch execution method under a single instruction multithreaded architecture provided in this application embodiment is applied to a general-purpose graphics processing unit (GPGPU). The GPGPU is provided with processing units and circuit units. The method includes: S101: If the processing unit detects a thread branch, it obtains the branch information, which includes the convergence point thread mask, the first branch count, the first branch thread mask, the second branch count, and the second branch thread mask.

[0031] S102: The processing unit inputs the branch information into the circuit unit, so that the circuit unit completes the first setting. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask into the first stack layer of the stack, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask.

[0032] S103: The processing unit executes the first target branch program.

[0033] S104: After the processing unit completes the execution of the first target branch program, it triggers the circuit unit to complete the second setting. The second setting includes setting the program counter to the second branch count according to the data stored in the first stack layer, and setting the thread mask to the second branch thread mask.

[0034] S105: The processing unit executes the second target branch program.

[0035] It should be noted that the GPGPU in this embodiment may only have one program counter (PC). In this embodiment, both the program counter and the thread mask are set through circuit units to assist the processing unit in executing branch programs. The circuit unit in this application is a unit composed of hardware circuits. Because it is composed of hardware circuits, it has high execution efficiency and can usually complete the setting within one clock cycle.

[0036] The branch execution method under the single instruction multithreaded architecture provided in this application sets up processing units and circuit units in the GPGPU. The processing unit is used to execute the program and does not perform data setting. It does not need to consider the specific details of data setting, so there is no need to write complex quantization programs for the processing unit. The circuit unit is only used to perform data setting, so its hardware complexity is relatively low. Thus, the technical solution of this application can maintain good processing performance under the SIMT architecture with low hardware complexity of GPGPU.

[0037] In this embodiment, after the processing unit completes the execution of the second target branch program, it can input a preset count into the circuit unit, causing the circuit unit to complete a third setting. The third setting includes setting the program counter to a preset count, setting the thread mask to a convergence point thread mask based on the data stored in the first stack layer, and deleting the branch information in the stack. It should be noted that after the circuit unit completes the third setting, the program count and thread mask can be restored, and the branch program execution is complete, so as to prevent the program count and thread mask from affecting subsequent thread execution.

[0038] As an example, this application provides an example of a branching procedure. Figure 2 As shown, the processing unit identifies a thread branch through the BRANCH{.if} flag and informs the circuit unit that the software expects a restrictive if block. When the circuit unit executes, it will execute the if block in a limited manner, saving the information of the else block in the SIMT stack.

[0039] It should be noted that the circuit unit in this embodiment is a hardware circuit unit with high execution efficiency. In this embodiment, the circuit unit can complete the first setting, the second setting, or the third setting within one clock cycle.

[0040] In this embodiment of the application, the stack can be a last-in-last-out SIMT stack, such as... Figure 3 As shown, the first setting may include saving the convergence point thread mask (101), the second branch count (102), the second branch thread mask (103), and the branch level number (104) to the top of the stack.

[0041] As one possible implementation, the general-purpose graphics processor also includes a circuit triggering unit, and the branch information includes a branch level number, which indicates the function nesting level corresponding to the second branch program. In this embodiment, after the first target branch program is executed, the processing unit inputs the current level number corresponding to the current program into the circuit triggering unit, so that the circuit triggering unit completes the level comparison; the level comparison includes comparing the current level number with the branch level number. If the current level number and the branch level number are consistent, the circuit unit is triggered. This ensures that the branch execution method under the single instruction multithreaded architecture of this application can support the execution of branch programs with function nesting.

[0042] In practical applications, if the current level number does not match the branch level number, the circuit unit will not be triggered, and the GPGPU processor will skip the execution of the second branch program. The processor will only return to execute the second branch program when it recognizes that the level number matches the branch level number during subsequent program execution.

[0043] In the embodiments of this application, the circuit triggering unit is also a circuit hardware unit. Typically, the circuit triggering unit can complete the hierarchical comparison within one clock cycle.

[0044] In this embodiment, when the processing unit executes the branch procedure, it identifies a program branch and can execute it using logic similar to that described above. For example... Figure 4 As shown, the method also includes: S201: If a thread branch is identified during the execution of the first target branch program or the second target branch program by the processing unit, the sub-branch information is obtained. The sub-branch information includes the sub-convergence point thread mask, the first sub-branch count, the first sub-branch thread mask, the second sub-branch count, and the second sub-branch thread mask.

[0045] S202: The processing unit inputs the sub-branch information into the circuit unit, enabling the circuit unit to complete the first sub-setting. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask into the second stack layer of the stack, setting the program counter to the first sub-branch count, and setting the thread mask to the first sub-branch thread mask.

[0046] S203: The processing unit executes the first sub-target branch program.

[0047] S204: After the processing unit completes the execution of the first sub-target branch program, it triggers the circuit unit to complete the second sub-setting. The second sub-setting includes setting the program counter to the second sub-branch count according to the data stored in the second stack layer, and setting the thread mask to the second sub-branch thread mask.

[0048] S205: The processing unit executes the second sub-target branch program.

[0049] S206: After the processing unit completes the execution of the second sub-target branch program, it inputs the sub-preset count into the circuit unit, so that the circuit unit completes the third sub-setting. The third sub-setting includes setting the program counter to the sub-preset count, setting the thread mask to the sub-convergence point thread mask according to the data stored in the second stack layer, and deleting the sub-branch information in the stack.

[0050] It should be noted that the stack in this embodiment can be a last-in-last-out (LIFO) SIMT stack; the first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask to the top of the stack, and pushing the branch information onto the next stack level; the third sub-setting includes deleting the sub-branch information from the stack, so that the branch information returns to the top of the stack. After the sub-branch information is deleted, the sub-branch program is executed, and the first target branch program or the second target branch program can continue to be executed.

[0051] In this embodiment, program branches can also be identified during the execution of the first sub-target branch program or the second sub-target branch program. The execution logic is similar to that of the sub-branch program in the above embodiment, and will not be repeated here.

[0052] The branch execution method under a single-instruction multithreaded architecture provided in this application sets up a processing unit and a circuit unit in the GPGPU. The processing unit is used to execute the program and does not perform data setting, so it does not need to consider the specific details of data setting and therefore does not need to write complex quantization programs for the processing unit. The circuit unit is only used for data setting, so its hardware complexity is relatively low. The key reason why this application can improve the branch execution efficiency is that the processing unit does not need to maintain the SIMT stack. The circuit unit can complete the stack processing and target branch setting within one clock cycle. The technical solution of this application can use less hardware resources and consume less power because the software program executed by the processing unit can accurately instruct the circuit unit to query the stack, without the need for real-time hardware monitoring. Thus, the technical solution of this application can maintain good processing performance under the SIMT architecture with low hardware complexity of the GPGPU.

[0053] In the description of this specification, references to terms such as "some possible implementations," "some implementations," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that implementation or example is included in at least one implementation or example of this application, and the aforementioned terms do not necessarily refer to the same implementation or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more implementations or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different implementations or examples described in this specification, as well as the features of different implementations or examples.

[0054] The method flowcharts for embodiments of this application describe certain operations as different steps performed in a certain order. Such flowcharts are illustrative and not restrictive. Some steps described herein may be grouped together and performed in a single operation, or some steps may be divided into multiple sub-steps, and some steps may be performed in an order different from that shown herein. The various steps shown in the flowcharts may be implemented in any way by any circuit structure and / or tangible mechanism (e.g., by software running on a computer device, hardware (e.g., logic functions implemented by a processor or chip), and / or any combination thereof).

[0055] Those skilled in the art will understand that in the methods described in the above specific embodiments, the order in which the steps are written does not imply a strict execution order, and the specific execution order of each step should be determined by its function and possible internal logic.

[0056] Based on the branch execution method under a single instruction multithreaded architecture provided in the above embodiments, this application also provides a general-purpose graphics processor.

[0057] like Figure 5 As shown, the general-purpose graphics processor 100 provided in this embodiment of the application includes a processing unit 101 and a circuit unit 102. The processing unit 101 is used to identify a thread branch and then obtain branch information, including the convergence point thread mask, the first branch count, the first branch thread mask, the second branch count, and the second branch thread mask. Processing unit 101 is used to input branch information into circuit unit 102, so that circuit unit 102 completes the first setting. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask into the first stack layer of the stack, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask. Processing unit 101 is used to execute the first target branch program; Processing unit 101 is used to trigger circuit unit 102 after the first target branch program is executed, so that circuit unit 102 completes the second setting. The second setting includes setting the program counter to the second branch count according to the data stored in the first stack layer, and setting the thread mask to the second branch thread mask. The processing unit 101 is used to execute the second target branch program.

[0058] As one possible implementation, the processing unit is used to input a preset count into the circuit unit after the second target branch program is executed, so that the circuit unit completes a third setting. The third setting includes setting the program counter to the preset count, setting the thread mask to the convergence point thread mask according to the data stored in the first stack layer, and deleting the branch information in the stack.

[0059] As one possible implementation, the general-purpose graphics processor is also provided with a circuit triggering unit, and the branch information also includes a branch level number, which indicates the function nesting level corresponding to the second branch program; The processing unit is used to input the current level number corresponding to the current program into the circuit trigger unit after the first target branch program is executed, so that the circuit trigger unit can complete the level comparison. The level comparison involves comparing the current level number with the branch level number. If the current level number matches the branch level number, the circuit unit is triggered.

[0060] As one possible implementation, the circuit unit can complete the first setting, the second setting, or the third setting within one clock cycle, and the circuit triggering unit can complete the hierarchical comparison within one clock cycle.

[0061] As one possible implementation, the stack is a last-in-last-out stack; the first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to the top of the stack.

[0062] As one possible implementation, if the processing unit identifies a thread branch during the execution of the first target branch program or the second target branch program, the processing unit is further configured to obtain sub-branch information, which includes a sub-convergence point thread mask, a first sub-branch count, a first sub-branch thread mask, a second sub-branch count, and a second sub-branch thread mask. The processing unit is used to input sub-branch information into the circuit unit, so that the circuit unit completes the first sub-setting. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask into the second stack layer of the stack, setting the program counter to the first sub-branch count, and setting the thread mask to the first sub-branch thread mask. The processing unit is used to execute the first sub-target branch program; The processing unit is used to trigger the circuit unit after the first sub-target branch program is executed, so that the circuit unit completes the second sub-setting. The second sub-setting includes setting the program counter to the second sub-branch count according to the data saved in the second stack layer, and setting the thread mask to the second sub-branch thread mask. The processing unit is used to execute the second sub-target branch program; The processing unit is used to input the sub-preset count into the circuit unit after the second sub-target branch program is executed, so that the circuit unit can complete the third sub-setting. The third sub-setting includes setting the program counter to the sub-preset count, setting the thread mask to the sub-convergence point thread mask according to the data stored in the second stack layer, and deleting the sub-branch information in the stack.

[0063] As one possible implementation, the stack is a last-in-last-out stack; the first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask to the top of the stack, and pushing the branch information onto the next stack layer; the third sub-setting includes deleting the sub-branch information in the stack, so that the branch information returns to the top of the stack.

[0064] It should be noted that the general-purpose graphics processor in the embodiments of this application can implement each process of the aforementioned branch execution method under the single instruction multithreaded architecture and achieve the same effect and function, which will not be repeated here.

[0065] While the spirit and principles of this application have been described above with reference to several specific embodiments, it should be understood that this application is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined. This application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A branch execution method under a single-instruction multi-threaded architecture, characterized in that, The method is applied to a general-purpose graphics processing unit (GPGPU), which includes a processing unit and a circuit unit. The method includes: If the processing unit identifies a thread branch, it obtains the branch information, which includes the convergence point thread mask, the first branch count, the first branch thread mask, the second branch count, and the second branch thread mask. The processing unit inputs the branch information into the circuit unit, causing the circuit unit to complete the first setting. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask into the first stack layer of the stack, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask. The processing unit executes the first target branch program; After the first target branch program is executed, the processing unit triggers the circuit unit to enable the circuit unit to complete the second setting. The second setting includes setting the program counter to the second branch count according to the data stored in the first stack layer, and setting the thread mask to the second branch thread mask. The processing unit executes the second target branch program.

2. The method according to claim 1, characterized in that, The method further includes: After the second target branch program is executed, the processing unit inputs a preset count into the circuit unit, causing the circuit unit to complete a third setting. The third setting includes setting the program counter to a preset count, setting the thread mask to the convergence point thread mask based on the data stored in the first stack layer, and deleting the branch information in the stack.

3. The method according to claim 2, characterized in that, The general-purpose graphics processor is also provided with a circuit triggering unit, and the branch information also includes a branch level number, which indicates the function nesting level corresponding to the second branch program; The processing unit triggers the circuit triggering unit after the first target branch program is executed, including: After the first target branch program is executed, the processing unit inputs the current level number corresponding to the current program into the circuit triggering unit, so that the circuit triggering unit can complete the level comparison. The level comparison includes comparing the current level number with the branch level number. If the current level number and the branch level number are the same, the circuit unit is triggered.

4. The method according to claim 3, characterized in that, The circuit unit can complete the first setting, the second setting, or the third setting within one clock cycle, and the circuit triggering unit can complete the hierarchical comparison within one clock cycle.

5. The method according to claim 1, characterized in that, The stack is a last-in, first-out (LIFO) stack. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to the top of the stack.

6. The method according to claim 2, characterized in that, The method further includes: If the processing unit identifies a thread branch during the execution of the first target branch program or the second target branch program, it obtains sub-branch information, which includes a sub-convergence point thread mask, a first sub-branch count, a first sub-branch thread mask, a second sub-branch count, and a second sub-branch thread mask. The processing unit inputs the sub-branch information into the circuit unit, so that the circuit unit completes the first sub-setting. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask into the second stack layer of the stack, setting the program counter to the first sub-branch count, and setting the thread mask to the first sub-branch thread mask. The processing unit executes the first sub-target branch procedure; After the first sub-target branch program is executed, the processing unit triggers the circuit unit to enable the circuit unit to complete the second sub-setting. The second sub-setting includes setting the program counter to the second sub-branch count according to the data stored in the second stack layer, and setting the thread mask to the second sub-branch thread mask. The processing unit executes the second sub-target branch procedure; After the second sub-target branch program is executed, the processing unit inputs the sub-preset count into the circuit unit, so that the circuit unit completes the third sub-setting. The third sub-setting includes setting the program counter to the sub-preset count, setting the thread mask to the sub-convergence point thread mask according to the data stored in the second stack layer, and deleting the sub-branch information in the stack.

7. The method according to claim 6, characterized in that, The stack is a last-in, first-out (LIFO) stack. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask to the top of the stack, and pushing the branch information onto the next stack layer; The third sub-setting includes deleting the sub-branch information from the stack, so that the branch information returns to the top of the stack.

8. A general-purpose graphics processor, characterized in that, The general-purpose graphics processor includes a processing unit and a circuit unit. The processing unit is used to identify a thread branch and then obtain branch information, which includes a convergence point thread mask, a first branch count, a first branch thread mask, a second branch count, and a second branch thread mask. The processing unit is used to input the branch information into the circuit unit, so that the circuit unit completes the first setting. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask into the first stack layer of the stack, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask. The processing unit is used to execute the first target branch program; The processing unit is used to trigger the circuit unit after the first target branch program is executed, so that the circuit unit completes the second setting. The second setting includes setting the program counter to the second branch count according to the data stored in the first stack layer, and setting the thread mask to the second branch thread mask. The processing unit is used to execute the second target branch program.

9. The general-purpose graphics processor according to claim 8, characterized in that, The processing unit is configured to input a preset count into the circuit unit after the second target branch program is executed, so that the circuit unit completes a third setting. The third setting includes setting the program counter to a preset count, setting the thread mask to the convergence point thread mask according to the data stored in the first stack layer, and deleting the branch information in the stack.

10. The general-purpose graphics processor according to claim 9, characterized in that, The general-purpose graphics processor is also provided with a circuit triggering unit, and the branch information also includes a branch level number, which indicates the function nesting level corresponding to the second branch program; The processing unit is used to input the current level number corresponding to the current program into the circuit triggering unit after the first target branch program is executed, so that the circuit triggering unit can complete the level comparison. The level comparison includes comparing the current level number with the branch level number. If the current level number and the branch level number are the same, the circuit unit is triggered.

11. The general-purpose graphics processor according to claim 10, characterized in that, The circuit unit can complete the first setting, the second setting, or the third setting within one clock cycle, and the circuit triggering unit can complete the hierarchical comparison within one clock cycle.

12. The general-purpose graphics processor according to claim 8, characterized in that, The stack is a last-in, first-out (LIFO) stack. The first setting includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to the top of the stack.

13. The general-purpose graphics processor according to claim 9, characterized in that, If the processing unit identifies a thread branch during the execution of the first target branch program or the second target branch program, the processing unit is further configured to obtain sub-branch information, the sub-branch information including sub-convergence point thread mask, first sub-branch count, first sub-branch thread mask, second sub-branch count and second sub-branch thread mask; The processing unit is used to input the sub-branch information into the circuit unit, so that the circuit unit completes the first sub-setting. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask into the second stack layer of the stack, setting the program counter to the first sub-branch count, and setting the thread mask to the first sub-branch thread mask. The processing unit is used to execute the first sub-target branch program; The processing unit is used to trigger the circuit unit after the first sub-target branch program is executed, so that the circuit unit completes the second sub-setting. The second sub-setting includes setting the program counter to the second sub-branch count according to the data stored in the second stack layer, and setting the thread mask to the second sub-branch thread mask. The processing unit is used to execute the second sub-target branch program; The processing unit is used to input a sub-preset count into the circuit unit after the second sub-target branch program is executed, so that the circuit unit completes the third sub-setting. The third sub-setting includes setting the program counter to the sub-preset count, setting the thread mask to the sub-convergence point thread mask according to the data stored in the second stack layer, and deleting the sub-branch information in the stack.

14. The general-purpose graphics processor according to claim 13, characterized in that, The stack is a last-in, first-out (LIFO) stack. The first sub-setting includes saving the sub-convergence point thread mask, the second sub-branch count, and the second sub-branch thread mask to the top of the stack, and pushing the branch information onto the next stack layer; The third sub-setting includes deleting the sub-branch information from the stack, so that the branch information returns to the top of the stack.

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