A millimeter wave phase-locked loop

Abstract

The application discloses a kind of millimeter wave phase-locked loop, including by sub-sampling phase detector, voltage-controlled oscillator, proportional path unit, voltage comparator and integral path unit constitute feedback loop phase-locked loop, according to frequency control word and phase error signal gain control signal, first control word, second control word and the digital logic circuit of selection signal, according to reference signal, gain control signal and the digital time converter of first control word generation delay signal, according to delay signal and the auxiliary digital time converter of second control word duty cycle error compensation, generation digital output signal, according to digital output signal clock generation circuit generates a plurality of sampling clock signals, sub-sampling phase detector according to a plurality of sampling clock signals and the output signal of rising edge sampling and falling edge sampling of voltage-controlled oscillator according to selection signal.The embodiment of the application realizes extremely low jitter and in-band decimal spur, occupies extremely small area, can be widely applied in electronic circuit technical field.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a millimeter-wave phase-locked loop. Background Technology

[0002] In high-speed wireless communication systems, millimeter-wave (mmWave) bands are increasingly favored due to their increased bandwidth, enabling higher data transmission rates. However, due to stringent jitter and spurious requirements for the local oscillator (LO) and clock, modulation schemes are typically limited to 64-QAM (Quadrature Amplitude Modulation) or lower. For example, 256QAM applied at 26 GHz requires the LO to have low phase noise of <-39 dBc, which is equivalent to an RMS (Root Mean Square) jitter requirement of <100 fs. Compared to integer PLLs (Phase Locked Loops), fractional PLLs have a wider range of applications. However, fractional operations in PLLs introduce quantization noise, worsening jitter performance. Generally, a smaller PLL bandwidth can more effectively suppress quantization noise; however, millimeter-wave PLLs require a wider bandwidth to suppress the phase noise of the voltage-controlled oscillator. Therefore, the design of fractional millimeter-wave PLLs involves a trade-off between in-band and out-of-band noise. In related technologies, most fractional millimeter-wave phase-locked loop (PLL) schemes that achieve 100fs or less use multi-stage PLLs, but multi-stage PLLs occupy a larger area. Summary of the Invention

[0003] In view of this, in order to solve one of the above problems, the purpose of this invention is to provide a millimeter-wave phase-locked loop that achieves extremely low jitter and in-band fractional spurious noise while occupying a very small area.

[0004] This invention provides a millimeter-wave phase-locked loop (PLL), comprising a subsampling phase detector, a voltage-controlled oscillator (VCO), a proportional path unit, a voltage comparator, an integral path unit, digital logic circuitry, a digital-to-time converter (DTC), an auxiliary DTC, and a clock generation circuit. The subsampling phase detector, the VCO, the proportional path unit, the voltage comparator, and the integral path unit constitute a feedback loop PLL.

[0005] The digital logic circuit is used to generate a gain control signal, a first control word, a second control word, and a selection signal based on the frequency control word and the phase error signal;

[0006] The digital time converter is used to generate a delay signal based on the reference signal, the gain control signal, and the first control word;

[0007] The auxiliary digital time converter is used to compensate for the duty cycle error based on the delay signal and the second control word to generate a digital output signal;

[0008] The clock generation circuit is used to generate several sampling clock signals based on the digital output signal;

[0009] The subsampling phase detector is used to sample the rising edge and falling edge of the output signal of the voltage-controlled oscillator according to a plurality of the sampling clock signals and the selection signal.

[0010] Optionally, the subsampling phase detector includes a first capacitor, a second capacitor, and six sampling switches. The first sampling switch is connected to one end of the first capacitor and the first input terminal of the subsampling phase detector. The second sampling switch is connected to the other end of the first capacitor and the second input terminal of the subsampling phase detector. The third sampling switch is connected to one end of the first capacitor and one end of the second capacitor. The fourth sampling switch is connected to the other end of the first capacitor and the other end of the second capacitor. The fifth sampling switch is connected to one end of the first capacitor and the other end of the second capacitor. The sixth sampling switch is connected to the other end of the first capacitor and one end of the second capacitor. The two ends of the second capacitor are the output terminals of the subsampling phase detector.

[0011] Optionally, the sampling clock signal includes three clock signals: a first clock signal controls the first sampling switch and the second sampling switch; a second clock signal controls the third sampling switch and the fourth sampling switch; and a third clock signal controls the fifth sampling switch and the sixth sampling switch. The second clock signal and the third clock signal are complementary signals.

[0012] Optionally, the digital logic circuit includes a quantization error circuit, a first calibration circuit, and a second calibration circuit, wherein,

[0013] The quantization error circuit is used to determine the quantization error compensation signal and the selection signal according to the frequency control word;

[0014] The first calibration circuit is used to generate a gain control signal and a first control word based on the quantization error compensation signal and the phase error signal;

[0015] The second calibration circuit is used to generate a second control word based on the selection signal and the phase error signal.

[0016] Optionally, the quantization error circuit includes a first modulator, a first accumulator, a first adder, a second accumulator, and a first multiplier. The first modulator is connected to the frequency control word and the input of the first accumulator. The output of the first accumulator is the selection signal. The input of the first adder is connected to the frequency control word and the output of the first modulator. The second accumulator is connected to the output of the first adder and the input of the first multiplier. The output of the first multiplier is the quantization error compensation signal.

[0017] Optionally, the first calibration circuit includes a 1-3 order symbolic minimum mean square error operator formed by a square operator, a cube operator, five multipliers and three weighted accumulators.

[0018] Optionally, the second calibration circuit includes a second multiplier, a third multiplier, and a weighted accumulator. The inputs of the second multiplier are the selection signal and the phase error signal. The weighted accumulator is connected to the output of the second multiplier and the first input of the third multiplier. The second input of the third multiplier is connected to the selection signal. The output of the third multiplier is a second control word.

[0019] Optionally, the digital-to-analog converter includes a first digital-to-analog converter, a first filter, a first-stage inverter, a second-stage inverter, and a switched-capacitor bank. The first digital-to-analog converter is connected to the gain control signal and the input of the first filter. The output of the first filter and the reference signal are connected to the input of the first-stage inverter. The first control word controls the switched-capacitor bank. The output of the first-stage inverter and the output of the switched-capacitor bank are connected to the input of the second-stage inverter. The output of the second-stage inverter serves as the output of the first calibration circuit.

[0020] Optionally, the proportional path unit includes a transconductance amplifier and a second filter, the input of the transconductance amplifier being connected to the output of the subsampling phase detector, and the second filter being connected to the output of the transconductance amplifier and the first input of the voltage-controlled oscillator.

[0021] Optionally, the integration path unit includes a second accumulator, a second modulator, a second digital-to-analog converter, and a third filter. The second accumulator is connected to the output of the voltage comparator and the input of the second modulator. The second digital-to-analog converter is connected to the output of the second modulator and the input of the third filter. The output of the third filter is connected to the second input of the voltage-controlled oscillator.

[0022] Implementing the embodiments of the present invention has the following beneficial effects: In this embodiment, the subsampling phase detector samples the output signal of the voltage-controlled oscillator on the rising edge and falling edge according to several sampling clock signals and selection signals, which reduces the dynamic range required by the digital time converter to compensate for quantization noise by half. Therefore, the noise and nonlinear performance of the digital time converter are improved. This makes it possible to use a subsampling phase-locked loop to directly generate millimeter-wave signals, thereby achieving extremely low jitter and in-band fractional spurious noise, while occupying a very small area. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a millimeter-wave phase-locked loop provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of another millimeter-wave phase-locked loop provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram illustrating the working principle of a subsampling phase detector provided in an embodiment of the present invention;

[0026] Figure 4 This is a circuit diagram of a quantization error circuit provided in an embodiment of the present invention;

[0027] Figure 5 This is a circuit diagram of a first calibration circuit provided in an embodiment of the present invention;

[0028] Figure 6 This is a circuit diagram of a second calibration circuit provided in an embodiment of the present invention;

[0029] Figure 7 This is a circuit diagram of a digital time converter provided in an embodiment of the present invention;

[0030] Figure 8 This is a circuit diagram of a proportional path unit provided in an embodiment of the present invention;

[0031] Figure 9 This is a circuit diagram of an integration path unit provided in an embodiment of the present invention;

[0032] Figure 10 This is a chip diagram and area / power consumption table of a millimeter-wave phase-locked loop provided in an embodiment of the present invention;

[0033] Figure 11 This invention provides a phase noise diagram and spectrum diagram of a millimeter-wave phase-locked loop.

[0034] Figure 12 These are stray diagrams and animations of a millimeter-wave phase-locked loop provided in an embodiment of the present invention. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0036] like Figure 1 As shown, this embodiment of the invention provides a millimeter-wave phase-locked loop (PLL), including a subsampling phase detector, a voltage-controlled oscillator (VCO), a proportional path unit, a voltage comparator, an integral path unit, a digital logic circuit, a digital-to-time converter (DTC), an auxiliary DTC, and a clock generation circuit. The subsampling phase detector, VCO, proportional path unit, voltage comparator, and integral path unit constitute a feedback loop PLL; wherein,

[0037] Digital logic circuits are used to generate a gain control signal (Kdtc1), a first control word (Ddtc1), a second control word (Ddtc,aux), and a selection signal (Spol) based on a frequency control word and a phase error signal (e[k]).

[0038] A digital time converter (DTC) is used to generate a delayed signal (DTCout1) based on a reference signal (CKR), a gain control signal (Kdtc1), and a first control word (Ddtc1).

[0039] An auxiliary digital time converter (DTCaux) is used to compensate for the duty cycle error based on the delay signal (DTCout1) and the second control word (Ddtc,aux) to generate a digital output signal (DTCout).

[0040] The clock generation circuit is used to generate several sampling clock signals based on the digital output signal (DTCout);

[0041] A subsampling phase detector is used to sample the rising edge and falling edge of the output signal of a voltage-controlled oscillator based on several sampling clock signals and a selection signal.

[0042] The two outputs of the voltage-controlled oscillator are connected to the subsampling phase detector. Several sampled clock signals output by the clock generation circuit are connected to the input of the subsampling phase detector. The output of the subsampling phase detector is connected to the input of the proportional path unit and the voltage comparator. The output of the proportional path unit is connected to the voltage-controlled oscillator. The output of the voltage comparator is connected to the input of the integral path unit. The output of the integral path unit is connected to the voltage-controlled oscillator.

[0043] See Figure 2 In one specific embodiment, the voltage signal output V of the voltage-controlled oscillator G+ / V G-The voltage signal V is sampled by a reversible gain subsampling phase detector (PR-SSPD). H+ and V H- This process can be represented by a mathematical model as (V H- -V H+ ) = K SSPD *Φ E Among them, K SSPD For the gain of PR-SSPD, Φ E This represents the phase error between the sampling clock CLK1 and the oscillator output signal. Φ E Unlike others, CLK1 will sample to V. G At different voltages. Therefore, PR-SSPD achieves Φ E Conversion to voltage signals.

[0044] The input to the clock generation circuit is the output signal DTC. out. It uses a pulse generator circuit to generate DTC. out The signal is converted into sampling clocks CLK1 and CLK2,R, and CLK2,F with short pulse widths.

[0045] The input signal to the DTC is the reference signal CKR of the phase-locked loop. The DTC delays the CKR signal by a corresponding time according to the first control word Ddtc1. The delay time of the DTC is τ. dtc =Kdtc1*Ddtc1*T res。 Where Kdtc1 is the gain control signal of DTC, T res This refers to the time precision of the DTC itself. Both Ddtc1 and Kdtc1 are generated by digital logic circuits. The output signal of the main DTC is the DTC. out1 It is sent to the auxiliary DTC (DTC) aux The input of ) is used to assist DTC in compensating for duty cycle errors, and its second control word D dtc,aux Generated by digital logic circuits. Compensating for duty cycle errors can improve the spurious and jitter performance of the phase-locked loop. The output of the auxiliary DTC is the DTC. out It serves as the input to the clock generation circuit.

[0046] The proportional path multiplies the output voltage signal of the PR-SSPD by a gain to obtain the signal V. P Its function is V P =K P *(V H- -V H+ ), where K P It is the gain of the proportional path, which is composed of analog circuits.

[0047] The voltage comparator (VC) will extract the signal (V)H- -V H+ The sign of ) is used to obtain the digital signal output e[k], whose function is e[k] = sign[(V H- -V H+ ], when (V H- -V H+ If )>0, e[k]=1; otherwise, e[k]=0. From (V H- -V H+ ) and Φ E Given the relationship, it can be seen that e[k] also represents the sign of the phase error. Therefore, e[k] will also be used for digital circuit calibration.

[0048] The digital integration path multiplies the digital signal output e[k] of the voltage comparator by a gain and accumulates the results to obtain the signal V. I Its function is V I =∑(K I *(V H- -V H+ Among them, K I This is the gain of the integration path. The integration path consists of digital circuits.

[0049] proportional path voltage output V P and the voltage V of digital circuits I Together, they control the frequency of the voltage-controlled oscillator, forming a type II feedback loop phase-locked loop.

[0050] See Figure 3 In traditional SSPDs, only the VCO (voltage-controlled oscillator) outputs (V... G+ The rising edge of the signal is sampled. If a first-order DSM (delta-sigma modulator) is used, the DTC used for quantization noise compensation requires one cycle time (T) of the VCO output signal. VCO The dynamic range of ) . If SSPD can simultaneously sample V G+ If the rising and falling edges are both present, the DTC range will be halved to T. VCO / 2. However, when sampling at both the rising and falling edges, the SSPD gain (K) SSPD The sign of V will be different because V G+ The slope (K) slope The value is positive on the rising edge and negative on the falling edge. This K... SSPD Changes in the sign may cause the subsampling loop to lose lock. In this embodiment, V G+ First, C S1 Sampling to generate V SP+ When sampling on the rising edge (K) slope When V > 0), SP+ via switch SWR The positive input (V) transmitted to Gm H+ In this case, K SSPD =K slope And sampling on the falling edge (K) slope When V < 0), SP+ via switch SW F The negative input (V) transmitted to Gm H- This makes K SSPD =-K slope Therefore, K SSPD The sign of the signal can always remain positive, which ensures that the phase-locked loop is always a negative feedback loop.

[0051] Optionally, see Figure 2 The subsampling phase detector includes a first capacitor (consisting of two capacitors C). S1 Composition), the second capacitor (consisting of two capacitors C) S2 The system consists of a first capacitor and six sampling switches, with the first sampling switch connected to one end of the first capacitor (V). SP- ) and the first input terminal (V) of the subsampled phase detector G- The second sampling switch is connected to the other end of the first capacitor (V). SP+ ) and the second input terminal (V) of the subsampled phase detector G+ The third sampling switch is connected to one end of the first capacitor (V). SP- ) and one end of the second capacitor (V H+ The fourth sampling switch is connected to the other end of the first capacitor (V). SP+ ) and the other end of the second capacitor (V H- The fifth sampling switch is connected to one end of the first capacitor (V). SP- ) and the other end of the second capacitor (V H- The sixth sampling switch is connected to the other end of the first capacitor (V). SP+ ) and one end of the second capacitor (V H+ The two ends of the second capacitor are the output terminals of the subsampling phase detector.

[0052] Optionally, the sampling clock signal includes three clock signals: the first clock signal controls the first and second sampling switches, the second clock signal controls the third and fourth sampling switches, and the third clock signal controls the fifth and sixth sampling switches. The second and third clock signals are complementary signals.

[0053] All sampling switches in the PR-SSPD are implemented using PMOS transistors. The sampling clock (CLK1) of its main sampling switch is generated by a pulse signal generator within the clock generation circuit based on the output signal of the DTC (DTC). out A voltage pulse is generated on the falling edge of the sampling switch (SW).R ,SW F The control clock is first generated by the pulse signal generator based on CLK1 to produce CLK2. CLK1 serves as the sampling clock for the main sampler. At the rising edge of CLK1, the signal V is... G+ V G- The voltage is sampled to capacitor C. S1 Above, the voltage V is obtained. SP+ and V SP- CLK 2,R and CLK 2,F This serves as the sampling clock for the sampler. The clock generation circuit selects the signal S based on the polarity of the PR-SSPD. pol Choose CLK as either 1 or 0. 2,F Or CLK 2,R This is used as the sampling clock from the sampler. Then it is controlled by signal S. pol Enable CLK2 to send to SW via an OR gate. R (CLK 2,R ) or SW F (CLK 2,F When S pol CLK is 1. 2,F As the sampling clock from the sampler, voltage V SP+ Sent to V H+ Voltage V SP- Sent to V H- When S pol CLK is 0. 2,R As the sampling clock from the sampler, voltage V SP+ Sent to V H- Voltage V SP- Sent to V H+ When CLK1 samples the differential output of VCO, the differential voltage (V SP+ V SP- ) stored in capacitor C S1 Then, the clock generation circuit determines whether the target sampling point is on the rising edge (at which point S...). pol =0) or falling edge (at this time S) pol =1) to borrow CLK 2,R Control SW R Open or controlled by CLK 2,F Control SW F Open. When SW R When opened, V SP+ (V SP- ) will be given to V H+ (V H- When SW F When opened, V SP+ (V SP- ) will be given to V H- (VH+ This allows the signal S to be used. pol Sending data to SW via CLK2. R Still SW F Control the polarity of the PR-SSPD. Since the quantization error is predetermined in the locked state, the signal S... pol It can be generated based on the DSM output.

[0054] Optionally, see Figure 2 The digital logic circuit includes a quantization error circuit, a first calibration circuit, and a second calibration circuit, wherein...

[0055] Quantization error circuit, used to determine the quantization error compensation signal (Q) based on the frequency control word. E ) and selection signal (Spol);

[0056] The first calibration circuit is used to adjust the quantization error compensation signal (Q) according to the quantization error compensation signal (Q). E The gain control signal (Kdtc1) and the first control word (Ddtc1) are generated from the phase error signal (e[k]) and the phase error signal (e[k]).

[0057] The second calibration circuit is used to generate a second control word (Ddtc,aux) based on the selection signal (Spol) and the phase error signal (e[k]).

[0058] It should be noted that the specific structure of the quantization error circuit, the first calibration circuit, and the second calibration circuit is determined according to the actual application, and this embodiment does not impose specific limitations.

[0059] Optionally, the quantization error circuit includes a first modulator, a first accumulator, a first adder, a second accumulator, and a first multiplier. The first modulator is connected to the frequency control word and the input of the first accumulator, and the output of the first accumulator is a selection signal. The input of the first adder is connected to the frequency control word and the output of the first modulator. The second accumulator is connected to the output of the first adder and the input of the first multiplier, and the output of the first multiplier is a quantization error compensation signal.

[0060] See Figure 4 The quantization error circuit generates a quantization error compensation signal Q based on the frequency control word (FCW) input. E and PR-SSPD polarity selection signal S pol Among them, Q E =∑(FCW–Q[2FCW]*0.5), where the operator Q[·] represents rounding. Thus, Q... E This represents the quantization error generated by the first-order ΔΣ modulator performing integer quantization on the fractional frequency control word FCW; Q EThis also reflects the time delay that should occur for an ideal DTC. Spol represents whether the PR-SSPD should select the rising or falling edge of the sampling oscillator. It is obtained by passing the quantized output of the first-order ΔΣ modulator through a 1-bit accumulator.

[0061] Because DTC has non-ideal factors, therefore, Q E The actual DTC control word Ddtc1 and DTC gain control word Kdtc1 need to be generated through the first calibration circuit, and the gain error and nonlinear effect of DTC are compensated in real time through the first calibration circuit.

[0062] Optionally, the first calibration circuit includes a 1-3 order symbolic minimum mean square error arithmetic unit consisting of a square arithmetic unit, a cube arithmetic unit, five multipliers and three weighted accumulators.

[0063] See Figure 5 The first calibration circuit is composed of digital circuits and is implemented using a 1-3 order symbol-LMS algorithm. The first calibrator compares the output e[k] of the voltage comparator with the DTC control code Q. E A correlation test is performed, where e[k] represents the sign of the phase error. If the DTC exhibits nonlinearity that can be expressed by polynomials of orders 1 to 3, for example, a1x + a2x... 2 +a3x 3 Then e[k] is the same as Q. E The third-order polynomial (a1Q) E +a2Q E 2 +a3Q E 3 The correlation exists. Given that the initial values ​​of a1, a2, and a3 are 0, by calculating e[k]*(Q) E +Q E 2 +Q E 3 And by accumulating these values, the values ​​of a1, a2, and a3 are continuously adjusted. Eventually, a1, a2, and a3 will converge to a value such that e[k] equals (a1Q) / (a2Q) / (a3 ... E +a2Q E 2 +a3Q E 3 The values ​​are irrelevant. This set of convergence values ​​reflects the actual nonlinearity of the DTC. Compensating the control signal of the DTC with these convergence values ​​achieves calibration of the DTC in the digital domain.

[0064] Optionally, the second calibration circuit includes a second multiplier, a third multiplier, and a weighted accumulator. The inputs of the second multiplier are a selection signal and a phase error signal. The weighted accumulator is connected to the output of the second multiplier and the first input of the third multiplier. The second input of the third multiplier is connected to the selection signal. The output of the third multiplier is a second control word.

[0065] See Figure 6 The VCO output signal duty cycle may deviate from 50%, and the SW R SW F C S2 The unavoidable mismatch between them will cause errors in DTC compensation quantization noise, that is, for the same phase error Φ E When sampling the rising and falling edges of VG, there are different static voltage offsets, generating spurious signals and degrading jitter performance. Therefore, an auxiliary DTC is introduced to compensate for this voltage offset. The control word of the auxiliary DTC consists of a duty cycle error calibration circuit. Therefore, this embodiment of the invention introduces a duty cycle error calibration circuit based on the LMS algorithm. It further adjusts the delay of the auxiliary DTC by checking the correlation between the output e[k] of the voltage comparator and Spol. If the duty cycle is not 50% at this time, then e[k] and Spol will be different. pol The correlation between them makes the mean of their product non-zero. This product is accumulated and added to the control word of the auxiliary DTC, which then introduces an additional delay to compensate for the duty cycle. After the algorithm converges, e[k] and Spol are orthogonal and have no correlation, indicating that the duty cycle error and the additional error introduced by circuit mismatch have been fully compensated by the auxiliary DTC, improving the spurious and jitter performance of the PLL.

[0066] Optionally, the digital time converter includes a first digital-to-analog converter, a first filter, a first-stage inverter, a second-stage inverter, and a switched capacitor bank. The first digital-to-analog converter is connected to a gain control signal and the input of the first filter. The output of the first filter and a reference signal are connected to the input of the first-stage inverter. A first control word controls the switched capacitor bank. The output of the first-stage inverter and the output of the switched capacitor bank are connected to the input of the second-stage inverter. The output of the second-stage inverter serves as the output of the first calibration circuit.

[0067] See Figure 7 The DTC employs a variable ramp circuit architecture. The first control word is D... dtc1A set of switched capacitors is controlled to change the slope of the output signal of the first-stage inverter. The output signal of the first-stage inverter is then passed to the second-stage inverter to generate the output. A larger slope in the output signal of the first-stage inverter results in a longer time delay, but also greater noise due to the longer discharge time of the capacitors. A wider slope range also results in a larger dynamic range of the DTC, but also a greater nonlinearity introduced by the second-stage inverter. Therefore, reducing the DTC range can reduce noise and nonlinearity. The gain of the DTC is achieved by a transistor controlled by a digital-to-analog converter (DAC). The DAC converts the digital signal K... dtc1 The signal is converted into a voltage signal, which controls the on-resistance of the transistor. Therefore, the time constant of the discharge of the switched capacitor bank can be changed, thereby controlling the slope of the output signal of the first-stage inverter and achieving gain control.

[0068] Optionally, the proportional path unit includes a transconductance amplifier and a second filter. The input of the transconductance amplifier is connected to the output of the subsampling phase detector, and the second filter is connected to the output of the transconductance amplifier and the first input of the voltage-controlled oscillator.

[0069] See Figure 8 The analog circuit's proportional path consists of a transconductance amplifier (Gm) and a second filter (R1, C1). The transconductance amplifier converts the voltage signal (V) into a proportional path. H- -V H+ The signal is converted into a current signal, which is then filtered to generate the oscillator control voltage V. P The gain of the proportional path is K. P =Gm*R1 / 2, where Gm is the gain of the transconductance amplifier.

[0070] Optionally, the integration path unit includes a second accumulator, a second modulator, a second digital-to-analog converter, and a third filter. The second accumulator is connected to the output of the voltage comparator and the input of the second modulator. The second digital-to-analog converter is connected to the output of the second modulator and the input of the third filter. The output of the third filter is connected to the second input of the voltage-controlled oscillator.

[0071] In one specific embodiment, see Figure 9 The integration path unit accumulates the digital output e[k] of the voltage comparator using a digital accumulator (Σ). The accumulated 16-bit digital signal is then sent to a 5-bit digital-to-analog converter via a third-order ΔΣ modulator to generate the voltage output V. I The third-order ΔΣ modulator is used to convert a 16-bit digital signal using a 5-bit digital-to-analog converter without loss of accuracy. The quantization noise it introduces is filtered out by a filter consisting of R2 and C2.

[0072] In one specific embodiment, the millimeter-wave phase-locked loop employs a 28nm CMOS process, and its chip micrograph, along with power consumption and area data, are shown below. Figure 10 As shown. The test results for the fractional channel output at 27.000029297GHz are shown below. Figure 11 As shown in (a), the phase noise test plot shows that this PLL achieves a jitter of 57.9 fs, and the spectrum plot shows that the fractional spurious emissions are all below -55.2 dBc. This is due to the proposed PR-SSPD reducing the dynamic range of the DTC, thus reducing in-band noise and fractional spurious emissions introduced by nonlinearity. Test results on the 27 GHz integer channel are shown below. Figure 11 As shown in (b), it achieves extremely low jitter (51 fs) and reference spurious (-62.6 dBc). See also Figure 12 Under different fractional frequency control words, the phase-locked loop achieved jitter of less than 61.2 fs and fractional spurious noise of -53.9 dBc.

[0073] Implementing the embodiments of the present invention has the following beneficial effects: In this embodiment, the subsampling phase detector samples the output signal of the voltage-controlled oscillator on the rising edge and falling edge according to several sampling clock signals and selection signals, which reduces the dynamic range required by the digital time converter to compensate for quantization noise by half. Therefore, the noise and nonlinear performance of the digital time converter are improved. This makes it possible to use a subsampling phase-locked loop to directly generate millimeter-wave signals, thereby achieving extremely low jitter and in-band fractional spurious noise, while occupying a very small area.

[0074] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A millimeter-wave phase-locked loop, characterized in that, It includes a subsampling phase detector, a voltage-controlled oscillator, a proportional path unit, a voltage comparator, an integral path unit, digital logic circuits, a digital-to-time converter, an auxiliary digital-to-time converter, and a clock generation circuit. The subsampling phase detector, the voltage-controlled oscillator, the proportional path unit, the voltage comparator, and the integral path unit constitute a feedback loop phase-locked loop; wherein, The digital logic circuit is used to generate a gain control signal, a first control word, a second control word, and a selection signal based on the frequency control word and the phase error signal; The digital time converter is used to generate a delay signal based on the reference signal, the gain control signal, and the first control word; The auxiliary digital time converter is used to compensate for the duty cycle error based on the delay signal and the second control word to generate a digital output signal; The clock generation circuit is used to generate several sampling clock signals based on the digital output signal; The subsampling phase detector is used to sample the rising edge and falling edge of the output signal of the voltage-controlled oscillator according to a plurality of the sampling clock signals and the selection signal.

2. The millimeter-wave phase-locked loop according to claim 1, characterized in that, The subsampling phase detector includes a first capacitor, a second capacitor, and six sampling switches. The first sampling switch is connected to one end of the first capacitor and the first input terminal of the subsampling phase detector. The second sampling switch is connected to the other end of the first capacitor and the second input terminal of the subsampling phase detector. The third sampling switch is connected to one end of the first capacitor and one end of the second capacitor. The fourth sampling switch is connected to the other end of the first capacitor and the other end of the second capacitor. The fifth sampling switch is connected to one end of the first capacitor and the other end of the second capacitor. The sixth sampling switch is connected to the other end of the first capacitor and one end of the second capacitor. The two ends of the second capacitor are the output terminals of the subsampling phase detector.

3. The millimeter-wave phase-locked loop according to claim 2, characterized in that, The sampling clock signal includes three clock signals: the first clock signal controls the first sampling switch and the second sampling switch; the second clock signal controls the third sampling switch and the fourth sampling switch; and the third clock signal controls the fifth sampling switch and the sixth sampling switch. The second clock signal and the third clock signal are complementary signals.

4. The millimeter-wave phase-locked loop according to claim 1, characterized in that, The digital logic circuit includes a quantization error circuit, a first calibration circuit, and a second calibration circuit, wherein... The quantization error circuit is used to determine the quantization error compensation signal and the selection signal according to the frequency control word; The first calibration circuit is used to generate a gain control signal and a first control word based on the quantization error compensation signal and the phase error signal; The second calibration circuit is used to generate a second control word based on the selection signal and the phase error signal.

5. The millimeter-wave phase-locked loop according to claim 4, characterized in that, The quantization error circuit includes a first modulator, a first accumulator, a first adder, a second accumulator, and a first multiplier. The first modulator is connected to the frequency control word and the input of the first accumulator. The output of the first accumulator is the selection signal. The input of the first adder is connected to the frequency control word and the output of the first modulator. The second accumulator is connected to the output of the first adder and the input of the first multiplier. The output of the first multiplier is the quantization error compensation signal.

6. The millimeter-wave phase-locked loop according to claim 4, characterized in that, The first calibration circuit includes a 1-3 order sign minimum mean square error operator consisting of a square operator, a cube operator, five multipliers and three weighted accumulators.

7. The millimeter-wave phase-locked loop according to claim 4, characterized in that, The second calibration circuit includes a second multiplier, a third multiplier, and a weighted accumulator. The inputs of the second multiplier are the selection signal and the phase error signal. The weighted accumulator is connected to the output of the second multiplier and the first input of the third multiplier. The second input of the third multiplier is connected to the selection signal. The output of the third multiplier is a second control word.

8. The millimeter-wave phase-locked loop according to claim 1, characterized in that, The digital-to-analog converter includes a first digital-to-analog converter, a first filter, a first-stage inverter, a second-stage inverter, and a switched-capacitor bank. The first digital-to-analog converter is connected to the gain control signal and the input of the first filter. The output of the first filter and the reference signal are connected to the input of the first-stage inverter. The first control word controls the switched-capacitor bank. The output of the first-stage inverter and the output of the switched-capacitor bank are connected to the input of the second-stage inverter. The output of the second-stage inverter serves as the output of the first calibration circuit.

9. The millimeter-wave phase-locked loop according to claim 1, characterized in that, The proportional path unit includes a transconductance amplifier and a second filter. The input of the transconductance amplifier is connected to the output of the subsampling phase detector, and the second filter is connected to the output of the transconductance amplifier and the first input of the voltage-controlled oscillator.

10. The millimeter-wave phase-locked loop according to claim 1, characterized in that, The integration path unit includes a second accumulator, a second modulator, a second digital-to-analog converter, and a third filter. The second accumulator is connected to the output of the voltage comparator and the input of the second modulator. The second digital-to-analog converter is connected to the output of the second modulator and the input of the third filter. The output of the third filter is connected to the second input of the voltage-controlled oscillator.

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