Centralized alu time-multiplexed ecc coprocessor based on dynamic priority arbitration bus

Abstract

The application discloses a centralized ALU time-sharing multiplexing ECC coprocessor based on a dynamic priority arbitration bus, and relates to the technical field of integrated circuit design and information security. The coprocessor comprises a centralized ALU, an intelligent arbitration module, and an ECC core master module, a point operation module and a coordinate conversion module which are all function request units. The ECC core master module generates a scheduling instruction according to a task, or sends a verification request to the intelligent arbitration module to call the centralized ALU; the point operation and coordinate conversion module generates an arithmetic operation request according to the scheduling instruction and sends the arithmetic operation request to the intelligent arbitration module; the intelligent arbitration module judges the priority of each request unit, controls the request units to send the requests to the centralized ALU in sequence; and the centralized ALU executes the arithmetic operation and feeds back the result to the corresponding request unit. The coprocessor significantly reduces the response delay.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and information security technology, and in particular to a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus. Background Technology

[0002] With the advent of the Internet of Things era, the demand for information security at edge computing nodes is growing rapidly. Elliptic Curve Cryptography (ECC), due to its high security and short key characteristics, has become the mainstream encryption standard in resource-constrained environments. However, the hardware implementation of ECC faces the classic contradiction of "performance-resources-power consumption".

[0003] Among these bottlenecks, modular inverse operation is the key factor limiting performance. In affine coordinates, each point operation requires an extremely expensive modular inverse operation. Although the Jacobian coordinate system can eliminate intermediate modular inverses, in a single centralized arithmetic logic unit (ALU) architecture, multiple functional modules such as point addition, doubling, and coordinate transformation compete for the same set of computing resources. Furthermore, the traditional polling arbitration mechanism ignores the real-time differences between different stages of the ECC algorithm flow, causing tasks on the critical path (such as coordinate restoration in the output stage) to be blocked by non-critical tasks, significantly increasing the overall system latency. Summary of the Invention

[0004] Therefore, it is necessary to provide a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus to address the above-mentioned technical problems.

[0005] The following technical solution is adopted in this specification: This specification provides a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus. The coprocessor includes a centralized arithmetic logic unit (ALU), an elliptic curve cryptography (ECC) core control module, a point operation module, a coordinate transformation module, and an intelligent arbitration module. The centralized ALU is the coprocessor's sole arithmetic resource, implementing bit-serial or digital-serial modular addition, subtraction, multiplication, and inverse operations using pure logic gate circuits. The ECC core control module, point operation module, and coordinate transformation module are connected to the intelligent arbitration module as function request units, and the intelligent arbitration module is also connected to the centralized ALU. The ECC core main control module is used to parse the processing tasks issued by the host computer, generate corresponding sub-module scheduling instructions based on the processing tasks, and generate a legality verification request for the base point. The legality verification request is sent to the intelligent arbitration module to call the centralized ALU for calculation. The sub-module scheduling instructions include coordinate system transformation instructions or elliptic curve point calculation instructions. The point operation module and coordinate transformation module are used to decompose the received submodule scheduling instructions into a low-level arithmetic operation sequence and send the corresponding arithmetic operation request to the intelligent arbitration module; the arithmetic operation request includes the specific opcode and operands; The intelligent arbitration module is used to determine the priority of the point operation module, coordinate transformation module and ECC core main control module according to the built-in algorithm priority logic. It controls the function request unit to send arithmetic operation requests to the centralized ALU through the bus by controlling the priority order from high to low. The centralized ALU is used to perform corresponding arithmetic operations based on the arithmetic operation requests received from the authorized channel, and to feed back the operation results to the function request unit that initiated the request.

[0006] Optionally, the centralized ALU integrates an input latch interface, a multimodal arithmetic data path, and a submodule scheduling state machine. The input latch interface is used to latch the operation instructions from the bus during the clock cycle at which the operation begins, and to keep them locked during the operation; the operation instructions include operands, modulus, and opcode; The multimodal arithmetic data path includes a shared intermediate result register with a bit width of N+1 bits, which is time-division multiplexed for overflow detection logic of modular addition, borrow compensation logic of modular subtraction, and basic addition logic. The submodule scheduling state machine is configured to trigger the internally instantiated Montgomery modular multiplication submodule or binary GCD modular inverse submodule according to the opcode, and enter a suspended waiting state during the submodule operation until the operation result is received from the submodule. The Montgomery modular multiplier module or the binary GCD modular inverse module is used to perform corresponding arithmetic operations according to the operation instructions until the operation is completed.

[0007] Optionally, the shared intermediate result register is assigned different functions under different opcode control; The shared intermediate result register is used to store the addition result and retain the carry bit for overflow detection when performing ordinary addition and modular addition operations; when performing modular subtraction operations, it is used to perform borrow compensation logic.

[0008] Optionally, the intelligent arbitration module and the centralized ALU adopt an atomic handshake protocol of request-hold-release; A centralized ALU is used to pull up the busy signal and enter the execution state after the authorized function request unit sends a start pulse; The intelligent arbitration module is used to detect the busy signal fed back by the centralized ALU through the handshake signal line, and lock the current authorized channel after detecting the busy signal, blocking the requests of all other function request units until the centralized ALU outputs the operation completion signal and pulls the busy signal low.

[0009] Optionally, the point operation module has built-in parameters for elliptic curves. The optimized point multiplier hardware microinstruction sequence is configured to control the centralized ALU to calculate the point multiplier slope intermediate variable. M ; The point operation module is used to build in parameters for elliptic curves. The optimized point-multiplying hardware microinstruction sequence is used to sequentially send modular multiplication, modular addition, modular subtraction, modular multiplication, and shift addition instructions to the centralized ALU to perform the formula... Alternative standard formula .

[0010] Optionally, the coordinate transformation module is configured to perform domain transformations based on the Jacobian coordinate system; The coordinate transformation module is used to directly map the externally input affine coordinates (x, y) to Jacobian coordinates (x, y, 1) through register transfer logic in response to the first mode signal during the data input phase. In response to the second mode signal during the data output phase, it requests the centralized ALU to perform modular inverse operation to calculate the inverse of the Z coordinate and continuously requests the centralized ALU to perform a modular multiplication sequence to calculate the affine coordinates. During this output phase, the intelligent arbitration module ensures continuous resource supply according to the highest priority strategy.

[0011] Optionally, the coordinate transformation module has a higher priority than the point calculation module, and the point calculation module has a higher priority than the ECC core main control module.

[0012] Optionally, the coprocessor may also include a communication bridging module; The communication bridging module is used to parse the host computer instructions, generate processing tasks, and send the parsed processing tasks to the ECC core main control module, as well as to receive the task calculation results sent by the ECC core main control module and send the task calculation results to the host computer.

[0013] Optionally, the centralized ALU includes a basic arithmetic unit, a modular multiplier, and a modular inverter; the basic arithmetic unit is used to implement addition, subtraction, modular addition, and modular subtraction operations.

[0014] This specification provides an ECC encryption method based on the aforementioned coprocessor, the method comprising: The ECC core main control module receives the processing task sent by the host computer and loads the input data into the internal register through the intelligent arbitration bus; The ECC core control module controls the coordinate transformation module to map affine coordinates (x,y) to Jacobian coordinates (x,y,1); Based on the bit value of scalar k, the ECC core control module controls the point operation module to send continuous usage requests to the intelligent arbitration module, and performs point multiplication and point addition operations in a loop within the Jacobian domain. Centralized ALUs use a bit-serial algorithm to perform modular multiplication and update Jacobian coordinates without performing modular inverse operations; After the operation is completed, the coordinate transformation module takes over the bus control with the highest priority, requests the centralized ALU to perform the only modular inverse operation and subsequent coordinate restoration multiplication in the entire process, and converts the result back to the affine domain and outputs it.

[0015] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects: Compared with existing technologies, this invention utilizes the algorithm-aware priority logic built into the intelligent arbitration module to dynamically prioritize the point operation module and the coordinate transformation module, thereby ensuring that critical path tasks can obtain centralized ALU computing resources first. This effectively avoids the problem of critical tasks being blocked by non-critical tasks under the traditional polling arbitration mechanism. Since critical tasks no longer wait for a long time, the overall latency of the coprocessor is significantly reduced, thereby improving the real-time performance of elliptic curve cryptography operations. At the same time, this invention constructs a star-shaped computing power sharing architecture with the centralized ALU as the core. With the interaction mechanism between the function request unit and the intelligent arbitration module, it realizes the orderly sharing of a single ALU resource by multiple modules, avoiding resource conflicts and idle waiting, thereby reducing the overall latency of the coprocessor.

[0016] Furthermore, the centralized ALU implements bit-serial or digital-serial modular operations using pure logic gate circuits, reducing the number of logic gates and chip area while ensuring computing power. This balances computing throughput and hardware resource overhead, making it suitable for resource-constrained edge computing nodes. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 This specification provides a schematic diagram of a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus. Figure 2This specification provides a hardware state machine transition diagram for point multiplication based on the Jacobian coordinate system; Figure 3 This specification provides a schematic diagram of the internal architecture of a centralized ALU; Figure 4 This specification provides a schematic diagram of a centralized ALU resource reuse logic. Figure 5 This specification provides a priority control logic and handshake timing diagram for an intelligent arbitration module. Figure 6 This specification provides a schematic flowchart of an encryption method for a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus. Figure 7 A schematic diagram of another encryption method for a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus, as provided in this specification. Figure 8 This document presents a schematic diagram of an encryption and decryption method for a centralized ALU time-division multiplexed ECC coprocessor based on a dynamic priority arbitration bus, as provided in this specification. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without creative effort are within the scope of protection of this application.

[0020] In existing technologies, the contradiction of hardware resources is particularly prominent. In pursuit of speed, current high-performance solutions typically stack a large number of DSP hard cores to implement parallel multipliers. However, in low-cost field-programmable gate arrays (FPGAs) (such as the Lattice iCE40) or radiation-hardened application-specific integrated circuits (ASICs), digital signal processor (DSP) resources are often extremely scarce or non-existent. Existing DSP-free solutions often sacrifice performance by consuming massive look-up table (LUT) resources, resulting in increased chip area and negating the benefits of low cost.

[0021] Therefore, existing technologies urgently need a lightweight hardware architecture that can both avoid the bottleneck of massive modular inverse operations and completely get rid of the dependence on DSP hard cores, and has an efficient bus scheduling mechanism.

[0022] Based on this, the present invention provides a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus, aiming to resolve the aforementioned contradiction between resources and performance, and achieve low-cost, low-power ECC operations with a certain degree of real-time performance. The coprocessor includes a communication bridge unit, an ECC core control unit, a coordinate transformation unit, a point operation unit, a centralized ALU, and an intelligent arbitration bus. For resource-constrained devices, the present invention constructs a star-shaped computing power sharing architecture with a centralized ALU at its core. Through the intelligent arbitration bus, a dynamic priority scheduling strategy based on ECC algorithm flow awareness is implemented to coordinate the time-division access of each functional unit to the centralized ALU, solving the pipeline blocking problem under the traditional polling mechanism. The centralized ALU integrates a bit-serial Montgomery modular multiplier and a binary GCD modular inverter. Through time-division multiplexing of the multiplexer and intermediate result registers, full-stack SM2 and ECC algorithm acceleration is achieved with zero DSP hard core resource consumption. Furthermore, considering the characteristics of the SM2 curve, the present invention designs a specific hardware state machine sequence to optimize the point multiplication operation path. This invention significantly reduces hardware area and power consumption, making it particularly suitable for IoT security chip design.

[0023] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0024] Figure 1 This diagram illustrates the structure of a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus, as described in this specification. The coprocessor specifically includes: a centralized arithmetic logic unit (ALU), an elliptic curve cryptography (ECC) core control module, a point operation module, a coordinate transformation module, and an intelligent arbitration module. The centralized ALU is the coprocessor's sole arithmetic resource, implementing bit-serial or digital-serial modular addition, subtraction, multiplication, and inverse operations using pure logic gates. The intelligent arbitration module connects to the ECC core control module, the point operation module, the coordinate transformation module, and the centralized ALU via an instruction / data bus and handshake signal lines, forming a star-shaped computing power sharing architecture centered on the centralized ALU. The ECC core control module, the point operation module, and the coordinate transformation module are all connected to the intelligent arbitration module as function request units. None of the function request units have independent modular multiplication or inverse operation circuits.

[0025] The ECC core control module is used to parse the processing tasks issued by the host computer, generate corresponding sub-module scheduling instructions based on the processing tasks, and generate a legality verification request for the base point. The legality verification request is sent to the intelligent arbitration module to call the centralized ALU for calculation. The sub-module scheduling instructions include coordinate system transformation instructions or elliptic curve point calculation instructions.

[0026] Specifically, the ECC core control module is used to schedule the overall scalar multiplication process. In this embodiment, the ECC core control module, as one of the function request units, has a built-in base point validity verification submodule, ECC Point Validator. Before executing the scalar multiplication task, this submodule initiates an arithmetic operation request to the intelligent arbitration module, calling the centralized ALU to verify the input base point. Does it satisfy the equation of an elliptic curve? .

[0027] Based on the verification state machine, the main control module sequentially sends modular multiplication instructions OP_MOD_MULT to the centralized ALU to calculate the multiplications respectively. , and Then, a modulo-add instruction OP_MOD_ADD is sent to the centralized ALU to compute. and Ultimately, the main control module verifies the validity of the equations by comparing the results of the left and right equations. This design ensures that the centralized ALU is perfectly reused to perform global security checks without adding independent multipliers and adders.

[0028] After successful verification, the ECC core control module generates corresponding sub-module scheduling instructions based on the processing task and sends them to the point calculation module or coordinate transformation module. This design ensures that the global security verification task is completed by reusing the centralized ALU without increasing additional hardware overhead.

[0029] The point operation module and coordinate transformation module are used to decompose the received submodule scheduling instructions into a low-level arithmetic operation sequence and send the corresponding arithmetic operation request to the intelligent arbitration module; the arithmetic operation request contains the specific opcode and operands.

[0030] The point operation module has a built-in microinstruction sequence optimized for SM2 curves, which is used to perform point operations on elliptic curves; the coordinate transformation module is used to perform coordinate system domain transformations.

[0031] The intelligent arbitration module is used to determine the priority of the point operation module, coordinate transformation module and ECC core main control module according to the built-in algorithm priority logic. It controls the function request unit to send arithmetic operation requests to the centralized ALU through the bus by controlling the priority order from high to low.

[0032] The intelligent arbitration module is equipped with algorithm-aware priority logic, which is used to monitor the request signal status of each functional request unit in real time, and grant control of the centralized ALU and data path to specific functional request units by selecting the instruction / data bus according to the preset priority strategy.

[0033] Optionally, the coordinate transformation module has a higher priority than the point calculation module, and the point calculation module has a higher priority than the ECC core main control module.

[0034] The intelligent arbitration module breaks away from the traditional polling mechanism, implementing an asymmetric dynamic priority strategy based on algorithm flow awareness. This strategy assigns the coordinate transformation module the highest priority, the point operation module the second highest priority, and the ECC core control module the lowest priority. This design is based on the fact that the coordinate transformation module only operates at the beginning and end of the computation, and the coordinate restoration at the end directly determines the overall system latency. Therefore, assigning it the highest priority ensures that the computation results are processed and output immediately once ready, avoiding being blocked by unfinished background maintenance tasks.

[0035] The centralized ALU is used to perform corresponding arithmetic operations based on the arithmetic operation requests received from the authorized channel, and to feed back the operation results to the function request unit that initiated the request.

[0036] As the only shared arithmetic resource in the system, the centralized ALU is configured to perform finite field arithmetic operations, including modular addition, modular subtraction, modular multiplication, and modular inverse. The centralized ALU does not contain digital signal processing (DSP) hard core resources, but is composed of bit-serial or digital-serial arithmetic circuits built from pure logic gates.

[0037] In one embodiment, the centralized ALU integrates an input latch interface, a multimodal arithmetic data path, and a submodule scheduling state machine.

[0038] The input latch interface is used to latch the operation instructions from the bus during the first clock cycle of the operation and keep them locked during the operation; the operation instructions include operands, modulus and opcode.

[0039] The multimodal arithmetic data path includes a shared intermediate result register with a bit width of N+1 bits. This register is time-division multiplexed for overflow detection logic of modular addition, borrow compensation logic of modular subtraction, and basic addition logic.

[0040] The submodule scheduling state machine is configured to trigger the internally instantiated Montgomery modular multiplication submodule or binary GCD modular inverse submodule according to the opcode, and enter a suspended waiting state during the submodule operation until the operation result is received from the submodule.

[0041] The Montgomery modular multiplier module or the binary GCD modular inverse module is used to perform corresponding arithmetic operations according to the operation instructions until the operation is completed.

[0042] Specifically, the centralized ALU integrates various arithmetic operations through time-division multiplexing. To achieve 256-bit large number operations without a DSP, the unit integrates a bit-serialized Montgomery modular multiplier module and a binary GCD modular inverse module, which share the top-level input latch and output register.

[0043] Optionally, the centralized ALU internally incorporates a 257-bit shared intermediate result register (temp_result). This register is assigned different functions under different opcodes. During ordinary addition and modular addition operations, it stores the addition result and retains the carry bit for overflow detection. During modular subtraction operations, it performs borrow compensation logic. This deep register-level reuse significantly reduces the consumption of logic resources.

[0044] In one embodiment, the intelligent arbitration module and the centralized ALU employ a request-hold-release atomic handshake protocol to ensure that the internal state machine of the centralized ALU is not interrupted by high-priority requests during a single modular operation.

[0045] A centralized ALU is used to pull up the busy signal and enter the execution state after the authorized function request unit sends a start pulse.

[0046] The intelligent arbitration module detects the busy signal fed back by the centralized ALU via the handshake signal line. Upon detecting the busy signal, it locks the current authorized channel, blocking all new requests, regardless of their priority, until the centralized ALU outputs a completion signal and pulls the busy signal low. This mechanism effectively prevents low-priority tasks from being unexpectedly interrupted when high-priority tasks are inserted, thus ensuring the atomicity and non-preemptibility of a single modular arithmetic operation.

[0047] Optionally, the point operation module has built-in parameters for elliptic curves. The optimized point multiplier hardware microinstruction sequence is configured to control the centralized ALU to calculate the point multiplier slope intermediate variable. M .

[0048] The point operation module is used to build in parameters for elliptic curves. The optimized point-multiplying hardware microinstruction sequence is used to sequentially send modular multiplication, modular addition, modular subtraction, modular multiplication, and shift addition instructions to the centralized ALU to perform the formula... Alternative standard formula .

[0049] Specifically, to ensure compatibility with multiple standard curves and optimize for high-frequency application scenarios, the coprocessor internally (such as in the base point verification stage or point operation stage) is configured with dynamic hardware execution branches based on curve parameter characteristics. The hardware internally includes feature detection logic for real-time determination of input curve parameters. Does it meet the requirements? (Right now (e.g., the national cryptographic standard SM2 and NIST P-256 curves).

[0050] If the judgment result is yes, the hardware state machine switches to a specific optimized execution mode, using a combination of shift and addition / subtraction logic (i.e., calculation). (Directly derived) The intermediate results are bypassed, thus saving approximately 150 clock cycles of waiting latency by bypassing the modular multiplication operation of the centralized ALU.

[0051] If the judgment result is negative (as in general curves such as secp256k1), the state machine enters the general execution path and normally sends a modular multiplication request with opcode OP_MOD_MULT to the centralized ALU to calculate the multiplication. This design achieves efficient dynamic compatibility between general-purpose curves and specific optimization curves while maintaining a minimal hardware architecture.

[0052] like Figure 2 As shown, the sequence is configured to control the centralized ALU to sequentially perform the following steps to calculate the intermediate variable of point-multiple slope. M : Send a modular multiplication command to request the centralized ALU to calculate the square of the Z-coordinate. ; Sending modulus addition command requests centralized ALU calculation ; Send a modulo-reduction command to request centralized ALU calculation. ; Send a modular multiplication instruction to request centralized ALU computation. ; Send shift-add instruction to request centralized ALU calculation .

[0053] Through hardware sequence, using formula Alternative standard formula This sequence avoids the calculation of the fourth power and the multiplication with parameters. Under a single centralized ALU serial architecture, this directly reduces the total number of modular multiplication operations and improves the overall throughput.

[0054] In one embodiment, the coordinate transformation module is configured to perform a domain transformation based on the Jacobian coordinate system.

[0055] The coordinate transformation module, in response to a first mode signal during the data input phase, directly maps the externally input affine coordinates (x, y) to Jacobian coordinates (x, y, 1) via register transfer logic. This process bypasses the centralized ALU to achieve zero-computational-overhead domain transformation. In the data output phase, in response to a second mode signal, it requests the centralized ALU to perform modular inverse operation to calculate the inverse of the Z coordinate, and then continuously requests the centralized ALU to perform a modular multiplication sequence to calculate the affine coordinates. During this output phase, the intelligent arbitration module ensures continuous resource supply based on the highest priority strategy.

[0056] In one embodiment, please see [link to embodiment]. Figure 1 The coprocessor also includes a communication bridging module.

[0057] The communication bridging module is used to parse the host computer instructions, generate processing tasks, and send the parsed processing tasks to the ECC core main control module, as well as to receive the task calculation results sent by the ECC core main control module and send the task calculation results to the host computer.

[0058] The coprocessor provided by this invention has a hardware architecture that adopts a bus star topology with a centralized ALU as the core, and the modules are interconnected through an internal bus; wherein, the ECC core main control module is responsible for global scheduling, and the communication bridge module is responsible for data transmission and reception.

[0059] The overall system workflow is as follows: external commands enter through the communication bridging module, are parsed by the ECC core control module, and trigger the corresponding calculation process. During the calculation, the coordinate transformation module and the point calculation module, acting as "function request units," continuously send centralized ALU usage requests to the intelligent arbitration module. The arbitration module dynamically allocates the unique ALU resource to the requester based on the current bus status and priority policy.

[0060] In one embodiment, the centralized ALU is the core of the entire system's computing power, and its design employs a deep resource reuse strategy to achieve a zero-DSP goal. For example... Figure 3 As shown, a centralized ALU includes a basic arithmetic unit, a modular multiplier, and a modular inverter; the basic arithmetic unit is used to implement addition, subtraction, modular addition, and modular subtraction operations.

[0061] The centralized ALU mainly consists of input latch logic, a finite state machine (FSM), a bit serial modular multiplier module (Radix-2 Montgomery), a binary GCD modular inverse submodule, and a shared addition / logic operation path. To save resources, the ALU does not instantiate multiple adders, but instead uses a 257-bit shared register temp_result in conjunction with a multiplexer to implement various operations.

[0062] Specifically, when executing the opcode OP_ADD (normal addition) or OP_MOD_ADD (modulo addition), the ALU in the EXECUTE state uses addition logic to calculate {1'b0, latched_operand_a} + {1'b0, latched_operand_b} and stores the result in temp_result. Subsequently, if it is a modulo addition operation, the state machine jumps to the OUTPUT state, checks whether temp_result is greater than the modulus, and if it is, performs a reduction operation using the same set of subtraction logic. This design allows the adder, subtractor, and comparator logic to be reused in time.

[0063] For complex modular multiplication and modular inversion operations, the ALU triggers internal submodules via the mod_mult_start and mod_inv_start signals and suspends in the WAIT_MOD_OP state until the submodule returns a valid signal. This design, which encapsulates complex operations into atomic operations, greatly simplifies the upper-level control logic.

[0064] In one embodiment, such as Figure 4 As shown, Figure 3 A resource reuse logic diagram is provided, in which the coordinate transformation module, point operation module and ECC main control module can all send ALU requests to the intelligent arbitration module. The intelligent arbitration module authorizes the ALU requests of the corresponding modules through dynamic priority logic, controls the centralized ALU to perform the corresponding operations through the selected operands / opcodes, and sends the operation results to the corresponding modules through the bus.

[0065] In one embodiment, such as Figure 5 As shown, the intelligent arbitration module arbiter is key to resolving conflicts involving single ALU resources. This module monitors request signals in real time from the coordinate transformation module req_conv, the point operation module req_point, and the main control module req_main.

[0066] To optimize system performance, this embodiment employs an asymmetric static priority strategy: Priority (coordinate transformation module) > Priority (point operation module) > Priority (ECC core control module). When the coordinate transformation module initiates a request, the arbitrator will respond to the former first, regardless of whether the point operation module also has a request. The underlying technical consideration is that coordinate transformation typically occurs in the final stage of scalar multiplication (Jacobian to Affine), at which point the operation is complete and the system urgently needs to output the result to the host. Therefore, assigning it the highest priority minimizes the final handshake latency.

[0067] Compared with the prior art, the advantages of the present invention are: 1. The star-shaped computing power sharing topology constructed in this invention, combined with a centralized ALU design with zero DSP, achieves a measured core logic usage of only 9800 LUTs on a Xilinx Kintex-7 FPGA hardware platform at a 50MHz operating frequency, with zero DSP and BRAM resource consumption. Simultaneously, at this operating frequency, the normal latency for 256-bit scalar multiplication is 7.24ms. This completely eliminates the dependence on DSP hard cores, allowing this IP core to be easily integrated into any resource-constrained, low-cost FPGA or radiation-hardened ASIC, achieving an optimal balance between resources and performance.

[0068] 2. The asymmetric dynamic priority arbitration strategy proposed in this invention effectively solves the resource contention and deadlock problems under a single centralized ALU architecture. In particular, by prioritizing the bandwidth of the coordinate transformation module, it significantly reduces the I / O response latency of the system and improves the availability in scenarios with high real-time requirements (such as identity authentication).

[0069] 3. This invention reduces the number of modular inverses in 256-bit scalar multiplication from approximately 512 to 1 by combining the Jacobian coordinate system with a specific optimized sequence of SM2, and also reduces the number of modular multiplications in the intermediate process. It achieves an engineering-usable computing speed under a serial architecture, achieving the best balance between resources and performance.

[0070] The modules in the aforementioned centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus are preferably implemented using pure hardware logic circuits. Specifically, these modules can be embodied as hardware IP cores in field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), complex programmable logic devices (CPLDs), or system-on-a-chip (SoCs). This coprocessor can function as an independent hardware acceleration unit, connecting to external host computer devices (such as MCUs or CPUs) via the system bus, and directly processing low-level elliptic curve cryptography operations in hardware form, thereby offloading the computational load from the main processor.

[0071] The above are one or more embodiments of a centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus provided in this specification. Based on the same approach, this specification also provides corresponding encryption methods, such as... Figure 6 As shown, this specification provides an ECC encryption method based on the aforementioned coprocessor, which includes the following steps: S101, the ECC core main control module receives the processing task sent by the host computer and loads the input data into the internal register through the intelligent arbitration bus.

[0072] S102, the ECC core main control module controls the coordinate transformation module to map affine coordinates (x,y) to Jacobian coordinates (x,y,1).

[0073] S103, the ECC core main control module controls the point operation module to send continuous usage requests to the intelligent arbitration module based on the bit value of scalar k, and performs point multiplication and point addition operations in a loop within the Jacobian domain.

[0074] The dot operation module performs dot multiplication and dot addition operations cyclically within the Jacobian domain. During this process, the dot operation module frequently requests ALU resources, which are dynamically scheduled by the intelligent arbitration module based on priority.

[0075] S104, the centralized ALU uses a bit-serial algorithm to perform modular multiplication and updates the Jacobian coordinates without performing modular inverse operations.

[0076] S105 After the operation is completed, the coordinate transformation module takes over the bus control with the highest priority, requests the centralized ALU to perform the only modular inverse operation and subsequent coordinate restoration multiplication in the entire process, and converts the result back to the affine domain and outputs it.

[0077] After the loop ends, the normalization phase begins. At this point, the coordinate transformation module issues a high-priority modular inverse request, forcibly acquiring ALU control and performing the only modular inverse operation in the entire process. This calculates the inverse of the Z-axis coordinate and then the final affine coordinate output. The entire process is smooth and efficient, making full use of limited hardware resources.

[0078] Specifically, such as Figure 7 As shown, this invention also provides an ECC encryption method based on the aforementioned coprocessor, specifically including: after the system powers on and resets, it enters the initialization phase, where the communication bridge module parses the host computer instructions and stores the scalar k and base point P into a register. Subsequently, the ECC core main control module controls the coordinate transformation module to perform a zero-overhead domain transformation, directly mapping the affine coordinates (x, y) to Jacobian coordinates (x, y, 1). This process only involves register transfer and does not occupy centralized ALU resources.

[0079] Next, the core scalar multiplication loop begins. The ECC core control module, based on the bit value of scalar k, controls the point arithmetic module to perform point multiplication and point addition operations cyclically within the Jacobian domain. During this period, the point arithmetic module frequently requests ALU resources, which are dynamically scheduled by the intelligent arbitration module based on priority.

[0080] After the loop ends, the normalization phase begins. At this point, the coordinate transformation module issues a high-priority modular inverse request, forcibly acquiring ALU control and performing the only modular inverse operation in the entire process. This calculates the inverse of the Z-axis coordinate and then the final affine coordinate output. The entire process is smooth and efficient, making full use of limited hardware resources.

[0081] Specifically, such as Figure 8 As shown, this application also provides an encryption and decryption method based on the coprocessor provided by the present invention, specifically including the following steps: Step 1: The recipient first generates a private key locally. Subsequently, the system invokes the centralized ALU time-division multiplexing ECC coprocessor (hereinafter referred to as the ECC core) based on a dynamic priority arbitration bus in the hardware system to perform base-point scalar multiplication. The ECC core, through its internal point arithmetic module, collaborates with the centralized ALU to calculate the public key. ,in This is the base point of the elliptic curve. After calculation, the receiver publishes the public key. And keep your private key safe. .

[0082] Step 2: The sender obtains the public key published by the receiver. and the original message to be sent Subsequently, the sender generates a random temporary key locally. (Also known as a temporary private key), which serves as an encryption factor during a single session.

[0083] Step 3: The sender invokes the ECC core and utilizes its internal computing power scheduling mechanism to execute the following two scalar multiplication operations serially or in instruction-level parallel: 1. Calculation of the first ciphertext component: The ECC core is invoked to perform a base-point scalar multiplication operation, which yields the result. ; 2. Intermediate Vector Generation: Calls the ECC core to perform pointwise scalar multiplication operations, utilizing the public key. As the input point, the intermediate vector is calculated. ; During the operation, the intelligent arbitration module inside the ECC core ensures a fast response to the scalar multiplication sequence based on the computation priority.

[0084] Step 4: The intermediate vector obtained by the sender from Step 3 In this process, a symmetric key is derived using a predefined key derivation function (KDF). Then, this symmetric key is used to analyze the original message. Perform symmetric encryption to generate a second ciphertext component. Finally, the sender will generate a ciphertext pair ( , Send to the recipient.

[0085] Step 5: The receiver receives the encrypted pair ( , After that, the ECC core is invoked to perform a point-to-point scalar multiplication operation. During this process, the receiver passes its private key. and the first encrypted component received The input is fed into the ECC core, where the intermediate decryption vector is calculated. ,in At this point, the centralized ALU within the ECC core utilizes a bit-serial algorithm to ensure efficient reuse of storage resources.

[0086] Step 6: The receiver receives the decryption intermediate vector. A symmetric key is derived from this. Based on the bilinear property of elliptic curves, it satisfies... Therefore, the symmetric key derived by the receiver is exactly the same as that of the sender. Finally, this symmetric key is used to cipher the second ciphertext component. Decrypt and restore to obtain the original message. It then outputs the result, completing the entire secure communication process.

[0087] In summary, this invention constructs a star-shaped shared architecture with a centralized ALU as the computing core. Through deeply multiplexed bit-serial operation paths and multi-modal register time-division multiplexing mechanisms, it achieves efficient support for full-stack SM2 and general ECC algorithms with zero DSP hard core resource consumption, greatly reducing the hardware logic area overhead and static power consumption of IoT security chips. In addition, the algorithm flow-aware asymmetric dynamic priority scheduling strategy and "request-hold-release" atomic handshake protocol implemented in this invention effectively solve the bus conflict and deadlock problems under single computing resources. Combined with specific hardware micro-instruction sequences optimized for SM2 curve parameters, it achieves the best balance between processing throughput and real-time response performance in resource-constrained environments, demonstrating significant technical advancement, practical value, and innovation in low-cost FPGA integration and radiation-resistant ASIC design applications.

[0088] When applying the encryption methods provided in this manual, it is not necessary to follow the instructions. Figure 6 The steps shown are executed in sequence. The specific execution order of each step can be determined as needed, and this manual does not impose any restrictions on it.

[0089] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A centralized ALU time-division multiplexing ECC coprocessor based on a dynamic priority arbitration bus, characterized in that, The coprocessor includes a centralized arithmetic logic unit (ALU), an elliptic curve cryptography (ECC) core control module, a point operation module, a coordinate transformation module, and an intelligent arbitration module. The centralized ALU is the coprocessor's sole arithmetic resource, implementing bit-serial or digital-serial modular addition, subtraction, multiplication, and inverse operations using pure logic gates. The ECC core control module, point operation module, and coordinate transformation module are connected to the intelligent arbitration module as function request units, and the intelligent arbitration module is also connected to the centralized ALU. The ECC core main control module is used to parse the processing tasks issued by the host computer, generate corresponding sub-module scheduling instructions according to the processing tasks, and generate a legality verification request for the base point. The legality verification request is sent to the intelligent arbitration module to call the centralized ALU for calculation. The sub-module scheduling instructions include coordinate system transformation instructions or elliptic curve point calculation instructions. The point operation module and coordinate transformation module are used to decompose the received submodule scheduling instructions into a low-level arithmetic operation sequence and send the corresponding arithmetic operation request to the intelligent arbitration module; the arithmetic operation request includes a specific opcode and operands; The intelligent arbitration module is used to determine the priority of the point operation module, coordinate transformation module and ECC core main control module according to the built-in algorithm priority logic. It controls the function request unit to send arithmetic operation requests to the centralized ALU through the bus by controlling the priority order from high to low. The centralized ALU is used to perform corresponding arithmetic operations based on the arithmetic operation requests received from the authorized channel, and to feed back the operation results to the function request unit that initiated the request.

2. The coprocessor according to claim 1, characterized in that, The centralized ALU integrates an input latch interface, a multimodal arithmetic data path, and a submodule scheduling state machine. The input latch interface is used to latch the operation instructions from the bus during the clock cycle at which the operation is started, and to keep them locked during the operation; the operation instructions include operands, modulus and opcode; The multimodal arithmetic data path includes a shared intermediate result register with a bit width of N+1 bits. This register is time-division multiplexed for overflow detection logic of modular addition, borrow compensation logic of modular subtraction, and basic addition logic. The submodule scheduling state machine is configured to trigger the internally instantiated Montgomery modular multiplication submodule or binary GCD modular inverse submodule according to the opcode, and enter a suspended waiting state during the submodule operation until the operation result fed back by the submodule is received; The Montgomery modular multiplier module or the binary GCD modular inverse module is used to perform corresponding arithmetic operations according to the operation instructions until the operation is completed.

3. The coprocessor according to claim 2, characterized in that, The shared intermediate result register is assigned different functions under different opcode control; The shared intermediate result register is used to store the addition result and retain the carry bit for overflow detection when performing ordinary addition and modular addition operations; and to perform borrow compensation logic when performing modular subtraction operations.

4. The coprocessor according to claim 1, characterized in that, The intelligent arbitration module and the centralized ALU use an atomic handshake protocol of request-hold-release. The centralized ALU is used to pull up the busy signal and enter the execution state after the authorized function request unit sends a start pulse; The intelligent arbitration module is used to detect the busy signal fed back by the centralized ALU through the handshake signal line, and after detecting the busy signal, lock the current authorized channel and block the requests of all other function request units until the centralized ALU outputs a calculation completion signal and pulls the busy signal low.

5. The coprocessor according to claim 1, characterized in that, The point operation module has built-in parameters for elliptic curves. The optimized point-multiplication hardware microinstruction sequence is configured to control the intermediate variable of the slope for the centralized ALU calculation. M ; The point operation module is used to build in parameters for elliptic curves. The optimized point-multiplication hardware microinstruction sequence is used to sequentially send modular multiplication, modular addition, modular subtraction, modular multiplication, and shift addition instructions to the centralized ALU to perform the formula... Alternative standard formula .

6. The coprocessor according to claim 1, characterized in that, The coordinate transformation module is configured to perform domain transformations based on the Jacobian coordinate system; The coordinate transformation module is used to, in response to a first mode signal during the data input phase, directly map the externally input affine coordinates (x, y) to Jacobian coordinates (x, y, 1) through register transfer logic; and in response to a second mode signal during the data output phase, request the centralized ALU to perform modular inverse operation to calculate the inverse of the Z coordinate, and continuously request the centralized ALU to perform a modular multiplication sequence to calculate the affine coordinates. During this output phase, the intelligent arbitration module ensures continuous resource supply according to the highest priority strategy.

7. The coprocessor according to claim 1, characterized in that, The coordinate transformation module has a higher priority than the point calculation module, and the point calculation module has a higher priority than the ECC core main control module.

8. The coprocessor according to claim 1, characterized in that, The coprocessor also includes a communication bridging module; The communication bridging module is used to parse the host computer instructions, generate processing tasks, and send the parsed processing tasks to the ECC core main control module, as well as to receive the task calculation results sent by the ECC core main control module and send the task calculation results to the host computer.

9. The coprocessor according to claim 1, characterized in that, The centralized ALU includes a basic arithmetic unit, a modular multiplier, and a modular inverter; the basic arithmetic unit is used to implement addition, subtraction, modular addition, and modular subtraction operations.

10. An ECC encryption method based on the coprocessor according to any one of claims 1-9, characterized in that, The method includes: The ECC core main control module receives the processing task sent by the host computer and loads the input data into the internal register through the intelligent arbitration bus; The ECC core control module controls the coordinate transformation module to map affine coordinates (x,y) to Jacobian coordinates (x,y,1); Based on the bit value of scalar k, the ECC core control module controls the point operation module to send continuous usage requests to the intelligent arbitration module, and performs point multiplication and point addition operations in a loop within the Jacobian domain. The centralized ALU uses a bit-serial algorithm to perform modular multiplication and updates the Jacobian coordinates without performing modular inverse operations; After the operation is completed, the coordinate transformation module takes over the bus control with the highest priority, requests the centralized ALU to perform the only modular inverse operation and subsequent coordinate restoration multiplication in the entire process, and converts the result back to the affine domain and outputs it.

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