A modular mold for encapsulating a redistribution layer fabrication and applications thereof

Abstract

Embodiments of the present application disclose a kind of for encapsulating rewire layer preparation modular mold and its application;The modular mold of the present application embodiment can have greater than single processing field of view splicing pattern area, splicing pattern area is formed by multiple sub-molds with array arrangement, the pattern of splicing pattern area corresponds to the via-wiring interconnection structure of integrated circuit rewire layer, the pattern surface of sub-mold includes: high-density interconnection area, contains the microcircuit pattern for forming chip internal high-density signal wiring;Peripheral interconnection area is arranged in the side of high-density interconnection area, contains the widened wire pattern for forming electrical interconnection with adjacent sub-mold, widened wire pattern extends to the boundary of sub-mold, for forming lap joint interconnection with the corresponding wire pattern of adjacent sub-mold;Wherein, the line width of widened wire pattern of peripheral interconnection area is greater than the line width of microcircuit pattern.Thereby, the present application embodiment improves packaging efficiency and yield.

Description

Technical Field

[0001] This application relates to the field of packaging technology, specifically to a modular mold for preparing a packaging redistribution layer and its application. Background Technology

[0002] With the rapid development of wireless communication, automotive electronics, and other consumer electronics products, microelectronic packaging technology is constantly evolving towards multifunctionality, miniaturization, high speed, low power consumption, and high reliability. Currently, in advanced packaging solutions for applications such as high-performance computing and data centers, a re-distribution layer (RDL) is commonly introduced. This aims to overcome the data transmission bottleneck between chips through high-density interconnects, significantly improving the signal bandwidth and overall performance of the package.

[0003] However, due to the complex projection optics system of traditional lithography equipment, the imaging field of view of a single exposure has a physical limit, making it difficult to directly meet the integrated processing requirements of large-size RDL layers. To address this size limitation, existing technologies have to employ complex multi-mask step-by-step splicing and multiple exposure schemes. Furthermore, due to the image field characteristics of the optical system, the processing is typically only suitable for circular wafer substrates, making it difficult to apply to rectangular panels with higher utilization rates. This not only leads to cumbersome manufacturing processes and high costs, but also results in low product yield and production efficiency due to the accumulation of alignment errors at the splicing points, severely restricting the large-scale application of advanced packaging technologies in the field of high-performance computing chips. Summary of the Invention

[0004] This application provides a modular mold for preparing a redistribution layer and its application. The application includes a method for manufacturing the modular mold for preparing a redistribution layer, a mass production mold for preparing a redistribution layer, a method for manufacturing the mass production mold for preparing a redistribution layer, and the application of the mass production mold for preparing a redistribution layer in chip packaging. It can complete the high-precision imprinting of large-size panel-level redistribution layers in one go, effectively breaking through the physical size limitation of the single exposure field of traditional photolithography equipment, facilitating the large-scale production of large-area, high-density interconnect structures, improving packaging efficiency and yield, and reducing the manufacturing cost of advanced packaging processes.

[0005] This application provides a modular mold for fabricating a redistribution layer. The modular mold has a splicing pattern area larger than the field of view of a single processing step. The splicing pattern area is formed by multiple sub-molds arranged in an array. The pattern of the splicing pattern area corresponds to the via-wiring interconnect structure of the integrated circuit redistribution layer. The maximum size of one side of the sub-mold is adapted to the mold head size of the packaging processing equipment. The pattern surface of the sub-mold includes:

[0006] The high-density interconnect region contains micro-line patterns for forming high-density signal traces inside the chip, and the feature size of the micro-line patterns is on the nanometer scale.

[0007] The peripheral interconnection area, located around the high-density interconnection area, includes a widened wire pattern for forming an electrical interconnection with adjacent sub-molds. The widened wire pattern extends to the boundary of the sub-mold and is used to form an overlapping interconnection with the corresponding wire pattern of the adjacent sub-mold.

[0008] The peripheral interconnect region has a feature size in the micrometer range, and the linewidth of the widened conductor pattern is greater than that of the fine line pattern.

[0009] This application also provides a method for manufacturing a modular mold for packaging redistribution layers. The method is used to prepare any of the modular molds provided in this application, and the method includes:

[0010] At least one main template and a substrate to be processed are provided. The main template has an embossed structure corresponding to the surface of the sub-mold pattern. The embossed structure includes a high-density interconnect area pattern and a peripheral interconnect area pattern located on the periphery.

[0011] A UV-curable imprinting adhesive is coated onto the surface of the substrate to be processed;

[0012] According to the preset array arrangement order, at least one main template is controlled to perform multiple imprinting and stepping movements relative to the substrate to be processed; wherein, in the splicing area of ​​two adjacent imprinting operations, alignment is performed based on the position of the peripheral interconnect area pattern, so that the peripheral interconnect area pattern formed by the current imprinting at least partially overlaps with the peripheral interconnect area pattern formed by the previous imprinting in the splicing direction.

[0013] After each imprint, the UV-curable imprinting adhesive is cured by UV exposure.

[0014] After all the step-by-step imprinting is completed, the main mold is separated, and a splicing pattern area consisting of multiple arrayed sub-molds is formed on the substrate to be processed.

[0015] This application embodiment also provides a mass production mold for preparing a packaged redistribution layer, the mass production mold being replicated from the modular mold provided in this application embodiment;

[0016] Mass production molds are used to fabricate single interconnect layers in multilayer interconnect structures of integrated circuits. These single interconnect layers integrate via interconnect structures and wiring interconnect structures.

[0017] The mass production mold has a splicing pattern area that is larger than the field of view of a single processing, and the splicing pattern area is formed by multiple sub-mold units arranged in an array.

[0018] The surface relief pattern of each sub-mold unit includes an integrated through-hole forming area and a wiring forming area, which are used to simultaneously form through-hole cavities and wiring trenches within the dielectric material layer in a single imprinting process.

[0019] The sub-mold unit has a peripheral interconnect area on its periphery. The peripheral interconnect area includes a widened wire pattern and a package alignment mark. The widened wire pattern extends to the boundary of the sub-mold unit and is used to form an overlap interconnect with the corresponding wire pattern of the adjacent sub-mold unit to form a continuous through-hole-wiring interconnect structure after metal backfilling and chemical mechanical polishing.

[0020] The mass production mold is used as the Nth stage mold in the multilayer stacking process of integrated circuits. It performs step-by-step imprinting on the already formed N-1 via-wiring interconnect layer through substrate alignment to construct the Nth via-wiring interconnect layer, where N is an integer greater than or equal to 2.

[0021] This application also provides a method for manufacturing a mass production mold for preparing a redistribution layer. The method includes:

[0022] Provide a modular mold as a master mold, as provided in any of the embodiments of this application;

[0023] A substrate is provided, and a cured material layer is formed on the surface of the substrate;

[0024] The master mold is pressed and bonded to the substrate, so that the relief pattern on the surface of the master mold is transferred to the curing material layer. The relief pattern includes an integrated through-hole forming area and a wiring forming area.

[0025] The solidified material layer is cured, and the master mold is separated from the substrate to form a mass production mold with an embossing structure that complements the relief pattern.

[0026] The embossed structure has a peripheral interconnection area on its periphery, which includes a widened wire pattern that extends to the boundary of the sub-mold unit and is used to form an overlapping interconnection with the corresponding wire pattern of the adjacent sub-mold unit.

[0027] This application also provides an application of a mass production mold for preparing a redistribution layer in chip packaging. The mass production mold is the one provided in this application, which has a peripheral interconnect area and a widened wire pattern. The widened wire pattern is used to form an overlap interconnect with the corresponding wire pattern of an adjacent sub-mold unit. This application includes:

[0028] By using a step-printing process, a multi-layer interconnect structure of integrated circuits is constructed on a packaging substrate or chip. The multi-layer interconnect structure of integrated circuits includes at least one single-layer interconnect layer that integrates a through-hole interconnect structure and a wiring interconnect structure.

[0029] In the fabrication of a single interconnect layer, a mass production mold is used for a single imprinting process to simultaneously form via cavities and wiring trenches within the dielectric material layer. Subsequently, a conductive via-wiring interconnect layer is formed through metal backfilling and chemical mechanical polishing processes.

[0030] In this application, since the modular mold has a splicing pattern area larger than the field of view of a single processing, the splicing pattern area is formed by multiple sub-molds arranged in an array. The pattern of the splicing pattern area corresponds to the via-wiring interconnect structure of the redistribution layer of the integrated circuit. The maximum size of a single side of the sub-mold is adapted to the mold head size of the packaging processing equipment, which effectively avoids the physical limits of large-size molds in manufacturing and imprinting processes, and realizes the modular expansion of mold size and process adaptability.

[0031] The patterned surface of the sub-mold includes a high-density interconnect area and a peripheral interconnect area. The high-density interconnect area contains micro-line patterns for forming high-density signal traces inside the chip. The feature size of the micro-line patterns is at the nanometer level, which realizes the high-density and high-precision wiring requirements of signals inside the chip and ensures the electrical performance of the core functional area.

[0032] The peripheral interconnection area, located around the high-density interconnection area, includes a widened wire pattern for forming an electrical interconnection with adjacent sub-molds. The widened wire pattern extends to the boundary of the sub-mold and forms an overlapping interconnection with the corresponding wire pattern of the adjacent sub-mold. This solves the problem of electrical continuity at the splicing point of adjacent sub-molds and eliminates the adverse effects of splicing seams on circuit conduction through structural redundancy design.

[0033] This allows for high-precision imprinting of large-size panel-level redistribution layers in a single operation, effectively overcoming the physical size limitations of traditional photolithography equipment's single-exposure field of view. This facilitates the mass production of large-area, high-density interconnect structures, thereby improving packaging efficiency and yield, and reducing the manufacturing cost of advanced packaging processes. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1a This is a schematic diagram of the modular mold provided in an embodiment of this application;

[0036] Figure 1b This is a schematic diagram of the splicing pattern area provided in the embodiments of this application;

[0037] Figure 1cThis is a schematic diagram of the patterned surface of the sub-mold provided in the embodiments of this application;

[0038] Figure 1d This is a schematic diagram of the splicing of sub-models provided in the embodiments of this application;

[0039] Figure 2 This is a schematic diagram of a method for manufacturing a modular mold provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the mass production mold provided in the embodiments of this application;

[0041] Figure 4 This is a schematic diagram of the method for manufacturing a mass production mold provided in the embodiments of this application;

[0042] Figure 5a This is a schematic diagram of the chip package provided in an embodiment of this application;

[0043] Figure 5b This is a schematic diagram of a single-layer interconnect layer provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] This application provides a modular mold for preparing a packaged redistribution layer and its application.

[0046] It is understood that redistribution layer fabrication refers to the process of rearranging the input / output (I / O) pads inside the chip to more easily externally connected locations by constructing metal interconnect lines on the wafer or packaging substrate during chip packaging, thereby forming electrical interconnection channels. The modular mold used in this application for redistribution layer fabrication is a specialized tool to address the field-of-view limitations and processing efficiency bottlenecks faced by traditional photolithography processes in large-size panel-level packaging. Specifically, this mold is specifically designed to form large-area, high-density redistribution layer (RDL) patterns on the packaging substrate in a single step using nanoimprint lithography.

[0047] In application, this modular mold, utilizing its splicing pattern area formed by multiple sub-mold arrays, overcomes the physical size limitations of a single processing field of view, making large-size panel-level processing possible. Simultaneously, through the functional division of the sub-mold surface into a unique "high-density interconnect area" and a "peripheral interconnect area," this mold not only meets the high-precision manufacturing requirements of nanoscale micro-circuits in the core area of ​​the chip, but also utilizes the widened conductor pattern extending to the boundary to form a reliable overlapping interconnect with adjacent sub-molds, effectively eliminating the risk of electrical open circuits at the splicing seams. Thus, this mold achieves efficient, continuous, and high-precision imprinting of through-hole-wiring interconnect structures on large-size substrates.

[0048] Any references to “top,” “bottom,” “above,” “below,” “upper,” “lower,” “front,” “back,” “first,” “second,” “left,” or “right” herein are not intended to be limiting. In this document, the term “about” when applied to a value generally means within the tolerance range of the equipment used to produce that value, or may refer to plus or minus 10%, or plus or minus 5%, or plus or minus 1%, unless expressly stated otherwise. Furthermore, the term “substantially” as used herein means a quantity ranging from most, almost all, or all, or about 51% to about 100%. Moreover, the examples in this document are for illustrative and discussion purposes only and not as limitations.

[0049] The following sections provide detailed descriptions of each example. It should be noted that the sequence numbers of the following embodiments are not intended to limit the preferred order of the embodiments.

[0050] In this embodiment, a modular mold for fabricating a redistribution layer is provided. This modular mold has a splicing pattern area S1 larger than the field of view in a single processing step, such as... Figure 1a As shown, the splicing pattern area is formed by multiple sub-molds S2 arranged in an array, such as... Figure 1b As shown, the pattern of the splicing pattern area S1 corresponds to the via-wiring interconnect structure S3 of the integrated circuit redistribution layer. The maximum single-side dimension of the sub-mold S2 is adapted to the mold head size of the packaging processing equipment. The pattern surface of the sub-mold includes:

[0051] In this context, the single-process field of view refers to the field of view of a single exposure or a single imprinting operation. It represents the maximum effective working area that a packaging processing device (such as a stepper lithography machine or a nanoimprint lithography machine) can cover in a single static processing operation (such as a single exposure or a single imprinting). This parameter is limited by the physical dimensions of the device's optical lens or the mechanical dimensions of the imprinting die. In this embodiment, this parameter is a physical bottleneck that prevents traditional processes from directly processing ultra-large panel-level redistribution layers. For example, the single-process field of view is specifically 26mm × 33mm (i.e., the single exposure field of view of a standard lithography machine) or 200mm × 200mm (i.e., the maximum effective imprinting area of ​​a specific nanoimprint lithography device die).

[0052] Sub-mold S2 is the basic unit constituting a modular mold, referring to a small mold unit with an independent patterned surface. Its size is smaller than or equal to the single processing field of view of the packaging equipment. In this embodiment, the sub-mold serves as a carrier for pattern transfer, and through the physical splicing and combination of multiple sub-molds, a complete pattern covering a large-size substrate is formed.

[0053] In nanoimprint lithography, the sub-mold is typically a precision etched plate made of a high-hardness, high-wear-resistance material. Specifically, the sub-mold is a quartz glass (fused silica) template processed by electron beam lithography or laser direct writing, or a single-crystal silicon template. Its surface is etched with nanoscale relief patterns, and its external dimensions are standard rectangles. The length and width of this rectangle are both less than or equal to the size of the single imprinting field of view of the nanoimprint lithography machine, so that a complete pattern covering the entire plate can be formed by array splicing.

[0054] Multiple sub-molds refer to a set of two or more sub-molds. In the context of this embodiment, this term emphasizes that the modular mold is not composed of a single integral structure, but is composed of several independent sub-molds combined according to specific arrangement rules. These sub-molds may be physically separate, but functionally they are spliced ​​together to form a unified pattern transfer surface.

[0055] In some embodiments, the surface pattern configuration of multiple sub-dies is flexible. Specifically, when used for repetitive manufacturing of a large-area single chip, the surface patterns of multiple sub-dies can be identical to achieve parallel batch production; while when used for ultra-large panel-level packaging, the surface patterns of multiple sub-dies can be different or partially complementary, and the patterns of multiple sub-dies are spliced ​​together to form a complex interconnect circuit covering the entire panel.

[0056] An array pattern refers to a geometric arrangement in which multiple sub-molds are arranged in an orderly manner according to a preset row and column rule within a splicing pattern area. This arrangement typically includes a matrix arrangement (such as M rows × N columns), which aims to cover a large substrate area with small-sized sub-molds through regular periodic repetition, ensuring the uniformity of pattern distribution and the predictability of splicing.

[0057] The splicing pattern area S1 refers to the overall effective pattern area formed by multiple sub-molds arranged in an array. The total area of ​​this area is larger than the area of ​​a single sub-mold and larger than the single processing field of view of the packaging equipment. In this embodiment, the splicing pattern area S1 corresponds to the sum of the large-area redistribution layer patterns that ultimately need to be formed on the packaging substrate.

[0058] In some embodiments, the pattern configuration of the splicing pattern area S1 is highly flexible to adapt to different packaging requirements. Specifically, the splicing pattern area S1 can be a repeating unit structure formed by arranging multiple sub-molds with the same surface pattern in an array, suitable for large-scale parallel manufacturing of multi-chip modules or standardized circuits; or, the splicing pattern area S1 can also be composed of multiple sub-molds with different surface patterns, each sub-mold carrying differentiated circuit block patterns, which together form a complex non-repetitive interconnect network covering an ultra-large panel through complementary splicing.

[0059] An integrated circuit redistribution layer refers to a metal interconnect layer constructed on the surface of a chip or substrate in wafer-level or board-level packaging. Its function is to relocate the original input / output pads of the chip to new locations (such as fan-out areas) through redistribution to accommodate subsequent bump fabrication or external connection requirements. In this embodiment, it specifically refers to a high-density interconnect layer fabricated using nanoimprint lithography.

[0060] The fan-out region, or extended region in fan-out packaging technology, refers to an extended substrate area built outside the physical boundaries of the chip through packaging processes (such as molding compound packaging). This region overcomes the limitations of the chip's own area on input / output density, allowing the electrical signal contacts inside the chip to be "fanned out" beyond the chip's physical boundaries through redistribution layers, thereby rearranging more connection points over a larger area.

[0061] Redistribution layers, a key technology for achieving the aforementioned functions, are essentially one or more layers of sophisticated metal interconnects (typically copper wires). Like a "municipal road network" within the package, they guide densely packed pads on the chip to new locations in the fan-out area through a micrometer-level wiring structure. This not only achieves spatial reorganization of electrical connections but also reduces parasitic inductance by shortening signal transmission paths, thereby significantly improving the chip's signal integrity and thermal management efficiency.

[0062] The via-wiring interconnect structure S3 refers to a composite structure in a redistribution layer that simultaneously includes vertical interconnect channels (vias) and horizontal signal transmission lines (wiring). In terms of die patterning, this structure is represented by an integrated combination of recessed patterns for forming vias and grooved patterns for forming conductors. This structure aims to achieve both interlayer vertical connectivity and intralayer horizontal routing in a single imprinting process.

[0063] The maximum single-side dimension of the sub-mold refers to the physical dimension of the longest side of the sub-mold in its planar geometry (usually a rectangle or square). In this embodiment, this dimension is designed to fit the mold head size of the packaging processing equipment, that is, the long side of the sub-mold does not exceed the effective travel range of the equipment mold head or lens, to ensure the feasibility of a single imprinting or exposure operation.

[0064] Packaging processing equipment refers to automated mechanical equipment used to perform chip packaging manufacturing processes. In the context of this embodiment, it specifically refers to equipment with step-by-step imprinting or step-by-step photolithography functions. This equipment controls the movement of the mold head or lens on the substrate to perform pattern transfer in different areas, serving as the external carrier for realizing modular mold step-by-step splicing operations.

[0065] The die head size refers to the physical specifications or effective working range of the mechanical components in the packaging processing equipment used to support the die or apply imprinting pressure. In this embodiment, the die head size defines the maximum die size that can be performed in a single imprinting operation. The maximum single-side size of the sub-die is adapted to this parameter, meaning that the sub-die can be completely accommodated within the working range of the equipment's die head for processing.

[0066] In some embodiments, the maximum dimension of a single side of the sub-mold is equal to or less than the die head size of the step-type embossing device.

[0067] The patterned surface of a sub-mold refers to the physical interface on the sub-mold that has an embossed or micro / nano structure, and this surface directly participates in the pattern transfer process. For example... Figure 1c As shown, in this embodiment, the surface is not a single plane, but is divided into "high-density interconnect area S4" and "peripheral interconnect area S5" according to functional requirements. The etched or formed concave and convex patterns on it directly correspond to the line routing and via positions of the redistribution layer to be prepared.

[0068] The high-density interconnect region S4 contains a fine line pattern for forming high-density signal traces inside the chip, and the feature size of the fine line pattern is in the nanometer scale.

[0069] The peripheral interconnection area S5 is located on the periphery of the high-density interconnection area and includes a widened wire pattern for forming an electrical interconnection with an adjacent sub-mold. The widened wire pattern extends to the boundary of the sub-mold and is used to form an overlapping interconnection with the corresponding wire pattern of the adjacent sub-mold.

[0070] The peripheral interconnect region has a feature size in the micrometer range, and the linewidth of the widened conductor pattern is greater than that of the fine line pattern.

[0071] The high-density interconnect region S4 refers to a specific area on the surface of the sub-mold pattern specifically designed for manufacturing the core functional area circuitry of the chip. This region is located at the center of the sub-mold or in the area corresponding to the chip's projection, and it integrates an extremely high-density interconnect structure. During the nanoimprinting process, the pattern in this region is transferred to the substrate, forming micro-lines and micro-vias that carry the chip's main signal transmission tasks.

[0072] For example, the high-density interconnect region S4 is a core area used to adapt to advanced process logic chips or high-bandwidth memory fan-out packages. Its surface is etched with a trench array with a feature size of nanometers. After these trenches are imprinted and metallized, they will form copper interconnect lines with a linewidth / spacing of less than 100nm to achieve high-density fan-out and signal reassembly of thousands of input / output pads inside the chip.

[0073] In some embodiments, the feature size of the high-density interconnect region can be as small as 10 nm.

[0074] A chip is a semiconductor device that serves as the core functional carrier in a packaging process. It is typically cut from a silicon wafer and integrates complex transistor circuits. In the context of this embodiment, the chip is the object served by the redistribution layer. Its surface has densely arranged input / output pads, which need to be brought out and rearranged through the lines formed by the high-density interconnect region S4.

[0075] High-density signals inside a chip refer to the large amount of data signals, address signals, or clock signals that need to be transmitted within a very small space during high-speed operation of the chip. These signals have extremely high requirements for impedance control, line width and spacing accuracy, and signal integrity of the transmission lines, and typically correspond to the tightly packed circuit patterns with extremely narrow line widths within the high-density interconnect area S4 on the sub-die.

[0076] Micro-line patterns refer to tiny relief structures (such as trenches or protrusions) etched onto the surface of the high-density interconnect region S4 of the sub-mold. These patterns, after being imprinted and metallized, will form actual metal wires. Their geometry is extremely fine, designed to meet the high wiring density requirements of modern integrated circuits, and is a key microstructure determining chip interconnect performance.

[0077] The characteristic dimension of a micro-line pattern refers to the smallest resolvable geometric parameter within that pattern, typically the minimum linewidth or minimum line spacing. This dimension represents the manufacturing precision and process resolution of the die, and is a core indicator of the processing difficulty of the high-density interconnect region S4. In this embodiment, this dimension is controlled within an extremely small range to accommodate the interconnect requirements of advanced process chips.

[0078] Nanoscale refers to lengths ranging from 1 nanometer to 100 nanometers. In this embodiment, the feature size used to describe a fine circuit pattern means that the width or spacing of the lines is extremely small (e.g., less than 100 nm). This scale requires extremely high resolution in die-making and imprinting processes to achieve sub-micron level circuit integration.

[0079] The peripheral interconnect area S5 refers to the functional area located around (edge ​​of) the high-density interconnect area S4 of the sub-mold. This area does not contain the microcircuits of the chip core, but mainly carries coarse-line patterns for splicing and transition. Its function is to act as a "bridge" or "interface" for electrical connections when multiple sub-molds are spliced ​​together, ensuring that current and signals can be transmitted across the physical boundaries of the sub-molds.

[0080] In some embodiments, the feature size of the peripheral interconnect region is in the range of 1-100 μm.

[0081] Adjacent sub-molds refer to other sub-molds that are physically adjacent to any other sub-mold (e.g., connected vertically, horizontally, or vertically) in the array arrangement of modular molds. When the splicing pattern area S1 is formed, the edge of any sub-mold needs to be closely aligned with the edges of these adjacent sub-molds, and the continuity of the pattern and electrical performance is achieved through the peripheral interconnection area S5.

[0082] Electrical interconnection refers to the process of establishing a low-resistance conductive path between different conductors, allowing current or electrical signals to pass smoothly. In this embodiment, it specifically refers to the design of the mold pattern so that the stamped metal circuit can cross the splicing gap of the sub-molds, achieving electrical conduction between the circuits formed by the two physically separated sub-molds and preventing signal interruption.

[0083] Widened conductor patterns refer to mold structures engraved on the surface of the interconnect area S5 around the sub-mold, with line widths significantly larger than the fine lines within the high-density interconnect area S4. This widening design aims to reduce line resistance, increase mechanical strength, and reduce sensitivity to splicing alignment accuracy. After imprinting, these patterns form wider metal conductors, serving as "trunks" or "terminals" for signal transmission.

[0084] Overlapping interconnection refers to a mechanism that achieves electrical connection through physical overlap or end-to-end tight contact. In this embodiment, it specifically refers to the widened conductor pattern of the current sub-mold extending to its boundary and overlapping or seamlessly connecting with the corresponding widened conductor pattern of the adjacent sub-mold at the splicing point. This design ensures that even with minor errors in the mold splicing, the two conductors can still maintain reliable electrical contact, thereby enabling signal transmission across molds.

[0085] Understandably, while widening the conductor pattern reduces precision, it significantly reduces the alignment difficulty and interconnect resistance at the sub-mold splicing points, ensuring the reliability of signal transmission across molds. Specifically, the peripheral interconnect area, acting as a "bridge" for signals crossing the sub-mold boundary, benefits from a widened conductor pattern, effectively increasing the "contact area" of the electrical connection. Even with micron-level alignment deviations during physical splicing of the sub-molds, the widened conductors maintain effective electrical contact, preventing open circuits or poor contact due to misalignment. Simultaneously, the widened conductor pattern offers lower resistance and higher current-carrying capacity, effectively reducing signal attenuation and voltage drop over long distances. It is particularly suitable as a power ground line or a high-speed signal backbone, concentrating expensive nanometer-level high-precision manufacturing capabilities in the high-density interconnect area of ​​the chip core to ensure chip performance. Meanwhile, the micron-level widening design at the splicing edges, where precision requirements are relatively lower, reduces mold manufacturing difficulty and significantly improves the overall production yield of large-area panel-level packaging.

[0086] In some embodiments, the sub-mold is a rectangular structure, and multiple sub-molds are arranged in an array in the horizontal and vertical directions;

[0087] The peripheral interconnection area is located on at least part of the side of the rectangular structure, and the widened wire pattern extends to the edge of the side to form a splicing interface;

[0088] When two adjacent sub-molds are spliced ​​together, the widened wire patterns on opposite sides overlap and interconnect at the splicing interface to form a conductive path that spans the boundary of the adjacent sub-molds.

[0089] In this context, a rectangular structure refers to the basic outline of a sub-mold in planar geometry, typically formed by four sides (two long sides and two short sides), with adjacent sides perpendicular to each other. In this embodiment, the use of a rectangular structure facilitates close tiling on the substrate or wafer surface, maximizing the utilization of the mold area and reducing space waste caused by splicing gaps. It is the basic unit form for realizing large-area array manufacturing.

[0090] The horizontal dimension refers to the dimension along the width direction (usually the X-axis) when sub-molds are arranged in a plane. In an array arrangement, the horizontal dimension defines the arrangement order of sub-molds in the horizontal direction, that is, the arrangement direction of each sub-mold in a row.

[0091] The longitudinal direction refers to the dimension along the length of the sub-mold when it is arranged in a plane (usually the Y-axis direction), and is perpendicular to the horizontal direction. In an array arrangement, the longitudinal direction defines the stacking order of the sub-molds in the vertical direction, that is, the arrangement direction of each sub-mold in a column.

[0092] Array arrangement refers to the orderly distribution of multiple sub-molds in a matrix (e.g., M rows × N columns) within a processing area according to predetermined horizontal and vertical rules. This arrangement allows multiple small-sized sub-molds to cover an ultra-large packaging substrate by repeating and extending, much like "laying floor tiles," thereby achieving large-area synchronous processing.

[0093] At least part of the side refers to one or more of the four boundaries of the rectangular sub-mold, or a specific segment on a certain side. In this embodiment, the peripheral interconnect area does not necessarily have to be distributed on all four sides, but is only set on specific sides that need to interact with adjacent molds (e.g., only on the left and right sides, or the top and bottom sides) according to the signal flow direction of the circuit design.

[0094] The edge of the side refers to the outermost boundary line of the physical entity of the sub-mold, that is, the interface where the sub-mold contacts adjacent sub-molds or the external environment. Widening the conductor pattern to this edge means that the circuit pattern is physically guided to the end of the mold, ready to cross the mold boundary.

[0095] A splicing interface refers to a specific area or functional interface located at the side edge of adjacent sub-molds, specifically designed for electrical connection and pattern transition. It is the concrete manifestation of the peripheral interconnection area at the physical boundary, containing the endpoints or extensions of widened conductor patterns for contact with the corresponding pattern on the other side when the mold is closed or spliced.

[0096] The boundary between adjacent sub-molds refers to the common dividing line or seam formed between two physically adjacent sub-molds (such as the left and right molds) in an array arrangement. This is a physical obstacle that signal transmission must overcome, and it is also an area where alignment errors are easily generated in the splicing process.

[0097] A conductive path refers to a continuous path made of conductive material (such as copper) that allows unimpeded flow of current or electrical signals after the metallization process is completed. In this embodiment, it specifically refers to connecting the lines on two sub-molds that were originally physically separated by a boundary through overlapping interconnection at the splicing interface, thereby forming a complete transmission line that crosses the boundary, is logically continuous, and is electrically conductive.

[0098] This can be understood as follows: by arranging multiple rectangular sub-molds in an array both horizontally and vertically, the limitations of a single sub-mold size can be overcome, covering the surface of an ultra-large substrate and meeting the requirements of panel-level packaging. The peripheral interconnect area is located on at least part of the sides and forms a splicing interface, allowing the widened conductor patterns of adjacent sub-molds to precisely overlap during splicing. This ensures a continuous and complete conductive path even when crossing physical boundaries, solving the problem of difficult large-size mask manufacturing. It utilizes multiple small-size, high-precision molds to splice together a large-size pattern through a "divide and conquer" approach. Simultaneously, the design of extending the widened conductor patterns to the side edges greatly increases the contact area for electrical connections between adjacent molds, ensuring effective overlap and interconnection even with minor mechanical alignment errors during splicing. This avoids open circuits or poor contact caused by misalignment, significantly improving the yield and stability of large-area splicing processes. Furthermore, the widened conductor pattern in the peripheral interconnect area has lower resistance and higher current-carrying capacity, making it suitable as a power, ground, or main signal line for cross-mold transmission. This not only ensures signal integrity across adjacent sub-mold boundaries and reduces transmission loss but also enhances the mechanical strength of the mold edge area, making the sub-mold more durable in multiple stamping cycles. Since the peripheral interconnect area is only located on "at least part of the sides" of the rectangular structure, designers can flexibly choose the direction of splicing and interconnection according to actual circuit wiring requirements. This modular array arrangement facilitates horizontal or vertical expansion according to product needs, offering extremely high design flexibility and production adaptability.

[0099] In some embodiments, the peripheral interconnection area is disposed around the four edges of the rectangular structure to form a closed splicing interface layout, so as to support the omnidirectional array splicing of sub-molds in the horizontal and vertical directions.

[0100] In some embodiments, the patterned surface of the sub-mold further includes a density compensation area, in which a virtual fill pattern electrically insulated from the widened conductor pattern or the micro-line pattern is provided.

[0101] The density compensation area refers to an auxiliary area specifically designated on the surface of the sub-mold pattern to adjust the local metal coverage. This area is usually located in sparsely distributed blank areas (such as gaps between peripheral interconnect areas or the edges of high-density interconnect areas), and its main function is to act as a "fill container" to accommodate virtual fill patterns in order to balance the graphic density distribution of the entire sub-mold surface.

[0102] Virtual fill patterns refer to tiny geometric structures (such as suspended metal blocks, grids, or dummy lines) placed within a density compensation zone that do not have actual circuit signal transmission capabilities. These patterns are electrically completely insulated from widened conductor patterns or micro-circuit patterns (i.e., they are in a floating state and not connected to power or ground). Their sole purpose is to provide uniform metal density support during physical manufacturing processes (such as electroplating and chemical mechanical polishing), thereby eliminating process defects caused by density differences.

[0103] Understandably, by setting density compensation areas and virtual fill patterns on the pattern surface of the sub-mold, the uniformity and stability of the manufacturing process can be effectively improved. Specifically, this design introduces virtual fill patterns that are electrically insulated from functional circuits into the originally sparse blank areas, balancing the metal density distribution on the pattern surface. This avoids problems such as uneven thickness and surface morphology fluctuations caused by excessively high or low local density in key process steps such as electroplating and chemical mechanical polishing. This not only significantly improves the flatness of the chip surface but also effectively prevents defects such as open circuits and short circuits caused by over- or under-polishing, thereby improving the yield and reliability of large-area panel-level packaging.

[0104] Meanwhile, the virtual fill pattern remains electrically insulated from the widened conductor pattern and the micro-circuit pattern, ensuring that it exists solely as a physical density compensation structure and does not interfere with the electrical performance of the circuit. This avoids risks such as signal crosstalk and increased leakage current, guaranteeing the normal operation of the chip. Furthermore, by rationally arranging the density compensation area, the stress distribution on the mold during the imprinting process can be optimized, reducing mold deformation or damage caused by localized stress concentration, further improving the stability of the manufacturing process and the mold's lifespan.

[0105] In some embodiments, the peripheral interconnect region, disposed around the periphery of the high-density interconnect region, includes a widened wire pattern for interconnecting with adjacent sub-dies, the widened wire pattern extending beyond the boundary of the sub-dies;

[0106] The widened guide pattern is configured to overlap with the corresponding pattern of the adjacent sub-mold at the splicing point of the step embossing in order to compensate for the alignment error.

[0107] Step embossing refers to a pattern transfer process that involves dividing the process into regions and repeating the process. In this process, a sub-mold successively embosses and exposes specific areas on the surface of the substrate. After completing one region, the substrate moves ("steps") to the next preset position and then performs the next embossing. By repeating this process multiple times, the entire pattern is finally stitched together on a large-area substrate.

[0108] The overlapping area refers to the region where two corresponding widened conductor patterns physically overlap and cover each other at the junction of adjacent sub-molds. This area forms the physical basis for electrical connections, ensuring the continuity of the conductive path.

[0109] Alignment error refers to the slight deviation between the actual and theoretically designed positions of adjacent sub-dies during the step-printing process, caused by mechanical movement, platform positioning, or environmental factors. This deviation can lead to pattern misalignment and affect the splicing quality.

[0110] Understandably, by setting a widened conductor pattern that extends beyond the boundary in the peripheral interconnect area and using it to form an overlap at the step-printing splice, alignment errors can be effectively compensated, significantly improving the reliability of splicing and the process window.

[0111] Specifically, this design allows the widened conductor pattern to extend beyond the physical boundaries of the sub-mold, actively reaching the splicing area. During the step-printing process, even if adjacent sub-molds experience minor alignment errors due to equipment precision limitations or environmental fluctuations, the two corresponding widened conductor patterns can still maintain stable physical contact and electrical connection through a pre-defined overlap. This "redundant design" avoids defects such as open circuits, reduced contact area, or increased resistance caused by misalignment, ensuring the integrity of signal transmission across the sub-mold boundaries. Simultaneously, the widened conductor pattern itself has lower resistance and higher current-carrying capacity, further enhancing the electrical performance and mechanical strength of the splicing area, providing a reliable guarantee for achieving high-yield, large-area panel-level packaging manufacturing.

[0112] In some embodiments, the widened conductor pattern includes an overlap extending to the side boundary of the sub-mold;

[0113] In a plurality of sub-molds, the overlapping portions of two adjacent sub-molds overlap at least partially in the splicing direction, and the overlap length of the overlapping portions is greater than the alignment accuracy of the packaging processing equipment, so as to form a continuous electrical path in the formed redistribution layer.

[0114] The mold side boundary refers to the outermost contour line of the sub-mold physical entity on the plane, which is the boundary line between the sub-mold pattern area and the external environment (such as adjacent molds or non-functional areas). In this embodiment, it is the extreme position of the widened wire pattern extension.

[0115] The overlapping section refers to the functional structural portion in the widened conductor pattern that extends intentionally beyond the side boundary of the sub-mold. This portion is used to form physical and electrical contact with the corresponding portion of the adjacent sub-mold during the splicing process.

[0116] The splicing direction refers to the relative movement or arrangement direction of adjacent sub-dies when they are joined together in a step-by-step repetitive embossing process. For rectangular array arrangements, the splicing direction is usually horizontal (X-axis direction) or vertical (Y-axis direction).

[0117] Overlap length refers to the linear distance by which the overlapping portions of two adjacent sub-molds intersect in the splicing direction. This parameter determines the contact area of ​​the splicing interface.

[0118] Packaging equipment refers to mechanical equipment used to perform semiconductor packaging processes, such as imprinters, lithography machines, and electroplating equipment. In this context, it specifically refers to high-precision manufacturing systems used to perform step-by-step imprinting and pattern transfer. For example, packaging equipment could be a step-by-step ultraviolet imprinter used for panel-level packaging. It uses a high-precision linear motor to drive a platform to imprint patterns from a sub-mold onto a substrate coated with photoresist, and uses a vision alignment system (such as a CCD camera) at the splicing points to make fine adjustments to ensure precise overlap of the overlapping parts.

[0119] Alignment accuracy refers to the highest positional repeatability and accuracy that packaging processing equipment can achieve when performing splicing or alignment operations, usually expressed in micrometers (μm). It reflects the minimum error range of the equipment when moving and positioning sub-molds.

[0120] Understandably, by setting an overlap length greater than the alignment accuracy of the packaging and processing equipment, a robust splicing mechanism with "self-fault tolerance" can be constructed.

[0121] Specifically, this technical solution utilizes the extension characteristics of the widened conductor pattern to create a physically redundant overlapping area between adjacent sub-molds. Because the overlap length is designed to be strictly greater than the inherent alignment accuracy error of the equipment, even under the most extreme processing deviations (i.e., one mold shifts to the left by a limit value, and the other to the right by a limit value), an effective physical overlap can still be maintained between the two overlapping portions. This design fundamentally eliminates the risk of open circuits caused by equipment accuracy limits, ensuring the electrical continuity of the rewire layer when crossing mold boundaries.

[0122] Furthermore, this "over-designed" overlap strategy not only ensures the reliability of electrical connections but also reduces contact resistance at the interface by increasing the contact area, thereby improving the integrity of power and signal transmission. Simultaneously, this solution is insensitive to equipment aging and environmental fluctuations, significantly relaxing stringent requirements for the production environment, thus improving yield and process stability in large-scale mass production.

[0123] For example, suppose the alignment accuracy of a certain packaging processing equipment is ±5μm (i.e., the total deviation may reach 10μm). In this embodiment, the overlap length of the widened conductor pattern is designed to be 6μm. When two adjacent sub-dies are joined, the theoretical total overlap length is 12μm. Even considering the worst-case alignment error (one die +5μm, the other -5μm), the actual remaining overlap length is still 2μm (12μm - 10μm). This remaining 2μm overlap is still sufficient to form a stable conductive path, thereby ensuring the continuity of the redistribution layer.

[0124] In some embodiments, the overlap length is from 0.5 μm to 20 μm. Preferably, the overlap length is from 1 μm to 10 μm.

[0125] In some embodiments, the overlap length is greater than twice the alignment accuracy of the mounted processing equipment. For example, when the alignment accuracy of the equipment is ±2 μm, the overlap length can be selected from 5 μm to 10 μm.

[0126] Understandably, setting the overlap length to be greater than twice the equipment alignment accuracy (e.g., designing >4μm when the accuracy is ±2μm) is to cope with the worst-case scenario of bidirectional error superposition. That is, when two adjacent sub-molds are offset by their limit values ​​in opposite directions, the remaining overlap can still ensure that the electrical path does not become open, providing necessary safety redundancy.

[0127] A wide range of 0.5μm-20μm: designed to be compatible with different manufacturing equipment capabilities from high-precision wafer level (small size) to large-size panel level (large size, significant thermal expansion and contraction).

[0128] The preferred range is 1μm-10μm: This is the "golden range" for mainstream panel-level packaging. It can provide sufficient contact area to reduce resistance, while avoiding excessive local metal density due to excessive overlap, thereby preventing surface morphology defects (such as depressions or protrusions) in subsequent grinding or electroplating processes.

[0129] In some embodiments, the overlapping portion includes a plurality of finger-shaped protrusions spaced apart along the splicing direction, with the finger-shaped protrusions of two adjacent sub-molds interleaved to form a mechanical interlocking structure, thereby enhancing the structural continuity and electrical reliability of the splice.

[0130] The splicing direction refers to the direction in which two adjacent sub-dies are joined and arranged during the step-printing or pattern transfer process. It is the reference axis that defines the direction of interconnecting lines and the geometry of the splicing interface.

[0131] Interval arrangement refers to multiple finger-shaped protrusions that are not connected continuously in the splicing direction, but are arranged sequentially according to a preset spacing, with gaps between adjacent protrusions, forming an array structure similar to comb teeth or fences.

[0132] Finger protrusions are protruding conductive structures with a specific aspect ratio that extend from the edge of the overlapping portion. They are usually rectangular, trapezoidal, or dovetail-shaped and are the basic units for achieving physical contact and signal transmission.

[0133] Interlacing refers to the finger-like protrusions of one sub-mold extending into the gap between adjacent sub-molds at the splicing interface, while the finger-like protrusions of the adjacent sub-molds also extend into the gap between the two sub-molds, interlocking and interlocking in space.

[0134] Mechanical interlocking structures refer to physical connection forms with shear and separation resistance, created through the aforementioned interlocking. This structure simulates gear meshing or tenon-and-mortise connections on a macroscopic or microscopic scale, resulting in a three-dimensional structural lock at the joint, rather than just planar contact.

[0135] Understandably, designing the overlap section with a mechanically interlocking structure featuring finger-like protrusions and staggered insertion significantly improves the structural strength of the splicing interface and the robustness of the electrical connection. Specifically, compared to a flat mating interface, the staggered design of the finger-like protrusions increases the effective contact perimeter and contact area at the splice, thereby reducing contact resistance and improving current carrying capacity. More importantly, this "mortise and tenon" mechanical interlocking structure effectively resists shear forces caused by thermal expansion and contraction of the substrate or subsequent process stress, preventing breakage or delamination at the splice. Furthermore, because the finger-like protrusions are spaced apart, they allow for the release of minor deformations to some extent, avoiding stress concentration problems that may occur with large-area solid metal connections, thereby further improving the reliability of the redistribution layer.

[0136] For example, assuming the splicing direction is horizontal (X-axis), the design of the overlapping section is similar to two combs interlocking: the overlapping edge of sub-mold A has three rectangular finger-like protrusions extending to the right (similar to comb teeth), each protrusion being 2μm wide and 5μm long, with a 2μm gap between them; the overlapping edge of sub-mold B has correspondingly three rectangular finger-like protrusions extending to the left, with the same dimensions as A. During splicing, the protrusions of sub-mold A precisely insert into the gaps of sub-mold B, while the protrusions of sub-mold B insert into the gaps of sub-mold A, forming a mechanical interlocking structure similar to "crossed fingers" gripping tightly. Even if there is a slight vertical (Y-axis) alignment error in the equipment (e.g., a vertical offset of 1μm), the long side (5μm) of the finger-like protrusions can still maintain a large area of ​​side contact, ensuring that current can be transmitted through the sidewalls, thereby ensuring uninterrupted signal transmission and preventing the structure from being easily broken.

[0137] In some embodiments, the peripheral interconnect area is provided with packaging alignment marks for splicing and aligning with adjacent sub-molds;

[0138] The encapsulation alignment marks include a first alignment mark and a second alignment mark arranged at intervals along the splicing direction;

[0139] The feature size of the first alignment mark is larger than that of the second alignment mark. The first alignment mark is used to provide a coarse alignment reference, and the second alignment mark is used to provide a fine alignment reference.

[0140] Among them, the packaging alignment mark is set in a specific graphic structure in the interconnection area of ​​the sub-mold, which serves as a reference point for visual or optical recognition and is used to detect and correct the relative positional deviation between adjacent sub-molds during step-printing or splicing.

[0141] The first alignment mark is the main positioning feature in the encapsulation alignment mark. It is usually designed as a large, easily recognizable graphic (such as a wide line or a large cross) to quickly lock the approximate position in the initial assembly stage.

[0142] The second alignment mark is a fine positioning feature in the package alignment mark. It is usually designed as a small, high-precision graphic (such as a fine line or grating structure) to perform micron or nanometer-level precise calibration after initial positioning.

[0143] The characteristic dimensions of the first alignment mark refer to its key geometric parameters, such as line width, overall span, or diameter. This dimension is typically large to ensure clear capture over a wide field of view.

[0144] The characteristic dimension of the second alignment mark refers to the key geometric parameter of the second alignment mark. This dimension is typically smaller (smaller than the first alignment mark) to provide higher positional resolution and sensitivity.

[0145] The coarse alignment reference is a positional reference standard established based on the first alignment mark. It is used to guide the equipment to make rapid and wide-range positional adjustments, eliminate large translation and rotation errors, and bring the mold into the capture range of fine alignment.

[0146] The precision alignment benchmark is a positional reference standard established based on the second alignment mark. It is used to guide the equipment to make high-precision adjustments with minute strokes, eliminate minor positional deviations, and ensure that the patterns at the splicing points meet extremely high overlay accuracy requirements.

[0147] Understandably, by setting first and second alignment marks with different feature sizes, a "coarse-to-fine" hierarchical alignment mechanism was constructed, which significantly improved splicing efficiency and final accuracy.

[0148] Specifically, the first alignment mark, with its larger feature size, possesses stronger noise resistance and a wider recognition tolerance, enabling the equipment to quickly identify the mold's orientation in the initial stage and rapidly eliminate large deviations at the millimeter or tens of micrometer level, preventing the equipment from getting "lost" or taking excessive time when searching for the mark. Building on this, the second alignment mark, with its smaller feature size and high-density arrangement, provides extremely high positional resolution, capable of detecting alignment errors at the nanometer level or even smaller. This hierarchical strategy not only avoids the contradiction between "recognition speed" and "alignment accuracy" that is difficult to balance when using only a single mark, but also effectively prevents the fine alignment mark from exceeding the field of view due to excessive initial deviation, thus significantly shortening the production cycle while ensuring high-precision splicing.

[0149] In some embodiments, such as Figure 1d As shown, the first alignment mark S7 of any sub-mold S6 engages with the second alignment mark S9 of the adjacent sub-mold S8, and the second alignment mark of any sub-mold engages with the first alignment mark of the adjacent sub-mold.

[0150] Understandably, the interlocking of the first and second alignment marks not only achieves visually assisted alignment but also utilizes the structure of the marks themselves to create physical limits. This design provides additional mechanical guidance at the splicing interface, preventing relative slippage of the sub-molds during imprinting or curing, thereby further ensuring the alignment accuracy and structural stability at the splicing point.

[0151] In some embodiments, the patterned structure of the peripheral interconnect region has a first height in a direction perpendicular to the surface of the sub-mold, and the patterned structure of the high-density interconnect region has a second height in a direction perpendicular to the surface of the sub-mold, wherein the first height is greater than the second height.

[0152] The peripheral interconnect pattern structure refers to the metal lines or conductive layers arranged around the non-display area (or logic area) of the sub-mold. These structures are typically used for signal transmission, power distribution, or as interfaces for external connections. They are usually characterized by wide line widths, large spacing, and low requirements for optical transmittance.

[0153] The sub-mold surface refers to the physical top surface of the sub-mold (or wafer / substrate), which is the base plane for the formation of the pattern structure. In a vertical cross-sectional view, it is usually used as the reference plane (Z=0) for measuring the height of the pattern structure.

[0154] The first height refers to the vertical distance that the pattern structure of the peripheral interconnect area extends upward from the surface of the sub-mold (i.e., the thickness or stacking height of the metal layer in that area).

[0155] The patterned structure of high-density interconnect regions refers to the conductive lines arranged in the core functional areas of sub-molds (such as pixel array areas or logic gate-dense areas). These structures have extremely high wiring density, extremely fine linewidth, and tiny spacing, designed to achieve complex signal interconnections.

[0156] The second height refers to the vertical distance from the surface of the sub-mold where the patterned structure of the high-density interconnect area extends upwards.

[0157] For example, in the manufacturing process of semiconductor packaging or display panels, the high-density interconnect region—located in the pixel array area at the center of the chip—has a very thin metal layer (second height) designed to accommodate millions of pixels and fine signal lines, for example, 0.3 μm thick, to prevent short circuits between fine lines and ensure surface flatness. The peripheral interconnect region—located in the fan-out area or pad area at the edge of the chip—has wider lines and mainly serves for high current transmission or mechanical support. To reduce resistance and provide sufficient mechanical strength, the metal layer (first height) in this region is designed to be 0.5 μm or thicker. On the same sub-mold surface, the pattern structure of the peripheral interconnect region is 0.2 μm higher than that of the high-density interconnect region.

[0158] It is understandable that by designing the first height of the peripheral interconnect pattern structure to be greater than the second height of the high-density interconnect pattern structure, the dual effects of functional customization and yield optimization are achieved.

[0159] Specifically, in the high-density interconnect region, the thinner pattern structure (second height) helps maintain extremely high aspect ratio control, preventing line collapse or bridging (short circuits) during etching, thus ensuring the resolution and yield of fine lines. In the peripheral interconnect region, the thicker pattern structure (first height) effectively reduces line resistance, improves high-current carrying capacity, and increases the mechanical strength of the metal layer, making it more resistant to mechanical stress during subsequent cutting, packaging, or probe testing, reducing the risk of breakage. This differentiated height design breaks the limitation of uniform metal thickness across the entire board in traditional processes, achieving optimal performance in each area.

[0160] In some embodiments, the patterned surface of the sub-mold further includes a transition region disposed between the high-density interconnect region and the peripheral interconnect region;

[0161] The linewidth of the conductor pattern in the transition region gradually decreases in a stepped or linear manner from the outer interconnect region to the high-density interconnect region.

[0162] And / or, the pattern height in the transition zone gradually decreases from the first height to the second height in a sloping manner.

[0163] The transition zone refers to the buffer area set on the surface of the sub-mold pattern, located between the high-density interconnect area and the peripheral interconnect area. This transition zone acts as a "bridge" between two different pattern features (such as line width, height, and density), enabling a smooth transition of geometric parameters and avoiding drastic changes in physical form.

[0164] For example, the conductor pattern on the surface of the sub-mold is divided into a peripheral interconnect region, a transition region, and a high-density interconnect region from left to right. Regarding the planar gradient treatment of the linewidth, the peripheral interconnect region maintains a wide linewidth of 10μm to carry high current, while the high-density interconnect region uses a thinner linewidth of 2μm to meet the requirements of high-density wiring. In this architecture, the transition region acts as a crucial buffer; its internal conductors do not abruptly change from 10μm to 2μm, but rather undergo a morphological transformation through a stepped or multi-segment linear tapered structure. For example, the linewidth can gradually shrink in a stepped manner from 10μm, 6μm, 4μm to 2μm, or present as a continuous linear taper. This gradient design allows the conductor width to decrease gradually within a specific transition distance, effectively achieving a seamless transition from wide to thin lines.

[0165] Understandably, the core purpose of setting transition regions and employing gradient designs in linewidth or height is to eliminate the physical risks caused by geometric abrupt changes, thereby improving device reliability and manufacturing yield. If the linewidth or height undergoes a right-angle abrupt change (such as from wide to narrow or from high to low), stress concentration points will form at the abrupt change, easily leading to circuit breakage during thermal expansion or mechanical bending. Simultaneously, electrically, abrupt changes in cross-section can cause a sudden surge in current density (forming hotspots) or electric field concentration, increasing the risk of electromigration. The gradient structure of the transition region (whether stepped or sloping) allows for a gradual release of current density and mechanical stress, significantly reducing the probability of open-circuit or short-circuit failures. In photolithography and etching processes, drastic changes in pattern density can lead to a "loading effect," resulting in uneven development or etching rates and the formation of depressions or bumps. The transition region, acting as a buffer against density changes, can effectively balance local pattern density, improve the uniformity of photoresist coating and the consistency of etching, thereby enhancing the overall pattern formation quality. For high-speed signal transmission, abrupt changes in conductor geometry can cause impedance discontinuities, leading to signal reflection and noise. A linear or stepped transition in the transition region helps maintain the continuity of impedance changes, reduces signal reflection, and ensures the stability of signal transmission.

[0166] In some embodiments, the peripheral interconnect region is configured to form a low-resistance interconnect structure in the imprinted redistribution layer to form a raised support platform in the peripheral interconnect region, thereby improving the mechanical strength of the splice.

[0167] The difference between the first height and the second height is configured such that during the imprinting process, the peripheral interconnect area preferentially contacts the imprinting adhesive and forms a thickened conductive layer.

[0168] Low-resistance interconnect structures refer to conductive paths with a large cross-sectional area (determined by a larger initial height and wider linewidth) formed in the peripheral interconnect area. Since resistance is inversely proportional to the cross-sectional area of ​​the conductor, this thickened and widened metal structure can significantly reduce the sheet resistance and overall impedance of the circuit. It is mainly used for power transmission, grounding, or high-current signal transmission to ensure extremely low voltage drop and loss in electrical connections at the package or panel edges.

[0169] A supporting platform refers to a physical raised platform structure formed in the peripheral interconnect area relative to the high-density interconnect area due to the first height being greater than the second height. Viewed in vertical cross-section, the peripheral interconnect area rises like a "platform." This structure not only serves as an electrical layer but also physically acts as a "reinforcing rib" or "support column," capable of withstanding external mechanical stress and preventing collapse or deformation of the edge areas during processing or assembly.

[0170] Understandably, by utilizing the difference between the first and second heights, a "contact priority" mechanism is cleverly introduced into the embossing process, thereby achieving a dual improvement in electrical performance and mechanical strength.

[0171] Specifically, during the imprinting process, because the peripheral interconnect area has a higher initial height, the mold preferentially contacts and compresses the imprinting adhesive (or photoresist) in this area. This preferential contact allows the peripheral area to form a thicker metal deposition base or directly form a thicker conductive layer. This thickened design directly constructs a low-resistance interconnect structure, greatly improving the ability of the peripheral circuits to carry high currents and reducing heat generation and signal attenuation problems caused by excessively thin or narrow circuits.

[0172] Meanwhile, the supporting platform structure formed by this height difference physically enhances the mechanical rigidity at the splicing interface. When the sub-molds are spliced ​​or subsequently subjected to encapsulation stress, these raised platforms can serve as the main stress-bearing support points, effectively dispersing shear and tensile forces and preventing the delicate circuitry at the splicing point from breaking due to uneven stress. In short, this design makes the outer area both conductive and durable, ensuring signal transmission quality while acting as a robust outer shell protecting the delicate internal structure.

[0173] In summary, the embodiments of this application can complete the high-precision imprinting of large-size panel-level redistribution layers in one go, effectively breaking through the physical size limitation of the single exposure field of traditional photolithography equipment, facilitating the large-scale production of large-area, high-density interconnect structures, improving packaging efficiency and yield, and reducing the manufacturing cost of advanced packaging processes.

[0174] To better implement the above methods, embodiments of this application also provide a method for manufacturing a modular mold for preparing a redistribution layer. This method is used to prepare any of the modular molds provided in the embodiments of this application, such as... Figure 2 As shown, the method includes:

[0175] 201. Provide at least one main template and a substrate to be processed, wherein the main template has an embossed structure corresponding to the surface of the sub-mold pattern, the embossed structure including a high-density interconnect area pattern and a peripheral interconnect area pattern located on the periphery.

[0176] In this context, the master mold refers to a template mold (typically made of hard materials such as silicon, nickel, or quartz) with a micro-nano scale relief structure. It serves as the source for pattern replication, its surface structure being a "mirror image" or "negative" of the sub-mold pattern surface. It is used to transfer patterns in batches onto the substrate to be processed through processes such as embossing, hot pressing, or photolithography. In this context, the master mold is specifically used to manufacture sub-molds containing high-density interconnect regions and peripheral interconnect regions.

[0177] It should be noted that the geometric shapes of the main mold and the sub-mold at the contact and imprinting interface (i.e., the pattern surface) are in a reverse complementary relationship: the "convex" of the main mold generates the "concave" of the sub-mold, and the "concave" of the main mold generates the "convex" of the sub-mold.

[0178] At least one master template constitutes a complete set of templates required for the imprinting preparation of modular molds, wherein a single master template in the set is configured to carry local patterned areas of high-density interconnect regions and / or peripheral interconnect regions.

[0179] The substrate to be processed refers to the carrier platform that has not yet formed the final circuit pattern. It can be a glass substrate, silicon wafer, ceramic substrate, or flexible polymer film, etc. This substrate will form the desired relief structure on its surface through physical or chemical action by contacting the master mold, or it will be directly cured and molded.

[0180] High-density interconnect pattern refers to the micro-relief structure on the surface of the master mold used to form high-density interconnect areas (such as pixel arrays and logic operation areas) of the sub-mold. This pattern has extremely high wiring density, extremely fine linewidth (such as less than 2μm), and tiny spacing, and usually corresponds to a thinner metal layer (second height) on the sub-mold. Physically, it manifests as fine grooves or micro-boobs, designed to replicate a precision circuit network capable of complex signal transmission and device interconnection on the sub-mold through an imprinting process.

[0181] The peripheral interconnect pattern refers to the macroscopic relief structure on the surface of the main mold used to form the peripheral interconnect areas (such as fan-out areas, pad areas, and edge interfaces) of the sub-mold. This pattern has a wide linewidth (e.g., 10μm or more) and a large spacing, typically corresponding to a thicker metal layer (first height) on the sub-mold. Physically, it manifests as wide grooves or bumps, designed to create a "platform" structure on the sub-mold with low resistance, high mechanical strength, and support through an imprinting process, for carrying high currents or providing mechanical protection during packaging.

[0182] The relief structure refers to the three-dimensional morphology of the main template surface, characterized by raised or recessed areas. It includes high-density interconnect patterns (such as fine wiring trenches) corresponding to the functional requirements of the final product, and peripheral interconnect patterns (such as wider electrodes or connectors). This structure is the key physical basis for subsequent pattern replication (such as embossing deformation and metal filling).

[0183] Understandably, by providing a master template with a specific relief structure and a substrate to be processed, a highly efficient and high-precision pattern replication infrastructure has been established.

[0184] Specifically, by directly molding the substrate using the relief structure on the master mold, rapid mass replication of micro- and nano-scale features can be achieved, significantly improving production efficiency and reducing manufacturing costs. The relief design on the master mold, distinguishing between high-density interconnect areas and peripheral interconnect areas, ensures that composite structures with different functional requirements can be simultaneously constructed in a single imprinting or molding process—guaranteeing high-precision wiring capabilities in the core area while achieving strong mechanical support and low-resistance connections in the peripheral area. This direct physical transfer method avoids the complex mask alignment and multiple exposure steps of traditional photolithography processes, greatly improving the fidelity and consistency of pattern transfer, and providing a solid technical guarantee for manufacturing high-performance, high-reliability integrated devices.

[0185] 202. Apply UV-curable imprinting adhesive to the surface of the substrate to be processed.

[0186] Among them, UV-curable imprinting adhesive refers to a liquid photosensitive polymer material (such as acrylate, vinyl ether, or epoxy resin) coated on the surface of the substrate to be processed and specifically used for nanoimprint lithography. This material has the characteristics of low viscosity, high light transmittance, and rapid curing, and can fill the micro-nano gaps of the relief structure of the master template at room temperature; after being irradiated with ultraviolet light of a specific wavelength (such as 365nm), the photoinitiator inside is activated and initiates a polymerization reaction, causing the material to instantly crosslink and solidify from a liquid state into a solid polymer, thereby "freezing" the relief pattern on the master template and replicating it on the substrate surface with high fidelity, forming the required nanoscale microstructure.

[0187] 203. According to the preset array arrangement order, control at least one main template to perform multiple imprinting and stepping movements relative to the substrate to be processed; wherein, in the splicing area of ​​two adjacent imprinting operations, alignment is performed based on the position of the peripheral interconnect area pattern, so that the peripheral interconnect area pattern formed by the current imprinting at least partially overlaps with the peripheral interconnect area pattern formed by the previous imprinting in the splicing direction.

[0188] The preset array arrangement sequence refers to the logical sequence of the movement path of the master mold relative to the substrate to be processed and the number of imprinting operations in the step-over imprinting process. This sequence is usually determined based on the matching relationship between the size of the target mold and the size of the master mold, such as using raster scanning (from left to right, from top to bottom) or a serpentine scanning path. It specifies the exact position of each imprinting operation in the substrate coordinate system, ensuring that the patterns formed by multiple imprinting operations can be combined into a complete array according to predetermined geometric rules (such as close arrangement or specific spacing).

[0189] Two adjacent imprinting operations refer to two imprinting steps that are consecutive in time and spatially adjacent during the step imprinting process following the above array arrangement sequence. Specifically, it is the "Nth imprint" and the immediately following "N+1th imprint". Between these two operations, the master mold will undergo a cycle of "molding removal - stepping movement - alignment - pressing". The projection areas of the two on the substrate usually overlap to some extent, which is a key step pair that determines the continuity of pattern splicing.

[0190] The splicing region refers to the strip or strip-shaped area on the substrate where the current imprinting field (N+1th imprinting) and the previous imprinting field (Nth imprinting) geometrically overlap in two adjacent imprinting operations. Within this region, the newly imprinted peripheral interconnect pattern spatially coincides with the already cured peripheral interconnect pattern. This region is the core area for visual or mechanical alignment using the peripheral interconnect pattern as a "reference mark," aiming to achieve continuity of circuit connections or seamless connection of mechanical structures through the physical overlap of patterns, eliminating splicing gaps between fields.

[0191] In some embodiments, when at least one master template is single, the master template is controlled to perform multiple imprinting and stepping movements relative to the substrate to be processed according to a preset array arrangement order, thereby repeatedly replicating the same pattern on the substrate.

[0192] In some embodiments, when there are multiple master templates and the multiple master templates have the same relief structure, the multiple master templates are used to simultaneously or stepwise imprint the substrate to be processed, so as to improve the throughput of pattern reproduction.

[0193] In some embodiments, when there are multiple master molds with different relief structures, each master mold is controlled to imprint on the corresponding area of ​​the substrate to be processed, so as to realize the combination and splicing of different pattern areas to construct a modular mold with composite functions.

[0194] 204. After each imprint, the UV-curable imprinting adhesive is cured by UV exposure.

[0195] In nanoimprint lithography, UV curing refers to the photophysical-chemical process where, after the embossed structure of the master mold is pressed into and filled with UV-curable imprinting adhesive, the imprinted area is irradiated with UV light of a specific wavelength (e.g., 365nm). During this process, UV light penetrates the transparent master mold (e.g., quartz) and irradiates the imprinting adhesive, exciting the photoinitiator within the adhesive to generate free radicals or cations, initiating a rapid cross-linking polymerization reaction between monomers and oligomer molecules. This process instantly transforms the imprinting adhesive from a liquid or viscous state to a solid polymer at room temperature, thereby "freezing" and permanently shaping the micro / nano patterns on the master mold, forming a cured layer with a specific three-dimensional morphology.

[0196] 205. After completing all step-by-step imprinting, separate the main mold and form a splicing pattern area on the substrate to be processed, which consists of multiple arrayed sub-molds.

[0197] In summary, by employing a master mold with a specific relief structure and combining it with a step-and-repeat imprinting process, high-precision integrated molding of redistribution layers for large-area panel-level packaging has been achieved. Specifically, this method utilizes the peripheral interconnect pattern on the master mold as a splicing alignment reference, achieving at least partial overlap in the splicing area between adjacent imprints. This design enables the formation of a seamless splicing pattern area composed of multiple sub-mold arrays on the substrate to be processed after separating the master mold. This effectively overcomes the physical size constraints of the single exposure field of view (typically only 26mm × 33mm or smaller) of traditional photolithography equipment, making it possible to complete the patterning of large-size panel-level (such as a whole glass substrate or a large wafer) in one go. Through modular step-and-repeat imprinting, the cumulative error of multiple mask alignments is avoided, and the overlapping design of the peripheral interconnect area ensures electrical continuity and mechanical strength at the splicing point, significantly improving the production efficiency and product yield of redistribution layers in advanced packaging processes. This method does not rely on expensive ultra-large field-of-view projection lithography machines. It can achieve large-scale replication of high-density interconnect structures through low-cost ultraviolet curing imprinting technology, which greatly reduces the manufacturing cost of advanced packaging processes and provides a practical technical path for the commercial production of high-density, large-area integrated circuits.

[0198] To better implement the above methods, this application also provides a mass production mold for preparing a packaged redistribution layer, such as... Figure 3As shown, the mass production mold is replicated from the modular mold S10 provided in the embodiments of this application;

[0199] Mass production molds are used to fabricate single interconnect layers in multilayer interconnect structures of integrated circuits. These single interconnect layers integrate via interconnect structures and wiring interconnect structures.

[0200] The mass production mold has a splicing pattern area that is larger than the field of view of a single processing, and the splicing pattern area is formed by multiple sub-mold units arranged in an array.

[0201] The surface relief pattern of each sub-mold unit includes an integrated through-hole forming area and a wiring forming area, which are used to simultaneously form through-hole cavities and wiring trenches within the dielectric material layer in a single imprinting process.

[0202] The sub-mold unit has a peripheral interconnect area on its periphery. The peripheral interconnect area includes a widened wire pattern and a package alignment mark. The widened wire pattern extends to the boundary of the sub-mold unit and is used to form an overlap interconnect with the corresponding wire pattern of the adjacent sub-mold unit to form a continuous through-hole-wiring interconnect structure after metal backfilling and chemical mechanical polishing.

[0203] The mass production mold is used as the Nth stage mold in the multilayer stacking process of integrated circuits. It performs step-by-step imprinting on the already formed N-1 via-wiring interconnect layer through substrate alignment to construct the Nth via-wiring interconnect layer, where N is an integer greater than or equal to 2.

[0204] Among them, the mass production mold S11 refers to a mold specifically designed for large-scale industrial production, prepared by using the aforementioned "modular mold" as a master template (main mold) through replication processes (such as electroforming or hot stamping). This mold already possesses the complete pattern structure required for the final product and is directly applied to the stamping process in integrated circuit manufacturing to mass-produce single-layer interconnect layers. Compared to laboratory-grade master templates, mass production molds place greater emphasis on process stability, wear resistance, and adaptability to large-scale production.

[0205] A single-layer interconnect layer refers to an independent functional layer in a multilayer interconnect structure of an integrated circuit, formed by a complete imprinting, curing, and subsequent metallization process. This layer integrates two basic structures: vertical connection and horizontal routing. It is responsible for the lateral transmission of electrical signals within this layer and for vertical communication with adjacent upper or lower interconnect layers through the vias. It is the basic unit for building three-dimensional circuit networks.

[0206] A via interconnect structure S12 refers to a conductive channel structure (usually formed by metal filling) that runs vertically through a dielectric material layer, used to connect wiring layers at different stack-up heights. In this context, it is a component of a "single-layer interconnect layer" and together with the "wiring interconnect structure" constitutes a circuit network in a two-dimensional plane.

[0207] The wiring interconnect structure S13 refers to a conductive line structure (such as a metal trace) extending horizontally on the surface or inside a dielectric material layer, used to connect different devices, vias, or pads within the same layer. It works in conjunction with "via interconnect structures" to achieve complex signal routing and power distribution within the chip.

[0208] A sub-mold unit refers to the smallest independent functional block on the surface of a "mass production mold" divided by the splicing pattern area. It corresponds to the sub-mold in the aforementioned "modular mold," and its surface has a complete relief pattern (including through-hole forming area and wiring forming area). During the imprinting process, each sub-mold unit is responsible for forming a complete circuit pattern in the corresponding area of ​​the substrate.

[0209] The spliced ​​pattern area refers to the ultra-large pattern area formed by splicing multiple step-by-step imprintings on the surface of the mass production mold. The area of ​​this region is significantly larger than the processing field of view (field of view) of a single imprinting device. It is formed by seamlessly or overlapping multiple arrayed "sub-mold units" and aims to achieve patterning at the large-area panel level or the entire wafer level.

[0210] The through-hole forming area refers to the region on the surface of the "sub-mold unit" specifically designed to form through-hole structures within the embossed pattern. During the imprinting process, the raised or recessed structures in this area create through-hole cavities within the dielectric material layer, which are subsequently filled with metal to become conductive through-holes.

[0211] The wiring forming area refers to the region on the surface of the "sub-mold unit" specifically designed to form wiring structures within the embossed pattern. During imprinting, the specific embossed morphology of this area forms wiring trenches in the dielectric material layer, which are subsequently transformed into conductive wiring after metallization.

[0212] A through-hole cavity refers to a vertically oriented hole-like space or recessed structure imprinted inside the dielectric material layer by a "through-hole forming area" during the imprinting process. It is the "prototype" of a through-hole interconnect structure and is hollow before being filled with metal.

[0213] Wiring trenches refer to horizontal groove-like structures imprinted on or inside the surface of a dielectric material layer by a "wiring forming area" during the embossing process. They are the "prototype" of wiring interconnect structures, existing as trenches embedded in the dielectric before being filled with metal.

[0214] It is understood that the mass production mold provided in this application, by adopting a splicing pattern area formed by an array of multiple sub-mold units, effectively breaks through the physical size limitation of the single exposure field of traditional photolithography equipment, making it possible to complete the high-precision imprinting of large-size panel-level redistribution layers in one go.

[0215] Specifically, the through-hole forming area and wiring forming area integrated on the surface of each sub-mold unit can simultaneously form through-hole cavities and wiring trenches in a single imprinting process, greatly simplifying the manufacturing process of multi-layer interconnect structures. Meanwhile, the peripheral interconnect area around the sub-mold unit, through the overlapping interconnect design of the widened wire pattern, ensures that the splicing area forms a continuous, low-impedance through-hole-wiring interconnect structure after metal backfilling and chemical mechanical polishing, eliminating the risk of open circuit caused by splicing gaps.

[0216] It should be noted that by utilizing modular molds to replicate multiple mass-production molds, this technical solution not only achieves large-area, high-density interconnect structures on a large scale, but also ensures excellent alignment accuracy and manufacturing yield during multi-layer stacking by relying on high-precision substrate alignment and step-by-step imprinting processes. Furthermore, this modular mold-based mass-production mold design fundamentally reduces the need for ultra-large field-of-view masks, thereby significantly reducing the manufacturing cost of advanced packaging processes and providing a practical technical path for promoting the industrial application of panel-level packaging and high-density interconnect technologies.

[0217] In summary, the embodiments of this application improve packaging efficiency and yield, and reduce the manufacturing cost of advanced packaging processes.

[0218] To better implement the above methods, embodiments of this application also provide a method for manufacturing a mass production mold for preparing a packaged redistribution layer, such as... Figure 4 As shown, this method is used to prepare the mass production mold provided in the embodiments of this application. The method includes:

[0219] 401. Provide a modular mold as a master mold according to any of the embodiments provided in this application.

[0220] In this context, the master mold refers to the original mold used as the basis in the mold replication process (i.e., the "modular mold"). It has a high-precision surface relief pattern, which is used to transfer the pattern to a cured material layer, thereby replicating a child mold with a complementary structure (i.e., the "mass production mold"). In this context, the master mold is the "source" of the pattern, determining the structural precision and functional characteristics of the subsequent mass production mold.

[0221] 402. A substrate is provided, and a curing material layer is formed on the surface of the substrate.

[0222] The substrate refers to the basic platform used to support and carry the cured material layer. It provides physical support for the mold replication process, ensuring the stability of the cured material layer during imprinting and curing, and ultimately forming a complete mass production mold together with the cured structure. The substrate must have good flatness, thermal stability, and mechanical strength.

[0223] The cured material layer refers to a functional material layer coated on the surface of a substrate that is fluid and can be cured by external energy (such as ultraviolet light or heat). During the imprinting process, it fills the relief structure of the master mold; after curing, it forms an imprinted structure that complements the pattern of the master mold, ultimately constituting the functional layer of the mass production mold.

[0224] 403. Press and bond the master mold to the substrate to transfer the relief pattern on the surface of the master mold to the curing material layer. The relief pattern includes an integrated through-hole forming area and a wiring forming area.

[0225] The through-hole forming area refers to the region in the relief pattern on the surface of the master mold specifically designed to form vertical interconnecting channels. During the imprinting process, the specific morphology of this area will form corresponding recessed or raised structures in the cured material layer, which will then be replicated and transformed into the through-hole cavity forming structure in the mass production mold.

[0226] The wiring forming area refers to the region on the surface of the master mold specifically designed to form horizontal wiring paths within the embossed pattern. During the imprinting process, the linear embossing in this area forms corresponding grooves or ridges in the cured material layer, which are then replicated and transformed into wiring groove forming structures in the mass production mold.

[0227] 404. The solidified material layer is cured, and the master mold is separated from the substrate to form a mass production mold with an embossing structure that complements the relief pattern;

[0228] The embossed structure has a peripheral interconnection area on its periphery, which includes a widened wire pattern that extends to the boundary of the sub-mold unit and is used to form an overlapping interconnection with the corresponding wire pattern of the adjacent sub-mold unit.

[0229] The cured material layer refers to a functional material layer coated on the substrate surface that is fluid and can be cured by external energy (such as ultraviolet light or heat). During the imprinting process, it fills the relief structure of the master mold; after curing, it forms an imprinted structure that complements the pattern of the master mold, ultimately constituting the functional layer of the mass production mold.

[0230] An embossed structure refers to the final patterned structure formed on a substrate after the cured material layer is embossed, cured, and separated from the master mold. It is the "negative image" of the master mold's relief pattern, directly constituting the functional surface of the mass production mold, and is used for subsequent embossing of the dielectric material layer.

[0231] In summary, by using modular molds as master molds for high-precision replication, a mass-production mold with a large-size splicing pattern area was successfully manufactured. This mass-production mold integrates a single relief pattern for the through-hole forming area and the wiring forming area, and ensures reliable overlapping and interconnection of adjacent sub-mold units at the splicing points through the widened wire pattern design of the peripheral interconnection area.

[0232] This technical solution makes it possible to complete the high-precision imprinting of large-size panel-level redistribution layers in a single operation using this mass production mold, effectively overcoming the physical size limitations of the single-exposure field of view of traditional photolithography equipment. Simultaneously, this method facilitates the large-scale production of large-area, high-density interconnect structures. It not only improves packaging efficiency and yield through a simplified process flow but also significantly reduces the manufacturing cost of advanced packaging processes by decreasing reliance on expensive, ultra-large field-of-view masks. This provides a practical solution for the industrial application of panel-level packaging and high-density interconnect technologies.

[0233] To better implement the above methods, this application also provides an application of a mass production mold for preparing a redistribution layer in chip packaging. The mass production mold is the one provided in this application, and it has a peripheral interconnect area and a widened wire pattern. The widened wire pattern is used to form an overlap interconnect with the corresponding wire patterns of adjacent sub-mold units, such as... Figure 5a and Figure 5b As shown; the application includes:

[0234] By using a step-printing process, a multi-layer interconnect structure for integrated circuits is constructed on a packaging substrate or chip. The multi-layer interconnect structure for integrated circuits includes at least one single-layer interconnect layer that integrates through-hole interconnect structure and wiring interconnect structure.

[0235] In the fabrication of a single interconnect layer, a mass production mold is used for a single imprinting process to simultaneously form via cavities and wiring trenches within the dielectric material layer. Subsequently, a conductive via-wiring interconnect layer is formed through metal backfilling and chemical mechanical polishing processes.

[0236] The step-printing process refers to a cyclical manufacturing process of "printing-movement-alignment-re-printing" used when patterning large-size substrates using mass production molds. Since the size of the mass production mold (or the field of view of a single print) is smaller than the total area of ​​the target panel, this process controls the precise step-movement of the mold or substrate to transfer the embossed pattern on the mold surface to the substrate in sections and repeatedly. In this application, the process specifically utilizes the widened conductor patterns on the edge of the mold for overlapping interconnection, allowing multiple independent areas formed by step-printing to ultimately be spliced ​​into a continuous and complete large-area circuit network.

[0237] The packaging substrate S14-1 refers to the base material board used to carry the chip and provide electrical connections and mechanical support. In advanced packaging technologies such as fan-out packaging, it usually refers to the reconstituted wafer or panel carrier, on which the chip (Known Good Die, KGD) is embedded or mounted as the underlying base for subsequent construction of the redistribution layer (RDL).

[0238] Chip S14-2 refers to a semiconductor core device (Die) containing specific circuit functions and is the main object of packaging. In the application scenario of this application, the chip is the source of signal processing and transmission, and its surface pads need to be led out and redistributed through the subsequently formed interconnect structure to achieve connection with external circuits.

[0239] The multilayer interconnect structure S15 refers to a three-dimensional conductive network constructed between the chip and the packaging substrate, or on the chip surface. This structure is composed of multiple layers of insulating dielectrics (dielectric layers) and interlayer conductive pathways, used to achieve complex signal routing, power distribution, and expansion of input / output (I / O) ports. In this application, this structure specifically refers to the high-density interconnect system formed by mass production molding as described in this application.

[0240] Through-hole interconnects refer to conductive channels (such as metal-filled holes) that penetrate the dielectric layer along the vertical direction (Z-axis) in a multilayer interconnect structure. Their function is to connect horizontal wiring at different levels, enabling vertical transmission of electrical signals between different circuit layers; they are a key "bridge" for constructing three-dimensional circuit networks.

[0241] Wiring interconnects refer to conductive traces (such as metal traces) extending horizontally (XY plane) in a multilayer interconnect structure. Their function is to connect different vias, pads, or devices within the same layer, enabling lateral signal transmission and logical connections.

[0242] A single-layer interconnect layer S16 refers to an independent hierarchical unit constituting an "integrated circuit multilayer interconnect structure". In this application, the single-layer interconnect layer has the characteristic of high integration, that is, it simultaneously includes through-hole interconnect structures and wiring interconnect structures in the same process step. It is a complete conductive functional layer formed on a dielectric material layer through a single imprinting, curing, metal backfilling and planarization process.

[0243] Through-hole wiring interconnect layer 17.

[0244] Understandably, during mass production, a first imprint layer mass production mold is used to imprint and form the first structural layer. After backfilling with metal, chemical mechanical polishing is performed to obtain the first via-wiring layer. Subsequently, the substrate-second imprint layer mass production mold is used for alignment and imprinting to form the second structural layer. After backfilling, chemical mechanical polishing is performed to obtain the second via-wiring layer. The above steps are repeated until the Nth via-wiring layer is processed, resulting in the final multilayer wiring layer structure.

[0245] This application, through the splicing design of nanoimprint substructures, fully utilizes the high precision, three-dimensional structural compatibility, large imprint area, and panel-level size compatibility of nanoimprint technology, solving the problems of mask splicing, substrate utilization, and production capacity in RDL layer processing in advanced packaging. By splicing high-precision structures and large-size wiring structures in the same photomask layer, the separate processing and embedding of silicon bridge structures in traditional advanced packaging processes are avoided, resulting in greater economic benefits.

[0246] In summary, the embodiments of this application improve packaging efficiency and yield, and reduce the manufacturing cost of advanced packaging processes.

[0247] The above provides a detailed description of a modular mold for preparing a redistribution layer and its application, as provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A modular mold for fabricating a redistribution layer, characterized in that, The modular mold has a splicing pattern area larger than the field of view in a single processing step. This splicing pattern area is formed by multiple sub-molds arranged in an array. The pattern of the splicing pattern area corresponds to the via-wiring interconnect structure of the integrated circuit redistribution layer. The maximum dimension of a single side of each sub-mold is adapted to the mold head size of the packaging processing equipment. The patterned surface of the sub-mold includes: The high-density interconnect region includes a micro-line pattern for forming high-density signal traces inside the chip, the feature size of which is on the nanometer scale. The peripheral interconnection area, located around the high-density interconnection area, includes a widened wire pattern for forming an electrical interconnection with an adjacent sub-mold. The widened wire pattern extends to the boundary of the sub-mold and is used to form an overlapping interconnection with the corresponding wire pattern of the adjacent sub-mold. The peripheral interconnect region has a feature size in the micrometer range, and the line width of the widened conductor pattern is greater than the line width of the fine circuit pattern.

2. The modular mold as described in claim 1, characterized in that, The widened conductor pattern includes an overlapping portion extending to the side boundary of the sub-mold; The overlapping portions of two adjacent sub-molds in the plurality of sub-molds overlap at least partially in the splicing direction, and the overlap length of the overlapping portions is greater than the alignment accuracy of the packaging processing equipment, so as to form a continuous electrical path in the formed redistribution layer.

3. The modular mold as described in claim 2, characterized in that, The overlapping part includes multiple finger-shaped protrusions arranged at intervals along the splicing direction. The finger-shaped protrusions of two adjacent sub-molds are interleaved and inserted into each other to form a mechanical interlocking structure.

4. The modular mold as described in claim 1, characterized in that, The peripheral interconnection area is provided with packaging alignment marks for splicing and aligning with adjacent sub-molds; The encapsulation alignment marks include a first alignment mark and a second alignment mark arranged at intervals along the splicing direction; Wherein, the feature size of the first alignment mark is larger than the feature size of the second alignment mark, the first alignment mark is used to provide a coarse alignment reference, and the second alignment mark is used to provide a fine alignment reference.

5. The modular mold as described in claim 1, characterized in that, The pattern structure of the peripheral interconnect area has a first height in a direction perpendicular to the surface of the sub-mold, and the pattern structure of the high-density interconnect area has a second height in a direction perpendicular to the surface of the sub-mold, wherein the first height is greater than the second height.

6. The modular mold as described in claim 5, characterized in that, The patterned surface of the sub-mold also includes a transition region, which is disposed between the high-density interconnect region and the peripheral interconnect region; The line width of the conductor pattern in the transition region gradually decreases in a stepped or linear manner from the peripheral interconnect region to the high-density interconnect region. And / or, the pattern height within the transition zone gradually decreases in a sloping manner from the first height to the second height.

7. A method for manufacturing a modular mold for preparing a redistribution layer, characterized in that, The method is used to prepare a modular mold as described in any one of claims 1 to 6, the method comprising: At least one master mold and a substrate to be processed are provided. The master mold has an embossed structure corresponding to the surface of the sub-mold pattern. The embossed structure includes a high-density interconnect area pattern and a peripheral interconnect area pattern located on the periphery. A UV-curable imprinting adhesive is coated onto the surface of the substrate to be processed. According to the preset array arrangement order, the at least one main template is controlled to perform multiple imprinting and stepping movements relative to the substrate to be processed; wherein, in the splicing area between two adjacent imprinting operations, the alignment is performed based on the position of the peripheral interconnect area pattern, so that the peripheral interconnect area pattern formed by the current imprinting at least partially overlaps with the peripheral interconnect area pattern formed by the previous imprinting in the splicing direction. After each imprint, the UV-curable imprinting adhesive is cured by UV exposure; After all the step-by-step imprinting is completed, the main template is separated, and the splicing pattern area consisting of multiple arrayed sub-molds is formed on the substrate to be processed.

8. A mass production mold for preparing a packaged redistribution layer, characterized in that, The mass production mold is replicated from the modular mold as described in any one of claims 1 to 6; The mass production mold is used to prepare a single interconnect layer in the multilayer interconnect structure of integrated circuits, wherein the single interconnect layer integrates through-hole interconnect structure and wiring interconnect structure; The mass production mold has a splicing pattern area larger than the field of view of a single processing, and the splicing pattern area is formed by multiple sub-mold units arranged in an array. The surface relief pattern of each of the sub-mold units includes an integrated through-hole forming area and a wiring forming area, which are used to simultaneously form through-hole cavities and wiring trenches in the dielectric material layer in a single imprinting process. The sub-mold unit has a peripheral interconnection area on its periphery. The peripheral interconnection area includes a widened wire pattern and a package alignment mark. The widened wire pattern extends to the boundary of the sub-mold unit and is used to form an overlap interconnection with the corresponding wire pattern of the adjacent sub-mold unit, so as to form a continuous through-hole-wiring interconnection structure after metal backfilling and chemical mechanical polishing. The mass production mold is used as the Nth stage mold in the multilayer stacking process of integrated circuits. It performs step-by-step imprinting on the already formed N-1 via-wiring interconnect layer through substrate alignment to construct the Nth via-wiring interconnect layer, where N is an integer greater than or equal to 2.

9. A method for manufacturing a mass production mold for preparing a redistribution layer, characterized in that, The method is used to prepare the mass production mold as described in claim 8, and the method includes: Provide a modular mold as any one of claims 1 to 6 as a master mold; A substrate is provided, and a curable material layer is formed on the surface of the substrate; The master mold is pressed and bonded to the substrate, so that the relief pattern on the surface of the master mold is transferred to the curing material layer. The relief pattern includes an integrated through-hole forming area and a wiring forming area. The cured material layer is cured, and the master mold is separated from the substrate to form a mass production mold with an embossing structure that is complementary to the relief pattern; The embossing structure has a peripheral interconnection area on its periphery, which includes a widened wire pattern that extends to the boundary of the sub-mold unit and is used to form an overlapping interconnection with the corresponding wire pattern of the adjacent sub-mold unit.

10. The application of a mass production mold for preparing a redistribution layer in chip packaging, characterized in that, The mass production mold is the mass production mold as described in claim 8, the mass production mold having a peripheral interconnection area and a widened wire pattern, the widened wire pattern being used to form an overlapping interconnection with the corresponding wire patterns of adjacent sub-mold units; the application includes: By using a step-printing process, a multi-layer interconnect structure of integrated circuits is constructed on a packaging substrate or chip. The multi-layer interconnect structure of integrated circuits includes at least one single-layer interconnect layer that integrates a through-hole interconnect structure and a wiring interconnect structure. In the preparation of the single-layer interconnect layer, a single imprint is performed using the mass production mold to simultaneously form via cavities and wiring trenches within the dielectric material layer. Subsequently, a conductive via-wiring interconnect layer is formed through metal backfilling and chemical mechanical polishing processes.

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